vlogsl: A Strategy Language forSimulation-based Verification of Hardware

Michael Katelman and Jose Meseguer

University of Illinois at Urbana-Champaign

Haifa Verification Conference – October 5, 2010

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“Implied needs are in: (1) verification, which is a bottleneckthat has now reached crisis proportions . . . ”

“. . . due to the growing complexity of silicon designs, functionalverification is still an unresolved challenge, defeating the enor-mous effort put forth by armies of verification engineers andacademic research efforts.”

“Multiple sources report that in current development projectsverification engineers outnumber designers, with this ratioreaching two to one for the most complex designs.”

[ITRS 09]

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language-level approach to mitigating the verification burden:help verification engineers be more productive by providing abetter programming language to work in

strategy paradigm

explore the space of simulations in complex ways

vlogsl

an EDSL in Haskell supporting the strategy paradigm

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Outline:

1 strategy paradigm, motivation and definition

2 vlogsl architecture

3 maze examples

4 I2C case study

5 concluding remarks

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a data type called Config isthe linchpin of vlogsl; itprovides a first-classrepresentation of a Verilogdevice

event queues: active,non-blocking, future, etc.

current and past valuesof all source-level nodes

top-level input, clock,and reset names

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vlogsl does symbolic simulation

synthesizeable and behavioral Verilog

time efficient, extra memory required

vlogsl function: simulate

vlogsl is integrated with an SMT solver

integrated with an efficient bit-vector solver (STP)

vlogsl function: querySMT

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Intel Xeon X5570 (2.93GHz, 8MB L3, Nehalem), 24 GBRAM, Linux kernel 2.6.18, 64-bit. ghc 6.10.4 with -O1.VCS-MX D-2009.12 Full64.

vlogsl strategiesrandom 0.070sbreadth 0.293s

backtrack 0.013ssymbolic 0.018smixed 0.015s

vlogsl vs SystemVerilog +script

random 0.070sscript 7.111s

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I2C serial bus:

two serial, open-drain lines: clock (SCL), and data (SDA)

multi-master bus (requires arbitration), 7-bit addressing

used for low speed peripherals (speakers, cell-phone displays)

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I2C mastering controller fromopencores.org (open source):

core is roughly 1000 lines ofVerilog, FPGA proven

capable of multi-mastering

uses opencores.org“wishbone” interface

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I2C arbitration process:

SCL

SDA

SDA0

SDA1

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multi-mastering very difficult to test

opencores.org tested in real-world, no bugs found

submitted a potential bug, found via vlogsl, to author

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what vlogsl allowed us to do:

encapsulate bus transactions within an algebraic data type

iteratively insert delays between two conflicting transactions

re-use the initialization simulation steps, via backtracking

observe correctness, via querying statements

potential bug:

with just the right delay, slave reads wrong data (all 0s)

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Intel Xeon X5570 (2.93GHz, 8MB L3, Nehalem), 24 GBRAM, Linux kernel 2.6.18, 64-bit. ghc 6.10.4 with -O1.VCS-MX D-2009.12 Full64.

I2C write + read ×1 (vlogsl) 74.870sI2C write + read ×4 (vlogsl) 299.06s

I2C write + read ×1 (vcs) 0.404sI2C write + read ×4 (vcs) 0.470s

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summary and upcoming work:

strategy paradigm

vlogsl

novel use cases

I2C

vlogsl

large case study

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