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Vivado Design Suite Tutorial: Implementation

UG986 (v 2013.1) April 26, 2013

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Revision History The following table shows the revision history for this document.

Date Version Revision

04/26/2013 2013.1 First publication

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http://www.xilinx.com/warranty.htm%23critapps

Implementation www.xilinx.com 3 UG986 (v 2013.1) April 26, 2013

Table of Contents Revision History........................................................................................................................................................... 2

Vivado Design Suite Tutorial: Implementation ............................................................................................. 4

Overview ........................................................................................................................................................................ 4

Software Requirements ............................................................................................................................................ 4

Hardware Requirements .......................................................................................................................................... 4

Tutorial Design Description .................................................................................................................................... 4

Preparing the Tutorial Design Files ...................................................................................................................... 5

Lab #1: Using Implementation Strategies ...................................................................................................... 6

Introduction .................................................................................................................................................................. 6

Step 1: Opening the Example Project ................................................................................................................. 6

Step 2: Creating Additional Implementation Runs ........................................................................................ 8

Step 3: Launching and Analyzing Implementation Runs .......................................................................... 11

Step 4: Analyzing Implementation Runs Using Modified Timing Constraints ................................. 13

Conclusion .................................................................................................................................................................. 17

Lab #2: Using Incremental Compile ..............................................................................................................18

Introduction ............................................................................................................................................................... 18

Step 1: Opening the Example Project .............................................................................................................. 18

Step 2: Compiling the Reference Design ........................................................................................................ 20

Step 3: Create a New Synthesis and Implementation Run ...................................................................... 22

Step 4: Make Incremental RTL Design Changes .......................................................................................... 25

Step 5: Setting the Incremental Compile Checkpoint ............................................................................... 27

Step 6: Compiling Incrementally ........................................................................................................................ 28

Conclusion .................................................................................................................................................................. 31

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Vivado Design Suite Tutorial: Implementation

Overview This tutorial is comprised of two labs, each of which seeks to demonstrate an aspect of the Xilinx® Vivado® implementation flow:

• Lab #1: Using Implementation Strategies

• Lab #2: Using Incremental Compile

Vivado implementation includes all steps necessary to place and route the netlist onto the FPGA device resources, while meeting the design’s logical, physical, and timing constraints.

For more information about the design flows supported by the Vivado tools, see the Vivado Design Suite User Guide: Design Flows Overview (UG892).

Software Requirements This tutorial requires that the Vivado Design Suite 2013.1 release or later is installed.

Hardware Requirements • The supported Operating Systems include Redhat 5.6 Linux 64 and Windows 64 and 32

bit. • Xilinx recommends a minimum of 2 GB of RAM when using the Vivado tool.

Tutorial Design Description The sample design used for Lab #1 consists of a small design called project_cpu_netlist. There is a top-level EDIF netlist source file, as well as an XDC constraints file.

The sample design used for Lab #2 consists of a small RTL design called project_bft_core_hdl. The design includes both Verilog and VHDL RTL files, as well as an XDC constraints file.


http://www.xilinx.com/cgi-bin/docs/rdoc?v=2013.1;d=ug892-vivado-design-flows-overview.pdf

http://www.xilinx.com/cgi-bin/docs/rdoc?v=2013.1;d=ug892-vivado-design-flows-overview.pdf

Preparing the Tutorial Design Files


Both designs target an XC7K70T device. Small designs are used to allow the tutorial to be run with minimal hardware requirements and to enable timely completion of the tutorial, as well as to minimize the data size.

Preparing the Tutorial Design Files You can find the files for this tutorial in the Vivado Design Suite examples directory at the following location: <Xilinx_2013.1_install_area>/Vivado/<version>/examples/Vivado_Tutorial


Introduction


Lab1

Lab #1: Using Implementation Strategies

Introduction In this lab, you will learn how to use strategies with design runs by:

• Creating multiple implementation runs with different strategies.

• Comparing the Default Strategy results to the results of other strategies.

You will use the CPU Netlist example design that is included in the Vivado IDE.

Step 1: Opening the Example Project 1. Load the Vivado IDE by doing one of the following:

• Launch the Vivado IDE from the icon on the Windows desktop.

• Type vivado from a command terminal.

2. From the Getting Started page, click Open Example Project and select the CPU (Synthesized) design, as shown in the figure below.

Figure 1: Open Example Project


Step 1: Opening the Example Project


3. A dialog box appears entitled Project is Read-Only. Click Save Project As to specify a project name and location, as shown in the figure below.

Figure 2: Save Project As

The Vivado IDE displays project information in the Project Summary window. Because this is a netlist project, there are no options for synthesis in the Flow Navigator. As shown in the figure below, the Project Summary window shows that the next step in the design flow is Vivado implementation.

Figure 3: Project Summary Window


Step 2: Creating Additional Implementation Runs


Step 2: Creating Additional Implementation Runs Start by creating new implementation runs and changing the implementation strategy from the default. The sample design already contains one implementation run with the Vivado Implementation Defaults strategy.

1. From the main menu, select Flow > Create Runs. The Create New Runs wizard opens.

2. Click Next.

3. Select Performance_Explore as the Strategy for the run in the Configure Implementation Runs window, as shown in the figure below. Use the default settings for all other options.

Figure 4: Configure Implementation Runs Window

4. Click More to create another run.

5. Select Area_Explore as the Strategy for the run.

6. Click More to create another run.




7. Select Flow_RuntimeOptimized as the Strategy for the run.

The Configure Implementation Runs window now displays three new implementations along with the strategy you selected for each, as shown in the figure below.

Figure 5: Configure Implementation Runs Window Summary




8. Click Next to view the Launch Options and select Do not launch now.

Figure 6: Launch Options Window

9. Click Next to view the summary.

10. In the Create New Runs Summary page, click Finish.

Figure 7: Summary Window


Step 3: Launching and Analyzing Implementation Runs


Step 3: Launching and Analyzing Implementation Runs 1. In the Design Runs window, select all the implementation runs.

2. Click the Launch Selected Runs icon to open the Launch Selected Runs window.

3. Select Launch runs on local host and Number of jobs: 2 in the Launch Selected Runs window, as shown in the figure below. Two runs launch simultaneously; the others are queued.

Figure 8: Launch Selected Runs Window

Note: When the active implementation run (impl_1) finishes, you might see a prompt to Open Implemented Design, Generate Bitstream, or View reports (see figure below). Just click Cancel.

Figure 9: Implementation Completed Dialog Box


Step 3: Launching and Analyzing Implementation Runs


• Wait until all the runs have finished to analyze the results.

• The Project Summary window shows the settings and the results of the active run.

4. In the Project Summary window click the Post-Implementation tab at the bottom of the Utilization section.

The implementation utilization is displayed as a bar graph, as shown in the figure below. Note the LUT Utilization is 53%.


5. In the Design Runs window, right click the impl_3 run and select Make Active from the popup menu.

6. In the Project Summary window, click the Post-Implementation tab at the bottom of the Utilization section.

The implementation utilization is displayed as a bar graph. Note that the LUT Utilization is 51%. The Area_Explore strategy resulted in lower utilization, as expected.


Step 4: Analyzing Implementation Runs Using Modified Timing Constraints


7. Compare the Elapsed Time for each run in the Design Runs window.

Note that the run compiled with the Flow_RuntimeOptimized strategy compiled the fastest.

8. Compare the Worst Negative Slack (WNS) for each run in the Design Runs window.

All runs meet the timing constraints.

Step 4: Analyzing Implementation Runs Using Modified Timing Constraints To see the impact of the Performance_Explore strategy on meeting timing, you will change the timing constraints of the design to make timing closure more challenging.

1. In the Sources window, double-click the top_full.xdc file in the constrs_2 constraint set. As shown in the figure below, top_full.xdc opens in the Vivado text editor with the create_clock command highlighted in the toolbar.

Figure 11: Sources Window

2. Change the clock period constraint for clock sysClk from 10 ns to 6.5 ns.

Figure 12: top_full.xdc File




3. Save the changes by selecting File > Save File.

Note: Changing the active constraints changes the run status for all runs from “Complete” to “Out-of-date.”

4. Select all runs in the Design Runs window, and click the Reset Selected Runs icon .

5. At the Reset Runs prompt (shown in the figure below), enable the checkbox “Delete the generated files in the working directory” and click the Reset button.

The status of all runs changes from “Out-of-date” to “Not started.”

Figure 13: Reset Runs

6. In the Design Runs window, select all the implementation runs.

7. Click the Launch Selected Runs icon . The Launch Selected Runs window opens.

8. Select Launch runs on local host and Number of jobs: 2 in the Launch Selected Runs window (shown in the figure below) and click OK.

Figure 14: Launch Selected Runs Window




Note: When the first implementation run finishes, you might see a prompt to Open Implemented Design, Generate Bitstream, or View reports (see figure below). Just click Cancel.

Figure 15: Implementation Completed Prompt

• Two runs launch simultaneously; the others are queued.

• Wait until all the runs have finished to analyze the results.





9. In the Design Runs window, right click the impl_2 run and select Make Active from the popup menu.

Notice that only the run impl_2 compiled with the Performance_Explore strategy has a positive WNS.

10. Compare the Elapsed Time for each run in the Design Runs window.

You will notice that the run compiled with the Performance_Explore took almost twice as long as the other runs to complete. This is because the Performance_Explore strategy uses multiple algorithms for optimization, placement, and routing to get potentially better results.

RECOMMENDED: Reserve the Performance_Explore strategy for designs that have challenging timing constraints. When timing is easily met, the Performance_Explore strategy might increase compile times for no timing improvement benefit.

11. If you plan to continue to Lab #2, “Using Incremental Compile,” keep the Vivado IDE open. If you do not plan to continue, close the IDE.


Conclusion


Conclusion In this tutorial, you have:

• Learned how to create multiple runs with different implementation strategies

• Closed timing on a timing-critical design using the Performance_Explore strategy



Lab 2

Lab #2: Using Incremental Compile

Introduction In this lab, you will learn how to use the incremental compile flow to speed up place and route runtime for designs already implemented that require small changes and a re-compile. You will use the BFT HDL example design that is included in the Vivado IDE.

Step 1: Opening the Example Project 1. Start by loading Vivado IDE by doing one of the following:

• Launch the Vivado IDE from the icon on the Windows desktop

• Type vivado from a command terminal.

2. From the Getting Started page, click Open Example Project and select the BFT Core design, as shown in the figure below.

Figure 17: Open Example Design


Step 1: Opening the Example Project


3. A dialog box appears, entitled Project is Read-Only. Select Save Project As to specify a project name and location.

Figure 18: Save Project As

The Vivado IDE displays project information in the Project Summary Window, shown in the figure below.



Step 2: Compiling the Reference Design


Step 2: Compiling the Reference Design 1. From the main menu, select Flow > Run Implementation.

The Missing Synthesis Results dialog box opens, as shown in the figure below. The dialog box appears because you are trying to run implementation without an available synthesis netlist.

2. Click OK to launch synthesis first.

Implementation starts automatically when synthesis completes.

Figure 20: Missing Synthesis Results Dialog Box

3. After implementation finishes, the Implementation Complete dialog box opens. Click Cancel to dismiss the dialog box.

Figure 21: Implementation Completed Dialog Box


Step 2: Compiling the Reference Design


As shown in the figure below, the Design Runs window now shows the status of the current implementation run as Complete.

Figure 22: Design Runs Window Reference Design

During Implementation, Vivado saves intermediate results as checkpoints in the implementation runs directory. You will use the implementation results from the current run as the reference for the incremental compile.

4. In the Design Runs window, right click on impl_1 and select Open Run Directory from the popup menu.

This opens the run directory in a file browser, and you can see the various checkpoints that have been saved.

The location of the current implementation run directory is also a property of the run.

5. Check the location of the current implementation run directory in the Tcl Console by typing: get_property DIRECTORY [current_run]

This returns the path to the current run directory that contains the reference checkpoint.


Step 3: Create a New Synthesis and Implementation Run


Step 3: Create a New Synthesis and Implementation Run 1. From the main menu, select Flow > Create Runs.

Figure 23: Create New Runs Wizard

2. In the first page of the wizard, select Both and click Next.

The Configure Synthesis Runs window opens, as shown in the figure below.

Figure 24: Configure Synthesis Runs Window

3. Accept the default options by clicking Next. The Configure Implementation Runs window opens, as shown in the figure below.




Figure 25: Configure Implementation Runs Window

4. Accept the default options by clicking Next. The Launch Options window opens, as shown in the figure below.

5. Select Do not launch now and click Next.

Figure 26: Launch Options Window




6. In the Create New Runs Summary window, shown in the figure below, click Finish to create the new synthesis and implementation runs.

Figure 27: Create New Runs Summary Window

7. In the Design Runs window, right click the new implementation run impl_2 and select Make Active from the popup menu.

The Design Runs window shows the newly created runs in bold below the Reference Design runs, indicating that they make up the active run.

Figure 28: Design Runs Window


Step 4: Make Incremental RTL Design Changes


Step 4: Make Incremental RTL Design Changes 1. Double-click the top-level VHDL file bft.vhdl in the Sources window (shown below), to

open the file in the Vivado IDE text editor.

Figure 29: Sources Window

2. Go to line 45 of the bft.vhdl file and change the error port from an out to a buffer, as follows:

Figure 30: Line 45 Change to bft.vhdl File


Step 4: Make Incremental RTL Design Changes


3. Go to line 331 of the bft.vhdl file and modify the VHDL code, as described by the figures below. The first figure shows the code you start with. The second figure below shows how the code should look after you make modifications.

Figure 31: VHDL Code to Modify

Figure 32: Modified VHDL Code

4. Click File > Save File to save the changes.

Note: As you can see in the figure below, changing the active constraints also changes the run status for the reference run impl_1 from Complete to Out-of-date.

Figure 33: Design Runs Window Status Change


Step 5: Setting the Incremental Compile Checkpoint


Step 5: Setting the Incremental Compile Checkpoint 1. In the Design Runs window, right click the new implementation run impl_2 and select Set

Incremental Compile from the popup menu.

The Set Incremental Compile Window opens, as shown in the figure below. You are going to select the routed checkpoint from implementation run impl_1, which you previously compiled in Step 2, as the incremental compile checkpoint.

2. Click the icon in the Set Incremental Compile flow and browse to the ./project_bft_hdl.runs/impl_1 directory to select bft_routed.dcp as the incremental compile checkpoint.

Figure 34: Set Incremental Compile window

3. Click OK.

The INCREMENTAL_CHECKPOINT property of the current run is now set to the bft_routed.dcp checkpoint, enabling incremental compile for the current run.

Select the Properties tab, as shown highlighted in the figure below, to see the new incremental compile checkpoint.

Figure 35: Implementation Run Properties window


Step 6: Compiling Incrementally


4. Check the incremental checkpoint location in the Tcl Console by typing: get_property INCREMENTAL_CHECKPOINT [current_run]

This returns the full path to the bft_routed.dcp checkpoint.

TIP: To disable incremental compile for the current run, do one of the following:

• Clear the INCREMENTAL_CHECKPOINT property through the Set Incremental Compile window or the Implementation Run Properties window.

• Execute the following command in the Tcl Console: reset_property INCREMENTAL_CHECKPOINT [current_run].

Step 6: Compiling Incrementally 1. From the main menu, select Flow >Run Implementation.

This runs synthesis and implementation on the current run.

Note: When the first implementation run finishes, you might be prompted to Open Implemented Design, Generate Bitstream, or View reports (see figure below). Just hit Cancel.

Figure 36: Implementation Completed Prompt




2. From the Flow Navigator, select Open Implemented Design and click OK.

As shown in the figure below, the Design Runs window shows that the elapsed time for implementation run impl_2 is lower than for impl_1 because of the incremental compile flow.

Note: You will notice greater time savings for designs with longer run times.

Figure 37: Design Runs Window Summary

3. Select the Reports tab in the Results Window Area and double-click the Incremental Reuse Report in the Place Design section, as highlighted in the figure below.

Figure 38: Reports Window




The Incremental Reuse Report (see the figure below) shows the percentage of reused Cells, Ports and Nets. The higher the percentage, the more effective the reuse of placement and routing from the incremental checkpoint.

Figure 39: Incremental Reuse Report


Conclusion


4. Open the log file to view an Incremental Routing Summary:

a. Selecting the Log tab in the Results Window Area.

b. Scroll to the Incremental Routing Reuse Summary.

Figure 40: Incremental Routing Reuse Summary

The Incremental Routing Summary displays reuse statistics according to net fanout distribution. Fully reused indicates that the entire net’s routing is reused from the reference design. Partially reused indicates that some of the net’s routing from the reference design is reused. Some segments are re-routed due to changed cells, changed cell placements, or both. “Non reused” indicates that the net in the current design was not matched in the reference design.

Conclusion In this tutorial, you have:

• Learned how to run Incremental Compile using a checkpoint from a previously compiled run

• Examined the similarity between a reference design checkpoint and the current run by examining the Incremental Reuse Report


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