Virtual Prototyping with Carbon Design Tools

Aalap Tripathy, Rabi Mahapatra

Embedded Systems Codesign Lab

http://codesign.cse.tamu.edu

2

Overview

• SoC’s today• SoC design paradigm• SoC design issues• Virtual prototyping benefit• Virtual Prototyping options• What is a “Carbon model”?• Tools used & their interplay• Assignments Flow• Resources

3

Overview

• SoC’s today• SoC design paradigm• SoC design issues• Virtual prototyping benefit• Virtual Prototyping options• What is a “Carbon model”?• Tools used & their interplay• Assignments Flow• Resources

SoC’s today

Single chip DVR- 4 channel MPEG 4 DVR SoC

SoC’s today

802.11b radio, MAC, baseband processor, pn-chip flash, ARM Applications Processor

SoC’s today

Tablet/Smart TV/Thin Client SoC – ARM Applications Processor, Video Interface, CMOS Sensor Input, USB, Audio Interface (I2S, S/PDIF), SPI, I2C, UART, GPIOs

SoC’s today

Smartphone/Tablet SoC – ARM Mali 400 (single core) graphics card, Video Processing Unit, Audio Interface, Webcam Interface, Video Interface etc.

SoC’s today

Server SoC – ARM Quad Core

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Overview

• SoC’s today• SoC design paradigm• SoC design issues• Virtual prototyping benefit• Virtual Prototyping options• What is a “Carbon model”?• Tools used & their interplay• Assignments Flow• Resources

SoC design paradigm

• System Realization– System

requirements defined in h/w and s/w

• SoC Realization– Architecture for

semiconductor defined

– IP blocks chosen– Design matured

• Silicon Realization– Design

implemented in Silicon

• Concerns for SoC Architect– How to validate SoC design?– How to reduce risk? – Reuse IP – How to convey design intent to software development team? – Design is still in flux.– How to convey design impact to end-customer? – Black-box parts of design – How to quickly detect system corner cases?

SoC design paradigm

12

Overview

• SoC’s today• SoC design paradigm• SoC design issues• Virtual prototyping benefit• Virtual Prototyping options• What is a “Carbon model”?• Tools used & their interplay• Assignments Flow• Resources

SoC design issues

CPU(s) GPU

PCIe

USB3 Ethernet

MIPI

HDMI

WLAN

GPIO

UART

IP Selection• Which vendor?• Which IP?• Will they all play together?

Without Cycle Accurate Modeling• Forced to believe IP marketing• SoC may not meet spec• Can’t benchmark till purchase

SoC design issues

CPU(s) GPU

PCIe

USB3 Ethernet

MIPI

HDMI

WLAN

GPIO

UART

Without Cycle Accurate Modeling• No validation between layout and

performance• Inefficient power consumption• Missed performance spec• Waste power with overdesign

CCI/NoC NoC/Fabric

Per

iph

Fab

ric/N

oC

Interconnect Architecture• CCI vs. NOC vs. Fabric?• Make or buy?• How many?• What configuration(s)?

SoC design issues

CPU(s) GPU

PCIe

USB3 Ethernet

MIPI

HDMI

WLAN

GPIO

UART

Without Cycle Accurate Modeling• Wasted die space on

overdesigned cache• Poor cache performance• Overspend on IP• Wasted power

CCI/NoC NoC/Fabric

Per

iph

Fab

ric/N

oC

Memory subsystem• Cache sizing• How big?• Which memory technology?• System performance impact?

L2 Cache

DDRx

SoC design issues

Without Cycle Accurate Modeling• No guarantee of software

running on first day silicon• Inability to tune hardware/

software performance• Chip re-spin – huge cost

Firmware Development• Pre-silicon firmware

development• Software performance analysis• System integration issues

CPU(s) GPU

PCIe

USB3 Ethernet

MIPI

HDMI

WLAN

GPIO

UART

CCI/NoC NoC/Fabric Per

iph

Fab

ric/N

oC

L2 Cache

DDRx

SoC design issues

Without Cycle Accurate Modeling• Can’t black-box feature sets.• Can’t share with end customer• IP exposure• Design intent lost

Deployment• Secure platform for external

users

CPU(s) GPU

PCIe

USB3 Ethernet

MIPI

HDMI

WLAN

GPIO

UART

CCI/NoC NoC/Fabric Per

iph

Fab

ric/N

oC

L2 Cache

DDRx

CPU(s) GPU

PCIe

USB3 Ethernet

MIPI

HDMI

WLAN

GPIO

UART

CCI/NoC NoC/Fabric Per

iph

Fab

ric/N

oC

L2 Cache

DDRx

Internal Users External Users

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Overview

• SoC’s today• SoC design paradigm• SoC design issues• Virtual prototyping benefit• Virtual Prototyping options• What is a “Carbon model”?• Tools used & their interplay• Assignments Flow• Resources

Virtual Prototyping Benefit

Prototyping Options

Traditional Virtual

PrototypeRTL

Simulation Emulation

FPGA Based

Prototyping Silicon

Carbon SoC

Designer

Early Availability

Speed

Accuracy

HW Debug

SW Debug

Execution Control

Extra Devel Effort

Replication Cost

21

Overview

• SoC’s today• SoC design paradigm• SoC design issues• Virtual prototyping benefit• Virtual Prototyping options• What is a “Carbon model”?• Tools used & their interplay• Assignments Flow• Resources

What is a Carbon Model?

• What is a Carbon Model?– A high performance linkable software

object– Generated by proprietary compiler from

• synthesizable RTL design files• options & directives files

– Contains cycle-accurate & register-accurate description of hardware design

– Organized in the form of: • Software Object file (libdesign.a on Linux or

libdesign.lib on Windows)• Header file (libdesign.h)• Binary database (libdesign.symtab.db) –

database with information about all internal signals

• Using a Carbon Model– Linked with gcc (or Microsoft VC++)– Libcarbon5.so & carbon_capi.h are part of

installation on Linux– Simulator communicates with hardware

model through sockets using carbon_capi.h

Tools you will be using

http://www.carbondesignsystems.com/carbon-model-studio/

Carbon Model Studio• Enables carbon model

creation from RTL– Verilog/VHDL/

SystemC

http://www.carbondesignsystems.com/soc-designer-plus/

Carbon SoC Designer• Virtual Prototyping Canvas

– Assemble system– Drive system– Debug– Analyze (profile)– Optimize

http://www.carbondesignsystems.com/performance-analysis-kits/

CPAK• Carbon Performance Analysis

Kits• Ready-to-use assembly of

processor models + IP blocks + baremetal/OS + benchmarking tools

Interplay between tools

RTL

System LevelModel

Other IP Models

CA Model

CAModel

LT Model

LTModel

μP Model

Co-simulation

Firmware development/source

code

State Machine design

What will tools enable?

Architectural Analysis• Analyze memory subsystems

– Analyze cache statistics

• Analyze system throughput & latency• Validate bus & pipeline performance

assumptions– Zero silicon design & validation

• Validate HW/SW partitions– Software function profiling

• Synchronization & timing– Will arbitration logic work as expected?

• Enables quick re-configurability & re-run of SoC design

– Feature change is easy

What will tools enable?

Firmware Validation & Application software development• Begin firmware development even

while SoC is in “concept” stage.• Use the same platform as SoC

hardware & software designs mature– Maximize design reuse

• Integrated debug tools for hardware & software

– Analyze impact of software on hardware performance & vice versa

• Have complete system visibility– Set breakpoints in firmware debugger or in

hardware– Interrupt SoC operation at any point to examine

behavior

27

Overview

• SoC’s today• SoC design paradigm• SoC design issues• Virtual prototyping benefit• Virtual Prototyping options• What is a “Carbon model”?• Tools used & their interplay• Assignments Flow• Resources

Assignments Flow

• Introduction to SoC Designer– Construct & Debug an ARM Cortex A9 Bare-metal SoC– Understand the role of IP blocks/components necessary to design a system– Run an example sort application (insertion & bubble sort)

• Introduction to Model Studio– Create a carbon model from RTL (Vectored Interrupt Controller)– Write RTL for a APB compatible timer, create carbon model, integrate into ARM

Cortex A9 Baremetal SoC• Introduction to Co-simulation

– Export Interrupt Controller signals into Modelsim simulation kernel from SoC Designer.

– Use Interrupt Controller RTL & Top level test-bench to drive SoC Designer– Perform co-simulation for APB compatible timer

• Compilation & Simulation of Applications– How to create, compile, run and characterize an application on SoC Designer– “Hello World” & Vector multiplication – How to create an ARM Executable file

(axf)– Profile software code, observe bus level transactions & correlate to source

code

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2

3

4

Interplay between tools

RTL

System LevelModel

Other IP Models

CA Model

LT

ModelLT

Model

LTModel

μP Model

Co-simulation

Firmware development/source

code

State Machine design

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4

0

Example

ARM Cortex A9 Demo SoC• ARM application processor connected via an AXIv2 bus to program & data memory. Memory

mapped IO • Bridge to APB bus connects to timer, Bridge to AHB bus connects to interrupt controller• Core for processor compiled from ARM RTL, supports 32 kb Instruction Cache, 32kb Data cache,

128 KB TLB, no Floating Point Unit, does not contain Neon Media Processing Engine• AMBA – de-facto standard for on-chip communication, open standard – Learn more.

Who else is using these tools?

Resources

• ARM InfoCenter - http://infocenter.arm.com/• Carbon Tutorials - /opt/carbon_tutorials• Component User Guides - /opt/documents• ARM Specs - /opt/documents/arm_specs/• Carbon Tool User Guides - /opt/SoCDesigner/doc/• ModelSim User Guide -

/opt/ModelSim-SE-10.d/modeltech/docs/pdfdocs/modelsim_se_tut.pdf

• Please DO NOT register on Carbon Design Systems website. The models you may need for projects will be provided to you

• Contact for tool-related issues: – Prof. Rabi Mahapatra (rabi@cs.tamu.edu) – Deam Ieong (deam_ieong-0814@tamu.edu)

Conclusion

• Virtual prototyping tools can help accelerate– Architectural exploration– Firmware development– System integration & customer integration

• Familiarity & expertise with these tools will help– Job-relevant skills– Gain experience with ARM-based SoC, AXI– Experience switched fabrics and network topology

Acknowledgement