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South Asian Journal of Engineering and Technology Vol.7, No.1 (2018) 43–51

ISSN No: 2454-9614

DESIGN OF NOVEL LOW POWER HIGH-SPEED 1-BIT FULL ADDERS

SHREESATHYA.Ja, KESAVAN.S.Pb.

a) PG Scholar, ME (Communication Systems), Nandha College of TechnologyErode-638052.Tamilnadu, India.

b) Associate Professor, Dept of Electronics and Communication Engineering, Nandha College of Technology,Erode-638052.Tamilnadu, India.

Received: 3/12/2017, Revised: 19/2/2018 and Accepted: 21/3/2018

Abstract

The most commonly used arithmetic operation is addition and it is the speed-limiting element to make faster VLSI processors. As the demand for higher performance processors grows, there is a need to improve arithmetic unit performance. The aim of the project is to reduce the power consumption and delay of full adder circuit. The five full adder cells with driving power and one without driving power are designed. The modification work presents a parallel single-rail self-timed domino adder. It is based on a recursive formulation for performing multi bit binary addition. The Ripple Carry Adder is to be designed for each proposed full adders cells. Simulations with Tanner 13.0 tool confirm the superiority of the proposed cells compared with the previously reported ones in terms of power and delay.

Keywords: Power, Delay, Driving power, Domino logic.

1. Introduction

1.1. OverviewElevated usage of the battery-operated portable devices like mobile phones, personal digital assistants

(PDAs) and notebooks demand VLSI and ultra-large-scale integration designs with an enhanced power delay characteristics. Full adders, being one of the most basic building blocks of all the prior circuit applications, remain a vital focus domain of the researchers over the years. Different logic styles, each having its own merits and impediment, was investigated to implement1-bit full adder cells. The designs, reported so far, may be broadly classified into two categories: 1) static style and 2) dynamic style.

Different logic styles tend to favor one performance aspect at the expense of others. Standard static complementary metal– oxide–semiconductor (CMOS) dynamic CMOS logic complementary pass-transistor logic (CPL) and transmission gate full adder (TGA) are the most important logic design styles in the conventional domain. The other adder designs use more than one logic style, known as hybrid-logic design style, for their

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implementation [1]. These designs exploit the features of different logic styles to improve the overall performance of the full adder.

2. Existing System2.1 Classical Standard CMOS Full Adder

The C-CMOS consists of 28 transistors as shown in Figure 2.1. The C-CMOS design does not use complement of input signals, and therefore, the short-circuit current is reduced. Another benefit of C-CMOS is that it produces full voltage swing outputs. The critical path of C-CMOS circuit contains five transistors, which results in long propagation delay. In MOSFET technology, the ratio of size of PMOS to NMOS should be almost three to have equal switching speed between them and good noise margin for the circuit. This causes the existence of large input capacitance in MOSFET technology and consequently more delay and power dissipation Any gate in this design method consists of complementary logic networks composed of PMOS for pull-up and NMOS devices for pull-down. The design guarantees the output node move to and fro between the positive rail and ground so that the static power dissipation of the circuit is negligible.

Figure 2.1 Classical Standard CMOS Design

2.2 Full Adder Structure and OperationA 1-bit full adder adds binary numbers and accounts for values carried in sum out. A single-bit full adder

adds three single-bit numbers, often written as A, B, and Cin. The A and B used as operands and Cin bit are carried in from the succeeding least significant stage. Adder circuits produce double-bit output, carry-out and sum typically represented by the signals Cout and Sum, whereSum = A _ B _ Cin

Cout = A.B + A.Cin + B.Cin

2.2.1 Transmission Function Full Adder (TFA)

The TFA circuit is based on transmission function theory. The maximum propagation path of the TFA contains four transistors. The TFA is constructed using 16 transistors. The power consumption of the TFA is expected to be lower than that of the C-CMOS and Mirror cells due to lower transistor count and lower input capacitances. It is worth to point out that the TFA has not driving outputs, and its performance will significantly degrade either in the presence of large fan-outs or in a cascaded configuration. This is due to coupling the inputs to the outputs of the circuit.

2.3 Design MethodologyMost of the designed SUMs have been produced jointly or by cascading some modules. The cascaded

modules derived from reformulations of the Boolean function. As can be observed from the conventional circuits, all the published efficient designs rely on creative ideas of designers. They do not follow a systematic approach,

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whereas new solutions often have improved few characteristics, and so there is a free space for the systematic design methodology. The Manchester Carry Chain (MCC) is the most typical dynamic (domino) CLA adder architecture with a legitimate, agile and simple structure sufficient for implementation in VLSI. The extant methodology (MCC) generates all the carries enumerated conferring to relation in parallel, using a ceaseless shared transistor structure. In practice, the RCA length is constrained to four in order to dispatch the number of series-connected transistors.

3. Proposed system3.1 Design of Novel Full Adders

SCDM serves as a design technique for three-input XOR/XNOR, which is one of the most convoluted and competing as well as pragmatic three-input basic gates in arithmetic circuits. The technique puts significance on doing all the steps in a completely efficient way. It also enjoys high flexibility in design target, while it follows the same procedure to obtain the state-of-the-art designs. This brief has favored SCDM with the wise selection of the circuit components for the PDP target. The proposed methodology for three-input XOR/XNOR is presented according to the flowchart.

The design path is initiated by EBC efficient generation. In this step, general design targets are considered that the most peculiar ones are provoking reasonably balanced outputs, symmetric and power-ground-free structure, fewer transistors in the critical path, as well as allocating typical sub circuit.

Based on synergic combination of PTL and TGL, some novel two-input XOR/XNOR circuits were proposed. Then, they employed to form some novel low-power and high-speed full adder cells. In fact, five full adders with driving capability were proposed, each of which had their own merits.

3.2 Design of Proposed Domino 1-Bit Full AdderThe change work exhibits a parallel single-rail self-planned domino adder. It depends on a recursive plan

for performing multi bit double expansion. The task is parallel for those bits that needn't bother with any convey chain engendering. In this manner, the plan accomplishes logarithmic execution over irregular operand conditions with no unique speedup hardware or swell convey with domino diagram. A down to earth usage is given along a culmination discovery unit. The usage is consistent and does not have any common restrictions of high fan outs. A high fan-in entryway is required however yet this is unavoidable for non-concurrent logic and is overseen by interfacing the transistors in parallel.

This circuit administers programmed single-rail pipelining of the convey inputs separated by expansion and inertial postponements of the gates in the circuit way. It is satisfactorily an individual rail wave-pipelined get to and just dissimilar from common pipelined adders using double rail figuring to basically speak to the pipelining of carry signals. We introduce the design of an 8-bit adder module which is poised of two autonomous carry chains. These chains have the similar length (deliberated as the maximum number of series-connected transistors) as the 4-bit domino adders.

3.3 Block Diagram3.3.1 Driving Power Capability of a Full Adder

In many outlines, rationale entryways are associated with shape more intricate circuits. While no rationale gate information can be encouraged by in excess of one yield, it is normal for one yield to be associated with a few data sources. The innovation used to actualize rationale entryways more often than not permits a specific number of gate contributions to be wired specifically together without extra interfacing hardware. The most extreme fan-out of a yield measures its heap driving capacity as in Figure 3.1. It is the best number of contributions of entryways of a similar sort to which the yield can be securely associated.

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Figure 3.1 Full Adder Cell with Driving Capability

3.3.2 Domino CMOS Logic

Falling of Domino logic produces ripples to each assessment phase of the fell structure, like a domino falling in a steady progression. Once fallen, the hub states can't come back to "1" until the point that the following clock cycle, supporting the name Domino CMOS Logic. It diverges from different answers for the course issue in which falling is hindered by tickers or different means. They have littler region than the regular CMOS logic as in Figure 3.2. Higher working velocity is conceivable as their parasitic capacitance is less and task is free of glitches.

In Domino CMOS charge appropriation might be an issue and just non-rearranging structure are conceivable.

Figure 3.2 Domino CMOS Logic

3.4 Implementation

In the simulation, we embed all the full adders in an RCA with a word length of 4–32 bit without putting any buffers at intermediate cascaded stages as shown in Figure 3.3. The RCA test bed simulates a real environment for full adders. It is so likely that there is a full adder cell with good performance results when it is used solely, but it does not function well in large circuits. Therefore, it is very important to study the efficiency of full adder cells in large circuits. A good full adder cell will operate well even if in the presence of either the large fan-outs or cascaded structure.

Figure 3.3 N-Bit Ripple Carry Adder Cell

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3.5 Software UsedThe Tanner T-Spice test system, some portion of the Tanner Tool Suite, coordinates effortlessly with other

plan apparatuses in the stream and is perfect with industry-driving norms and furthermore it enhances re-enactment exactness with cutting edge displaying, multithreading support, gadget state plotting, on-going waveform survey and examination, and a charge wizard for basic SPICE linguistic structure creation.\

4. Designing of CMOS Hybrid Adder Circuits

4.1 New Pass Transistors Logic Full Adder (NEW-PT-FA) The New Pass-Transistor Full Adder (NEW-PT-FA) consists of 26 transistors. The critical path of the

NEW-PT-FA consists of four transistors as shown in Figure 4.1. This structure provides a good driving capability, using NOT gates at the output nodes. In fact, it guarantees the proper functionality when it is embedded inside large circuits in a cascaded form. Non full-swing outputs of XOR/XNOR circuits embedded in the NEW-PT-FA cause leakage current and consequently large power consumption than other circuits.

Figure 4.1 NEW-PT-FA Circuit design

4.2 New -Feedback Loop-Full Adder (NEW-FL-FA)The NEW-FL-FA contains more transistors compared with the NEW-PT-FA, 28 transistors. The critical

path of the NEW-FL-FA consists of four transistors as shown in Figure 4.2. The same as the NEW-PT-FA, inverters at the output nodes of NEW-FL-FA provide desired driving power for the following cells. Feedback loop transistors decrease power consumption by generating full output voltage swing and removing static power dissipation, while feedback loop decreases the delay of circuit as well.

Figure 4.2 NEW-FL-FA Circuit design

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4.3 New-Double Driving-Full Adder (NEW-DD-FA)The NEW-DD-FA employs transmission function along with PTL logic to produce full-swing outputs

for the XOR/XNOR circuit. It contains 30 transistors, and the propagation delay consists of four transistors as shown in Figure 4.3. Since TG is inherently a low-power circuit, the power consumption of the NEW-DD-FA is less than the NEW-PT-FA and NEW-FL-FA circuits.

Figure 4.3 NEW-DD-FA Circuit design

4.4 Proposed Domino AdderAnother adder cell comprises of two precharge transistors (M1, M8), assessment systems to assess convey and

entirety (PDN Carry, PDN Sum), two manager transistors (M2, M9), six footer transistors (M3, M4, M5, M10, M11, M12) and two semi-domino inverters as appeared in Figure 4.4.

Figure 4.4 DOMINO Adder Circuit design

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5. Result and Discussion5.1 Power Analysis

S. NO CMOS Full Adder Circuit Power Consumed (µm)

1 Classical Standard CMOS (C-CMOS) 0.2139

2 New Pass Transistor Logic Full Adder (NEW-PT-FA)

0.1707

3 New-Feedback Loop-Full Adder (NEW-FL-FA) 0.2113

4 New-Double Driving-Full Adder (NEW-DD-FA)

0.1909

5 Proposed DOMINO Adder 0.1693

Table 5.1 Power Analysis

5.2 Delay Analysis

S. NO CMOS Full Adder Circuit Delay Produced (Ps)



1.1645


1.1645


4 New-Double Driving-Full Adder (NEW-DD-FA)

0.3228


Table 5.2 Delay Analysis

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5.3 Power Delay Product

S. NOCMOS Full Adder Circuit

Power Delay Product


2 New Pass Transistor Logic Full Adder (NEW-PT-FA) 0.1987


4 New-Double Driving-Full Adder (NEW-DD-FA) 0.0616


Table 5.3 Power Delay Product

6. ConclusionThus the CMOS Full Adders and a DOMINO Full adder are designed using the Tanner 13.0 tool with 65nm

technology. The proposed cells perform well with supply voltage scaling. When they are used in large adders, such as RCA, they outperform their counterparts and make them to be fitting to the large circuits. In addition, the PDP of the proposed design is better than the existing designs. Thus, these circuits can be used for low power and high speed complex circuit design and their applications.

References

[1] Ahmed M. Shams, Tarek K. Darwish and Magdy A. Bayoumi (2002), ‘Performance Analysis of Low-Power 1-Bit CMOS Full Adder Cells’ IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 10, No. 1.

[2] BijoyKundu, Partha Bhattacharyya (2015), ‘Performance analysis of a Low Power High Speed Hybrid full adder circuit’ IEEE Transactions on Very large scale integration system vol.23 NO.10, pp2001-2008.[3] Dipankarsaha, subhramitabasak (2013), ‘A low voltage low power 4 bit BCD adder Designed using the clock gated power gating and the DVT scheme, IEEE Transactions on Very large scale integration system vol.17NO.15, pp 928-937.[4] Hamid Mahmoodi-Meimand and aliafzalikusha (2000), ‘Low power, low noise adder design with pass transistor adiabatic logic’, International conference on microelectronics, vol2.[5] Hung Tien Bui, Yuke Wang, and Yingtao Jiang (2002), ‘Design and Analysis of Low-Power 10-Transistor Full Adders Using Novel XOR–XNOR Gates’ IEEE Transactions on Circuits and Systems—Ii: Analog and Digital Signal Processing, Vol. 49, No. 1.

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[6][ Payal Soni and Shiwani Singh (2014), ‘Low Power Domino Full Adder’ International Journal of Computer Applications (0975 – 8887) Volume 93 – No 10.

[7] Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu and Cheng-Che Ho (2002), ‘A Novel High-Speed and Energy Efficient 10-Transistor Full Adder Design’ IEEE Transactions on Circuits and Systems—I: Regular Papers, Vol. 54, No. 5.[8] Morgenshtein. E.G, Friedman, Ginosar. R, and Kolodny. A (2010), ‘Unified logical effort-a method for delay evaluation and minimization in logic paths with interconnect’ IEEE Trans. Very Large Scale Integers. (VLSI)Syst., vol. 18, no. 5, pp. 689–696. Payal Soni and Shiwani Singh (2014), ‘Low Power Domino Full Adder’ International Journal of Computer Applications (0975 – 8887) Volume 93 – No 10.[9] Preetisudha Meher and Kamala Kanta Mahapatra (2014), ‘Low Power Noise Tolerant Domino 1-Bit Full Adder’ 978-1-4799-2206-2/14/$31.00_c 2014 IEEE.[10] Razak. H (2008) High Performance ASIC Design: Using Synthesizable Domino Logic in an ASIC Flow. Cambridge, U.K.: Cambridge Univ.[11] Sheng Lin, Yong-Bin Kim and Fabrizio Lombardi (2011), ‘CNTFET-Based Design of Ternary Logic Gates and Arithmetic Circuits’ IEEE Transactions on Nanotechnology, Vol. 10, No. 2.[12] Sheng Lin, Yong-Bin Kim and Fabrizio Lombardi (2011), ‘CNTFET-Based Design of Ternary Logic Gates and Arithmetic Circuits’ IEEE Transactions on Nanotechnology, Vol. 10, No. 2.[13] Soeleman. H, Roy. K, and Paul. B (2001) ‘Sub-domino logic: Ultralow power dynamic sub-threshold digital logic’ in Proc. 14th Int. Conf. VLSI Design, pp. 211–214.[14] Sumeer Goel, Ashok Kumar and Magdy A. Bayoumi (2006), ‘Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style’ IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 14, No. 12.[15] Yavar Safaei Mehrabani and Mohammad Eshghi (2016), ‘Noise and Process Variation Tolerant, Low-Power, High-Speed and Low-Energy Full Adders in CNFET Technology’ IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 24, NO. 11.

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