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PROGRAMMABLE LOGICDESIGN WITH VHDL

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Objectives

Upon completion of this training, your VHDL knowledge will enableyou to:

Implement efficient combinatorial and sequential logic Design state machines and understand implementation trade-offs

Use hierarchy / Create reusable components

Identify how VHDL will synthesize and fit into a PLD, CPLDand FPGA

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Objectives (contd.)

Upon completion of this training, you will be able to use Warp to:

Compile and synthesize VHDL designs for programmablelogic devices

Create VHDL or Verilog timing simulation models for

popular third party simulators. Target PLDs/CPLDs

Simulate the resulting device with the Aldec full timingsimulator

Use the report file to determine operating frequency, set-up time, clock to output delay, and device resource usage.

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Agenda

Intro, Why Use VHDL?, Design Flow

VHDL Design Descriptions

The Entity, Ports, Modes, Types

Exercise #1 - Write an entity statement

The Architecture, differing styles

Concurrent and Sequential statements

Processes: Signals vs. Variables

VHDL Operators/Overloading/Inferencing

VHDL Identifiers

Exercise #2 - write an architecture

Tri-State Logic, Don't Cares

Warp GUI overview

Exercise #3 - Design a bus controller

Aggregates and Subscripts Registers, Latches and Implicit Memory

Exercise #4 - Design a counter

Lunch

State Machines and State Encoding

Exercise #5 - Design a state machine

Design Hierarchy - components, pkgs, libraries

Exercise #6 - Design a loadable counter hierarchy

Generate Statement

Multiplexing I/O pins

Exercise #7 - DRAM output controller

User defined attributes

CPLD synthesis directives

Miscellaneous Topics and Wrap-up

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Introduction

VHDL is used to:

document circuits

simulate circuits

synthesize design descriptions

Synthesis is the reduction of a design description to a lower-level representation (such as a netlist or a set of equations).

This training course covers VHDL for PLD synthesis

The course will at times draw upon the concepts of VHDL as a

simulation language

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Why Use VHDL?

Quick Time-to-Market

Allows designers to quickly develop designs requiringtens of thousands of logic gates

Provides powerful high-level constructs for describing

complex logic Supports modular design methodology and multiple levels

of hierarchy

One language for design andsimulation

Allows creation of device-independent designs that areportable to multiple vendors. Good for ASIC Migration

Allows user to pick any synthesis tool, vendor, or device

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VHDL vs. VerilogHistory

Developed by DoD in early80s as means forContractors to DescribeDesigns-Funded VHSIC

1987 IEEE ratified 1076and DoD mandatedVHDL(F-22) and EDAvendors created tools.

1993 - IEEE 1076 93

1996 Commercial Sim and

Synthesis tools becomeavailable and 1164 pkgenables multi value logic

1983 -Gateway founded byGenrads HDL and HILOsimulator author.ReleasesVerilog HDL and Simulator

1985 Enhanced Verilog-XL-used for high enddesigns -Fast Simulator -interpretive-no need to

precompile

1990 Cadence buysGateway-nearly all ASICfoundries used XL asGolden Simulator

1995 IEEE 1364

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VHDL vs. VerilogCompilation/Data Types/High Level Constructs/Verbosity/Ease

Many E-A pairs may residein single system file.

User Can define DataTypes-Powerful

High Level Modeling w/Package, Config, Generate

Strongly Typed Language -models must be preciselycoded-often longer code

Less intuitive but much

more powerful constructs

Order or Code is crucial toobtaining desired output.

Simple Data Types arecontrolled by language

No Equivalent High LevelModeling Constructs

Verilog has looserstructure-can lead tounwanted and unidentifiederrors-more concise code.

Easiest to Grasp-moreprone to create unwantedresults

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WARP5.0

WARP2 Release 5.0 now supports Verilog Synthesis

Same great Synthesis as VHDL

Includes Aldec Full Timing Simulator and FSM Editor

Generates timing simulation models for major third party

VHDL and Verilog simulators

New GUI-Microsoft Std Interface

Even Better HDL Editor

Supports All Cypress Devices

Windows 95, NT, UNIX Same Great $99 Price

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Warp2/Warp3/Programming

Schematic Text/FSM

Synthesis

Simulation

Fitting

Sim. Model

DesignEntry

DesignCompilation

Front

End

Back

EndDesign

Verification

ISR/Impulse3

Simulator

JEDEC

JAM file

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VHDL Design Descriptions

VHDL design descriptions consist of an ENTITYdeclaration and an ARCHITECTURE body

The ENTITY declaration describes the design I/O

The ARCHITECTURE body describes thecontent or function of the design

Every architecture needs an entity so it is commonto refer to them together as anENTITY/ARCHITECTURE PAIR

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Example Entity/Architecture Pair:

A 2-Input And Function

ENTITY and2 IS PORT (

a,b : IN std_logic;

f: OUT std_logic);

END and2;

ARCHITECTURE behavioral OF and2 IS

BEGIN

f

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The Entity

A BLACK BOX

The ENTITY describes the periphery of theblack box (i.e., the design I/O)

BLACK_BOX

rst

d[7:0]

clk

q[7:0]

co

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Example Entity declaration

ENTITY black_box IS PORT (

clk, rst: IN std_logic;

d: IN std_logic_vector(7 DOWNTO 0);

q: OUTstd_logic_vector(7 DOWNTO 0);

co: OUTstd_logic);END black_box;

What does all this mean?

BLACK_BOX

rst

d[7:0]

clk

q[7:0]

co

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ENTITYentity_name IS

-- optional generics

PORT (

name : mode type ;

...

) ;

ENDentity_name;

entity_name is an arbitrary name

generics are used for defining parameterized components

name is the signal/port identifier and may be a comma

separated list for ports of identical modes and types mode describes the direction the data is flowing

type indicates the set of values name may be assigned

The Entity Declaration

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Ports

The Entity (BLACK BOX) has PORTS

PORTS are the points of communication

PORTS are usually the device pins

PORTS have an associated name, mode, and type

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Port Modes

A ports MODE indicates the direction that data is transferred:

IN Data goes into the entity only

OUT Data goes out of the entity only(and is not used internally)

INOUT Data is bi-directional (goes intoand out of the entity)

BUFFER Data that goes out of the entityand is also fed-back internally

Entity

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IEEE 1076 Types

VHDL is a strongly typed language (you cannot assign a signal ofone type to the signal of another type)

bit - a signal of type bitthat can only take values of '0' or '1'

bit_vector - a grouping of bits (each can be '0' or '1')

SIGNAL a: BIT_VECTOR(0 TO 3); -- ascending rangeSIGNAL b: BIT_VECTOR(3 DOWNTO 0); -- descending range

a

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INTEGER

useful as index holders for loops, constants, generics,or high-level modeling

BOOLEAN can take values TRUE or FALSE

ENUMERATED

has user defined set of possible values, e.g.,

TYPE traffic_light IS (green, yellow, red);

IEEE 1076 TYPES (contd.)

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IEEE 1164 A package created to solve the limitations of the BIT type

Nine values instead of just two ('0' and '1')

Allows increased flexibility in VHDL coding, synthesis, andsimulation

STD_LOGIC and STD_LOGIC_VECTOR are used instead

ofBIT and BIT_VECTOR when a multi-valued logicsystem is required

STD_LOGIC and STD_LOGIC _VECTOR must be usedwhen tri-state logic (Z) is required

To be able to use this new type, you need to add 2 lines toyour code:

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

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1164 Types std_logic and std_logic_vector are the industry

standard logic type for digital design

Values for Simulation & Synthesis

0 -- Forcing 0

1 -- Forcing 1

Z -- High Impedance L -- Weak 0

H -- Weak 1

- -- Dont care

Values for Simulation only (std_ulogic):

U -- Uninitialized

X -- Forcing Unknown

W -- Weak Unknown

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Entity Declaration Example

LIBRARY ieee;USE ieee.std_logic_1164.ALL;

ENTITY black_box IS PORT (

clk, rst: IN std_logic;


q:OUT

std_logic_vector(7DOWNTO

0);

co: OUTstd_logic);

END black_box;BLACK_BOX

rst

d[7:0]

clk

q[7:0]

co

MODETYPE

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Exercise #1: The Entity - A Walk through

Write an entity declaration for the following:

Port D is a 12-bit bus, input only

Port OE and CLK are each input bits

Port AD is a 12-bit, three-state bi-directional bus

Port A is a 12-bit bus, output onlyPort INT is a three-state output

Port AS is an output also used internally

my_design

d[11:0]oe

clk

ad[11:0]a[11:0]

intas

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Exercise #1: Solution

LIBRARY ieee;USE ieee.std_logic_1164.ALL;

ENTITY my_design IS PORT (


oe, clk: IN std_logic;

ad: INOUT std_logic_vector(11 DOWNTO 0);

a: OUT std_logic_vector(11 DOWNTO 0);

int: OUT std_logic;

as: BUFFERstd_logic);

END my_design;

-- In this presentation, VHDL keywords

-- are highlighted inbold, CAPITALS;-- however, VHDL is not case sensitive:

-- clock, Clock, CLOCK all refer to the

-- same signal, -- means a comment

my_design

d[11:0]

oe

clk

ad[11:0]

a[11:0]

intas

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The Architecture

Architectures describe what is in the black box (i.e., thestructure or behavior of entities)

Descriptions can be either a combination of

Structural descriptions

Instantiations (placements of logic-

much like in aschematic-and their connections) of building blocksreferred to as components

Behavioral/Dataflow descriptions

Algorithmic (or high-level) descriptions:

IF a = b THEN state

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ARCHITECTURE arch_name OFentity_name IS

-- optional signal declarations, etc.

BEGIN

--VHDL statements

ENDarch_name;

arch_name is an arbitrary name

optionalsignaldeclarations are used for signals local tothe architecture body (that is, not the entitys I/O).

entity_name is the entity name statements describe the function or contents of the entity

The Architecture Declaration

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Architecture Body Styles : BehavioralENTITY compare ISPORT (

a, b: IN std_logic_vector(0 TO 3);

equals: OUT std_logic);

END compare;

ARCHITECTURE behavior OF compare IS

BEGIN

comp: PROCESS (a,b)

BEGIN

IF a = b THEN

equals

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Architecture Body Styles : Dataflow

ENTITY compare ISPORT (



END compare;

ARCHITECTURE dataflow OF compare IS

BEGIN

equals

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Architecture Body Styles : Structural




END compare;

USEWORK.gatespkg.ALL ;

ARCHITECTURE structure OF compare ISSIGNAL x : std_logic_vector (0 to 3) ;

BEGIN

u0: xnor2 PORTMAP (a(0),b(0),x(0)) ;



u3: xnor2 PORTMAP (a(3),b(3),x(3)) ;u4: and4 PORTMAP (x(0),x(1),x(2),x(3),equals) ;

END structure;

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Mixing Architecture Styles

The various styles may be mixed in one architecture.

ENTITY logic IS PORT (

a,b,c: IN std_logic;

f: OUT std_logic);

END logic;

USE WORK.gatespkg.ALL;

ARCHITECTURE archlogic OF logic IS

SIGNAL d: std_logic;

BEGIN

d

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Comparing Architecture Styles

These examples synthesize to equivalent circuits

In more elaborate designs, some descriptions may yieldmore efficient circuits

sloppy code = inefficient results (see section 3.3.4)

Use styles that make your designs easier to describe andmaintain

Behavioral/Dataflow exploit module generation(described later)

Structural descriptions may make the design lessportable (may rely on a library of vendor-specificcomponents)

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Module Generation

In Warprelease 4.0, a package called std_arith can beused to overload the arithmetic (+, -, etc.) and relationaloperators (=, /=,

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Area SpeedAdders

Subtractors

Multipliers

Comparators

Counters

Shifters

Adders

Subtractors

Multipliers

Comparators

Counters

Shifters

Ultra39000

Ultra39000

Pre-optimized Circuits

Area SpeedAdders

SubtractorsMultipliers

Comparators

Counters

Shifters

Adders

SubtractorsMultipliers

Comparators

Counters

Shifters

FLASH370i

FLASH370i

Area SpeedAdders

Subtractors

Multipliers

Comparators

Counters

Shifters

Adders

Subtractors

Multipliers

Comparators

Counters

Shifters

Ultra37000

Ultra37000

The VHDL code

below describes

a comparator

if (a = b) then c

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A Simple CounterLIBRARY ieee;


USEWORK.std_arith.ALL;

ENTITY count8 ISPORT (

clk: IN std_logic;

count: BUFFERstd_logic_vector(7 DOWNTO 0));

END count8 ;

ARCHITECTURE arch_count8 OF count8 IS

BEGIN

upcount: PROCESS (clk)

BEGIN

IFclkEVENT and clk=1

THEN count

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VHDL Statements

There are two types of statements, Concurrent and Sequential

Concurrent Statements (means in parallel)

Concurrent statements are executed concurrently (atthe same time)

The order of concurrent statements is not important

Most of the examples we have seen so far have beenconcurrent statements:

Boolean Equations

WHEN-ELSE

WITH-SELECT-WHEN

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Sequential Statements (means in series)

Sometimes we need to model complex functions.In that case, we can use an algorithm or modelto describe the function. This is done withSequential Statements

With Sequential statements, the ORDER of thestatements is important (example later)

Therefore, we use aprocessto mark thebeginning and end of a block of sequentialstatements

Each completed process is considered to be onebig concurrent statement (there can be manyprocesses inside one architecture)

VHDL Statements (cont.)

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What is a VHDL Process ?

Processes are eitherawakeorasleep (active orinactive)

A process normally has a sensitivity list

When a signal in that sensitivity list changes value, theprocess wakes upand all of the sequential statements

are executed For example, a process with a clock signal in its

sensitivity list will become active on changes of theclock signal

At the end of the process, all outputs are assigned and theprocess goes back to sleepuntil the next time a signalchanges in the sensitivity list

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The Process (contd.)

label: PROCESS (sensitivity list)

-- variable declarations

BEGIN

-- sequential statementsEND PROCESS label;

The process label and variable declarations areoptional

The process executes when one of the signals in thesensitivity list has an event

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Combinational Logic

Can be described with concurrent statements

boolean equations

when-else

with-select-when

component instantiatons

Can be described with sequential statements

if-then-else

case-when

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Combinational Logic w/ Boolean Equations

Boolean Equations can be used in both concurrentand sequential signal assignment statements.

A 4-1 multiplexer is shown below

x

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Selective Signal Assignment:with-select-when

Assignment based on a selection signal WHEN clauses must be mutually exclusive

Use a WHEN OTHERS when all conditions are not specified

Only one reference to the signal, only one assignment operator (

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Combinational Logic w/

Selective Signal Assignment The same 4-1 multiplexer is shown below

with s select

x

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More on with-select-when

You can use a range of values

with int_value select

x

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Conditional Signal Assignment:when-else

Signal is assigned a value based on conditions

Any simple expression can be a condition

Priority goes in order of appearance

Only one reference to the signal, only one assignmentoperator (

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Conditional Signal Assignment The same 4-1 multiplexer is shown below

x

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Conditional Signal Assignment The when conditions do not have to be mutually

exclusive (as in with-select-when)

A priority encoder is shown below

j

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Combinatorial Logic

w/ Sequential Statements

Grouped together with Processes

Processes are concurrent with one another and withconcurrent statements

Order of sequential statements does make adifference in synthesis

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Sequential Statements: if-then-else

Used to select a set of statements to be executed

Selection based on a boolean evaluation of acondition or set of conditions

Absence ofELSE results in implicit memory

IF condition(s) THEN

do something;

ELSIF condition_2 THEN -- optional

do something different;

ELSE -- optional

do something completely different;

END IF ;

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if-then-else

4-1 mux shown below

mux4_1: process (a, b, c, d, s)

begin

if s = 00 then x

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Sequential Statements: Case-When

CASEselection_signalISWHEN value_1_of_selection_signal =>

(do something) -- set of statements 1

WHEN value_2_of_selection_signal =>

(do something) -- set of statements 2...

WHEN value_N_of_selection_signal =>

(do something) -- set of statements N

WHEN OTHERS =>(do something) -- default action

END CASE;

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The CASE Statement: 4-1 Mux

ARCHITECTURE archdesign OF design IS

SIGNAL s: std_logic_vector(0 TO 1);

BEGIN

mux4_1: PROCESS (a,b,c,d,s)

BEGIN

CASE s IS

WHEN "00" => x x

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Signal Assignment in Processes

Which Circuit is Correct?

ARCHITECTURE arch_reg OF reg IS

SIGNAL b: std_logic

reg2: PROCESS

BEGIN

WAIT UNTIL clock = '1' ; -- implied sensitivity list

b

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Signal Assignment in Processes

Inside processes, signals are not updated immediately.Instead, they are scheduled to be updated

The signals are not actually updated until the ENDPROCESS statement is reached

Therefore, on the previous slide, two registers will besynthesized (c

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Variables

When a concurrent signal assignment outside theprocess cannot be used, the previous problem can beavoided using a variable

Variables are like signals, BUT they can only beused inside a PROCESS. They cannot be used to

communicate information between processes Variables can be of any valid VHDL data type

The value assigned to a variable is availableimmediately

Assignment of variables is done using a colon (:),like this:

c := aAND b;

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Using Variables vs. Signals

Solution using a variable within a process:

-- assume a and c are signals defined elsewhere

ARCHITECTURE arch_reg OF reg IS

PROCESSVARIABLE b: std_logic ;

BEGIN

WAIT UNTIL clock = '1' ;

b := a ; -- this is immediate

c

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Native Operators Logical - defined for type bit, bit_vector, boolean*

AND, NAND OR, NOR

XOR, XNOR

NOT

Relational - defined for types bit, bit_vector, integer*

= (equal to)

/= (not equal to)

< (less than)

(greater than)

>= (greater than or equal to)

* overloaded for std_logic, std_logic_vector

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Native Operators (contd.)

Unary Arithmetic - defined for type integer* - (arithmetic negate)

Arithmetic - defined for type integer*

+ (addition), * (multiplication)

- (subtraction) Concatenation - defined for strings

&

Note, a STRING is any sequence of characters, therefore astd_logic_vectoris an example of a STRING

* overloaded for std_logic, std_logic_vector

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Overloaded Operators

In VHDL, the scope of all of the previous operatorscan be extended (or overloaded) to accept any typesupported by the language, e.g.,-- assume a declaration of a 16-bit vector as

SIGNAL pc IS std_logic_vector(15 DOWNTO 0);

-- then a valid signal assignment is

pc

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Legal VHDL Identifiers

Letters, digits, and underscores only (first character mustbe a letter)

The last character cannot be an underscore

Two underscores in succession are not allowed

Using reserved words is not allowed (the VHDL editor

will highlight reserved words for this reason)

Examples

Legal

tx_clk, Three_State_Enable, sel7D, HIT_1124

Not Legal

_tx_clk, 8B10B, large#num, case, clk_

W

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The WarpDesign Environment

Using the Project Wizard Entering Project Name / Path

Adding Files to the Project

Selecting a Device

Opening up a File for Editing

Additional Tools Review

Describing the left hand files pane

Overview of Pull down menus

Reviewing On-line Help

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Using the Project Wizard

Open Galaxy Using the pull down menu, select

Select Project - Target Device, then

i j /

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Entering Project Name / Path

In the Project Name dialog box, enter exercise2, then In the Project Path dialog box, browse to C:\warp\class,

then select

Addi Fil h P j

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Adding Files to the Project

Highlight ex2.vhd, select then

S l ti D i

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Selecting a Device

Double click on Small PLDs Select 22V10 on the left and PALCE22V10-5JC on the

right, then hit , then

O i Fil f Editi

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Opening up a File for Editing

In the left hand pane, double click on ex2.vhd.This will open the file up in the editor on the right

E i #2 A hit t

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Exercise #2: ArchitectureDeclaration of a Comparator

The entity declaration is as follows:

LIBRARY ieee;



a, b: IN std_logic_vector(3 DOWNTO 0);

aeqb: OUT std_logic);

END compare;

Write an architecture that causes aeqb to be asserted

when a is equal to b Multiple solutions exist

aeqba(3:0)

b(3:0)

Th ibl l ti

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Three possible solutions

Concurrentstatement solution using a conditionalassignment:

Concurrentstatement solution using booleanequations:

ARCHITECTURE arch_compare OF compare IS

BEGIN

aeqb

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Three possible solutions (contd.)

Solution using aprocess withsequentialstatements:

ARCHITECTURE arch_compare OF compare IS

BEGIN

comp: PROCESS (a, b)

BEGIN

IF a = b THEN

aeqb

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Using Tri-State Logic

ENTITY test_three IS

PORT( oe : IN std_logic;

data : OUT std_logic_vector(0 to 7));

END test_three;

ARCHITECTURE archtest_three OF test_three IS

BEGIN

PROCESS (oe)BEGIN

IF (oe = '1')

THEN data

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Behavioral Dont Cares

Warpuses explicit "dont care" conditions toproduce optimal logic equations

IF (a = '1') AND (b = '1') THEN

x

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Comparing Vectors to Strings-more on don't cares-

Comparing "1101" to "11-1" will return FALSE

Use std_match(a,"string")

Must include std_arith package

Example:...

signal a : std_logic_vector (1 to 4) ;

...

IF std_match(a,"10-1") THEN

x

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Additional Tools Review

Describing the left hand files pane Source File Listing

Design Hierarchy

Output File Listing

Pull down menus

File, Edit, View, Format, Project, Compile,Templates, Bookmarks, Tools, Window, Help

On-line Help

Source File Listing

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Source File Listing

Click on the leftmost tab on the bottom ofthe left hand pane

All source files for the current projectwill be displayed

Double click on any file to open it up in

the editor window on the right

Hierarchy Listing

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Hierarchy Listing

Click on the centermost tab on the bottomof the left hand pane

The project hierarchy will be displayed

Output File Listing

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Output File Listing

Click on the rightmost tab on the bottomof the left hand pane

All output files for the current projectwill be displayed

Double click on any file to open it up in

the editor window on the right By selecting a sub-heading within a file,

the editor will go to that section

Lower Status Windows

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Lower Status Windows

The lower window pane of Galaxy displays the following Compiler - A line by line account of the entire compilation

process. If an error is shown, you can jump into the properfile and line by double clicking on the error.

Errors & Warnings - This tab only shows errors & warnings

Search in files - Shows all occurrences generated by searchin files button

Pull-down Menus

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Pull down Menus

Files Menu - Allows the opening orclosing of files and projects, printing, andrecalling of prior files and projects

Pull-down Menus

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Pull down Menus

EditMenu - Typical Cut, Copy and Pastecommands as well as Find, Replace andSearch all files. Additionally, the editorand project user preferences dialog boxcan be selected.

Output File Listing

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Output File Listing

The Preferences screenallows the user to selecteditor options such asautosave, font size, tabspacing and highlighting.Additionally, project

settings can be set up aswell

Pull-down Menus

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Pull down Menus

View Menu - Allows the user to selectseveral viewing options such as viewingpane options and toolbars

FormatMenu - Allows block comment /un-comment as well as the setting of tabs

Pull-down Menus

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u dow e us

ProjectMenu - Used to add and removefiles from a project and perform librarymanagement. Additionally the user canselect/change device types, set compileroptions, set a project as the top level in ahierarchy as well as back annotate pins

and nodes to a control file.

Compiler Options

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p p

The Compiler options screenallows the user to choosegeneric attributes for his filesuch as area/speed andoptimization effort, I/Ovoltage, slew rate and bus

hold. Additionallytechnology mappingattributes can be set. Finally,the timing model output andtest bench output formats can

be selected.

Pull-down Menus

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Compile Menu - Allows the user to compilethe selected file or the entire project.

Templates Menu - The user can browsethrough VHDL constructs or place LPM

modules within his VHDL code.

Bookmarks Menu - Allows the user to addand recall bookmarks within his files.

Tools Menu - Launches the Jam Composer,Aldec Simulator and Aldec FSM Editor

Pull-down Menus

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Window Menu - Allows positioning offiles within the edit window as well asswapping between tabbed windows.

Help Menu - Access to on-line help anddevice selector guide.

Exercise #3:The Schematic

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The Schematic

en(1)

en(2)

en(3)

en[0:3]

dir

en(0)dir

gnd

dir

CY74FCT373T

CY74FCT245T

PLD

CY74FCT373T

CY74FCT373T

addr[1:0]

nvalid

nOE

LE

nOE

LE

nOE

LE

data[7:0]

status[7:0] control[7:0]

T/R

nOEgnd

Exercise #3

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Use Warp to compile the VHDL design description

of the truth table below:

Addr(1:0) nvalid

"00" '0'"00" '1'

"01" '0'"01" '1'

"10" '0'"10" '1'"11" '0'"11" '1'

dir

011

1

0111

en(3) en(2) en(1) en(0)

0 1 0 00 1 0 1

0 1 1 10 1 0 1

0 0 0 10 1 0 11 1 0 10 1 0 1

Write the Architecture for the given Entity (next)

Save design in file named ex3.vhd

Exercise #3:The Entity Declaration

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The Entity Declaration

the entity declaration is as follows:

LIBRARY ieee;


ENTITY ex3 ISPORT (

addr: IN std_logic_vector(1 DOWNTO 0);

nvalid: IN std_logic;

en: BUFFERstd_logic_vector(0 TO 3);

dir: OUT std_logic

);

END ex3;en

diraddr

nvalid

PLD

Exercise #3: Instructions

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Create a new project using the Project Wizard

Choose , ,

Name your project exercise3, click

Select the file ex3.vhd and it to the project

To choose a device: In the left hand window, double click onthe SPLD folder, then single click on the 22V10 folder. In theright hand window, select a PALCE22V10-5PC. Note thatthe details of the device are outlined below. Click

Double click on the ex3.vhd folder in the left hand window toopen the file up into the editor window on the right.

Exercise #3: Instructions (contd.)

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To designate that ex3.vhd is the top level design, eitherchoose or hit the shortcut button.

Output an 1164/VHDL timing file by selecting . In the Simulation Timing Model box,select 1164/VHDL

Modify the code in the editor window on the right toperform the function shown in the prior truth table.

To compile your design, either choose or hit the shortcut button.

If an error appear in the lower window, double click onit to highlight the location of the error in the editor.

Re-compile until all errors are gone


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Simulate the design using the Aldec simulator

Select

Select and selectc:\warp\class\vhd\ex3.vhd

Select and selectc:\warp\class\wave_ex3.awf

Assure the Time To Run is 200ns

Run the simulator or

Review against output on the following page

Reference the application note handout for additional details

Exercise #3: Aldec Simulator Waveform

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Exercise #3: The Solution

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The architecture is as follows:

ARCHITECTURE archex3 OF ex3 IS

BEGIN

en(0)

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An aggregate assignment concatenates signals together Good for creating a bus from several inputs

The concatenation operator can be used as well

tmp

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Using With/Select and aggregates

ARCHITECTURE archex3 OF ex3 ISSIGNAL control : std_logic_vector(2 DOWNTO 0);SIGNAL outputs : std_logic_vector(0 TO 4);

BEGINcontrol

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PLDs work well in synchronous applications

Two methods of creating synchronous logic

Structurally

instantiating components with registers

Behaviorally

Using a processes with a clock signal in thesensitivity list

Registers in Behavioral VHDL

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Example: a D-type flip-flop

ENTITY registered ISPORT (

d, clk: IN std_logic;

q: OUT std_logic);

END registered;

ARCHITECTURE archregistered OF registered IS

BEGIN

flipflop: PROCESS (clk)

BEGIN

IFrising_edge(clk)

THEN q

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The synthesis compilerinfers that a registeris to be createdfor which signal q is the output because

The clock (clk) is in the sensitivity list

The construct, rising_edge(clk), falling_edge(clk) orclkevent AND clock=1 appears in the process

The rising_edge(clk) or falling_edge(clk) statement impliesthat subsequent signal assignments occur on therising/falling edge of the clock

The absence of an else clause in the if-then statementimplies that if the clkevent and clk = 1 condition is not

fulfilled (i.e. not a rising-edge), q will retain its value untilthe next assignment occurs (this is referred to as impliedmemory)

Rising/Falling Edge Functions

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The 1164 package defines 2 functions for edge detection

rising_edge (signal)

similar to (signalevent andsignal=1)

falling_edge (signal)

similar to (signalevent andsignal=0)

ifrising_edge(clk) then

q

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A 4-bit counterwithsynchronous reset

USEWORK.std_arith.ALL;...

upcount: PROCESS (clk)

BEGIN

IF rising_edge(clk) THEN

IF reset = '1'

THEN count

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A 4-bit counterwith asynchronous reset


upcount: PROCESS (clk, reset)

BEGIN

IF reset = '1'

THEN count

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A 4 bit loadable counterwith asynchronous reset


upcount: PROCESS (clk, reset)

BEGIN

IF reset = '1

THEN count

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Instead of using the rising_edge or falling_edge function,replace it with clk=1 or clk=0 and put d in thesensitivity list

latch: PROCESS (clk, d)

BEGIN

IF clk = '1'

THEN q

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Example: Using LPM library

LIBRARY ieee;

USEieee.std_logic_1164.ALL;

USE WORK.lpmpkg.all ;

ENTITY registered ISPORT (

d: IN std_logic;

clk: IN std_logic_vector(3 DOWNTO 0);

q: OUT std_logic _vector(3 DOWNTO 0));

END registered;

ARCHITECTURE archregistered OF registered IS

BEGIN

flipflop: Mff generic map (lpm_width=>4,lpm_fftype=>lpm_dff)

PORT MAP (data=>d,clock=>clk,enable=>one,q=>q);END archregistered;

qd

clk

The WAIT statement

This is another method to activate a process

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This is another method to activate a process

The WAIT statement is a sequential statement whichsuspends the execution of a process until thecondition specified becomes valid (true)i.e., an implied sensitivity list, e.g.,

sync: PROCESS

BEGIN

WAIT UNTIL clock='1';

IF enable='1'

THEN q_out

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Signals in VHDL have a current value and may bescheduled for a future value

If the future value of a signal cannot be determined, alatch will be synthesized to preserve its current value

Advantages:

Simplifies the creation of memory in logicdesign

Disadvantages:

Can generate unwanted latches, e.g., when all ofthe options in a conditional sequential statementare not specified

Implicit memory:Example of incomplete specification

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p p p

Note: the incomplete specification of the IF...THEN...

statement causes a latch to be synthesized to store theprevious state of c

ARCHITECTURE archincomplete OFincomplete IS

BEGIN

im_mem: PROCESS (a,b)

BEGIN

IF a = '1'THEN c

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p p p

The conditional statement is fully specified, and thiscauses the process to synthesize to a single gate

ARCHITECTURE archcomplete OFcomplete IS

BEGIN

no_mem: PROCESS (a, b)

BEGIN

IF a = '1'

THEN c

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To avoid the generation of unexpected latches

always terminate an IF...THEN... statement with anELSE clause

cover all alternatives in a CASE statement

define every alternative individually, or

terminate the CASE statement with a WHENOTHERS... clause, e.g.,CASE coin_inserted IS

WHEN quarter => total total total total

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Making use of the previous examples, write an

entity/architecture pair for the following design:

ENR

DIN

Q

REGISTER

4

4

Q

P

P=Q

COMPARATOR

4

COUNT

CLOCK

ENC

LD

DATA

ENR

RESET (sync)

ENCLD

DIN

Q

COUNTER

RST


Create a new project using the Project Wizard

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p j g j

Choose , , Name your project exercise4, click

Select the file ex4.vhd and it to the project

The target device is 32 Macrocell 8.5 ns CPLD in a 44 pin

TQFP package. Choose CY7C371I-143AC Modify the code in the editor window on the right to perform the

function shown in the prior diagram.

Hints:

Use 2 processes and a concurrent statement

Use the register, counter, and comparator shown previously

Incorporate count enable logic in count process


To simulate your design with the Aldec Simulator open the

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To simulate your design with the Aldec Simulator, open the

VHDL file C:\warp\class\vhd\ex4.vhd and then select

Add all of the signals by selecting (or using the shortcut ). When the windowopens, double click on each signal in the right hand box until

all signals are added. Enter the stimulus found on the following page, reference the

applications note handed out in class for additional details


Add the following stimulus:

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Add the following stimulus:

reset

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To get help on the format for adding stimulators (or any other

topic), open up the stimulator dialog box and click on thequestion mark in the upper right corner ( ) then in theEnterFormula box.


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Exercise #4: SolutionLIBRARY ieee;


ENTITY ex4 IS PORT (

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clock, reset, enc, enr, ld: IN std_logic;data: IN std_logic_vector (3 DOWNTO 0);

count: BUFFERstd_logic_vector(3 DOWNTO 0));

END ex4;

USEWORK.std_arith.ALL; -- for counter and Ultragen


SIGNAL comp: std_logic;

SIGNAL regout: std_logic_vector (3 DOWNTO 0);BEGIN

reg: PROCESS (clock)

BEGIN

IFRISING_EDGE(clock)

THEN

IF enr = '1' THEN

regout

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BEGINIFRISING_EDGE(clock) THEN

IF reset = '1'

THEN count

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Attribute PIN_NUMBERS of count(1) is "37" ;


Attribute PIN_NUMBERS of data(2) is "29" ;






Attribute PIN_NUMBERS of ld is "14" ;

Attribute PIN_NUMBERS of enc is "13" ;

Attribute PIN_NUMBERS of reset is "12" ;

Attribute PIN_NUMBERS of clock is "7" ;

Attribute PIN_NUMBERS of enr is "4" ;

State machines

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Moore Machines A finite state machine in which the outputs

change due to a change of state

Mealy Machines

A finite state machine in which the outputs canchange asynchronously i.e., an input can causean output to change immediately

Moore machines

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Outputs may change only with a change of state Multiple implementations include:

Arbitrary state assignment

outputs must be decoded from the state bits

combinatorial decode registered decode

Specific state assignment

outputs may be encoded within the state bits

one-hot encoding

Example: A Traffic Light Controller

Lets take a look at an example state machine and see

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p

how to describe it using the 3 types ofimplementations:

RESET

(asynchronous)

RED

TIMER1

YELLOWGREENTIMER1

TIMER2

TIMER2

Y='1'G='1'

TIMER3

TIMER3

R='1'

Moore state machine implementations (1)

Outputs decoded from state bits COMBINATORIALLY

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Outputs decoded from state bits COMBINATORIALLY

combinatorial output logic is in serieswith state registers

outputsare a function of the present state only

time from clock to output (tco) is long

Inputs

Next

State

Logic

State

Registers

Output

Logic

Outputs

Present State

Next State

Tco + tpd

Example: The Entity Declaration

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The entity declaration remains exactly the same for eachimplementation.

For example:

LIBRARY ieee;


ENTITY state_machine IS PORT (

clock, reset: INstd_logic;

timer1, timer2, timer3: IN std_logic;

r, y, g:OUT std_logic);

END state_machine;

Example: Solution 1

Combinatorial outputs decoded from the state registers

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ARCHITECTURE arch_1 OF state_machine ISTYPE traffic_states IS (red, yellow, green); -- enumerated typeSIGNAL sm: traffic_states;

BEGIN

fsm: PROCESS (clock, reset) -- the process describes theBEGIN -- state machine only

IF reset = '1' THEN

sm IFtimer1=1THEN sm

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ELSE sm sm

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registered output logic is in parallel with state registers

outputs are a function of the previous state and the inputs

tco is shorter, but you need more registers

Outputs

State

Registers

Output

Logic

Output

Registers

Inputs

NextState

Logic

Present State

tco

Example: Solution 2 Registered outputs decoded from the state registers

ARCHITECTURE arch 2 OF state machine IS

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ARCHITECTURE arch_2 OF state_machine IS

TYPE traffic_states IS (red, yellow, green);SIGNAL sm: traffic_states;

BEGIN

fsm: PROCESS (clock, reset) -- the process describes theBEGIN -- state machine AND the outputs

IF reset = '1' THEN

sm

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s ye o ;r

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Red Green Yellow State Encoding

1 0 0 100

0 1 0 010

0 0 1 001

p g

Note: Both bits of the state encoding are used as outputs

State

Registers

Outputs

InputsLogic

Tco

State

S0

S1

S2

Example: Solution 3

Outputs encoded inside the state registers


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SIGNAL sm: std_logic_vector(2 DOWNTO 0) ;

CONSTANT red: std_logic_vector(2 DOWNTO0) := 100" ;

CONSTANT green: std_logic_vector(2 DOWNTO 0) := "010" ;

CONSTANT yellow: std_logic_vector(2 DOWNTO 0) := "001" ;

BEGIN


IF reset = '1' THENsm IFtimer1=1THEN sm

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THEN sm

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in FPGA-type architectures

reduces the next state logic

requires fewer levels of logic cells

enables high-speed state machines (> 100MHz)

in CPLDs

reduces the number of product terms

can eliminate expander product terms (i.e.reduce delays, and increase operating speed)

but, uses more macrocells

Example: One-hot-one Solution Combinatorial outputs decoded from the state registers


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TYPE traffic_states IS (red, yellow, green); -- enumerated typeSIGNAL sm: traffic_states;ATTRIBUTE state_encoding OF traffic_states: TYPE IS one_hot_one;

BEGIN


IF reset = '1' THEN

sm IFtimer1=1THEN sm

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ELSE sm sm

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S1 001 000010

S2 010 000100

S3 011 001000

S4 100 010000

S5 101 100000

S3 State Logic

Sequential - enable * /b2 * b1 * b0

One-hot-one - enable * b3

Moore Machines: Summary Outputs decoded from the state bits

flexibility during the design process

i d ll i

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using enumerated types allows automaticstate assignment during compilation

Outputs encoded within the state bits

manual state assignment using constants

the state registers and the outputs are merged reduces the number of registers

but, may require more product terms

One-Hot encoding

reduces next state decode logic

high speed operation but, uses more registers

Mealy Machines

O t t h ith h f t t OR ith

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Outputs may change with a change of state OR witha change of inputs

Mealy outputs are non-registered because theyare functions of the present inputs

Inputs

State

Registers

Logic Outputs

Example: The Wait State Generator

St t di

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State diagram:

PWAIT

RESET

(async)

IDLE RETRYREQ

PWAIT

if, ENABLE='0'

RETRY_OUT='1'

REQ

Example: Mealy Machine SolutionARCHITECTURE archmealy1 OF mealy1 IS

TYPE fsm_states IS (idle, retry);SIGNAL wait_gen: fsm_states;

BEGIN

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BEGINfsm: PROCESS (clock, reset)BEGINIF reset = '1' THEN

wait_gen IF req = '0' THEN wait_gen

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hold extendsamplePOS

POS

RESET

(sync)

track='1'clear='0'

track='1'

Exercise #5: Instructions Using the Project Wizard create a new project named exercise5

and add the template ex5.vhd

The target device is 32 Macrocell 10 ns CPLD in a 44 pin PLCC

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The target device is 32 Macrocell 10 ns CPLD in a 44 pin PLCCpackage. Choose CY7C371I-110JC

Use automatic state bit assignment using an enumerated type

Compile and synthesize your design using Warp

Check the report file for the number of macrocells used. What is the clock-to-output time (tco)?

Change your state machine to use constants as follows:

hold=10 sample=01 extend=11

Re-compile your design and check the report file again How many macrocells are utilized now ? What is the tco?


To simulate your design with the Aldec Simulator, open the

VHDL file C:\warp\class\vhd\ex5 vhd and then selectSi l i I i i li Si l i

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VHDL file C:\warp\class\vhd\ex5.vhd and then select

Add all of the signals by selecting (or using the shortcut ). When the windowopens, double click on each signal in the right hand box until

all signals are added. Select the clock signal with the button. Now

depress the button and select .Choose from the stimulator type pull down menu, setthe frequency to 50MHz and then depress .


Select the reset signal with the button. Now

choose (or using the shortcut )M th i t t th h ld d th

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choose (or using the shortcut ).Move the mouse pointer to then hold down the button and drag to the mark (section willhighlight). Depress the key. Select to and depress the key. Select the reset signal with thebutton. Now depress the button

and select . Choose from thestimulator type pull down menu, then depress .

Repeat the above for the pos signal, making it high from to , low from to then highfrom to . Remember to set to

Run the simulator for 300ns


If you are having a problem drawing waveforms, assure that

the simulator is not running To stop the simulation choose f th ll d

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the simulator is not running. To stop the simulation, choose from the pull down menu.

If you are having problems saving the waveforms that youhave drawn in by hand, assure that the the letters Cs are inthe stimulator column of the waveform view. If a Cs is not

displayed it is because the button was not depressedafter setting the signal to a stimulator type.

After loading a new waveform it is best to reset the simulatorby choosing from the pull down menu.

Verify that your waveform is similar to the view on thefollowing page.


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Exercise #5: Solution AUsing an Enumerated Type

Macrocells = 3, Tco2 (Tco + Tpd) = 10.5ns

LIBRARY ieee;

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clock, pos,

reset: IN std_logic;

clear, track: OUT std_logic);

END ex5;


TYPE states IS (hold, sample, extend);

SIGNAL fsm: states;

BEGIN

clear

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fsm < hold;

ELSE

CASE fsm IS

WHEN hold => IF pos = '0'

THEN fsm

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clock, pos,

reset: IN std_logic;

clear, track: OUT std_logic);

END ex5;

ARCHITECTURE archex5 OF ex5 ISSIGNAL fsm : std_logic_vector(1 downto 0);

CONSTANThold : std_logic_vector(1 downto 0) := 10;

CONSTANTsample : std_logic_vector(1 downto 0) := 01;

CONSTANTextend : std_logic_vector(1 downto 0) := 11;

BEGIN

clear

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;

ELSE

CASE fsm IS

WHEN hold => IF pos = '0'

THEN fsm

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hierarchical designinto many levels, with a top level design bringing allthe lower-level components together

This allows very complex designs to be divideddown into smaller, more easily managed modules

In the past, this was the major advantage ofschematic capture tools

But, VHDL also supports hierarchical designs !!

Hierarchical Design Methodology

Advantages:

Components (VHDL models) can be created tested

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Components (VHDL models) can be created, testedand stored for later use

Allows the re-use of common building blocks

Allows you to purchase 3rd Party off-the-shelf

modules (e.g. UART, PCIbus Interface etc) Makes the design more readable and easier to

understand

Complex design tasks can be split across manydesigners in a team

VHDL Hierarchy Decomposition

In VHDL, hierarchy is composed of:

COMPONENTs

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entity/architecture pairs which can beinstantiated (placed) within other designs

PACKAGEs

a collection of one or more COMPONENTsand other declarations

LIBRARIES

a collection of COMPILED design units

e.g. packages, components, entity/architecturepairs etc.

Packages: How it all fits together

b

a

c r

q

cb

mux2to1a

sel

i t

p

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selmux2to1

c

b

mux2to1a

sel

symbol

component

schematic

entity/architecture

library

package

schematic

entity/architecture

toplevel

s

sel

Hierarchy ManagementLibraries are used to store re-usable components, type definitions,

overloaded operators etc. You add the LIBRARY and USE

clauses to your code to get access to them

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Your Design (VHDL)

LIBRARY ieee;

USE ieee.std_logic_1164..

USE work.std_arith.all

Library (Compiled)

ieee

Library (Compiled)

work

Packages (VHDL) Others (VHDL)

std_logic

type

definitions

Others (VHDL)

overloaded

operators

Packages (VHDL)

std_logic_1164

std_arith

Package and Component Declarations

When you have created a working entity/architecture

pair, you need to add a component declaration tok it bl COMPONENT

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make it a re-usable COMPONENT

COMPONENTS need to be stored in PACKAGES,so you need to write a package declaration to storeall your components

When you compile your package with no errors, thecomponents will be stored in the WORKlibrary

WORKis the default librarywhere everythingYOUcompile gets stored. Because it is the default library,you do NOT need to add:

LIBRARY WORK; -- not required

Package and ComponentDeclarations: An Example

LIBRARY ieee;


PACKAGE mymuxpkg IS

COMPONENT mux2to1 PORT (

a b sel: IN std logic;Package and Component

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a, b, sel: IN std_logic;

c: OUT std_logic);

END COMPONENT;

END mymuxpkg;

LIBRARY ieee;


ENTITY mux2to1 IS PORT (

a, b, sel: IN std_logic;

c: OUT std_logic);

END mux2to1;

ARCHITECTURE archmux2to1 OF mux2to1 IS

BEGIN

c

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ENTITY toplevel IS PORT (

s: IN std_logic;

p, q, r: IN std_logic_vector(2 DOWNTO 0);

t: OUT std_logic_vector(2 DOWNTO 0));

END toplevel;

USE WORK.mymuxpkg.ALL;

ARCHITECTURE arch_top_level OF toplevel IS

SIGNAL i: std_logic_vector(2 DOWNTO 0);

BEGIN

m0: mux2to1 PORT MAP (a=>i(2), b=>r(0), sel=>s, c=>t(0));

m1: mux2to1 PORT MAP (c=>t(1), b=>r(1), a=>i(1), sel=>s);

m2: mux2to1 PORT MAP (i(0), r(2), s, t(2));i

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s

c

b

a

sel

i(2)

r(0)

m0

t(0)

c

b

a

sel

i(1)

r(1)

m1

t(1)

c

b

a

sel

i(0)

r(2)

m2

t(2)

Exercise #6

Making use of exercise #4, we will use a separateentity/architecture for each block and use VHDL hierarchy

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ENR

DIN

Q

REGISTER

4

4

Q

P

P=Q

COMPARATOR

4

COUNT

CLOCK

ENC

LD

DATA

ENR

RESET (sync)

ENC

LD

DIN

Q

COUNTER

RST

Exercise #6 : Instructions

Write a hierarchical VHDL description of the previous

schematic which instantiates all of the components shown inthe design

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g

The entity/architecture is given for all 3 components

count4.vhd, reg4.vhd, comp4.vhd

Complete the package which has the componentdeclarations for all 3 components

package.vhd

Complete the top level file which instantiates the 3components and makes the interconnections

ex6.vhd


Using the Project Wizard create a new project named exercise6and add the templates count4.vhd, reg4.vhd, comp4.vhd,

package.vhd and ex6.vhd in THE ORDER shown

h d i i ll i i

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The target device is 256 Macrocell 7.5 ns CPLD in a 160 pinTQFP package. Choose CY7C37256P160-154AC

Highlight the top-level (lowermost) file (ex6.vhd) and Click-onthe Set topbutton

Highlight the top 3 files (one at a time) and Click-on the Compileselectedbutton

Before compiling package.vhd and ex6.vhd, you must completethe files.

Once all of the files have been compiled separately, use theCompile Project button for subsequent compiles

LIBRARY ieee;


PACKAGE ex6 pkg IS

Exercise 6 Solution: package.vhd

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C G e 6_p g S

COMPONENT comp4 PORT (

p, q : IN std_logic_vector (3 DOWNTO 0);

peqq : OUT std_logic);

END COMPONENT;

COMPONENT reg4 PORT (

clk, enr : IN std_logic;

din : IN std_logic_vector(3 DOWNTO 0);

q : OUT std_logic_vector(3 DOWNTO 0));

END COMPONENT;

Exercise 6 Solution: package.vhd (cont)

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COMPONENT count4 PORT(

clk, enc, ld, rst : IN std_logic;

din : IN std_logic_vector(3 downto 0);

q : BUFFERstd_logic_vector(3 downto 0));

END COMPONENT;

END ex6_pkg;

Exercise 6 Solution: Top Level File - ex6.vhd

LIBRARY ieee;


6 (

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load, clock, reset : IN std_logic;

enr, enc : IN std_logic;

data : IN std_logic_vector(3 downto 0);

count : BUFFERstd_logic_vector(3 downto 0));END ex6;

USE work.ex6_pkg.ALL; -- get access to your components

ARCHITECTURE ex6_arch OF ex6 IS

SIGNAL regout : std_logic_vector(3 downto 0); -- internal bus

SIGNAL peqq : std_logic; -- internal net

SIGNAL not_peqq : std_logic; -- internal net

Exercise 6 Solution :Top Level File - ex6.vhd

BEGIN

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U1: count4 PORT MAP (din=>data, ld=>load, enc=>not_peqq,

clk=>clock, rst=>reset, q=>count);

U2: reg4 PORT MAP (din=>data, enr=>enr, clk=>clock,

q=>regout);

U3: comp4 PORT MAP (p=>count, q=>regout, peqq=>peqq);

not_peqq

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Your Design (VHDL)

LIBRARY ieee;

USE ieee.std_logic_1164..

USE work.ex6_pkg.all

Library (Compiled)

ieee

Library (Compiled)

work

Packages (VHDL) Others (VHDL)

std_logic

type

definitions

reg4.vhd

Components(VHDL)Packages (VHDL)

std_logic_1164

ex6_pkg.vhd

count4reg4

comp4

comp4.vhd

count4.vhd

Creating repetitive structures

e.g., a 32-bit serial to parallel converter:

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reset

si

clock

q(31) q(30) q(29) q(1) q(0)

po(31) po(30) po(29) po(0)po(1)

The GENERATE statement Used to specify repetitive or conditional execution of

a set of concurrent statements

Useful for instantiating arrays of componentsUSE WORK.rtlpkg.ALL; -- User-defined package containing dsrff

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USEWORK.rtlpkg.ALL; User defined package containing dsrffENTITY sipo IS PORT (

clk, reset: IN std_logic;si: IN std_logic;po: BUFFERstd_logic_vector(31 DOWNTO 0));

END sipo;

ARCHITECTURE arch_sipo OF sipo ISSIGNAL p_temp: std_logic_vector(31 DOWNTO 0);SIGNALzero: std_logic := 0;BEGIN

gen: FORi IN 0 TO 30 GENERATEnxt: dsrff PORT MAP (p_temp(i+1), zero, reset, clk, p_temp(i));

END GENERATE;

beg: dsrff PORT MAP (si, zero, reset, clk, p_temp(31));po

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SIGNAL int_count: std_logic_vector(7 DOWNTO 0);BEGIN

cnt: PROCESS (clk)BEGIN

IF RISING_EDGE(clock) THENIF ld = '1' THEN int_count

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Output

Enable

Controller

DRAM

Controller

DRAM BANK DDRAM BANK C

Exercise #7: The FSM chart Use the following FSM chart:

IDLE

OE=1111

RESETRAM

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CHOOSE

OE=1111

BANK A

OE=1110

BANK B

OE=1101

BANK C

OE=1011

BANK D

OE=0111

EOC EOC EOC

/EOC

EOC

/RAM

/A3 AND /A2 /A3 AND A2 A3 AND /A2 A3 AND A2


The target device is a CY7C371I-143JC

Use a synchronous reset Decode the outputs in parallel with the next state

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p p

Compile and synthesize your design using Warp

Determine the maximum frequency of operationusing the report file

Exercise #7: Solution

ENTITY ex7 ISPORT (clk, reset: IN std_logic;ram, eoc: IN std_logic;a3a2: IN std_logic_vector(1 DOWNTO 0) ;oe: OUT std logic vector(3 DOWNTO 0));

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oe: OUT std_logic_vector(3 DOWNTO 0));END ex7;


TYPE oe_states IS (idle, choose, banka, bankb, bankc, bankd);ATTRIBUTE state_encoding OF oe_states : TYPEIS gray ;SIGNAL present_state, next_state : oe_states ;SIGNAL oe_out : std_logic_vector(3 DOWNTO 0) ;

BEGIN

Exercise #7: Solution (contd.)fsm: PROCESS (clk)BEGIN

IF RISING_EDGE(clock) THENIF reset = '1' THEN

next_state IF ram = '0'

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WHEN idle > IF ram 0THEN next_state next_state next_state next_state next_state next_state IF eoc = '1'

THEN next_state

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_ENDIF ;

WHEN bankc => IF eoc = '1'THEN next_state

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WHEN bankb > oe_out < 1101 ;WHEN bankc => oe_out oe_out oe_out

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Warp user-defined attributes are used as synthesisdirectives to the compiler. These include:

state_encoding

enum_encoding

pin_numbers

synthesis_off

The state_encoding attribute

This is used to specify the state encoding scheme of the FSMs

in a VHDL file.

The default scheme for CPLDs issequential.

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q

Other schemes such as one_hot_one,one_hot_zero andgrayencodings are available.

TYPE state_type IS (idle,state1,state2,state3);

ATTRIBUTE state_encoding OF state_type: TYPE IS sequential;

The enum_encoding Attribute

Used to specify the exact internal encoding to be use for

each value of a user-defined enumerated type.

Overrides state encoding in same description.

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_ g p

TYPE states IS (idle,state1,state2,state3);

ATTRIBUTE enum_encoding OF states: TYPE IS "11 01 00 10";

Thepin_numbers attribute

Used to map the external signals of an entity to the

pins on the target device

Allows the back-annotation of pin placements

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LIBRARY ieee;


ENTITY counter IS PORT (clock, reset: IN std_logic;

count: OUT std_logic_vector(3 DOWNTO 0)

);

ATTRIBUTE pin_numbers OF counter:ENTITY IS

"clock:13 reset:2" &

" count(3):3 count(2):4 count(1):5 count(0):6";

END counter;

p pafter synthesis, e.g.,

The synthesis_off attribute

Controls the flattening and factoring of signals

Makes the signal a factoring point

Useful when a signal with a large number of product

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Useful when a signal with a large number of productterms is used in other equations

Helpful in cases where substitution causes

unacceptable compile time (due to exponentiallyincreasing CPU and memory requirements)

Achieves more efficient implementation

Should only be used on combinatorial equations

Registered equations are natural factoring points

synthesis_off: CPLD Example

An 8-bit comparator controlling a 4-bit, 2-to-1

multiplexer

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a(3 DOWNTO 0)

b(3 DOWNTO 0)

x(3 DOWNTO 0)

c(7 DOWNTO 0)

d(7 DOWNTO 0)

mux

8-bit

compare

Without synthesis_off

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;ENTITY mux IS PORT (

a, b: IN std_logic_vector(3 DOWNTO 0);

An implementation (without synthesis_off)

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Resources used: 1092 product terms, 68 sum splits,72 macrocells - the comparison is not done on a bit

by bit basis

c, d: IN std_logic_vector(7 DOWNTO 0);

x: OUT std_logic_vector(3 DOWNTO 0));

END mux;

ARCHITECTURE archmux OF mux ISBEGIN

x

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+ a /c_3 /c_2 c_1 /c_0 /d_3 /d_2 d_1 /d_0+ a * c_3 * c_2 * /c_1 * /c_0 * d_3 * d_2 * /d_1 * /d_0+ a * /c_3 * c_2 * /c_1 * /c_0 * /d_3 * d_2 * /d_1 * /d_0+ a * c_3 * /c_2 * /c_1 * /c_0 * d_3 * /d_2 * /d_1 * /d_0+ a * /c_3 * /c_2 * /c_1 * /c_0 * /d_3 * /d_2 * /d_1 * /d_0

+ a * c_3 * c_2 * c_1 * c_0 * d_3 * d_2 * d_1 * d_0+ a * /c_3 * c_2 * c_1 * c_0 * /d_3 * d_2 * d_1 * d_0+ a * c_3 * /c_2 * c_1 * c_0 * d_3 * /d_2 * d_1 * d_0+ a * /c_3 * /c_2 * c_1 * c_0 * /d_3 * /d_2 * d_1 * d_0+ a * c_3 * c_2 * /c_1 * c_0 * d_3 * d_2 * /d_1 * d_0+ a * /c_3 * c_2 * /c_1 * c_0 * /d_3 * d_2 * /d_1 * d_0+ a * c_3 * /c_2 * /c_1 * c_0 * d_3 * /d_2 * /d_1 * d_0+ a * /c_3 * /c_2 * /c_1 * c_0 * /d_3 * /d_2 * /d_1 * d_0

/x0 =/S_1.CMB * /S_2.CMB

With synthesis_off

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;ENTITY mux IS PORT (a, b: IN std_logic_vector(3 DOWNTO 0);c, d: IN std logic vector(7 DOWNTO 0);

A better implementation (with synthesis_off)

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Resources used: 24 product terms, 1 partial result, 5macrocells

, _ g _ ( );x: OUT std_logic_vector(3 DOWNTO 0));

END mux;

ARCHITECTURE archmux OF mux IS

SIGNAL sel: std_logic;ATTRIBUTE synthesis_off OF sel:SIGNAL is TRUE;

BEGINsel

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x_2 /sel.CMB b_2 + sel.CMB a_2

x_1 = /sel.CMB * b_1 + sel.CMB * a_1

x_0 = /sel.CMB * b_0 + sel.CMB * a_0

/sel = c_0 * /d_0 + /c_0 * d_0 + c_1 * /d_1 + /c_1 * d_1

+ c_2 * /d_2 + /c_2 * d_2 + c_3 * /d_3 + /c_3 * d_3

+ c_4 * /d_4 + /c_4 * d_4 + c_5 * /d_5 + /c_5 * d_5

+ c_6 * /d_6 + /c_6 * d_6 + c_7 * /d_7 + /c_7 * d_7

CPLD Synthesis Directives

Some Warp synthesis directives only apply to CPLDarchitectures, e.g.,

Floor planning

lab_force

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node_num

pin_avoid

Product Term distribution sum_split

Speed/Power/Edge rates

slew_rate

low_power

The lab_force Attribute

Forces signals into specific logic blocks in CPLDs

Should be used sparingly as it restricts the fitter

First example below forces signal to upper half of

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logic block A.

Second example forces signal to lower half of logic

block B

ATTRIBUTE lab_force OFmysig1: SIGNAL IS A1;

ATTRIBUTE lab_force OFmysig2: SIGNALIS B2;

The node_num Attribute

Used to specify internal location for a signal in a CPLD

Allows signals to be manually allocated to aspecific macrocell location

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May be used to improve product-term allocation

Example: to assign a signal to the first buried

macrocell in a CY7C372:ATTRIBUTE node_num OF buried:SIGNAL IS 202;

More restrictive than lab_force

Can be used with SPLDs too

The pin_avoid Attribute

Instructs Warp to leave specified pins unused

Useful for avoiding ISRTM pins on FLASH370idevices with dual-function pins

C ld l b d i f l

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Could also be used to reserve pins for later use

ATTRIBUTE pin_avoid OF mydesign: ENTITY IS "21 24 26";

The sum_split Attribute

Sum splitting occurs in FLASH370 when a signal's

equation requires more than 16 product terms Two types of sum splitting

B l d (d f lt)

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Balanced (default)

More reliable timing for combinatorial signals

Uses more macrocells Cascaded

ATTRIBUTE sum_split OF mysig:SIGNALIS balanced ;

ATTRIBUTE sum_split OF mysig:SIGNALIS cascaded ;

Balanced Sum Splitting

All inputs arrive at same time

Buried Macrocell #1

16 PTs S_1

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Buried Macrocell #2

PIM

6 PTsS_2

Output = S_1 + S_22 PTs

Cascaded Sum Splitting

Other inputs arrive before S_1

If output combinatorial, it may be unstable

Buried Macrocell16 PTs

S_1

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Output = S_1 + ...

PIM6 PTs

7 PTs

The low_power attribute

The low power directive can be used to lower the power

consumption in a logic block(s) by 50%. As a result, the logicblock(s) slows down by 5 ns. This directive is valid only forthe Ultra37000 family of CPLDs.

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In VHDL, use the following syntax.ATTRIBUTE low_power OF entity_name: ENTITY IS b g e;

In Verilog, use the following syntax.ATTRIBUTE low_power OF module_name:MODULE IS b g e;

The slew_rate attribute

The slew_rate directive can be used to control the output slew

rate of individual pins. This directive is valid only for theUltra37000 family of CPLDs.

Legal values for the slew rate directive are fast and slow.

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ega va ues o e s ew_ a e d ec ve a e as a d s ow.

A value of fast sets the output slew rate to 3V/ns.

A value of slow sets the output slew rate to 1V/ns.

ATTRIBUTE slew_rate OF sig_name: SIGNAL IS fast;

Warp2/Warp3/Programming

Schematic Text/FSM

Synthesis

Simulation

Design

Entry

Design

FrontEnd

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Fitting

Sim. Model

Design

Compilation

Back

EndDesign

Verification

ISR/Impulse3

Simulator

JEDEC

JAM file

CAE Bolt-in Tools

-

Viewlogic Workview Plus/Powerview/WorkView Office- Mentor (CY3144), Cadence (Q4)

Synthesis Tools

Third Party Tool Support

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- Synopsys, Exemplar

PLD Development Tools

- Data I/O Abel 4/5/6 and Synario, CUPL, LOG/iC, OrCAD

Simulation Tools

- LMG SmartModels

- All VHDL and Verilog Simulators (with timing)

In System Reprogrammability ISRTM is the ability to program or reprogram a device after it

has been soldered to the board

Must be able to retain pin-out and timing to be useful CPLD architecture is the key here(Routability/Timing)

Advantages of ISR

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PC Parallel portISR connector

Advantages of ISR

Reduce device handling

Ease prototyping

Enable field upgrades

Improve manufacturing efficiency

Top Three Issues with ISR

#1: Large file sizes

120KB to 22 MB for a 256-macrocell device

complicates production

impractical for field upgrades

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#2: No Software Standard

Beyond JTAG, each approach is different

Confusing file formats

Solutions are vendor and platform-specific

#3: Long Programming Times

Time is money

Programming can take several minutes on some equipment

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