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MINISTERE DE L'ENSEIGNEMENT SUPERIEUR ET DE LA RECHERCHE SCIENTIFIQUE ECOLE NATIONALE SUPERIEURE D’INFORMATIQUE TP strm_2 Année Universitaire : 20010/2011 Quelques d’exercices en vhdl Présenté par : BENYAGOUB MOHAMED 3siq groupe 3

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MINISTERE DE L'ENSEIGNEMENT SUPERIEUR ET DE LA RECHERCHE SCIENTIFIQUE

ECOLE NATIONALE SUPERIEURE DINFORMATIQUE TP strm_2 Anne Universitaire: 20010/2011

Quelques dexercices en vhdlPrsent par :

BENYAGOUB MOHAMED 3siq groupe 3

Exercice 01 Ecrire en VHDL la modlisation du circuit hexa(7 segments. Solution: library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity Dec7Seg is Port ( x : in STD_LOGIC_VECTOR (3 downto 0); sig : out STD_LOGIC_VECTOR (6 downto 0)); end Dec7Seg; architecture arch_Dec7Seg of Dec7Seg is begin sig


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