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VHDL Development VHDL Development for ELEC7770 VLSI Project for ELEC7770 VLSI Project Chris Erickson Chris Erickson Graduate Student Graduate Student Department of Electrical and Computer Department of Electrical and Computer Engineering Engineering Auburn University, Auburn, AL 36849 Auburn University, Auburn, AL 36849 [email protected] [email protected]

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Page 1: VHDL Development for ELEC7770 VLSI Project Chris Erickson Graduate Student Department of Electrical and Computer Engineering Auburn University, Auburn,

VHDL Development VHDL Development for ELEC7770 VLSI Projectfor ELEC7770 VLSI Project

Chris EricksonChris EricksonGraduate StudentGraduate Student

Department of Electrical and Computer EngineeringDepartment of Electrical and Computer EngineeringAuburn University, Auburn, AL 36849Auburn University, Auburn, AL 36849

[email protected]@auburn.edu

Page 2: VHDL Development for ELEC7770 VLSI Project Chris Erickson Graduate Student Department of Electrical and Computer Engineering Auburn University, Auburn,

ObjectivesObjectives

Logically perform the designed functionsLogically perform the designed functions

Be efficientBe efficient– Code lengthCode length– RoutinesRoutines– Signal utilizationSignal utilization

Perform the functions appropriately per Perform the functions appropriately per cyclecycle

Page 3: VHDL Development for ELEC7770 VLSI Project Chris Erickson Graduate Student Department of Electrical and Computer Engineering Auburn University, Auburn,

Component DevelopmentComponent Development

All components designed & developed All components designed & developed independentlyindependently

Instruction RegisterInstruction Register

Program CounterProgram Counter

Register FileRegister File

Data RegisterData Register

MultiplexersMultiplexers

Test RSTest RSTest RTTest RT

Test RDTest RDTest RegWriteTest RegWrite

Register Register FileFile

BB

AA

Page 4: VHDL Development for ELEC7770 VLSI Project Chris Erickson Graduate Student Department of Electrical and Computer Engineering Auburn University, Auburn,

Multicycle DatapathMulticycle Datapath

Cycles per instruction (CPI):Cycles per instruction (CPI): Load WordLoad Word 55

Store WordStore Word 44

Register-typeRegister-type 44

BranchBranch 33

JumpJump 33

Page 5: VHDL Development for ELEC7770 VLSI Project Chris Erickson Graduate Student Department of Electrical and Computer Engineering Auburn University, Auburn,

3 to 5 Cycles per instruction3 to 5 Cycles per instructionStepStep R-typeR-type

(4 cycles)(4 cycles)

Mem. Ref.Mem. Ref.

(4 or 5 cycles)(4 or 5 cycles)

Branch Branch typetype

(3 cycles)(3 cycles)

J-typeJ-type

(3 cycles)(3 cycles)

Instruction Instruction fetchfetch

IR ← Memory[PC]; PC ← PC+1IR ← Memory[PC]; PC ← PC+1

Instruction Instruction decode/ decode/

Register fetchRegister fetch

A ← Reg(IR[25-21]); B ← Reg(IR[20-16])A ← Reg(IR[25-21]); B ← Reg(IR[20-16])

Execution, Execution, Branch & Branch &

Jump Jump completioncompletion

ALUOut ←ALUOut ←

A op BA op B

ALUOut ←ALUOut ←

A+sign extendA+sign extend

IR[15-0]IR[15-0]

If (A=B)If (A=B)

thenthen

PC←ALUOutPC←ALUOut

PC←PC[31-26] PC←PC[31-26] & IR[25-0]& IR[25-0]

Mem. Access Mem. Access or R-type or R-type

completioncompletion

Reg(IR[15-11]) Reg(IR[15-11]) ← ALUOut← ALUOut

MDR←M[ALUout] or MDR←M[ALUout] or M[ALUOut]←BM[ALUOut]←B

Memory read Memory read completioncompletion

Reg(IR[20-16]) ← Reg(IR[20-16]) ← MDRMDR

Page 6: VHDL Development for ELEC7770 VLSI Project Chris Erickson Graduate Student Department of Electrical and Computer Engineering Auburn University, Auburn,

Control FSMControl FSM

Instruction decode

ALU operation

Write PC on branch condition

Write memory

data

Write PC on jump

Write register

Read memory

data

Instruction fetch

Compute memory

addr.

Write register

lw or sw

lw

sw

RB

J

Start

State 0 1

23

4 5

6

7

8 9

Page 7: VHDL Development for ELEC7770 VLSI Project Chris Erickson Graduate Student Department of Electrical and Computer Engineering Auburn University, Auburn,

CodeCode

Initialize, set state = 0Initialize, set state = 0If state = 0 thenIf state = 0 thenSet state 0 signalsSet state 0 signalsSet state = 1 for next clock cycleSet state = 1 for next clock cycleIf state = 1 thenIf state = 1 thenSet state 1 signalsSet state 1 signalsSet state = 2 for next clock cycleSet state = 2 for next clock cycleIf state = 2, depending on opcode, we will either If state = 2, depending on opcode, we will either go down path of register-type, load word, store go down path of register-type, load word, store word, branch, or jump instruction.word, branch, or jump instruction.

Page 8: VHDL Development for ELEC7770 VLSI Project Chris Erickson Graduate Student Department of Electrical and Computer Engineering Auburn University, Auburn,

Cycle BoundariesCycle Boundaries

Multiplexers are handled at the end of Multiplexers are handled at the end of each cycleeach cycle

Multiplexer outputs serve as “variables” to Multiplexer outputs serve as “variables” to be used as inputs for the next clock cyclebe used as inputs for the next clock cycle

Either a multiplexer or another stand-alone Either a multiplexer or another stand-alone component must have a steady-state component must have a steady-state output to serve as input for the next cycleoutput to serve as input for the next cycle

Page 9: VHDL Development for ELEC7770 VLSI Project Chris Erickson Graduate Student Department of Electrical and Computer Engineering Auburn University, Auburn,

Multicycle DatapathMulticycle DatapathP

C

Inst

r. r

eg

. (IR

)

Me

m. D

ata

(M

DR

)

AL

UO

ut

Re

g.

A R

eg

.B

Re

g.

A

LU

Re

gis

ter

file

Mem

ory

Ad

dr.

Data

1

Sign extend

Shift left 2

Opcode

31-25

0-15

20-1625-21

Shift left 225-0

28-31

15

-11

Page 10: VHDL Development for ELEC7770 VLSI Project Chris Erickson Graduate Student Department of Electrical and Computer Engineering Auburn University, Auburn,

Completed !!Completed !!

Any Question? Comments? Any Question? Comments?


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