vhdl codes for mips instructions lw,sw,beq,bne,j,jal,lui,add,addi,or,ori,slt,nor,and,exceptions
TRANSCRIPT
VHDL Code for ALU
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY alu IS
PORT(
a, b : IN STD_ULOGIC_VECTOR(31 DOWNTO 0);
aluctl : IN STD_ULOGIC_VECTOR(3 DOWNTO 0);
aluresult : OUT STD_ULOGIC_VECTOR(31 DOWNTO 0);
zero : OUT STD_ULOGIC);
END alu;
ARCHITECTURE behavioral OF alu IS
BEGIN
PROCESS(a, b, aluctl)
VARIABLE a_u : UNSIGNED(31 DOWNTO 0);
VARIABLE b_u : UNSIGNED(31 DOWNTO 0);
VARIABLE result_u : UNSIGNED(31 DOWNTO 0);
VARIABLE zero_u : UNSIGNED(0 DOWNTO 0);
BEGIN
a_u := UNSIGNED(a);
b_u := UNSIGNED(b);
result_u := (OTHERS => '0');
zero_u(0) := '0';
CASE aluctl IS
WHEN "0000" =>result_u := a_u AND b_u;--and
WHEN "0001" =>result_u := a_u OR b_u; --or
WHEN "0010" =>result_u := a_u + b_u;--add
WHEN "0110" =>result_u := a_u - b_u;--sub
WHEN "0111" =>result_u := a_u - b_u;--slt
IF SIGNED(result_u) < 0 THEN
result_u := TO_UNSIGNED(1, result_u'LENGTH);
ELSE
result_u := (OTHERS => '0');
END IF;
WHEN "1100"=>result_u:=(a_u nor b_u);--nor
WHEN OTHERS => result_u := (OTHERS => 'X');
END CASE;
IF TO_INTEGER(result_u) = 0 THEN
zero_u(0) := '1';
ELSE
zero_u(0) := '0';
END IF;
aluresult <= STD_ULOGIC_VECTOR(result_u);
zero <= zero_u(0);
END PROCESS;
END behavioral;
VHDL Code for ALU Control
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY ALUControl IS
PORT (
Funct : IN std_ulogic_vector(5 downto 0);
ALUOp : IN std_ulogic_vector(1 downto 0);
ALUCtl : OUT std_ulogic_vector(3 downto 0)
);
END ALUControl;
ARCHITECTURE behavioural OF ALUControl IS
BEGIN
PROCESS( Funct, ALUOp)
BEGIN
case ALUOp is
when "00" => ALUCtl <= "0010"; --for lw,sw,addi
when "01" => ALUCtl <= "0110"; --for beq,bne
when "10" =>
case Funct is
when "100100" => ALUCtl <= "0000"; --and
when "100101" => ALUCtl <= "0001"; --or
when "100000" => ALUCtl <= "0010"; --add
when "100010" => ALUCtl <= "0110"; --sub
when "101010" => ALUCtl <= "0111"; --slt
when "100111" => ALUCtl <= "1100"; --nor
when others => ALUCtl <= "1111";
end case;
When "11" => AluCtl <="0001"; --For ori
when others => ALUCtl <= "1111";
end case;
END PROCESS;
END behavioural;
VHDL Code for Execution Stage including ALU and ALU
Control
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY executionstage IS
PORT(
instruction25_21 : IN std_ulogic_vector(4 downto 0);
instruction20_16 : IN std_ulogic_vector(4 downto 0);
instruction15_0 : IN std_ulogic_vector(15 downto 0);
ALUSrcA : IN std_ulogic;
ALUSrcB : IN std_ulogic_vector(1 downto 0);
ALUOp : IN std_ulogic_vector(1 downto 0);
reg_A, reg_B : IN std_ulogic_vector(31 downto 0);
PCout : IN std_ulogic_vector(31 downto 0);
instruction15_0SignExtend : IN std_ulogic_vector(31 downto 0);
instruction15_0SE_SL:IN std_ulogic_vector(31 downto 0);
jump : OUT std_ulogic_vector(31 downto 0);
alu_result : OUT std_ulogic_vector(31 downto 0);
zero : OUT std_ulogic
);
END executionstage;
ARCHITECTURE behavioural OF executionstage IS
COMPONENT alu
PORT(
a, b : IN STD_ULOGIC_VECTOR(31 DOWNTO 0);
aluctl : IN STD_ULOGIC_VECTOR(3 DOWNTO 0);
aluresult: OUT STD_ULOGIC_VECTOR(31 DOWNTO 0);
zero : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT ALUControl
PORT (
Funct : IN std_ulogic_vector(5 downto 0);
ALUOp : IN std_ulogic_vector(1 downto 0);
ALUCtl : OUT std_ulogic_vector(3 downto 0)
);
END COMPONENT;
SIGNAL mux_A_out : std_ulogic_vector(31 downto 0);
SIGNAL mux_B_out : std_ulogic_vector(31 downto 0);
SIGNAL ALUctl : std_ulogic_vector(3 downto 0);
BEGIN
alu_inst: alu
PORT MAP (
a => mux_A_out,
b => mux_B_out,
aluctl => ALUctl,
aluresult => alu_result,
zero => zero
);
alu_control:ALUControl
PORT MAP(
Funct=>instruction15_0(5 downto 0),
ALUOp=>ALUOp,
ALUCtl=> ALUctl
);
-- Multiplexor for ALU input A:
mux_A : PROCESS (ALUSrcA, PCout, reg_A)
BEGIN
CASE ALUSrcA IS
WHEN '0' => mux_A_out <= PCout;
WHEN '1' => mux_A_out <= reg_A;
WHEN OTHERS => mux_A_out <= (OTHERS => 'X');
END CASE;
END PROCESS;
-- Multiplexor for AlU input B:
mux_B : PROCESS(ALUSrcB)
BEGIN
CASE ALUSrcB IS
WHEN "00"=>mux_B_out<= reg_B;
WHEN "01"=>mux_B_out<= STD_ULOGIC_VECTOR(TO_UNSIGNED(4, 32));
--constant 4
WHEN "10" => mux_B_out <= instruction15_0SignExtend;
WHEN "11" => mux_B_out <= instruction15_0SE_SL;
WHEN OTHERS => mux_B_out <= (OTHERS => 'X');
END CASE;
END PROCESS;
-- Computation of Jump Address:
Process (instruction25_21,instruction20_16,instruction15_0)
VARIABLE instruction25_0:STD_ULOGIC_VECTOR(25 DOWNTO 0) ;
BEGIN
instruction25_0:=instruction25_21&instruction20_16&instruction15_0;
jump<=PCout(31 downto 28)&instruction25_0&"00";
END PROCESS;
END behavioural;
VHDL Code for Register File
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY registerfile IS
PORT (
clk,reset: IN std_ulogic;
Regwrite : IN std_ulogic;
writedata : IN std_ulogic_vector(31 DOWNTO 0);
writeregister :IN std_ulogic_vector(4 DOWNTO 0);
readregister1 :IN std_ulogic_vector(4 DOWNTO 0);
readregister2 :IN std_ulogic_vector(4 DOWNTO 0);
readdata1 :OUT std_ulogic_vector(31 DOWNTO 0);
readdata2 :OUT std_ulogic_vector(31 DOWNTO 0)
);
END registerfile;
ARCHITECTURE behavioral OF registerfile IS
SUBTYPE WordT IS std_ulogic_vector(31 DOWNTO 0); -- reg word TYPE
TYPE StorageT IS ARRAY(0 TO 31) OF WordT; --reg array
SIGNAL registerfile : StorageT; -- reg file contents
BEGIN
-- perform write operation
PROCESS(reset, clk)
BEGIN
IF reset = '0' THEN
FOR i IN 0 TO 31 LOOP
registerfile(i) <= (OTHERS => '0');
END LOOP;
ELSIF (clk'event and clk='1') THEN
IF Regwrite = '1' THEN
registerfile(to_integer(unsigned(writeregister)))<=writedata;
END IF;
END IF;
END PROCESS;
readdata1 <= registerfile(to_integer(unsigned(readregister1)));
readdata2 <= registerfile(to_integer(unsigned(readregister2)));
END behavioral;
VHDL Code for 32 bit Register used to implement
registers like A,B,ALUOut and MDR
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY register32 IS
PORT (
clk : IN STD_ULOGIC;
reset : IN STD_ULOGIC;
reginput : IN STD_ULOGIC_VECTOR(31 DOWNTO 0);
regoutput : OUT STD_ULOGIC_VECTOR(31 DOWNTO 0)
);
END register32;
ARCHITECTURE behavioral OF register32 IS
BEGIN
PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
regoutput <= (OTHERS => '0');
ELSIF (clk' event and clk='1') THEN
regoutput <= reginput;
END IF;
END PROCESS;
END behavioral;
VHDL Code for Decode Stage including Registers A and B
and Register File
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY decodestage IS
PORT (
clk : IN STD_ULOGIC;
reset : IN STD_ULOGIC;
instr_25_21 : IN STD_ULOGIC_VECTOR(4 DOWNTO 0);
instr_20_16 : IN STD_ULOGIC_VECTOR(4 DOWNTO 0);
instr_15_0 : IN STD_ULOGIC_VECTOR(15 DOWNTO 0);
MDR : IN STD_ULOGIC_VECTOR(31 DOWNTO 0);
alu_out : IN STD_ULOGIC_VECTOR(31 DOWNTO 0);
PCplus4:IN STD_ULOGIC_VECTOR(31 DOWNTO 0);
ShiftRight:IN STD_ULOGIC_VECTOR(31 DOWNTO 0);
ShiftLeft :IN STD_ULOGIC_VECTOR(31 DOWNTO 0);
RegDst : IN STD_ULOGIC_VECTOR(1 DOWNTO 0);
RegWrite : IN STD_ULOGIC;
MemtoReg : IN STD_ULOGIC_VECTOR(2 DOWNTO 0);
reg_A : OUT STD_ULOGIC_VECTOR(31 DOWNTO 0);
reg_B : OUT STD_ULOGIC_VECTOR(31 DOWNTO 0);
instr_15_0_se : OUT STD_ULOGIC_VECTOR(31 DOWNTO 0);
instr_15_0_se_sl : OUT STD_ULOGIC_VECTOR(31 DOWNTO 0)
);
END decodestage;
ARCHITECTURE behavioral OF decodestage IS
COMPONENT registerfile IS
PORT (
clk,reset : IN std_ulogic;
registerwrite : IN std_ulogic; -- control
writedata : IN std_ulogic_vector(31 DOWNTO 0);
writeregister : IN std_ulogic_vector(4 DOWNTO 0);
readregister1 : IN std_ulogic_vector(4 DOWNTO 0);
readregister2 : IN std_ulogic_vector(4 DOWNTO 0);
readdata1 : OUT std_ulogic_vector(31 DOWNTO 0);
readdata2 : OUT std_ulogic_vector(31 DOWNTO 0)
);
END COMPONENT;
COMPONENT register32 IS
PORT (
clk : IN STD_ULOGIC;
reset : IN STD_ULOGIC;
reg_in : IN STD_ULOGIC_VECTOR(31 DOWNTO 0);
reg_out : OUT STD_ULOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
SIGNAL write_reg : STD_ULOGIC_VECTOR(4 DOWNTO 0);
SIGNAL write_data : STD_ULOGIC_VECTOR(31 DOWNTO 0);
SIGNAL data_1 : STD_ULOGIC_VECTOR(31 DOWNTO 0);
SIGNAL data_2 : STD_ULOGIC_VECTOR(31 DOWNTO 0);
SIGNAL ShiftLeft16out :STD_ULOGIC_VECTOR(31 DOWNTO 0);
BEGIN
A : register32
PORT MAP (
clk => clk,
reset => reset,
reg_in => data_1,
reg_out => reg_A
);
B : register32
PORT MAP (
clk => clk,
reset => reset,
reg_in => data_2,
reg_out => reg_B
);
inst_regfile : registerfile
PORT MAP (
clk => clk,
reset => reset,
registerwrite => RegWrite,
writedata => write_data,
writeregister => write_reg,
readregister1 => instr_25_21,
readregister2 => instr_20_16,
readdata1 => data_1,
readdata2 => data_2 );
-- multiplexer for write register
write_reg <= instr_20_16 WHEN RegDst = "00"-- select rt
ELSE
instr_15_0(15 DOWNTO 11) WHEN RegDst = "01"-- select rd
Else
STD_ULOGIC_VECTOR(TO_UNSIGNED(31,5)) WHEN RegDst="10"--$ra for jal
ELSE
(OTHERS => 'X');
-- multiplexer for write data
write_data <= alu_out WHEN MemtoReg = "000" --R-type
ELSE
MDR WHEN MemtoReg = "001"--LW
ELSE
PCplus4 WHEN MemtoReg ="010"--JAL
ELSE
ShiftLeft16out WHEN MemtoReg ="011"--LUI
ELSE
ShiftRight WHEN MemtoReg ="100"--SRL
ELSE
ShiftLeft WHEN MemtoReg = "101"--SLL
ELSE
(OTHERS => 'X');
PROCESS(instr_15_0)
-- variables needed for reading result of sign extension
VARIABLE temp_instr_15_0_se : STD_ULOGIC_VECTOR(31 DOWNTO 0);
VARIABLE temp_instr_15_0_se_sl : STD_ULOGIC_VECTOR(31 DOWNTO 0);
BEGIN
-- sign extend instr_15_0 to 32 bits
temp_instr_15_0_se := STD_ULOGIC_VECTOR(RESIZE(SIGNED(instr_15_0),
instr_15_0_se'LENGTH));
-- shift left 2
temp_instr_15_0_se_sl := temp_instr_15_0_se(29 DOWNTO 0) & "00";
ShiftLeft16out<=temp_instr_15_0_se(15 DOWNTO 0)&"0000000000000000";
--in above line we calculated value for lui instruction
instr_15_0_se <= temp_instr_15_0_se;
instr_15_0_se_sl <= temp_instr_15_0_se_sl;
END PROCESS;
END behavioral;
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
VHDL Code for 32 bit Register used as PC,EPC and Cause
Register
ENTITY pc IS
PORT (
clk : IN STD_ULOGIC;
reset : IN STD_ULOGIC;
pcinput : IN STD_ULOGIC_VECTOR(31 DOWNTO 0);
PCena : IN STD_ULOGIC;
pcout : OUT STD_ULOGIC_VECTOR(31 DOWNTO 0)
);
END pc;
ARCHITECTURE behavioral OF pc IS
BEGIN
PROCESS(clk, reset)
VARIABLE pc : STD_ULOGIC_VECTOR(31 DOWNTO 0);
BEGIN
IF reset = '0' THEN
pc := (OTHERS => '0');
ELSIF (clk'event and clk='1') THEN
IF PCena = '1' THEN
pc := pcinput;
END IF;
END IF;
pcout <= pc;
END PROCESS;
END behavioral;
VHDL Code for Writeback and Exception Stage Combined
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY writebackexception IS
PORT (
clk, reset : IN std_ulogic;
EPCWrite : IN std_ulogic;
jumpaddress : IN std_ulogic_vector(31 downto 0);
alu_result : IN std_ulogic_vector(31 downto 0);
PCSource : IN std_ulogic_vector(2 downto 0);
IntCause : IN std_ulogic;
CauseWrite : IN std_ulogic;
registerA : IN std_ulogic_vector(31 downto 0);
pc_in : OUT std_ulogic_vector(31 downto 0);
EPCOut : OUT std_ulogic_vector(31 downto 0);
CauseOUT : OUT std_ulogic_vector(31 downto 0);
alu_out : OUT std_ulogic_vector(31 downto 0)
);
END writebackexception;
ARCHITECTURE behavioral OF writebackexception IS
COMPONENT register32
PORT (
clk : IN STD_ULOGIC;
reset : IN STD_ULOGIC;
reg_in : IN STD_ULOGIC_VECTOR(31 DOWNTO 0);
reg_out : OUT STD_ULOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
COMPONENT pc
PORT(
clk:IN STD_ULOGIC;
reset:IN STD_ULOGIC;
pcinput : IN STD_ULOGIC_VECTOR(31 DOWNTO 0);
PCena : IN STD_ULOGIC;
pcout : OUT STD_ULOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
SIGNAL alu_out_internal,EPCO,causeO,MUXOut : std_ulogic_vector(31 downto 0);
BEGIN
ALUOut: register32
PORT MAP (
clk => clk,
reset => reset,
reg_in => alu_result,
reg_out => alu_out_internal
);
EPC: pc -- EPC register
PORT MAP(
clk=>clk,
reset=>reset,
pcinput=>alu_result,
PCena=>EPCWrite,
pcout=>EPCO
);
cause: pc --cause register
PORT MAP(
clk=>clk,
reset=>reset,
pcinput=>MUXOut,
PCena=>IntCause,
pcout=>causeO
);
-- Multiplexer for pc address selection:
PROCESS (PCSource, alu_result, alu_out_internal, jumpaddress)
BEGIN
CASE PCSource IS
WHEN "000"=>pc_in<=alu_result;--pc+4
WHEN "001"=>pc_in<=alu_out_internal;--beq,bne
WHEN "010"=>pc_in<=jumpaddress;--jump,JAL
WHEN "011"=>pc_in<=STD_ULOGIC_VECTOR(TO_UNSIGNED(80000180,32));
WHEN "100"=>pc_in<=registerA;--JR instruction address
WHEN OTHERS=>pc_in<=(OTHERS => 'X');
END CASE;
END PROCESS;
PROCESS(IntCause)
BEGIN --cause register multiplexer
CASE IntCause IS
WHEN '0'=>MUXOut<=STD_ULOGIC_VECTOR(TO_UNSIGNED(0,32));
WHEN '1'=>MUXOut<=STD_ULOGIC_VECTOR(TO_UNSIGNED(1,32));
WHEN OTHERS=>MUXOut<=(OTHERS=>'X');
END CASE;
END PROCESS;
alu_out <= alu_out_internal;
EPCOut <=EPCO;
CauseOUT<=causeO;
END behavioral;
VHDL Code for Datapath which includes Instruction
decode,Execution and Writeback+Exception Stage
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY datapath IS
PORT (
clk, rst_n,RegWrite : IN std_ulogic;
PCWrite, IorD, IRWrite, ALUSrcA: IN std_ulogic;
ALUSrcB,RegDst : IN std_ulogic_vector(1 downto 0);
PCSource, MemtoReg: IN std_ulogic_vector(2 downto 0);
ALUOp : IN std_ulogic_vector(1 downto 0);--control signal
reg_B : OUT std_ulogic_vector(31 downto 0);--to memory
instr_31_26 : OUT std_ulogic_vector(5 downto 0);--to control
zero : OUT std_ulogic--combining with pc write condional
);
END datapath;
ARCHITECTURE behavioral OF datapath IS
COMPONENT decodestage
PORT (
clk : IN STD_ULOGIC;
rst_n : IN STD_ULOGIC;
instr_25_21 : IN STD_ULOGIC_VECTOR(4 DOWNTO 0);
instr_20_16 : IN STD_ULOGIC_VECTOR(4 DOWNTO 0);
instr_15_0 : IN STD_ULOGIC_VECTOR(15 DOWNTO 0);
MDR : IN STD_ULOGIC_VECTOR(31 DOWNTO 0);
alu_out : IN STD_ULOGIC_VECTOR(31 DOWNTO 0);
RegDst : IN STD_ULOGIC_VECTOR(1 DOWNTO 0);
RegWrite : IN STD_ULOGIC;
MemtoReg : IN STD_ULOGIC_VECTOR(2 DOWNTO 0);
reg_A : OUT STD_ULOGIC_VECTOR(31 DOWNTO 0);
reg_B : OUT STD_ULOGIC_VECTOR(31 DOWNTO 0);
instr_15_0_se : OUT STD_ULOGIC_VECTOR(31 DOWNTO 0);
instr_15_0_se_sl : OUT STD_ULOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
COMPONENT executionstage
PORT (
instr_25_21 : IN std_ulogic_vector(4 downto 0);
instr_20_16 : IN std_ulogic_vector(4 downto 0);
instr_15_0 : IN std_ulogic_vector(15 downto 0);
ALUSrcA : IN std_ulogic;
ALUSrcB : IN std_ulogic_vector(1 downto 0);
ALUOp : IN std_ulogic_vector(1 downto 0);
reg_A, reg_B : IN std_ulogic_vector(31 downto 0);
pc_out : IN std_ulogic_vector(31 downto 0);
instr_15_0_se : IN std_ulogic_vector(31 downto 0);
instr_15_0_se_sl : IN std_ulogic_vector(31 downto 0);
jump_addr : OUT std_ulogic_vector(31 downto 0);
alu_result : OUT std_ulogic_vector(31 downto 0);
zero : OUT std_ulogic
);
END COMPONENT;
COMPONENT writebackexception
PORT (
clk, rst_n : IN std_ulogic;
jump_addr : IN std_ulogic_vector(31 downto 0);
alu_result : IN std_ulogic_vector(31 downto 0);
PCSource : IN std_ulogic_vector(2 downto 0);
pc_in : OUT std_ulogic_vector(31 downto 0);
alu_out : OUT std_ulogic_vector(31 downto 0)
);
END COMPONENT;
SIGNAL pc_in_intern : std_ulogic_vector(31 downto 0);
SIGNAL alu_out_intern : std_ulogic_vector(31 downto 0);
SIGNAL reg_memdata_intern : std_ulogic_vector(31 downto 0);
SIGNAL instr_25_21_intern : std_ulogic_vector(4 downto 0);
SIGNAL instr_20_16_intern : std_ulogic_vector(4 downto 0);
SIGNAL instr_15_0_intern : std_ulogic_vector(15 downto 0);
SIGNAL pc_out_intern : std_ulogic_vector(31 downto 0);
SIGNAL reg_A_intern : std_ulogic_vector(31 downto 0);
SIGNAL reg_B_intern : std_ulogic_vector(31 downto 0);
SIGNAL instr_15_0_se_intern : std_ulogic_vector(31 downto 0);
SIGNAL instr_15_0_se_sl_intern : std_ulogic_vector(31 downto 0);
SIGNAL jump_addr_intern : std_ulogic_vector(31 downto 0);
SIGNAL alu_result_intern : std_ulogic_vector(31 downto 0);
BEGIN
inst_data_decode : decodestage
PORT MAP (
clk => clk,
rst_n => rst_n,
instr_25_21 => instr_25_21_intern,
instr_20_16 => instr_20_16_intern,
instr_15_0 => instr_15_0_intern,
MDR => reg_memdata_intern,
alu_out => alu_out_intern,
RegDst => RegDst,
RegWrite => RegWrite,
MemtoReg => MemtoReg,
reg_A => reg_A_intern,
reg_B => reg_B_intern,
instr_15_0_se => instr_15_0_se_intern,
instr_15_0_se_sl => instr_15_0_se_sl_intern
);
inst_data_execution: executionstage
PORT MAP (
instr_25_21 => instr_25_21_intern,
instr_20_16 => instr_20_16_intern,
instr_15_0 => instr_15_0_intern,
ALUSrcA => ALUSrcA,
ALUSrcB => ALUSrcB,
ALUOp => ALUOp,
reg_A => reg_A_intern,
reg_B => reg_B_intern,
pc_out => pc_out_intern,
instr_15_0_se => instr_15_0_se_intern,
instr_15_0_se_sl => instr_15_0_se_sl_intern,
jump_addr => jump_addr_intern,
alu_result => alu_result_intern,
zero => zero
);
inst_data_memwriteback : writebackexception
PORT MAP (
clk => clk,
rst_n => rst_n,
jump_addr => jump_addr_intern,
alu_result => alu_result_intern,
PCSource => PCSource,
pc_in => pc_in_intern,
alu_out => alu_out_intern
);
reg_B <= reg_B_intern;
END behavioral;