vhdl code for d ff using behavior model - ashwani goyal -...

B.S.ANANGPURIA INSTT. OF TECHNOLOGY MGT.

Name: Prabhjot kaurSubject : Digital System Design(EE-310-E)

Sem: 6th (ECE/CSE)Unit: 4

Sequential Circuit design:

1: Flip-Flopsa.D-FFb.T-FFc.S-R FFd. J-K FF2. Shift Registersa. SISO(Serial In Serial Out)b.SIPO(Serial In Parallel Out)c. PIPO(Parallel In Parallel Out)d. PISO(Parallel In Serial Out)3. Countera. 4-bit Johnson counterb.10-bit ring counterc.4-bit binary counterd. 4-bit decade countere. 3 bit synchronous UP/DOWN counter

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Vhdl code for D FF using behavior modellibrary IEEE;use IEEE.STD_LOGIC_1164.all;

entity dff is port(

d : in STD_LOGIC; pr : in STD_LOGIC; cr : in STD_LOGIC; clk: in std_logic; q : out STD_LOGIC; qbar : out STD_LOGIC

);end dff;

--}} End of automatically maintained section

architecture dff of dff isbegin

process(clk,pr,cr)begin

if (pr='0' and cr='1')thenq <='1';

elsif(pr='1'and cr='0')thenq<='0';

elsif(pr='1' and cr='1' and clk='0' and clk'event)thenq<=d;

qbar<= not d;end if;end process;

-- enter your statements here --

end dff;

Vhdl code for T FF using behavior model

library IEEE;use IEEE.STD_LOGIC_1164.all;

entity tff is port(

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t : in STD_LOGIC; pr : in STD_LOGIC; cr : in STD_LOGIC; clk : in STD_LOGIC; q : inout STD_LOGIC; qbar : out STD_LOGIC

);end tff;


architecture tff of tff isbegin

process(clk,pr,cr)begin

if (pr='0' and cr='1')thenq <='1';

elsif(pr='1'and cr='0')thenq<='0';

elsif(pr='1' and cr='1' and clk='0' and clk'event)thenq<=(not t and q) or (not q and t);

end if;qbar<= not q;end process;

end tff;

Vhdl code for SR FF using behavior model


entity srff is port(

s : in STD_LOGIC; r : in STD_LOGIC; clk : in STD_LOGIC; q : out STD_LOGIC );

end srff;

--}} End of automatically maintained section3

architecture srff of srff isbegin

process(clk,s,r)begin

if (clk='0' and clk'event)thenif (s='0' and r ='0' ) then

q<= 'X';elsif(s='1' and r ='0' ) thenq<= '1';elsif(s='0' and r ='1' ) thenq<= '0';elsif(s='1' and r ='1' ) thenq<= 'X';end if;elseq<= 'X';end if;end process;end srff;

Vhdl code for JK FF using behavior model

entity jkff is port(

j : in STD_LOGIC; k : in STD_LOGIC; clk : in STD_LOGIC; q : out STD_LOGIC ; qbar: out std_logic

);end jkff;


architecture jkff of jkff isbegin

process(clk,j,k)begin

if (clk='0' and clk'event)thenif(j='1' and k ='0' ) then

q<= '1';qbar<= '0';elsif(j='0' and k ='1' ) then

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q<= '0';qbar<= '1';elsif(j='1' and k ='1' ) thenq <= 'X';end if;elseq <= 'X';qbar<='X';end if;end process;

end jkff;

Vhdl code for SISO register using behavior model


entity \siso(dff)\ is port(

d : in STD_LOGIC; clk : in STD_LOGIC; pr : in STD_LOGIC; cr : in STD_LOGIC; z : out STD_LOGIC

);end \siso(dff)\;


architecture \siso(dff)\ of \siso(dff)\ is

signal q0,q1,q2: std_logic;begin

process(clk,cr,pr)begin

if (pr='1' and cr='1' and clk='0' and clk'event) thenq0<= d;q1<= q0;q2<= q1;z<= q2; elsif (pr='0' and cr='1'and clk='0' and clk'event ) thenq0<= '1';q1<= '1';q2<= '1';

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z<= '1';elsif (pr='1' and cr='0'and clk='0' and clk'event ) thenq0<= '0';q1<= '0';q2<= '0';z<= '0';elsif (pr='0' and cr='0' and clk='0' and clk'event) thenq0<= 'X';q1<= 'X';q2<= 'X';z<= 'X';

end if;

end process ;

end \siso(dff)\;

Vhdl code for SIPO register using behavior model


entity sipo is port(

d : in std_logic; cr : in std_logic; pr : in std_logic; clk : in std_logic; q: inout std_logic_VECTOR(3 downto 0)

);end sipo;

architecture sipo of sipo isbegin

process(pr,cr,clk)begin

if(pr='1' and cr='1' and clk='0' and clk'event)thenq(0)<=d;q(1)<=q(0);q(2)<=q(1);q(3)<= q(2);

elsif(pr='1' and cr='0')thenq(0)<='0';q(1)<='0';q(2)<='0';q(3)<= '0';

elsif(pr='0' and cr='1')then6

q(0)<='1';q(1)<='1';q(2)<='1';q(3)<= '1';

elsif(pr='0' and cr='0')then q(0)<='0';

q(1)<='0'; q(2)<='0'; q(3)<= '0';

end if;end process;

end sipo;

Vhdl code for PIPO register using behavior model


entity pipo is port( clk : in STD_LOGIC; pr,cr: in std_logic;

d : in STD_LOGIC_VECTOR(3 downto 0); q : out STD_LOGIC_VECTOR(3 downto 0)

);end pipo;

architecture pipo of pipo isbegin

process( d,clk)BEGIN

if(pr='1' and cr='1' and clk='0' and clk'event)thenq(0)<=d(0);q(1)<=d(1);q(2)<=d(2);q(3)<= d(3);

elsif(pr='1' and cr='0')thenq(0)<='0';q(1)<='0';q(2)<='0';q(3)<= '0';

elsif(pr='0' and cr='1')thenq(0)<='1';q(1)<='1';q(2)<='1';

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q(3)<= '1';elsif(pr='0' and cr='0')then q(0)<='X';

q(1)<='X'; q(2)<='X'; q(3)<= 'X';

end if;end process;

end pipo;

Vhdl code for bi-directional register using behavior model


entity bi_directional is port(

clk : in STD_LOGIC; d : in STD_LOGIC; shift : in STD_LOGIC; q : inout STD_LOGIC_VECTOR( 0 to 3)

);end bi_directional;


architecture bi_directional of bi_directional isbegin

process(clk,d)begin

if(clk='1' and clk'event)thenif(shift='1')then

q(0)<=d;q(1)<=q(0);q(2)<= q(1);q(3)<=q(2);

elsif (shift='0')thenq(3)<= d;q(2)<=q(3);q(1)<=q(2);q(0)<= q(1);

end if;end if;end process;

end bi_directional;

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VHDL code for 4-bit Johnson counter using behavior model.library IEEE;use IEEE.STD_LOGIC_1164.all;

entity counter is port(

clk : in STD_LOGIC; qa,qb,qc,qd : inout STD_LOGIC:='0' );

end counter;


architecture counter of counter isbegin

process(clk)begin

if(clk='1' and clk'event)then qa <= not qd; qb<= qa; qc<=qb; qd<=qc;

end if; end process;end counter;

VHDL code for 10-bit ring counter using behavior model.


entity ring_counter is port(

clk : in STD_LOGIC; q1 : inout STD_LOGIC := '1'; q : inout STD_LOGIC_VECTOR(2 to 10):= "000000000"

);end ring_counter;

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architecture ring_counter of ring_counter isbegin

process(clk)begin

if(clk='1' and clk'event)thenq1<=q(10);q(2)<=q1;q(3)<=q(2);q(4)<=q(3);q(5)<=q(4);q(6)<=q(5);q(7)<=q(6);q(8)<=q(7);q(9)<=q(8);q(10)<=q(9);

end if;end process;

VHDL code for 4-bit binary counter using behavior model.


entity binary_counter is port(

clk : in STD_LOGIC; qa,qb,qc,qd : inout STD_LOGIC:= '0'

);end binary_counter;


architecture binary_counter of binary_counter isbegin

process(clk)begin

if(clk='1' and clk'event)thenqa <= not qa;qb <= qb xor qa;qc<= qc xor (qa and qb);qd<= qd xor (qa and qb and qc);end if;end process;

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end binary_counter;

VHDL code for 4-bit decade counter using behavior model.


entity decade_counter is port(

clk : in STD_LOGIC; qa,qb,qc,qd : inout STD_LOGIC :='0'

);end decade_counter;


architecture decade_counter of decade_counter isbegin

process(clk)begin

if(clk='1' and clk'event)thenqa<= not qa;qb<= qb xor (qa and (not qa));qc<= qd xor ((qa and qd)or (qa and qb and qc));

end if;end process;end decade_counter;

VHDL code for 4-bit synchronous counter using behavior model.


entity sync_up_down is port(

clk,up : in STD_LOGIC; qa,qb,qc,qd : inout STD_LOGIC := '0');

end sync_up_down;


architecture sync_up_down of sync_up_down is11

begin process(clk)beginif (clk='1' and clk'event)then

qa<= not qa;qb<= qb xor ((qa and up)or ((not qa) and (not up)));qc<= qc xor ((qa and qb and up)or ((not qa)and (not qb) and (not up)));

end if;end process;

-- enter your statements here --

end sync_up_down;

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VHDL code for a 4-bit register with a positive-edge clock, asynchronous set and clock enable.

entity flop is port(C, CE, PRE : in std_logic; D : in std_logic_vector (3 downto 0); Q : out std_logic_vector (3 downto 0)); end flop;architecture archi of flop is begin process (C, PRE) begin if (PRE='1') then Q = "1111"; elsif (C'event and C='1')then if (CE='1') then Q = D; end if; end if; end process; end archi;

VHDL code for a 4-bit unsigned Up counter with asynchronous clear .

entity counter is port(C, CLR : in std_logic; Q : out std_logic_vector(3 downto 0)); end counter;

architecture archi of counter is signal tmp: std_logic_vector(3 downto 0); begin process (C, CLR) begin if (CLR='1') then tmp = "0000"; elsif (C'event and C='1') then tmp = tmp + 1; end if; end process; Q = tmp; end archi;

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VHDL code for a 4-bit unsigned Down counter with synchronous set.

entity counter is port(C, S : in std_logic; Q : out std_logic_vector(3 downto 0)); end counter;

architecture archi of counter is signal tmp: std_logic_vector(3 downto 0); begin process (C) begin if (C'event and C='1') then if (S='1') then tmp = "1111"; else tmp = tmp - 1; end if; end if; end process;

Q = tmp; end archi;

Following is the VHDL code for a 4-bit unsigned Up Counter with asynchronous load from primary input.

entity counter is

port(C, ALOAD : in std_logic;

D : in std_logic_vector(3 downto 0);

Q : out std_logic_vector(3 downto 0));

end counter;

architecture archi of counter is

signal tmp: std_logic_vector(3 downto 0);

begin

process (C, ALOAD, D)

begin

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if (ALOAD='1') then

tmp = D;

elsif (C'event and C='1') then

tmp = tmp + 1;

end if;

end process;

Q = tmp;end archi;

Following is the VHDL code for a 4-bit unsigned Up Counter with synchronous load with a constant.

entity counter is

port(C, SLOAD : in std_logic;


end counter;



begin

process (C)

begin

if (C'event and C='1') then

if (SLOAD='1') then

tmp = "1010";

else

tmp = tmp + 1;

end if;

end if;

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end process;

Q = tmp;

end archi;

VHDL code for a 4-bit unsigned Up counter with asynchronous clear and clock enable.

entity counter is

port(C, CLR, CE : in std_logic;


end counter;



begin

process (C, CLR)

begin

if (CLR='1') then

tmp = "0000";


if (CE='1') then

tmp = tmp + 1;

end if;

end if;

end process;

Q = tmp;

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end archi;

The VHDL code for a 4-bit unsigned Up/Down counter with asynchronous clearentity counter is

port(C, CLR, up_down : in std_logic;


end counter;



begin

process (C, CLR)

begin

if (CLR='1') then

tmp = "0000";


if (up_down='1') then

tmp = tmp + 1;

else

tmp = tmp - 1;

end if;

end if;

end process;

Q = tmp;end archi;

17

VHDL code for a D Flip Flop

process (signal names)beginif (clock’ event and clock = ‘1’) thenoutput <= data;end if;end process ;

VHDL code for a D Flip Flop with Reset and Clear

if reset = ‘0’ thenoutput <= ‘0’;elsif set = ‘0’ thenoutput <= ‘1’;elsif (clock’ event and clock = ‘1’) thenoutput <= data;end if;

VHDL code for a D Flip Flop

if (clock’event and clock = ‘0’) thenif (reset = ‘0’ and data = ‘0’) thenoutput <= ‘0’;elsif (reset = ‘0’ and data = ‘1’) thenoutput <= ‘0’;elsif (reset = ‘1’ and data = ‘0’) thenoutput <= ‘0’;elsif (reset = ‘1’ and data = ‘1’) then

Output <= ‘1’;end if;

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VHDL code for a JK Flip Flop

if (clock’event and clock = ‘1’) thenif (in1 = ‘0’ and in2 = ‘0’) thenoutput <= output;elsif (in1 = ‘1’ and in2 = ‘0’) thenoutput <= ‘1’;elsif (in1 = ‘0’ and in2 = ‘1’) thenoutput <= ‘0’;elsif (in1 = ‘1’ and in2 = ‘1’) thenoutput <= not(output);end if;end if;

VHDL code for a Serial to Parallel Converter

if clear = ‘0’ thenshift_reg <= “00000000”;elsif (clock’event and clock = ‘1’) thenshift_reg(7 downto 1) <= (6 downto 0);shift_reg(0) <= serial;end if;

VHDL code for a Parallel to Serial Converter

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if load = ‘0’ thenshift_reg <= parallel;elsif (clock’event and clock = ‘1’) thenserial <= shift_reg(7);shift_reg(7 downto 1) <= (6 downto 0);end if;

VHDL code for a 4 bit Counter

if load = ‘0’ thenoutput <= “1111”;elsif (clock’event and clock = ‘1’) thenoutput <= data - ‘1’;end if;carry <= ‘0’ when output = “0000” else ‘1’;load <= carry;

VHDL code for a 1 bit Adder

if c = ‘0’ thenif (a and b) = ‘1’ thensum <= ‘0’;carry <= ‘1’;

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elsif (a or b) = ‘1’ thensum <= ‘1’;carry <= ‘0’end if;elsif c = ‘1’ thenif (a and b) = ‘1’ thensum <= ‘1’;carry <= ‘1’;elsif (a or b) = ‘1’ thensum <= ‘0’;carry <= ‘1’;end if;end if;

VHDL code for a State Machine

if reset = ‘0’ thenstate <= stateA;output <= ‘0’;elsif (clock’event and clock) = ‘1’ thencase state iswhen stateAoutput <= ‘0’;state <= stateBwhen stateBoutput <= ‘1’;if input = ‘1’ thenstate <= stateB;elsestate <=stateC;end if;when stateCoutput <= ‘0’state <= stateA;end case;

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vhdl code for d ff using behavior model - ashwani goyal -...

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