vhdl aes 128 encryption/decryption bradley university department of electrical and computer...
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VHDL AES 128 Encryption/Decryption
Bradley UniversityDepartment of Electrical and
Computer Engineering
Advisor: Dr. Vinod Prasad
David LeifkerGentre Graham
April 7th 2005
Senior Capstone Project
Presentation OutlinePresentation Outline
Project IntroductionProject Introduction
Functional DescriptionFunctional Description
Difficulties & SolutionsDifficulties & Solutions
Simulation, Verification, & DemonstrationSimulation, Verification, & Demonstration
ConclusionConclusion
Project Introduction: AESProject Introduction: AES
AES (Advanced Encryption Standard)AES (Advanced Encryption Standard) Key Lengths Key Lengths 128128,192,256 bits (FIPS 197),192,256 bits (FIPS 197) Block CipherBlock Cipher Approved by NSA (National Security Agency) Approved by NSA (National Security Agency)
Plain TextPlain Text Unencrypted DataUnencrypted Data
Cipher TextCipher Text Encrypted DataEncrypted Data
Encryption Key (Secret Key)Encryption Key (Secret Key) Enables conversion between Cipher Text & Plain Enables conversion between Cipher Text & Plain
TextText
Project IntroductionProject Introduction
VHDL (Very High Speed Integrated VHDL (Very High Speed Integrated Circuit Hardware Description Language) Circuit Hardware Description Language)
FPGA (Field-Programmable Gate Array)FPGA (Field-Programmable Gate Array)
HID ( Human Interface Device)HID ( Human Interface Device) PS/2 KeyboardPS/2 Keyboard LCD ( Liquid Crystal Display )LCD ( Liquid Crystal Display )
Project Introduction: Project Introduction: ApplicationsApplications
Secure CommunicationSecure Communication ATMATM DVD ContentDVD Content Secure NetworksSecure Networks
Secure StorageSecure Storage Confidential Corporate DocumentsConfidential Corporate Documents Government DocumentsGovernment Documents FBI FilesFBI Files Personal Storage DevicesPersonal Storage Devices Person Information ProtectionPerson Information Protection
Project Introduction: Project Introduction: HardwareHardware
PC with Xilinx ISE 6.31iPC with Xilinx ISE 6.31i NU Horizons NU Horizons
Xilinx Spartan III Development Xilinx Spartan III Development BoardBoardXCS400-4 PQ208CXCS400-4 PQ208CPS/2 InputPS/2 Input4 x 20 Line LCD Display4 x 20 Line LCD Display
Presentation OutlinePresentation Outline
Project IntroductionProject Introduction
Functional DescriptionFunctional Description
Difficulties & SolutionsDifficulties & Solutions
Simulation, Verification, & Simulation, Verification, &
DemonstrationDemonstration
ConclusionConclusion
Functional Description
Sub-System Block DiagramSub-System Block Diagram
AES CoreAES Core
Program Program ControlControlLogicLogic
PS2 PS2 KeyboardKeyboardInterfaceInterface
LCD LCD InterfaceInterface
RAMRAM
ROMROM
1254 LoC1254 LoC
180 LoC180 LoC
51 LoC51 LoC
67 LoC67 LoC
719 LoC719 LoC
440 LoC440 LoC
Misc. LoC: 290Misc. LoC: 290
Total Lines of Code ≈ 3000Total Lines of Code ≈ 3000
Sub-System Block DiagramSub-System Block Diagram
Inside The AES CoreInside The AES Core
EncryptionEncryptionKey ExpansionKey Expansion DecryptionDecryption
MixColumns
Shift Rows
Substitute Byte
Add Round Key
RconInverse
MixColumns
Inverse Shift Rows
Inverse Substitute Byte
Inside The AES CoreInside The AES Core
Key ScheduleKey ScheduleCurrent StateCurrent State Next StateNext State
Add Round Key
Inside The AES CoreInside The AES Core
Current StateCurrent State Next StateNext State
Substitute Byte & Inverse
256 Byte 256 Byte ArrayArray
Inside The AES CoreInside The AES Core
Current StateCurrent State Next StateNext State
Shift Rows & Inverse
Inside The AES CoreInside The AES Core
Current StateCurrent StateNext StateNext State
MixColumns
Inside The AES CoreInside The AES Core
Current StateCurrent StateNext StateNext State
Inverse MixColumns
Presentation OutlinePresentation Outline
Project IntroductionProject Introduction
Functional DescriptionFunctional Description
Difficulties & SolutionsDifficulties & Solutions
Simulation, Verification, & Simulation, Verification, &
DemonstrationDemonstration
ConclusionConclusion
Difficulties & SolutionsDifficulties & Solutions Development Board PS/2 PortDevelopment Board PS/2 Port
Replaced with External PS/2 PortReplaced with External PS/2 Port Development Board Documentation Did Not Development Board Documentation Did Not
Reflect Board SpecificationsReflect Board Specifications Clock SpeedClock Speed LCD Character Addressing (4x24 vs 4x20)LCD Character Addressing (4x24 vs 4x20)
LCD TimingLCD Timing Test Bench DevelopmentTest Bench Development
Area Constraints of the FPGAArea Constraints of the FPGA Hard Coded Encryption KeyHard Coded Encryption Key Reduction of States by Looping (LCD)Reduction of States by Looping (LCD)
Presentation OutlinePresentation Outline
Simulation, Verification, & Simulation, Verification, &
DemonstrationDemonstration
FIPS 197 Documented ExampleFIPS 197 Documented Example
ModelSim Computer SimulationModelSim Computer Simulation
FPGA DemonstrationFPGA Demonstration
Demonstration: FIPS 197Demonstration: FIPS 197
Demonstration: EncryptionDemonstration: Encryption
Demonstration: DecryptionDemonstration: Decryption
Demonstration: EncryptionDemonstration: Encryption
ModelSim Computer SimulationModelSim Computer Simulation
Demonstration: DecryptionDemonstration: DecryptionModelSim Computer SimulationModelSim Computer Simulation
Software Flow ChartSoftware Flow Chart
Demonstration: Splash ScreenDemonstration: Splash Screen
Demonstration: ASCII InputDemonstration: ASCII Input
Demonstration: ASCII InputDemonstration: ASCII Input
Demonstration: ASCII InputDemonstration: ASCII Input
Demonstration: HEX InputDemonstration: HEX Input
Demonstration: EncryptionDemonstration: Encryption
Demonstration: DecryptionDemonstration: Decryption
Improvements & AdditionsImprovements & Additions
Larger LCD DisplayLarger LCD Display
192 or 256 Bit level Encryption192 or 256 Bit level Encryption
High Speed ModeHigh Speed Mode
PC IntegrationPC Integration
Questions?