very large scale integration (vlsi) · dr. ahmed h. madian-vlsi problem 4 design a fsm that detects...
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Dr. Ahmed H. Madian-VLSI
Problem 1Draw the transistor circuit level for the layout shown in the figure and then get the logic functionTo which logic family this layout belongsRealize the logic function using the static CVSL family
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Dr. Ahmed H. Madian-VLSI
solution
Static CVSL
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Dr. Ahmed H. Madian-VLSI
Problem 2Apply domino logic for the following circuit use single-phase clock schemeDescribe the problem of clock skew and how we could get ride of it in this designDescribe the effect of charge sharing problem in your design and how you could over-come it?Make any necessary modifications to use the self resetting technique
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Dr. Ahmed H. Madian-VLSI
solutionSplit the circuit to equally delay inverting blocks
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Dr. Ahmed H. Madian-VLSI
Solution (cont.)
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Dr. Ahmed H. Madian-VLSI
Problem 3
Design a circuit to implement the logic function using mentioned technologies
F = A.B.C + A.B.CCMOS technologyCVSL technologySingle phase dynamic CMOSTwo phase dynamic CMOS
Compare without calculations between the realizations in number of transistors, speed.
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Dr. Ahmed H. Madian-VLSI
Solution
A
B
C
A
B
C
A B
B
C
CA
VDD
CMOS
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Dr. Ahmed H. Madian-VLSI
Solution
A B C
VDD
A B C
F
Φ1 Φ2
Two-phase
A B C
VDD
A B C
FΦ1
Single-phase
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Dr. Ahmed H. Madian-VLSI
Problem 4Design a FSM that detects 3 or more consecutive ones.
Steps:1. Understand the statement of the Specification 2. Obtain a state diagram of the FSM from the
specification3. Perform state assignment4. Determine the number of flip flop
(to represent 4 states => 2 flip flops)5. Choose type of flip-flop if not given
(for example we will choose D-FF)
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Dr. Ahmed H. Madian-VLSI
6.Using D-FF
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Dr. Ahmed H. Madian-VLSI
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Dr. Ahmed H. Madian-VLSI
Dynamic Implementation
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Dr. Ahmed H. Madian-VLSI
Dynamic Implementation (cont.)
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Dr. Ahmed H. Madian-VLSI
Logic Implementation (cont.)