verification without simulation - nmi › wp-content › uploads › 2014 › 12 ›...

© 2014 Synopsys. All rights reserved. 1

Verification without simulation

Static Circuit Checks

for

Robust Low Power Design

Paul Chapman

[email protected]

©2014 Synopsys, Inc.


Increasing Verification Coverage

Architectural spec

Design

Layout

Lab

Spin

Production

$

$/fix

$$$$$$$$$$

Tapeout

VE

RIF

ICA

TIO

N

Issues found

with Circuit Check

Leakage issue found

in lab testing

Standby mode floating gate

Production test fails

ERC issue found with

exhaustive simulation


Which tool is best ?

Leakage

Detection

ERC

Digital Logic

Diagnostics

Timing

Check

Signal

Integrity

• There are many ways to chase down balls floating nodes

• Solutions can vary in speed, reliability and setup


Improve Verification Speed & Coverage One solution is not enough

Power-up

Power-down

Functional

Analysis

Electrical

Rule Checks

Reliability

Analysis

Design

Verification

Power Consumption

DC current path

Leakage

Timing

Power Domains

IPs connectivity

Functionalities

IR drop

EM

Transistor Aging

Transient Simulation

Rail Analysis

PWRA/SIGRA/MOSRA

Static Checks

Cross Talk


Detect Errors that Simulation Won’t

Static Circuit Check


• Circuit Check Static vs. Dynamic ERC tradeoff is comparable to digital

logic STA vs. dynamic simulation

Static vs. Dynamic ERC

Static ERC Dynamic ERC

Coverage Exhaustive Vector-dependent

False violations Possible None

Speed Fast, no simulation necessary

May require significant simulation time

Reporting Limited Detailed


Circuit Check flow

Transistor-level

netlist

Device

models

Spice stimuli

CustomSim

CircuitCheck

Command file 1

CircuitCheck

Output

CircuitCheck


Voltage Propagation Elements

• Elements always conducting

Resistors

Inductors

• Elements never conducting

Capacitors

BJT devices

Diodes (unless when running fgate analysis)

Other elements

• Electrical conditional rules

NMOS/PMOS

Other elements: VerilogA block, Controlled sources (VCCS, VCVS, CCCS and CCVS)

0 V

Conducting path

3 V

Conducting path

3 V

Propagated Voltage

3 V 3 V

Non-Conducting path

Non-Conducting path

3 V

Propagated Voltage

0 V

Conducting path 3 V

3 V

Conducting path

Propagated Voltage

Propagated Voltage


Floating Gate, a classic one!

Designer-1

IP1

IP1

Designer-2

SOC

Leakage, where???

IP2

IP3

IP4


CCK Static ERC - Floating Gate Analysis

mp1

mn1

mp3

mn4

mn2

mn3

mp2

Physically unconnected gate

DC current source driven gate

cckFloatGateIsrc 1

Fast connectivity check


CCK Static ERC - Floating Gate Analysis

mp1

mn1

mp3

mn4

mn2

mn3

mp2

a

cckFloatGateIsrc 1

Device conducting state determined

by static propagation

Electrically unconnected gate


cckMosV Static Voltage Propagation

• Constant voltage sources values propagated through the design

1.8V

n6

1.8V

1.2V

1.2V

n1 (0,1.8V)

(0,1.8V)

(0,1.8V)

(0,1.8V) (0,1.2V)

(0,1.2V)


cckMosV Evaluation

• Resulting voltage ranges at devices terminals compared with

specified limits (maximum ratings)

2.5V

n6

1.8V

1.2V

1.2V

(0,1.8V) Max=1.8

(0,1.8V) Max=1.2

(0,1.8V) Max=1.2

(0,1.8V) Max=1.8

(0,1.8V) Max=1.8

n5

n2

n4

n1

n3 n7

n8


Through voltage propagation, identify

domain low-v to high-v device

High-V domain

Low-V domain

Essential Low Power ERC Coverage -Design Rule Check

• Missing level shifter

• Report domain boundary device without LS protection

• Pattern match to avoid invalid violations

Conduct local pattern matching to

confirm level shifter protection High-V domain

Low-V domain


Global PM Example

pmInit

pmSetMatchPattern "topo.sp" “lshift“

pmSetParam "checkSubName" "TLC“

pmSetParam "dumpMatchedSub" "1“

pmSetCheckFunc callback_func

pmSetDumpOutFile $fileName

pmExecute

pmFinalize


Essential Low Power ERC Coverage

• Netlist Sanity Check

• Device parameter, dangling net , and more

• Voltage Bias/Stress Check

• Device terminal voltage analysis , and more

• Design Rule Check

• Multi-driver, level shifter, weak-driver , and more

• Leakage Analysis

• Gated-power path analysis , and more

• Productivity Utilities

• Connectivity trace, net-device and port-pin

relationship, effective FinFet width , PODE device

detection, and more

cckERC

Leakage Utility

Design Rule Netlist Sanity

Voltage Bias/Stress

CircuitCheck

Built-in

Check

Tcl App

Library Tcl API


CustomSim Circuit Check CCK feature in Renesas leakage check

Static Leakage Analysis

Static Voltage Analysis

Static Forward Bias Diode Analysis

Static HiZ and DCPath Analysis

CCK is the leakage check tool for us

to avoid respin.

It helps us find problematic leakage

devices and paths in our IP

products and design chips before

tape-out

Takao Sato SIP & Analog EDA Technology Development Dept.

Leakage MosV F- bias HZ DCpath

Runtime 0.38h 0.16h 0.15h 0.09h 0.06h

memory 602M 602M 602M 602M 602M


Runtime 4.54h 0.20h 1.97h 0.23h 0.34h

memory 470M 470M 470M 470M 470M


Runtime 1.00h 0.69h 0.37h 0.24h 0.11h

memory 3630M 3640M 3627M 2441M 2442M


Runtime 1.26h 0.50h 0.48h 0.27h 0.11h

memory 6315M 6312M 6310M 4827M 4577M

MCU_A / 8M devices

SoC_A / 50M devices SoC_B / 22M devices

MCU_B / 58M devices


Circuit Check Customer Success Story Verifying Electrical Rule Violations

Find Bugs Known to Cause Silicon Failure

Floating Gates

Missing Level Shifters

Forward Biased Bulk Diodes

Double Oxide Voltage on Single Oxide Gates

Source: ST, SNUG

Found

numerous

design bugs

before tape-

out


Predictable Success

verification without simulation - nmi › wp-content › uploads › 2014 › 12 ›...

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