veloce2(r) the enterprise verification platformarmtechforum.com.cn/2014/sz/c-2_mentor.pdf ·...
TRANSCRIPT
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Veloce2® the Enterprise
Verification Platform
Simon Chen
Emulation Business
Development Director
Mentor Graphics
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© 2014 Mentor Graphics Corp. Company Confidential
www.mentor.com
Agenda
Emulation Use Modes
Veloce® Overview
ARM® case study
Conclusion
ARM Tech Symposia 2014 2
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© 2014 Mentor Graphics Corp. Company Confidential
www.mentor.com
Veloce Emulation Use Modes Solutions portfolios address all use modes
In Circuit Emulation
Simulation Acceleration
Software Debug
Virtual Lab Emulation
One Platform – All use modes
iSolve™ solutions
JTAG, Virtual Probe,
Veloce® Codelink™
VIP /Transactors
VirtuaLAB and
Memories
ARM Tech Symposia 2014 3
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© 2014 Mentor Graphics Corp. Company Confidential
www.mentor.com
Veloce Delivers Real Value
Design: Network switch with multiple 10G ports
Mode: Streaming 64-byte packets on all ports
Billions of transactions across all Ethernet ports
~1/4th frame/sec
~3,662 frames/sec
Simulation Emulation
Vs
~15,000x faster than simulation
ARM Tech Symposia 2014 4
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© 2014 Mentor Graphics Corp. Company Confidential
www.mentor.com
Crystal2 Custom Architecture
Rich interconnect yields 5 minute chip compiles
Built-in logic analyzer – all signals visible all of the time
Custom Virtual Wires logic for reliable chip-to-chip routing
Switched backplane interconnect for board-to-board routing
Fully automated software to compile designs
Crystal2 Veloce2 Quattro
Advanced Logic Board
Full custom IC
ARM Tech Symposia 2014 5
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© 2014 Mentor Graphics Corp. Company Confidential
www.mentor.com
Maximus: Enterprise Verification Platform
AVB Up to 64
Capacity (user gates)
Up to 1Billion
ICE users Up to 16
TBX or stand alone users
Up to 64
Physical IOs Up to 9600 (120*80)
Extended IO Up to 4X
Power 50 kW
Noise Level 75 dBA
ARM Tech Symposia 2014 6
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© 2014 Mentor Graphics Corp. Company Confidential
www.mentor.com
Veloce OS3 Enterprise Server
ARM Tech Symposia 2014
Consolidates global Veloce resources into a unified high-capacity entity
Speeds high-priority jobs by suspending jobs of low priority
Shields emulator complexity from LSF and Netbatch queue managers
Automatically adapts to change in HW availability
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www.mentor.com
Veloce Enables Full Chip Validation
The confidence level in the design before tape-out is maximized with full chip emulation — System level architectural bugs detection such as Performance,
HW-SW tests, Interrupts, Cache configuration, Memory Coherency, interconnect, and others
— Verifying the integration: interconnect, memory map, clocks, reset sequences
— Real life HW-SW test cases on OS create sequences that get to corner cases almost impossible to reach in sub-system clusters.
— Power aware verification. – Measuring power metrics is best done with real SW in full chip – Verifying different power modes – Verifying power with real OS task-switching effects
ARM Tech Symposia 2014 8
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© 2014 Mentor Graphics Corp. Company Confidential
www.mentor.com
Full-Chip Validation Prior to Silicon: Boot OS, Drivers Validation
OS and device drivers run on RTL or ISS processor models
VirtuaLAB peripherals exercise interfaces
SW debug solutions
Power analysis
CPU
Arbiter
Fabric
UART
Slave IF
GPIO
Slave IF
PCI Express
PHY
Fabric
Software
Memory
Master IF
Display Processor
PHY
Slave IF
SATA
PHY
Slave IF
Ethernet
PHY
Slave IF
USB
PHY
SlaveIF Master IF
CPU
Master IF
SoC
Codelink Multi-core SW/HW debug
ARM Tech Symposia 2014 9
http://sandisk.com/products/usb-flash-drives/sandisk-ultra-backup-usb-flash-drivehttp://www.frys.com/product/3805567
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© 2014 Mentor Graphics Corp. Company Confidential
www.mentor.com
Veloce Peripheral Interface Solutions
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iSolve Physical Peripherals
VirtuaLAB Virtual Peripherals
Verification IP Protocol Transactors
Example Test Suite
Users’ Test Sequences
Coverage and
Assertions
Test Plan
Users’ DUT Accelerated Transactor
Peripheral Interface Design IP
Identical IP used for all solution offerings
Silicon proven
ARM Tech Symposia 2014
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© 2014 Mentor Graphics Corp. Company Confidential
www.mentor.com
Advantages of VirtuaLAB
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Attractive alternative to ICE
Ideal for multi-user and multi-project
VirtuaLAB runs on Linux host
Peripherals are hardware accurate
Instantly reconfigured
Datacenter compatible
ROI
Quality
Productivity
ARM Tech Symposia 2014
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© 2014 Mentor Graphics Corp. Company Confidential
www.mentor.com
Off-line HW/SW Co-Debug with Codelink
ARM Tech Symposia 2014 12
Many Software Engineers at the same time
SW Debugger
Waveform View
Many Off-Line
Execution Data Bases
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© 2014 Mentor Graphics Corp. Company Confidential
www.mentor.com
ARM Case Study
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Going Beyond Simulation Acceleration
USB PCIe Physical I/O
Accelerated Transactors
OVM/UVM SystemVerilog C/SystemC
Simulation Acceleration
Testb
ench
Xpre
ss
.... iSolve Solutions
VirtuaLAB Solutions
USB
Virtual Protocol Solutions
SATA Video Ethernet
Software Debug
Codelink
SW Debug
VProbe Warpcore QEMU
Video SATA
Co
-Mo
de
l Ch
an
ne
ls
Physical Protocol Solutions
Ethernet
PCIe
ARM Tech Symposia 2014 20
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