various operating points within the limits of operation of...
TRANSCRIPT
Various operating points within the limits of operation of a transistor
Robert L. Boylestad
Electronic Devices and Circuit Theory, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Linear active operation region
Cut off operation region
Saturation
operation region
Fixed-bias circuit
Robert L. Boylestad
Electronic Devices and Circuit Theory, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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DC biasing
Robert L. Boylestad
Electronic Devices and Circuit Theory, 9e
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GRAPHICAL
Given circuit
DC equivalent circuit
MATHMAICAL
DC equivalent circuit
Robert L. Boylestad
Electronic Devices and Circuit Theory, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Base–emitter loop. ( input section loop)
Robert L. Boylestad
Electronic Devices and Circuit Theory, 9e
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Upper Saddle River, New Jersey 07458
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Collector–emitter loop. (output section loop)
Robert L. Boylestad
Electronic Devices and Circuit Theory, 9e
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Measuring VCE and VC
Robert L. Boylestad
Electronic Devices and Circuit Theory, 9e
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Example : find IBQ , ICQ , VCEQ , VB , VC , VBC
Robert L. Boylestad
Electronic Devices and Circuit Theory, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Saturation regions: (a) actual; (b) approximate
Robert L. Boylestad
Electronic Devices and Circuit Theory, 9e
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Upper Saddle River, New Jersey 07458
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Determining ICsat
Robert L. Boylestad
Electronic Devices and Circuit Theory, 9e
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Upper Saddle River, New Jersey 07458
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Determining ICsat for the fixed-bias configuration
Robert L. Boylestad
Electronic Devices and Circuit Theory, 9e
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Upper Saddle River, New Jersey 07458
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Load-line analysis: (a) the network; (b) the device characteristics
Robert L. Boylestad
Electronic Devices and Circuit Theory, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Fixed-bias load line
Robert L. Boylestad
Electronic Devices and Circuit Theory, 9e
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Upper Saddle River, New Jersey 07458
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Movement of the Q-point with increasing level of IB
Robert L. Boylestad
Electronic Devices and Circuit Theory, 9e
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Effect of an increasing level of RC on the load line and the Q-point
Robert L. Boylestad
Electronic Devices and Circuit Theory, 9e
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Upper Saddle River, New Jersey 07458
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Effect of lower values of VCC on the load line and the Q-point
Robert L. Boylestad
Electronic Devices and Circuit Theory, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Example : find VCC , RC , RB for the fixed biasing configuration
Robert L. Boylestad
Electronic Devices and Circuit Theory, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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BJT bias circuit with emitter resistor
Robert L. Boylestad
Electronic Devices and Circuit Theory, 9e
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Upper Saddle River, New Jersey 07458
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Base–emitter loop. (input section loop)
Robert L. Boylestad
Electronic Devices and Circuit Theory, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Network derived from Eq. (4.17). (input loop)
Robert L. Boylestad
Electronic Devices and Circuit Theory, 9e
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Reflected impedance level of RE
Robert L. Boylestad
Electronic Devices and Circuit Theory, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Collector–emitter loop. (output loop)
Robert L. Boylestad
Electronic Devices and Circuit Theory, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Example
Robert L. Boylestad
Electronic Devices and Circuit Theory, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Determining ICsat for the emitter-stabilized bias circuit
Robert L. Boylestad
Electronic Devices and Circuit Theory, 9e
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Upper Saddle River, New Jersey 07458
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Load line for the emitter-bias configuration
Robert L. Boylestad
Electronic Devices and Circuit Theory, 9e
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Voltage-divider bias configuration
Robert L. Boylestad
Electronic Devices and Circuit Theory, 9e
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Voltage-divider bias configuration
Robert L. Boylestad
Electronic Devices and Circuit Theory, 9e
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Approximated solution
Exact solution
Defining the Q-point for the voltage-divider bias configuration
Robert L. Boylestad
Electronic Devices and Circuit Theory, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Redrawing the input side of the network of Fig. 4.25
Robert L. Boylestad
Electronic Devices and Circuit Theory, 9e
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Upper Saddle River, New Jersey 07458
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Determining RTH
Robert L. Boylestad
Electronic Devices and Circuit Theory, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Determining ETH
Robert L. Boylestad
Electronic Devices and Circuit Theory, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Inserting the Thévenin equivalent circuit
Robert L. Boylestad
Electronic Devices and Circuit Theory, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Example
Robert L. Boylestad
Electronic Devices and Circuit Theory, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Approximated method
Robert L. Boylestad
Electronic Devices and Circuit Theory, 9e
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Voltage-divider configuration for Example 4.10
Robert L. Boylestad
Electronic Devices and Circuit Theory, 9e
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Upper Saddle River, New Jersey 07458
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DC bias circuit with voltage feedback
Robert L. Boylestad
Electronic Devices and Circuit Theory, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Base–emitter loop for the network ( input loop)
Robert L. Boylestad
Electronic Devices and Circuit Theory, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Collector–emitter loop for the network (output loop)
Robert L. Boylestad
Electronic Devices and Circuit Theory, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Example
Robert L. Boylestad
Electronic Devices and Circuit Theory, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Example
Robert L. Boylestad
Electronic Devices and Circuit Theory, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Example : Collector feedback with RE = 0Ω
Robert L. Boylestad
Electronic Devices and Circuit Theory, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Example
Robert L. Boylestad
Electronic Devices and Circuit Theory, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Example : Common-collector (emitter-follower) configuration
Robert L. Boylestad
Electronic Devices and Circuit Theory, 9e
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Upper Saddle River, New Jersey 07458
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Common-base configuration
Robert L. Boylestad
Electronic Devices and Circuit Theory, 9e
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Upper Saddle River, New Jersey 07458
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Example
Robert L. Boylestad
Electronic Devices and Circuit Theory, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Determining RTH
Robert L. Boylestad
Electronic Devices and Circuit Theory, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Determining ETH
Robert L. Boylestad
Electronic Devices and Circuit Theory, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Substituting the Thévenin equivalent circuit
Robert L. Boylestad
Electronic Devices and Circuit Theory, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Example : Design the circuit
Robert L. Boylestad
Electronic Devices and Circuit Theory, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Example : Design the circuit
Robert L. Boylestad
Electronic Devices and Circuit Theory, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Example : Design
Robert L. Boylestad
Electronic Devices and Circuit Theory, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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DESIGN : Emitter-stabilized bias circuit for design consideration
Robert L. Boylestad
Electronic Devices and Circuit Theory, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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DESIGN : Current-gain-stabilized circuit for design considerations
Robert L. Boylestad
Electronic Devices and Circuit Theory, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Network for Example 4.25
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Electronic Devices and Circuit Theory, 9e
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Fig. 4.63 Network for Example 4.26
Robert L. Boylestad
Electronic Devices and Circuit Theory, 9e
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pnp transistor in an emitter-stabilized configuration
Robert L. Boylestad
Electronic Devices and Circuit Theory, 9e
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Fig. 4.65 pnp transistor in a voltage-divider bias configuration
Robert L. Boylestad
Electronic Devices and Circuit Theory, 9e
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Fig. 4.68 Equivalent circuit for the voltage-divider configuration
Robert L. Boylestad
Electronic Devices and Circuit Theory, 9e
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Upper Saddle River, New Jersey 07458
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