validation of data converter speciﬁcations with behavioral...

Measurement 31 (2002) 231–245www.elsevier.com/ locate /measurement

Validation of data converter specifications with behavioralmodeling simulations

a,b a b , a*F. Maloberti , P. Estrada , P. Malcovati , A. ValeroaDepartment of Electrical Engineering, Analog and Mixed Signal Center, Texas A&M University, College Station, TX 77843-3128,

USAbDepartment of Electrical Engineering, University of Pavia, Via Ferrata 1, 27100 Pavia, Italy

Abstract

The increasing complexity of data converter architectures makes it necessary to use behavioral models to simulateelectrical performances and to determine the relevant data converter features. For this purpose, special input stimuli andspecific output data processing are required. In view of that, it is necessary to offer a specific data-converter simulationenvironment that permit the designer to validate the data converter specification and to extract the basic blocks key featuresbefore starting the transistor level design. Pointed toward this objective, this paper analyses the most utilized architecturesand identifies the basic (active and passive) building blocks used. Behavioral models of such basic blocks are discussed. Theproposed behavioral models are then used in a pipeline and a S–D converter. Specific routines for the determination of dataconverter parameters are presented. Simulations show how specific features of basic blocks affect the overall performances.Thus, guidelines on how to design the circuit in order to meet specifications are given. 2002 Elsevier Science Ltd. Allrights reserved.

Keywords: Data converters; Behavioral modeling; Simulation

1. Introduction passive components). Therefore, it is required to usesuitable behavioral models that account for the limits

The increasing importance of data converters in of the basic blocks produced by the transistor levelsystems-on-chip (SoC) makes it necessary to find limits and it is necessary to consider also the noiseefficient ways to extract and validate data converter performances and the variation of parameters withspecifications. Since the validation process is per- technological changes.formed before the transistor level design, the en- Simulation tools are mainly used to validate newvironment should use a high level of abstraction, algorithms or architectures. They permit us to evalu-using behavioral description of the required func- ate static and dynamic responses of the ADCs ortions. However, the performances of any data con- DACs. For N bits of resolution the number of digital

Nverter critically depend on the features of the basic codes is 2 . Therefore, for more than 10 bits ofblocks used (like the op-amp, the comparator and the resolution it becomes extremely time-consuming

exploring all the codes. Even with a powerfulcomputer, the transistor-level simulation time be-*Corresponding author. Tel.: 139-382-505-205; fax: 139-382-comes so long that designer utilizes this kind of505-677.

E-mail address: [email protected] (P. Malcovati). analysis only for studying critical transition points,

0263-2241/02/$ – see front matter 2002 Elsevier Science Ltd. All rights reserved.PI I : S0263-2241( 01 )00045-8

232 F. Maloberti et al. / Measurement 31 (2002) 231 –245

assuming that if the circuit operates properly in the making them ideal for mixed-signal behavioralcritical (or presupposed to be critical) points, it will modeling.work satisfactorily for any condition of operation.The strategy is obviously risky and it should be, atleast, complemented by a less particularized but 3. Input signals and output signalsexhaustive system analysis.

The use of behavioral models helps in achieving For the simulation of data converters, besides thethe target. Behavioral simulators work much faster model itself, we need suitable input signal generatorsthan the transistor level counterparts thus permitting as well as post-processing tools for calculating theto explore all the regions of operation. Moreover, the performance parameters of the device. The typicalbehavioral description of the electrical design fea- test signal used for characterizing data converters is atures (like the gain, the bandwidth, the offset, the sinusoid or a ramp, which are easy to implement inparasitic elements and so forth) allows the designer any computer simulation environment. Hardwareto appraise the basic blocks limitations on the characterization may limit the input signal to sinusoi-converter performances. Thus, starting from the data dal type, if the resolution is high. Also in many casesconverter specifications it becomes possible to derive white noise sources are required. In fact, to properlythe electrical specifications of the building blocks. model data converters, especially at behavioral level,

the thermal noise produced by resistors, switches andoperational amplifiers has to be considered. Since adata converter is a sampled data system, the aliasing

2. Simulation tools effect of the thermal noise has to be taken intoaccount. For example, in a switched-capacitor (SC)

Behavioral modeling is a task that can be tackled circuit, such as a sample and hold circuit or a SCby different approaches according to the type of integrator, we typically find a sampling capacitor Csproblem that we want to solve. In the case of in series with a switch, with finite resistance R thatonmixed-signal problems, there are several languages periodically opens. The intrinsic noise of the switchor tools available that allow us to construct be- is, therefore, sampled onto the capacitor togetherhavioral models, among them we have: AHDL with the useful signal x(t). The total noise power can

languages, MATLAB , and Mentor. AHDL (Analog be found evaluating the integralHardware Description Language) is a programming

`

language that allows an analog system to be de- 4kTR kTon2 ]]]]] ]e 5E df 5 , (1)Tscribed using high level abstract equations since they 2 C1 1 2pfR C ss don s0provide capability of dealing with differential equa-tions, non-linear systems, but also allow working where k is the Boltzman constant, T the absolutewith events. The most used AHDL languages are temperature and a series noise source with powerMast, VHDL-A, SpectreHDL, VERILOG-A. Some of 4kTR models the resistance noise. The switchonthese languages have development tools to make the thermal noise voltage n (t) (usually called kT /CT

2modeling task easier. For instance, MATLAB has the noise) has a white spectrum with power e ; it isTSIMULINK toolbox in order to describe continuous superimposed to the useful signal leading toand discrete systems in a graphical environment;

]Saber is the equivalent for Mast. AHDL languages kT]y t 5 x t 1 n t 5 x t 1 n t , (2)s d s d s d s d s dcan have analog and digital simulation. The differ- T Cœ s

ence between them is that in the analog simulation,the tool solves systems whose values can change where n(t) denotes a Gaussian random process withcontinuously during simulation, while digital simula- unity standard deviation. The SIMULINK model oftion is event-driven, and system values can change Fig. 1 implements Eq. (2), for example.only at prescribed times. These languages can deal Once we have a model of the data converter andwith both types of simulation in the same system, the proper input signals, a simulation of the circuit in

F. Maloberti et al. / Measurement 31 (2002) 231 –245 233

the SNDR. The effective number of bits result fromthe maximum SNR of a data converter (when consi-dering a sinusoidal input signal) by the equation

SNR 2 1.76dB]]]]N 5 . (5)eff 6.02

We perform the calculation of the SNR or SNDRof a data converter starting from the raw output data

Fig. 1. Modeling switches thermal noise (kT /C noise) with by two steps. The first step extracts the sinusoidalSIMULINK. signal (S) from the sequence of N output data (O ,O i

at time t ). Typically a discrete Fourier transformi

(DFT) of O at the signal frequency ( f ) achievesi inthe time domain provides a sequence of sampled datathe result (the use of the DFT is more accurate than

values. Then, a suitable processing of the raw outputthe use of the FFT)

data permits us to evaluate the performance of theNOdata converter. Typically, depending on the data 1

]S t 5 O 2O cos 2pf t cos 2pf tconverter architecture, we are interested in the S Ds ds d s dj i in i in jNO i51linearity parameters (integral non-linearity or INLNOand differential non-linearity or DNL) or in the i

]1 O 2O sin 2pf t sin 2pf t . (6)S Ds d s di in i in jresolution parameters (effective number of bits or NO i51N , signal-to-noise ratio or SNR and the signal-to-eff

noise and distortion ratio or SNDR). The obtained signal is then subtracted from theBoth the INL and the DNL, usually expressed in raw output signal in the time domain to produce a

fraction of LSB, easily result from the raw output signal (N ), made by the noise and distortion contri-T

data by applying the definitions. However, to achieve butions only. In the second step, the fast Fourieraccurate results we need a sufficient number of transform of S and of N 5 N 1 D, determines theT

simulation points within the single LSB, especially spectra of the signal (S ) and the one of the noiseS

when taking into consideration A/D converters. (S ). Finally, it is possible to calculate the signalN 1D

The SNR and the SNDR of a data converter are (P ) and noise (P ) power by integrating theS N 1D

defined as power spectra,

N NP P B BS S] ]]]SNR 5 and SNDR 5 , (3) 2 2P 5O S i and P 5O S i , (7)P P 1 P s d s dS S N1D N1DN N D

i51 i51

respectively, where P denotes the signal power, PS N where N denotes the number of samples corre-Bthe noise power and P the power of the harmonicsD sponding to the desired bandwidth (baseband, B).of the signal. In an ideal data converter, the SNRThe SNR (or SNDR) is then obtained from Eq. (3).depends on the quantization noise only according to

2 2N22FS /8 2 12]]] ]]]SNR 5 5 , (4)2 4. Data converters architectures and basic8FS]]] blocks2N222 12

where FS denotes the full-scale signal of the A/D We achieve data conversion with many possibleconverter. algorithms. The ones mostly used are the successive

However, other noise or distortion sources (e.g., approximation algorithm, the flash approach, the SD

thermal noise or non-linearity) increase the total technique [1] and all the algorithms that can benoise power of the data converter above the quanti- achieved with pipeline implementations. We willzation noise level and contribute to both the SNR and focus on those classes and we will identify the basic


Table 1Use of basic blocks in common data converter architectures

Algorithm Capacitor Resistor Comparator Op-Amp Digital

Charge redistribution Yes No One No MediumFlash Offset canc. Many Many No MediumTwo-step flash Offset canc. Yes Yes Yes MediumSD Yes Rarely Yes Yes High

blocks that they typically use. Normally, other 5.1. Operational amplifieralgorithms use partially or totally the same blocks.Therefore, the extension to other data converter Operational amplifiers are key components in mostarchitectures is relatively straightforward. electronic circuits, including data converters. In fact,

The charge redistribution architecture is widely pretty often the performance of the operationalused to achieve the successive approximation con- amplifiers determines the performance of a completeverter. By inspection of its block diagram we iden- data converter. It is therefore necessary to include antify the following two basic blocks: a capacitive accurate model of the operational amplifiers, consi-array controlled by switches and a comparator. The dering all of the non-ideal effects. In particular,flash converter utilizes a passive resistive network to besides the linear parameters such as finite gain andgenerate reference voltages and comparators. The bandwidth, we have to consider also the non-linearSD uses switched capacitor integrators, a comparator effects, such as saturation and slew-rate.and complex digital circuitry. DAC and pipeline Since data converters are sampled-data systems,architectures use operational amplifiers (to achieve there are two possible approaches for modelingamplification by a given factor or to subtract volt- operational amplifiers. The first approach is based onages) and, again comparators. Therefore, the ar- traditional models of the operational amplifiers. Thechitectures implementing the above considered algo- models consist of a set of equations and differentialrithms use one of more of the basic blocks listed in equations, which describe the behavior of the circuit,Table 1. We also observe that digital circuitry with typically using analog behavioral languages. In themedium or high complexity is used. This is im- simulation, then, we consider the transient behaviorportant for the simulation, digital circuits generate of the circuit during each clock cycle. The simulationspur that through the supply lines and the substrate obviously allows us to obtain a good accuracy, but ataffect the analog part. Therefore, the designer needs the expense of a long simulation time. The secondproper simulation tools for studying this kind of approach ground on models of the complete sub-limitations. circuit (for example an integrator or a buffer), which

includes the operational amplifier. The model doesnot perform the time simulation each clock cycle butuses given equations that account for the global

5. Behavioral modeling of basic block effect of the operational amplifier non-idealities atthe end of each clock cycle. Therefore, the use of

This section presents possible behavioral models behavioral simulation equations permits us to esti-of the basic blocks identified in the previous section. mate the error produced at the output of the sub-We will discuss the operational amplifier, and, in circuit without going into the details of the transientparticular, its use in switched capacitor integrators, behavior within the clock cycle. This approach is ofthe comparator and the resistive array used in flash course less accurate than the previous one, but by farconverters. The models proposed use, when possible, faster [2].the electrical features of the block as behavioral As an example, we can consider a switchedparameters of the model. capacitor (SC) integrator with transfer function


21 tz ]2S Dt]]]H z 5 . (8) v t 5 v nT 2 T 1 aV 1 2 e ,s d s d s d21 0 0 S1 2 zT]nT 2 , t , nT, (11)2Analog circuit implementations of the integrator

deviate from this ideal behavior due to several non-where V 5V (nT–T /2), a is the integrator leakageS inideal effects. One of the major causes of perform-and is the time constant of the integrator (GBW is theance degradation in the SC integrators is the incom-unity gain frequency of the operational amplifierplete transfer of charge. This non-ideal effect is awhen loaded by C ). The slope of this curve reachesfconsequence of the operational amplifier non-its maximum value when t 5 0, resulting inidealities, namely finite gain and bandwidth, slew

rate and saturation voltages. Fig. 2 shows the model Vd S] ]v t u 5 a . (12)s dof the integrator including all the non-idealities, 0 maxdt t

which will be considered in detail in the morecomplex circuits discussed in the next paragraphs. We must consider now two separate cases:The Matlab function that implements the slew rate,actually comprises Eqs. (11)–(15). 1. The value specified by Eq. (12) is lower than the

The op-amp of the integrator described by Eq. (8) operational amplifier slew-rate, SR. In this caseis ideal. However, the gain of any op-amp is not there is not slew-rate limitation and the evolutioninfinite and this causes a first limit. The consequence of v conforms Eq. (11).0is an integrator ‘leakage’: only a fraction a of the 2. The value specified by Eq. (12) is larger than SR.previous output of the integrator is added to each In this case, the operational amplifier is in slewingnew input sample. The transfer function of the and, therefore, the first part of the temporalintegrator with leakage becomes evolution of v (t , t ) is linear with slope SR.0 0

The following equations hold (assuming t ,T )021z]]]H z 5 . (9)s d 211 2 az t , t , v t 5 v nT 2 T 1 SRt (13)s d s d0 0 0

The dc gain H becomes therefore:0 t . t ,0

t2t0]21 S Dtv t 5 v t 1 aV 2 SRt 1 2 e . (14)s d s d s d0 0 0 s 0]]H 5 H 0 5 . (10)s d0 1 2 a

Imposing the condition for the continuity of theThe effect of the finite bandwidth and the slew- derivatives of Eqs. (13) and (14) in t , we obtain0

rate are related to each other and may be interpretedaVas a non-linear gain. The evolution of the output s]t 5 2 t. (15)0node during the nth integration period is governed by SR

If t . T only Eq. (13) holds. The MATLAB0

function in Fig. 2 implements the above equations tocalculate the value reached by v (t) at time T, which0

will be different from V due to the gain, bandwidth0

and slew-rate limitations of the operational amplifier.The saturation voltages of the operational am-

plifier are modeled using the saturation block insidethe feedback loop of the integrator, as shown in Fig.

Fig. 2. SIMULINK model of a SC integrator. 2.


5.2. Comparator for the integrator discussed above, the behavioralmodel should be able to determine the region of

A widely used configuration of comparator com- operation and to apply the proper behavioral model.prises the cascade of a preamplifier and a latch (with The final stage of the comparator is a latch withhysteresis). The input signal can vary significantly; hysteresis; the hysteresis is included to account forthen, the amplifier can operate in the linear or the the metastability error due to signals whose mag-overdrive region of operation. Therefore, as we have nitude is very close to the comparator reference.

Fig. 3. SIMULINK model of a comparator.

Fig. 4. Voltage transient in a string made of 16 equal resistors when used in a flash converter.


Additionally, fixed offset voltage and random offset used is not enough the voltages of the intermediatevoltage must be added to the input to model the nodes do not reach the expected value. A similaroffset and any time-dependent spur signals. limit occurs during the next complementary phase,

The block diagram of the SIMULINK model is when the auto-zero capacitor is charged to the newgiven in Fig. 3. Several SIMULINK blocks in Fig. 3 input voltage. Therefore, the combination of the twodepict an operation similar to the one represented by limits leads to a memory error. We describe it with athe Matlab function in Fig. 2. behavioral approach using look-up tables that contain

responses like the ones shown in Fig. 4.5.3. Passive components

A capacitive array and a resistor divider are the 6. Behavioral simulation of converters andpossible passive components used in data converters. resultsTheir limit must be studied at the circuit level andthe effect must be then translated into a behavioral We discuss now the use of the basic blocksdescription. The static mismatch of nominally equal behavioral models in two popular architectures. Weelements can be described by the use of random assume some specification requirements for the datanumbers with a given variance stored on an array. converter. An ideal architecture permits to achieveMore complex is the modeling of dynamic limita- better performances than a real implementation.tions. Let us consider, for example, the dynamic Therefore, the specification requirements shouldevolution of the string of equal resistances that a leave some margin to account for the non-idealities.flash converter uses. The designer should use this ‘budget’ properly. The

The auto-zero and the parasitic capacitance of all non-critical parameters will utilize a little of thethe comparators are pre-charged to the input voltage budget, so that the major part of it can be devoted toand then, they are connected to the intermediate the real limitations. For example, in a medium-nodes of the resistive string. The transient voltage of resolution high-speed converter, the gain is not muchthe intermediate nodes leads to diagrams similar to important, the offset cannot be a problem (if the dcthe ones in Fig. 4. If the time allowed by the phase response is not relevant) but the gain-bandwidth and,

Fig. 5. Basic cell of a 1.5-bit-per-cell pipeline converter.


tmuch more, the slew-rate are very critical. The ji]DV 5V n 1 V n 1 1 2V ns d s s d s ddin, jiresults of the behavioral simulations quantify the T

relevance of the above mentioned limitations and if t , 0 (17)jipermit a proper ‘budget’ assignment for an optimumdesign trade-off. where a suitable random number generator models

the jitter. The use of the above behavioral modelpermits to calculate the diagram in Fig. 6. We can6.1. Pipeline convertersobserve that the SNR degrades when the jitter ismore than 0.2% of the clock period. Therefore, theA pipeline converter is the cascade of a number ofdesigner can define the specification on the jitter oncells that generate one or more bits and provide athe basis of the given result.residual voltage for the next cell of the pipeline. For

1.5 bits per cell, the block diagram of the single celllooks like the one in Fig. 5. It includes an input 6.1.1. Validation of pipeline specificationssample and hold (S&H), a flash ADC, a DAC, a A 10-bit Pipeline ADC was simulated and thesubtraction and a multiplier by 2. All these functions main features of the design blocks were extracted. Inare modeled using a behavioral description. Signifi- Fig. 7 the SNR performance of the ADC is shown.cant limits result from the S&H. For instance, a jitter This figure shows the performance when the gain ofin the sampling instant (especially in the first stage of the amplifiers is degraded in the MDAC for the firstthe pipeline) degrades the SNR. Since the jitter is six stages of the ADC. The x-axis shows the gainsmaller than the sampling period, the error can be variation while the y-axis shows the effect in everycalculated as the jitter multiplied by the time deriva- stage while keeping the rest of the stages with idealtive of the input voltage. We model the effect as values. It can be seen from Fig. 7 that the mostfollows critical stages are the first ones and that a minimum

4gain of 10 (80 dB) is required to maintain the SNRtji above 62 dB. So, careful attention must be put into]DV 5V n 1 V n 2V n 2 1s d s s d s ddin, ji T the design of the first three stages, while a more

relaxed design is allowed for the rest of the stages.if t . 0 (16)ji

Fig. 6. Limitations to the SNR produced by the jitter in the first stage S&H.


Fig. 9. Effect of slew rate in the SNR normalized at 1 kHz.Fig. 7. SNR degradation as a function of gain in different stages.

Fig. 10. SNR degradation due to capacitor mismatch.Fig. 8. SNR performance versus gain-bandwidth normalized at 1kHz.

pipeline design takes into consideration 1.5 bits ofThe same effect occurs with other variables, like the digital correction, and therefore the effects of each

design variable are not as big as they would withoutgain-bandwidth product, shown in Fig. 8, slew rate,this consideration.as shown in Fig. 9 and capacitor mismatch of the

Using the information presented in Figs. 6–12 weMDAC, as shown in Fig. 10.can obtain the specifications for a 10-bit pipelineThe same study can be carried out for the com-ADC working at 200 MHz. Considering that anparators located in each stage. Two variables areeffective number of bits of 9 is allowed, then weconsidered: comparator offset and comparator speed.need to determine how the 6-dB degradation of theFig. 11 shows the degradation of the SNR with offsetSNR is going to be distributed among all theand Fig. 12 shows the number of time constantsparameters of the building blocks. Table 2 shows theneeded, within half sampling period, for the com-set of specifications for such converter.parator to respond. It should be noted that this


6.2. Sigma–delta modulators

In the design of high-resolution switched-capacitorSD modulators we have typically to optimize a largeset of parameters. Initially, on the basis of the systemspecifications we have to choose the architecture andthe order of the modulator, as well as the oversam-pling ratio and the sampling frequency. Then wehave to determine the performance of the buildingblocks required to achieve the specifications. In viewof the inherent non-linearity of the SD modulatorloop the specifications of the building blocks arederived with behavioral simulations: we have to usea large number of simulation points to properlyevaluate a SD modulator; moreover, the heavy post-processing used to analyze the data takes benefit

Fig. 11. Limitations of the SNR due to comparator speed.from the speed and flexibility of behavioral engines.

We consider a SC second-order SD modulator[1,3,4] with the specifications reported in Table 3.These specifications are challenging, thus requiring acareful optimization of the building block perform-ances.

The SIMULINK model used for the behavioralsimulations is shown in Fig. 13. The model, based onthe building blocks described in Section 4, includesthe clock jitter, the thermal noise of the switches(kT /C) and the operational amplifier non-idealities(finite gain, finite bandwidth, slew-rate and satura-tions). Under ideal conditions (i.e., with ideal analogbuilding blocks) the SD modulator with an oversam-pling ratio R5256 achieves 101 dB of the signal-to-noise and distortion ratio (SNDR). Therefore, the‘budget’ for the SNDR is 9 dB.

As mentioned above, in order to determine thespecifications of the building blocks, we should

Fig. 12. Dependence of SNR on comparator offset. evaluate the effect of each non-ideality on the SNDRof the modulator and then choose the proper value

Table 2Optimal set of parameters for the 10-bit 200-MHz pipeline ADC

Table 3Simulation parameters for the second-order SD modulatorParameter SNR Value

budgetParameter Value

(dB)Signal bandwidth BW5200 kHzAmplifier gain 0.1 A 580 dBv

Oversampling frequency F 5102.4 MHzGain-bandwidth product 3.0 GBW51.22 GHz s

Oversampling ratio R5256Slew rate 2.2 SR51880 V/msSignal-to-noise and SNDR592 dBCapacitor mismatch 0.5 0.3%distortion ratioComparator offset 0.1 150 mVResolution N515 bitComparator bandwidth 0.1 800 MHz


Fig. 13. SIMULINK model used for the simulations of the second-order SD modulator.

for the corresponding parameter. To this end, a Before selecting the optimal values of the parame-single non-ideality at a time is used in the behavioral ters, we have also to determine if each non-idealitysimulations. As a result, we obtain the family of affects the SNDR by raising the noise floor or bycurves, shown in Figs. 14–17, which represent the introducing harmonic distortion. From the powerSNDR of the modulator as a function of each spectral densities of the SD modulator output bit-parameter. stream, shown in Fig. 18, we observe that the clock

Fig. 14. SNDR of the second-order SD modulator as a function of the clock jitter.


Fig. 15. SNDR of the second-order SD modulator as a function of the switch thermal noise (determined by the integrator feedbackcapacitance C ).f

Fig. 16. SNDR of the second-order SD modulator as a function of the operational amplifier noise.


Fig. 17. SNDR of the second-order SD modulator as a function of the operational amplifier slew-rate for different values of the operationalamplifier bandwidth.

Fig. 18. Power spectral densities of the second-order SD modulator output bitstream in the presence of different non-idealities.

jitter, kT /C noise and operational amplifier noise idealities, from Figs. 14–17 we obtain the optimalraise the noise floor, while the slew-rate limitation set of parameters reported in Table 4.introduces harmonic distortion. As we could expect in view of the large sampling

Taking this into account as well as the 9-dB frequency used, the most critical parameters are theSNDR ‘budget’ that we have available for the non- operational amplifier slew-rate and the clock jitter.


Table 4Optimal set of parameters for the second-order SD modulator

Parameter Value

Clock jitter 1 nsIntegrator feedback 2.5 pFcapacitance (C )f

Operational amplifier 20 mVnoiseOperational amplifier 500 V/msslew-rateOperational amplifier 500 MHzbandwidth

By considering all of the non-idealities with theparameter values of Table 4, we obtain the output Fig. 20. SNDR of the second-order SD modulator as a function ofbitstream power spectral density and the SNDR as a the input signal amplitude in the presence of all the non-idealities

with optimal parameters.function of the input signal amplitude shown in Figs.19 and 20, respectively. The peak SNDR is 92.3 dB,while the dynamic range (i.e., the SNR without proper input stimuli and we perform specific process-harmonic distortion) is 99 dB, as required. ing of the output data. A library of behavioral

models of basic blocks permits to quickly implementthe behavioral description of any data converter

7. Conclusions architecture. If the behavioral models of basic blocksare based on key electrical parameters, the be-

The behavioral simulation of data converters is an havioral simulation permits the designer to analyzeimportant step of the design process. We have shown their contribution to limits and to define proper basicthat with a proper design environment we define the blocks specifications.

Fig. 19. Power spectral densities of the second-order SD modulator output bitstream in the presence of all the non-idealities with optimalparameters.


[3] S. Brigati, F. Francesconi, P. Malcovati, D. Tonietto, A.ReferencesBaschirotto, F. Maloberti, Modeling Sigma–Delta ModulatorNon-Idealities in SIMULINK, Proceedings of IEEE Interna-

[1] S.R. Norsworthy, R. Schreier, G.C. Temes, in: Delta-Sigma tional Symposium on Circuits and Systems (ISCAS ’99),Data Converters. Theory, Design and Simulation, IEEE Orlando, USA, Vol. 2, 1999, pp. 384–387.Press, Piscataway, NJ, 1997.

[4] B.E. Boser, B.A. Wooley, The design of Sigma-Delta modu-[2] F. Medeiro, B. Perez-Verdu, A. Rodriguez-Vazquez, J.L.

lation analog-to-digital converters, IEEE J. Solid-State Circ.Huertas, Modeling OpAmp-Induced Harmonic Distortion for

23 (1988) 1298–1308.Switched-Capacitor SD Modulator Design, Proceedings ofISCAS ’94, London, UK, Vol. 5, 1994, pp. 445–448.

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