utm power point ucsi nikd 16 july 10 pin1

8/3/2019 UTM Power Point UCSI Nikd 16 July 10 Pin1

1/82

1

Simulation of Power ElectronicSystems Using PSpice

Presented by Nik Din Muhamad


2/82

2

Presentation Outlines

Know background of SPICEUnderstand Power Electronics Circuits/SystemsKnow how to use VPULSE to generate usefulwaveforms

Know how to make simple models using ABM

In order to use Pspice for power electronicsystems, we have to:


3/82

3

Scope

PSpiceSystem/Circuit Level SimulationPower Electronic Circuits/Systems

Simulation

This presentation covers :


4/82

4

SPICE/PSpice

SPICE turns 38 years old this yearI Knew SPICE when she was 17 years oldI love PSpice because she can do almost

anything I need with FOC.I like to talk about her.

Did you know?


5/82

5

Why simulation?

Saving of development time

Saving of costs ( burnt power circuits tendto be expensive

)

Better understanding of the function

Simulations are essential ingredients of theanalysis and design process in powerelectronics:


6/82

6

continued

Testing and finding of critical states andregions of operation (Worst Case Analysis)Stress test (Smoke Analysis)Optimization of systemTesting new ideas


7/82

7

Overview

Simulation of analog circuits normallyuses three basic tools:

SPICE simulator,Mathematical analysis package,and Microsoft Excel.


8/82

8

SPICE

S imulation P rogram for Integrated CircuitEmphasis

Intended for ICs, not for power electronics.

Uses iterative Newton-Raphson Algorithmto solve a set of nonlinear equations.


9/82

9

SPICE LIMITATIONS

The Newton-Raphson algorithm is guaranteedto converge if the equations is continuous .

The transient analysis has the additionalpossibility of unable to converge because of thediscontinuity in time.


10/82

10

Voltage and currents are limited to +/-1e10.

Derivatives in PSpice are limited to 1e14. The arithmetic used in PSpice is double

precision and has 15 digits of accuracy.

Computer Hardware Limitation:

SPICE LIMITATIONS


11/82

11

Power Electronic Circuit

Power electronic circuitsare characterized by switchingon and off of powersemiconductor switches; thegenerated waveform ispassed through inductors and

capacitors for filtering.


12/82

12

Power Electronic Circuit

Due to switching action of the switch,discontinuity (in circuit variables and in

time) can easily occur during simulation,which leads to convergence problem.

Avoid discontinuity


13/82

13

Discontinuity Analogy:A Bump on the Road

Whole car shakes when I hit a bump on the road

PSpice doesnt like discontinuity as we dont likea bump on the road.

Unacceptable Bump

Acceptable Bump


14/82

14

Avoid Discontinuity

G

S

VGS

t

VGS

tAll signals must be made less discontinuousAll relationships must be continuous


15/82

15

VPULSEWaveform generator

PULSESAWTOOTH

TRIANGULAR


16/82

16

VPULSE

Waveform generatorIn order to use PSpice for power electroniccircuits, the first thing you have to know is to

program VPULSE to produce these waveforms:

PULSESawtoothTriangular


17/82

17

VPULSE

Waveform Generator Part

V1=V2=TD=TR=

TF=PW=PER=

V1

V2

TD

PW

PER

has 7 parameters to setTD can be zero, others can not!

know what parameters to adjust and to fix.


18/82

18

VPULSETo Generate Pulse Waveform

V1=0V2=12TD=0TR=10n

TF=10nPW=10uPER=20u

Very small values for TR and TFDuty cycle = PW/PER

PW

TR 0 TF 0

PER

V1

V2


19/82

19

A Typical applicationBuck Converter (Open Loop)

V2

20V

0

V+

MUR1520V3

TD = 0TF = 10nPW = 10uPER = 20u

V1 = 0TR = 10nV2 = 12V

V-

10680uF

M2IRF150

100uH

A Pulse waveform is used to drive a MOSFETON and OFF.


20/82

20

Its Pulse (I)

V1=0V2=12

TD=0TR=10nTF=10nPW=10uPER=20u

Duty Cycle , %5020

10===

PER

PW D


21/82

21

Its Pulse (II)

V1=0V2=12TD=0

TR=10nTF=10nPW=5uPER=20u

Duty cycle of the waveform is adjusted by adjusting PW

%2520

5===

PER

PW D


22/82

22

V1=0V2=12TD=0TR={20u-20n}TF=10n

PW=10nPER=20u

Very small values for TF and PWTRPER

PW

TF

PER

VPULSETo Generate Sawtooth


23/82

23

A Typical applicationBuck Converter (Closed Loop)

10

100uH

0

M2IRF150

V4

680uF - +

+ -

E1

E

GAIN = 4

0

MUR1520

V2

20V

Comparator

SawtoothGen .

ControlSignal

+-

Gate

Driver

For Closed-loop, the control signal

is compared with a sawtoothwaveform to produce the pulsewaveform.


24/82

24

PSpice Implementation

Sawtooth VPULSEControl VDCVpulse

ComparatorControlSignal

GateDriver

100uH

- +

+ -

E1

EGAIN = 1

0

10

0

M2

IRF150

0

MUR1520

680uF

E2

V(%IN+, %IN-)

ETABLE

TABLE = (0,0 (200u,12)

OUT+OUT-

IN+IN-

V5

2.5Vdc

0

V2

20V

V3

TD = 0TF = 10nPW = 10nPER = 20uV1 = 1VTR = {20u-20n}V2 = 4V

Gate Driver EComparator ETABLE


25/82

25

Its Waveform (I)

Sawtooth

Control

Pulse

D = 50 %


26/82

26

Its Waveform (II)

Sawtooth

Control

Pulse

Duty Cycle of the Pulse is adjusted by adjustingControl Signal.

D = 33%


27/82

27

V1= -1V2= +1TD=0TR= {10u-10n}TF= {10u-10n}PW=20nPER=20u

Very small value for PWTRTF PER/2

PW

PER

VPULSETo Generate Triangular wave


28/82


29/82

29

Triangular WaveTypical applications

VV1

TD = 0

TF = {(1/(FTRI*2)-10n)}PW = 20nPER = {1/FTRI}

V1 = -1

TR = {(1/(FTRI*2))-10n}

V2 = +1

SINE

0

V

V

0

TRI

PARAMETERS:Ma = 0.8Mf = 21FTRI = {FSINE*Mf }FSINE = 50VDC = 100

VDC*(V(SINE)-V(TRI))/ABS(V(SINE)-V(TRI))

SPWMV2

FREQ = {FSINE}VAMPL = {Ma}VOFF = 0

PHASE = {-90/Mf}

Bipolar SPWM

Comparator


30/82

30


Bipolar SPWM

Time [ms]40ms 42ms 44ms 46ms 48ms 50ms 52ms 54ms 56ms 58ms 60ms

V(SPWM) 0

-100

0

100V(TRI) V(SINE) 0

-1.0V

0V

1.0V


31/82

31


Unipolar SPWM

BV2a


PHASE = {-90/Mf +180}

SINE1

V

V2


PHASE = {-90/Mf}

0

A

0

V

V

0

TRI

0.5*VDC*(V(SINE2)-V(TRI))/ABS(V(SINE2)-V(TRI))

SINE2

0.5*VDC*(V(SINE1)-V(TRI))/ABS(V(SINE1)-V(TRI))

VPARAMETERS:Ma = 0.8Mf = 21FTRI = {FSINE*Mf }FSINE = 50VDC = 100

VV1

TD = 0

TF = {(1/(FTRI*2)-10n)}PW = 20nPER = {1/FTRI}

V1 = -1

TR = {(1/(FTRI*2))-10n}

V2 = +1

Comparator 1

Comparator 2


32/82

32


Unipolar SPWM

Time [ms]

40ms 42ms 44ms 46ms 48ms 50ms 52ms 54ms 56ms 58ms 60msV(A)-V(B)

-100V

0V

100V

V(A)-V(B)

V(SINE1) V(SINE2) V(TRI)-1.0V

0V

1.0V


33/82

33

Analog Behavior Model (ABM)Makes the Circuit Simpler

Use equations to model circuitsComparatorSingle Phase RectifierThree Phase RectifierBuck Converter in CCMSingle Phase Inverter


34/82

34

ABMBehavior Model of Comparator

IF the voltage at the terminal V(+) isgreater than the voltage at terminalV(-) the output V(out) is HIgh,otherwise the output is LOw.

IF(V(+)>V(-),HI, LO)(1) Using IF-Then-Else function

(2) Using signum function(V(+)-V(-))/ABS(V(+)-V(-))

-V(-)

V(out)

+V(+)


35/82

35


-V(-)

V(out)

+V(+)

(4) Using Op-amp alike

0

V(+)

V(-)

+- A*(V(+)-V(-))

V(out)(3) Using I/O graph

0 V(+)-V(-)

V(out)

ABM


36/82

36

ABMComparator in PSpice

TRI

V1

TD = 0

TF = {(1/(FTRI*2)-10n)}PW = 20n

PER = {1/FTRI}

V1 = -1

TR = {(1/(FTRI*2))-10n}

V2 = +1

out3

V

LIMIT(10k*(V(SINE)-V(TRI)),10,-10)

0

IF(V(SINE)>V(TRI),10,-10)

V

out1

PARAMETERS:Ma = 0.8Mf = 21FTRI = {FSINE*Mf }FSINE = 50VDC = 10

0

out4

E1

V(%IN+, %IN-)ETABLE

TABLE = (-100u,-10) (100u,10)

OUT+OUT-

IN+IN-

TRI

V

V

V

V2


PHASE = {-90/Mf}0

out2

V

SINE

SINE

VDC*(V(SINE)-V(TRI))/ABS(V(SINE)-V(TRI))

NO 2 is implemented using ETABLEOthers are implemented using ABM partNO 2 & NO 4 are suitable for Op-amp

(Error Amplifier)

1

2

3

4


37/82

37


Time [ms]

40ms 42ms 44ms 46ms 48ms 50ms 52ms 54ms 56ms 58ms 60msV(OUT3) V(OUT2) V(OUT1) V(OUT4)

-10V

0V

10VV(TRI) V(SINE)

-1.0V

0V

1.0V

These waveforms come from the outputs of four comparators


38/82

38

ABMBehavior Model of Rectifier (I)

V1a

FREQ = 50VAMPL = 340

VOFF = 0R1a

1k

DbreakD6

0

DbreakD4

DbreakD5

DbreakD3

in

R1b

1k

E1

ABS(V(IN))EVALUE

OUT+OUT-

IN+IN-

V1

FREQ = 50VAMPL = 340

VOFF = 0

00

V(out)=ABS(V(IN))


39/82

39

ABMBehavior Model of Rectifier (II)

VanVbn

Vcn

+

-

V(out) = 0.5*(ABS(V(an)-V(bn)

+ABS(V(bn)-V(cn))+ABS(V(cn)-V(an)))

ABM


40/82

40

ABMBehavior Model of Buck in CCM

0

RLMUR1520

100uH

680uF

IRF540

V3

TD = 0TF = 10nPW = 10uPER = 20uV1 = 0TR = 10nV2 = 12V

V2

20 Vdc

+

-

Vd

Vd = d*Vin

100uH

d

0

680uF RL

Vin

E1

V(%IN+)*V( %IN-)EVALUE

OUT+OUT-

IN+IN-

+

-

Vdd is a PWM signal

with 1V amplitude.

ABM


41/82

41

ABMBehavior Model of Inverter

a

b

+

-Vab

Bipolar SPWM

0

+

-

E1

VDC*(V(%IN+)-V( %IN-))/ABS(V(%IN+)-V( %IN-))EVALUE

OUT+OUT-

IN+IN-

SINE

TRIVab

VDC


42/82

42

#TIPS

There are many different waysto model the same thing. So, becreative!

Use a simple model whereverpossible to reduce modeling time

and make simulation run fasterand converge better!


43/82

43

Quote about Model !

Models are like shoes; there is no one-size-fits-all model.


44/82

44

Our Case Study

A Buck Converter with VMCA Simple PWM Controller IC ModelA PWM IC Controller IC Model including

Soft-start

A PWM IC Controller IC Model IncludingSoft-start, Duty Cycle Max and CurrentLimiter

O C St d


45/82

45

Our Case StudyA Buck Converter with VMC

SG3525PWM Controller IC

- +

+ -

0

0


46/82

46

SG3525PWM Controller IC

Key Functions: Oscillator

(Sawtooth Generator)PWM Comparator

and SR Flip-flopError Amplifier5.1 V ReferencePulse Steering

LogicShutdown and

Soft-start Circuitry


47/82

47

SG3525

We do not need to have SG3525 model inPSpices library to simulate buck converter withVMC.

Error AmplifierComparatorSawtooth generator

To verify the controller design, all we need arefunctional models of these:

SG3525


48/82

48

SG3525A Simple Model

To MOSFETDriver

-

++

-

Sawtooth

Error Amp.Comparator


49/82

49

A Buck Converter with VMC

- +

+ -

-

0

-

VPULSE

0

Vref

+

0

0

+

Comparator Error Amp.

Sawtooth

Buck Converter

Consider we know allcircuit parameters.

Our interest is tosimulate the system.

The controller is usedto regulate the outputvoltage at 5 V.


50/82

50

The controller is a linear controller and thedesign is based on a small-signal model.

So, the controller can not cope with largesignal scenario such as start-up.

Initial values , which are equal to their steady

state values, for the inductor current and thecapacitor voltage must be set.

A Buck Converter with VMC


51/82

51

Load Disturbance

How to set a load disturbance ?Let the load disturbance is:

0 A1 A

8 ms 8.5 ms

3A

R = 5 R = 1.666

R = 5

R is changed from 5 to 1.666


52/82

52

Our Case StudyHow to set load disturbance ?

Using IPULSE

I1

TD = 8m

TF = 0.1uPW = 0.5mPER = 1m

I1 = 1I2 = 3

TR = 0.1u

ILOAD

Allocate enough times for TR and TF

1


53/82

53

Load Disturbance

How to set load disturbance ?

5

TOPEN = 8.5m

1 2TCLOSE = 8m

2.5

Using SW_tclose and SW_topen

5//2.5 =1.666

2


54/82

54

Load Disturbance: PSpice

0

R4av

{R3}

R7av

{R1}

R2av

{Resr}

ILOAD0VdcI

0

0

I1

TD = 8m

TF = 0.1uPW = 0.5mPER = 1m

I1 = 1I2 = 3

TR = 0.1u

- +

+ -

E1

EGAIN = 3

0

DbreakD5

L1

{L}

IC = 1A

E1av

-V(%IN+, %IN-)ETABLE

(0,0) (250u,6)

OUT+OUT-

IN+IN-

0

IV

E2av

V(%IN+, %IN-)ETABLE

(0,0) (250u,5)

OUT+OUT-

IN+IN-

C4av

{C1}

input

V2av

{Vref}

C2av

{C2}

M1IRF150

R2

{Rbias}

R1av

50m

V1

TD = 0

TF = 10nPW = 10nPER = 10u

V1 = 0

TR = {10u-20n}

V2 = 3

V215Vdc

C1av

{C}IC = 5V

C3av

{C3}

out

R6av

{R2}

0


55/82

55

Load Disturbance: Results

Time [ms]

7.8ms 7.9ms 8.0ms 8.1ms 8.2ms 8.3ms 8.4ms 8.5ms 8.6ms 8.7ms 8.8msI(L1) I(ILOAD)

0A

2.0A

4.0A V(OUT)

4.8V

5.0V

5.2V

Inductor Current

Output Voltage


56/82

56

Input Disturbance

How to set an input disturbance ?Let the input disturbance is:

0 V

15 V

25 V

8 ms 8.5 ms


57/82

57

Input Disturbance

How to set an input disturbance ?Use VPWL (Piece-Wise Linear Voltage Source)

0 V

15 V

8 ms 9 ms

25 V

PWL(T1,V1)(T2,V2)(T3,V3)(T4,V4)(T5,V5)

PWL (0,15) (8m,15) (8.0001m,25) (9m,25) (9.0001m,15)


58/82

58

Input DisturbanceResponses

Time [ms]7.8ms 8.0ms 8.2ms 8.4ms 8.6ms 8.8ms 9.0ms 9.2ms 9.4ms 9.6ms 9.8ms 10.0ms

I(L1)

0A

1.0A

2.0AV(OUT)

4.8V4.9V

5.0V

5.1V

V(INPUT)10V

20V25V

30V

Input Voltage

Inductor Current

Output Voltage


59/82

59

Start-up Scenario

Previous simulation skips start-up scenario.To know how the controller handles start-up, set the initialvalues for i L and v c to zero.

Time [ s]0s 100us 200us 300us 400us 500us 600us 700us 800us

I(L1) V(OUT)

0

5

10

15

20

Output Voltage

Inductor Current


60/82

60

Start-up ScenarioA very large overshoot and undershoot occur in inductor current.

The duty cycle is at first at 1 for a long time and later at 0 for a longtime too, then after that it gradually increases.

Convergence problem can easily occurs at this extreme condition.

Time0s 100us 200us 300us 400us 500us 600us 700us 800us

I(L1) V(OUT)

0

5

10

15

20V(E1:1)

0V

2.5V

5.0V

Gate Signal


61/82

61

Start-upIn practical circuit, another auxiliary controller is

required to handle start-up.This circuit is known as soft-start.

Soft-start circuit works by gradually increasing the dutycycle. So do the inductor current and capacitor voltage.

Time [ s]0s 100us 200us 300us 400us 500us 600us 700us 800us

I(L1) V(OUT)

0

5

10

15

20V(E1:1)

0V

2.5V

5.0V

Gate Signal

Soft startController

VMCController

Soft-start


62/82

62

Soft startTo add Soft-start

The previous PWM IC model is very useful and it issimple to set-up in PSpice.

It is enough to verify the design of controller based onsmall signal model.

However, to add soft-start controller and other

protection circuits, we need a more flexible PWM ICmodel.


63/82

63

A Modified PWM IC Model

RS

Oscillator

-

++

- Q

Sawtooth

Clock

Error Amp.

ComparatorSR Flip-flop

The output of SR flip-flop is set by the Clock.The output of SR flip-flop is reset by Comparator.


64/82

64


Analog signals can be added at minus terminals of thecomparator.

Digital signals can be added at the input Resets of FF.

RS

RR

Oscillator

-+

+

-Q

Sawtooth

Clock

Error Amp.Comparator SR Flip-flop

--Analog

Signals DigitalSignals

Soft-start


65/82

65

Soft startTo add Soft-start Signal

Sawtooth is still compared with the control signal.

But, Control Signal can be either Error Amp. output(EAO) or Soft-start signal (SS), whichever is lower.

-

+

-

Sawtooth

Error Amp.

OutputSoft-start

To R of SR

Flip-FlopControlSignal

Soft-start


66/82

66


The soft-start voltage is the capacitor voltage.The capacitor C is charged by a constant currentsource of 50 A. The result is a ramp voltage.

C determines the duration of soft-start.

-

+

-

Sawtooth

Error Amp.Output (EAO)

Soft-start (SS) To R of SR

Flip-FlopC

50 A

Soft-start


67/82

67

Soft startHow Soft-start works?

10 ms

Soft-startVoltage

t

Use PWL to emulate soft-start voltageFor the graph, PWL(0,0)(10ms,4V)

t

V C I

=

4 V

Slope =C

50

C = 125 nF

Soft-start


68/82

68


We need a selector to select either SS or EAO,whichever is lower, to be Control Signal.

We can use IF-Then-Else functionIF(SS < EAO, SS, EAO)

+

-

Sawtooth

EAO

SS To R of SR

Flip-FlopC

50 A

ControlSignal

Selector

Soft-start


69/82

69

Soft startIn PSpice

IF( V (%IN2)


70/82

70

Soft startStart-up Signals

Time [ms]

Control Signal

0s 1.0ms 2.0ms 3.0ms 4.0ms 5.0ms 6.0ms0V

1.0V

2.0V

0V

2.5V

5.0V

0V

2.5V

5.0V

Soft-Start Signal

Error Amplifier Output

Control = IF(SS < EAO, SS, EAO)

S ft t t


71/82

71

Soft-startC = 125 nF (Too Small!)

Time [ms]

I(L1)

V(OUT)

0s 1.0ms 2.0ms 3.0ms 4.0ms 5.0ms 6.0ms0A

2.0A

4.0A

0V

2.5V

5.0V

7.5V

Soft-start signal ramps up too fast

tstart-up = 1ms

S ft t t


72/82

72

Soft-startStart-up Current and Voltage

Time [ms]

0s 1.0ms 2.0ms 3.0ms 4.0ms 5.0ms 6.0ms

I(L1)

0A

1.0A

2.0A

V(OUT)

0V

2.5V

5.0V

7.5V

Still has a small overshoot and undershoot ininductor current

has a room for improvement by increasing C.

tstart-up = 3.2 ms

C = 25 nF

S ft t t


73/82

73

Soft-startStart-up Current and Voltage

C = 125 nF ; Start-up time is 30 ms.Time

0s 5ms 10ms 15ms 20ms 25ms 30ms 35msI(L1)

0A

1.0A

2.0A

SEL>>

V(OUT)0V

2.0V

4.0V

6.0V

I(L1)

V(OUT)

d f d d l


74/82

74


To add digital signals for protection.For examples, Maximum Duty Cycle and Current LimiterFlip-flop can be reset either by PWM comparator, or

Maximum duty cycle, or Current Limiter.

RS

RR

Oscillator

-+

+

-Q

Sawtooth

Clock

Error Amp.Comparator SR Flip-flop

--Analog

Signals DigitalSignals

To Add Digital Signals


75/82

75

g gDutyMax and CurrentLimit

Maximum duty cycle limiter is in digital form. It can beapplied directly to the Reset of FF.The switch current (or inductor current) must be compared

with its limit value to produce a digital signal.

0U12A7432

1

23

U16A7432

1

23

8A

U11A7402

2

31 R

I(L1)

0

U10A7402

2

31

VClock

TD = 0

TF = 1nPW = 0.1uPER = 10u

V1 = 0

TR = 1n

V2 = 5V

Vduty max

TD = {10u*0.85}

TF = 10nPW = {(10u-10u*0.85)-20n}PER = 10u

V1 = 0

TR = 10n

V2 = 5V

0S

QEcurr_limit

+V(%IN+, %IN-)ETABLE

(0,0) (250u,5)

OUT+OUT-

IN+IN-

Dutymax

RESET 1 (EAO)

RESET 2 (CL)

RESET 3 (DMax)

SET

Set only by one i. e. the clockReset can be done by three, whichever

comes first.



76/82

76

Time

0s 20us 40us 60us 80us 100us 120us 140us 160us 180us 200usV(SAWTOOTH)

0V

2.0V

4.0VV(DUTYMAX)

0V

2.5V

5.0V

V(DUTYMAX)

V(S)0V

2.5V

5.0V

DUTYMAX

CLOCK

SAWTOOTH

DUTYMAX signal will only reset FF if the duty cycle is more than 0.85This DUTYMAX is to make sure that the MOSFET always turns-off foreach cycle

CurrentLimit signal will only appear and reset FF if the peak switch isgreater than pre-specified value.




77/82

77

Time

5.6ms 5.7ms 5.8ms 5.9ms 6.0ms 6.1ms 6.2ms 6.3ms 6.4ms 6.5ms 6.6msV(OUT) I(L1)

0

5

10


We want to limit this current at 8A

Inductor Current

Output Voltage



78/82

78

Time

5.6ms 5.7ms 5.8ms 5.9ms 6.0ms 6.1ms 6.2ms 6.3ms 6.4ms 6.5ms 6.6msV(OUT) I(L1)

0

5

10

Output Voltage

Inductor Current

8A Limiter


What do we expect ?

Reset by EAO Reset byDutyMax

Reset byCurrentLimit

Reset by EAO



79/82

79

A Load disturbanceat 6.0 ms

Time [ms]5.90ms 5.95ms 6.00ms 6.05ms 6.10ms 6.15ms 6.20ms

V(DUTYMAX) V(Q)

0V

2.5V

5.0VV(CURRENTLIM) V(Q)

0V

2.5V

5.0VV(PWMCOMP) V(Q)

0V

2.5V

5.0VV(CLOCK)

0V

2.5V

5.0V



80/82

80

Knowing

There is no substitute for knowingwhat we are doing

CONCLUSION


81/82

81

CONCLUSION

Know how to program VPULSE for Pulse,Sawtooth, and Triangular waveforms.

Avoid discontinuity at any costUse the simplest model possibleUse a simple model first, and add

complexity in stages.

No replacement for good understanding

In order to simulate power electronic circuit:


82/82

Q & A

utm power point ucsi nikd 16 july 10 pin1

Documents