utilizing design of experiments, monte carlo simulations and partial least squares in snapback...

QUALITY AND RELIABILITY ENGINEERING INTERNATIONAL

Qual. Reliab. Engng. Int.14: 227–235 (1998)

UTILIZING DESIGN OF EXPERIMENTS, MONTE CARLO SIMULATIONSAND PARTIAL LEAST SQUARES IN SNAPBACK ELIMINATION

MIKE CHURCH1 AND RICHARD O. LYNCH2∗

1 Harris Semiconductor, PO Box 883, Melbourne, FL 32902, USA2 Lynch Statistical Consulting, 1571 Breezewood Lane, NW Palm Bay, FL 32907, USA

SUMMARYThe first test structures built on a newly developed semiconductor process revealed that product could besusceptible to an operational fault called the snapback condition. The process architect identified five factorsthat might be adjusted to greatly reduce the occurrence of snapback. A response surface type of experiment wasrun on the process simulator so that the ideal combination of settings for these five factors could be identified.Monte Carlo simulations were then run at the new settings for those process factors. The data from the MonteCarlo simulations were analysed using partial least squares to identify the process variables that would be mostcritical to control in maintaining a snapback-resistant process. The new settings were confirmed on actual product.1998 John Wiley & Sons, Ltd.

KEY WORDS: D-optimal experiment; partial least squares (PLS); Monte Carlo simulations; snapback

BACKGROUND

MOS transistors, primarily the n-channel (NMOS), canbe prone to a failure mechanism termed snapback [1].When an NMOS transistor is inadvertently placed in thesnapback operation regime, it will draw a tremendousamount of current, typically latching the circuit into anon-operational mode. Even if the circuit continues tofunction, the reliability of the integrated circuit will likelybe compromised, since the metallization, transistor andconnected circuitry are not designed with this high cur-rent in mind.

NMOS transistor architecture

Shown in Figure1 is a typical layout of a three-stripeNMOS transistor as viewed from a cross-section. TheNMOS N+ drain electrodes (D1, D2) are electrically tiedtogether by metal lines (not shown). Similarly, the N+source electrodes (S1, S2) are electrically connected. Thegate electrodes (G1, G12, G2) are at the same potential aswell. The P Well body is common to the entire structureand is biased through the P Well body tie (BT). The N+buried layer(N + BL) is included in the architecture toisolate this transistor from others in the integrated circuit.

Consider the NMOS transistor biased in the OFF state.In this situation the N+ drain electrodes are at the highcircuit potential (5 V) and the N+ source and gate elec-trodes are at the low circuit potential (0 V). The P Wellbody is tied to 0 V through the BT and the N+BL is tiedto 5 V. In this configuration the N+ drain to P Well bodypotential is reverse biased, so no current flows.

The transistor is switched to the ON state by increas-ing the gate bias from 0 to 5 V. The act of increasingthe gate bias inverts the P Well body region under thegate electrodes from P-type to N-type. Now there is a

∗Correspondence to: R. O. Lynch, Lynch Statistical Consulting, 1571Breezewood Lane, NW Palm Bay, FL 32907, USA.

conductive channel from the N+ source to the N+ drain,so electrons flow from the N+ source to the N+ drain;or in the conventional sense, current flows from the N+drain to the N+ source. As the electrons approach theN+ drain–P Well body junction, they are accelerated bythe large electric field present at this reverse-biased junc-tion. An accelerated electron now has sufficient energyto create electron–hole pairs when it collides with thecrystal lattice. The electron and the newly freed electronare again accelerated and either leave the device throughthe N+ drain contact or collide with the lattice again,creating additional electron–hole pairs.

The interesting carrier is the hole. It is accelerated inthe opposite direction into the P Well where eventuallyit is collected by the BT. This hole current component iscommonly referred to as the NMOS transistor substratecurrent. The generation of substrate current is only amomentary event. As the conductive channel is formedbetween the N+ drain and N+ source, the N+ drainpotential begins to collapse towards the N+ source po-tential. As this happens, the N+ drain to P Well bodypotential decreases, thereby reducing the electric field.As the strength of the electric field is reduced, so gothe acceleration of the channel electron and the rate ofcreation of electron–hole pairs.

Although the substrate current is but momentary, thecollection of the substrate current is the factor leading toNMOS snapback.

Parasitic bipolar transistor

Embedded in the NMOS transistor shown in Figure1is a form of NPN bipolar transistor. This is made clearerby the re-labelling of features shown in Figure2. TheNPN collector, base and emitter are the N+ BL, P Welland N+ source respectively. Since it is not a desiredfeature of the process, we will call it ‘parasitic’. Ideally,this transistor is inactive. However, in that short moment

CCC 0748–8017/98/040227–09$17.50 Received 21 January 19981998 John Wiley & Sons, Ltd. Revised 17 March 1998

228 M. CHURCH AND R. O. LYNCH

Figure 1. NMOS transistor

Figure 2. Parasitic NPN transistor

of substrate current generation a voltage drop is createdacross the resistance of the P Well body as the substratecurrent exists through the BT. As the NMOS transistoris transitioning to the ON state, the internal voltage ofthe P Well body under an N+ source (emitter) may notbe actually 0 V as applied to the BT contact. When thispotential rises to a few tenths of a volt, the emitter–basejunction of the parasitic bipolar NPN transistor becomesforward biased and begins to become active.

Snapback scenario

As the parasitic NPN transistor becomes active, elec-trons are injected from the emitter through the base (PWell) and into the collector (N+BL). The collector–basejunction is also reverse biased, so these electrons willbe accelerated by this electric field of the collector–baseand might collide with the lattice, creating an electron–hole pair. (Note that this is a similar situation to thecreation of NMOS substrate current.) The created holesare accelerated back towards the base. Here the holescan behave in one of two ways. First, they can becomean additional component of the P Well body current andexit the transistor through the BT. If sustained, this onlytends to increase the voltage drop through the P Well bodyso that the emitter–base junction becomes more forwardbiased. Second, they can be back injected into the emit-ter. This second behaviour is ‘worse case’, because theNPN transistor action multiplies this hole current by theNPN transistor current gain (β), causingβ times as manyelectrons to be injected back into the P Well body [2].This second behaviour could accelerate the whole cycleowing to the multiplication effect. Depending on the NPNcurrent gain, the resistance from the NPN transistor to theBT and the electric field of the collector–base junction, aregenerative, positive feedback condition could exist. Ifthis is the case, the NPN transistor would become self-sustaining such that the substrate current which triggered

the event is no longer necessary. The voltage across theNPN transistor would collapse to as low as the operatingvoltage of the NPN transistor (BVceo). Since BVceo ofthis process is less than the maximum circuit operatingvoltage (5.5 V), the transistor is in the ‘snapback mode’.The only way to reverse this condition is to decrease theoperating voltage (which is still applied to the N+ BL,NPN collector) to less than BVceo. Shown in Figure3is the power supplyI–V curve of a circuit susceptibleto snapback. In this case, as the voltage is raised above8 V, internal NPN transistor(s) become active and self-sustaining. Depending on the current limitations of thepower supply, the circuitI–V will fall somewhere on theparasitic,I–V snapback curve. Only when the supply isreduced below the 5 V holding voltage will the circuitrevert to the normalI–V curve. It might appear thatapplying 8 V is excessive for a 5 V circuit, but there areother stimuli such as voltage transients, temperature, etc.which can significantly reduce the snapback triggeringvoltage to less than 8 V.

PROBLEM-SOLVING APPROACH

Because the first NMOS transistors that were built on ournew process showed a tendency to snapback, we soughta rapid remedy. Our problem-solving approach consistedof five steps as discussed below.

Step 1. Identification of factors and responses

Whether or not an NMOS transistor goes into snap-back mode is a complex question. If electron–hole pairsare not created in the NPN collector–base junction, thenthere is no mechanism for positive feedback. If most or allof the holes exit the transistor through the BT, then thereis no current to be multiplied by NPN transistor action. Ifthe NPN transistor gain is low, then the transistor actionis insufficient to sustain itself. If the resistance to the

1998 John Wiley & Sons, Ltd. Qual. Reliab. Engng. Int.14: 227–235 (1998)

STATISTICAL METHOD FOR SNAPBACK ELIMINATION 229

Figure 3.I–V curve for snapback-susceptible circuit

BT is low, then the voltage drop caused by the substratecurrent is insufficient to forward bias the NPN emitter–base junction, so snapback is not initiated. Likewise, ifthere is little or no substrate current, then snapback is alsonot initiated by the same argument.

To avoid NMOS snapback, it is desirable to:

A. Reduce the resistance to the BT. This could be ac-complished by one of three methods: (1) increasethe doping of the P Well body so that the resis-tivity of the region is lowered, (2) increase the epithickness such that the conductive path to the BT iswider or (3) move the BT closer to the origin of thesubstrate current by adding more BTs to the circuit.Method (3) is too restrictive on integrated circuitdesign (larger die sizes), so will not be consideredfurther.

B. Reduce the electric field at the NPN base–collector(P Well/N+ BL) junction. This could be accom-plished by one of two methods: (1) decrease the dop-ing of the P Well body in the vicinity of the junction(the maximum electric field at this junction is setby the region with the lower doping concentration,which, in this case is the P Well body) or (2) increasethe epi thickness such that the N+ BL is deeperand spaced further away from the peak P Well bodydoping concentration.

C. Reduce the NPN transistor action (β). This could beaccomplished by one of three methods: (1) increasethe NPN base width (increase the epi thickness),(2) increase the NPN base doping (increase the PWell body doping) or (3) decrease the NPN emitterdoping (decrease the N+ doping). The last has seri-ous negative consequences on the performance of theNMOS transistor, so will not be considered further.

D. Reduce the NMOS substrate current. This can be ac-complished to a certain degree, but with detrimentalconsequences to the NMOS transistor performance.This option will not be considered further.

Factor constraints. Based on the above, it wouldappear that snapback is a trivial problem to solve: simplyincrease the P Well body doping concentration near theN+ source/drain away from the N+ BL (reduces BTresistance and NPN transistor action) and increase the epithickness (reduces BT resistance, NPN transistor actionand the NPN collector–base electric field). If only it werethat simple! Two additional constraints must be consid-ered. Increasing the P Well body doping concentrationnear the N+ drain leads to an increase in the NMOSN+ drain to P Well body capacitance. Larger capacitanceresults in slower switching NMOS transistors, a severepenalty to pay.

Also, there are fabrication tool constraints onincreasing the epi thickness indefinitely. Front-sideimplants must be performed to provide isolation betweenN + BL regions and to create passive diodes with theN + BL. As the epi thickness increases, the naturaltolerance of the passive diode parametrics increasessuch that the diode becomes unattractive or useless. The‘slope’ parameter in the experiment outlined below refersto this parametric variation with respect to epi thicknessvariation. It is desirable to minimize ‘slope’.

Selected factors. In this process the P Well bodydoping profile actually consists of three separateimplants. The shallowest implant sets the thresholdvoltage (switching voltage) of the NMOS transistor.Because of the criticality of this parameter, this implantis fixed and not subject to adjustment. The remaining twoP Well implants, P Mid and P Deep, qualify as process



Table 1. 32-Trial experiment run on process simulator

Run DEEPE DEEPD MIDE MIDD EPI RES CAP E5DB SLOPE

1 320 4.0E+12 160 4.0E+12 4.05 18500 722 310.0 7.22 260 5.0E+12 160 1.0E+11 4.00 ∞ 578 318.0 5.83 300 1.3E+13 115 1.6E+12 4.10 4130 683 414.0 7.24 320 1.6E+13 160 1.0E+11 4.10 3740 603 455.0 7.25 300 5.0E+12 100 4.0E+12 4.15 10400 751 300.0 14.66 260 1.3E+13 100 4.0E+12 4.15 2940 832 348.0 14.67 320 1.6E+13 160 4.0E+12 3.95 5670 762 465.0 1.18 240 4.0E+12 160 1.0E+11 4.15 67100 585 241.0 14.69 240 4.0E+12 115 4.0E+12 4.10 12400 786 265.0 7.2

10 240 1.6E+13 160 4.0E+12 4.05 2540 866 412.0 7.211 320 1.6E+13 160 4.0E+12 4.15 2430 763 435.0 14.612 320 4.0E+12 100 4.0E+12 3.95 ∞ 740 269.0 1.113 300 1.6E+13 100 1.0E+11 3.95 8300 640 467.0 1.114 240 4.0E+12 160 4.0E+12 3.95 22500 761 339.0 1.115 240 1.6E+13 160 1.0E+11 3.95 4560 777 458.0 1.116 320 1.3E+13 145 1.0E+11 4.00 11400 576 435.0 5.817 300 4.0E+12 160 2.5E+11 3.95 ∞ 499 259.0 1.118 320 1.6E+13 100 4.0E+12 4.10 3010 781 455.0 7.219 240 5.0E+12 100 1.6E+12 4.00 60700 681 313.0 5.820 260 4.0E+12 100 1.0E+11 4.10 82E10 549 272.0 7.221 240 1.6E+13 100 4.0E+12 3.95 3530 886 459.0 1.122 260 4.0E+12 145 1.6E+12 4.15 20400 648 258.0 14.623 240 1.6E+13 145 2.5E+11 4.15 2730 782 341.0 14.624 260 1.3E+13 115 2.5E+11 3.95 7850 702 438.0 1.125 280 1.6E+13 130 4.0E+12 4.00 3320 823 466.0 5.826 320 7.9E+12 145 2.5E+11 4.10 12700 537 371.0 7.227 280 7.9E+12 130 6.3E+11 4.05 11500 626 367.0 7.228 320 4.0E+12 115 1.0E+11 4.15 686E13 455 285.0 14.629 240 4.0E+12 100 1.0E+11 3.95 ∞ 582 292.0 1.130 320 5.0E+12 115 1.0E+11 3.95 ∞ 475 263.0 1.131 240 1.6E+13 100 1.0E+11 4.15 2760 777 341.0 14.632 320 1.6E+13 100 6.3E+11 4.00 6420 622 468.0 5.8

steps which can be altered to affect NMOS snapback.Within these implants there are four factors, two implantdoses (DEEPD and MIDD) and two implant energies(DEEPE and MIDE), which may be independentlyvaried. The fifth process factor that we chose forexperimentation was the epi thickness (EPI).

Primary responses. While snapback elimination wasour target, our process simulator provides more funda-mental outputs such as sheet resistance, area capacitanceand field voltages. For the experiments we ran on theprocess simulator, the key responses that we sought tooptimize were the P Well resistance (RES), the NMOSN+ drain to P Well body capacitance (CAP), the NPNcollector–base electric field (E5DB) and the epi thicknesscontrol response (SLOPE). All four of these responsesneeded to be reduced to make the snapback scenario un-likely. In our final verification of our process adjustmentswe used a more direct response, our product circuit’sholding voltage (HVOLT). We needed to see the HVOLTwell above 5.5 V.

Several other responses were collected and analysedalong the way, but our work can be described well withthese primary responses.

Step 2. Experiments run on process simulator

We decided that the experimental region for our firsttrials should be:

Factor Setting rangeDEEPE 240 to 320 keVDEEPD 4E+12 to 16E+12MIDE 100 to 160 keVMIDD 1E+11 to 40E+11EPI 3.95 to 4.15 (coded)

Experimental design. All of our process simulationswere run using the SUPREM-3 simulation software [3].We chose to run a 32-trial, D-optimal experiment. Theexperimental plan is listed in Table1 along with theresponses that were collected for each trial. This was nota standard second-order D-optimal design, but was D-optimal for a quadratic model plus cubic terms. Also,candidate settings for each factor were limited to fivedistinct levels. We used RS/Discover [4] to generate thedesign. In retrospect, a design that avoids redundancy offactor levels can have benefits when the experiment is runon a computer. Alternative experimental strategies havebeen prescribed in papers by Owen [5] and Beattie andLin [6]. Further discussion of the experimental designchoice is provided at the end of this case study.

Data analysis. The two implant doses in the exper-iment were dealt with on a log scale in the experimentalplanning stage and in the subsequent data analysis. Notethat our simulator came back with resistance values ofinfinity in some of our trials. In order to proceed inanalysing that response, we used the reciprocal resistanceas a response to be maximized.



Figure 4. Statistica optimizer output



Initially, the data were analysed using the PC softwarepackage called Statistica [7]. Statistica has a multiple-response optimizing feature that is based on a desirabilityfunction [8]. This optimizing feature is similar to the onefound in the SAS/JMP [9] statistical software. In Figure4a view of the results of the Statistica optimization isprovided. In the result graphic the settings of the factorsthat are found to optimize a desirability function are an-notated at the bottom of the page. Observe from Figure4that DEEPE= 240, LDEEPD= 13.049, MIDE= 115,LMIDD = 11.6 and EPI= 4.05 is identified as an optimalcombination of factors. Also, notice on the left side ofthe graph that the predicted responses at the optimum arewritten.

Step 3. Prediction of optimal factor settings

When the desired response compromises are withinthe region of experimentation, the Statistica optimizationroutine is quite appealing. However, when a path of steep-est ascent needs to be constructed, which may involveextrapolation beyond the region of experimentation, theStatistica routine is inadequate. The path of steepest as-cent can be seen as a collection of optimal points obtainedby finding best solutions within a sequence of expandinghyper-ellipses [10]. In our case the Statistica optimizationindicated that we needed to take the DEEPE variable allthe way down to the lower bound of the search. Sincethe optimum was not in the interior of Statistica’s searchregion, we needed to construct a path of ascent.

Following techniques described in a paper byLynch [10], we identified a sequence of points that wouldfall on a path of steepest ascent, using RS/Discover.We ran follow-up process simulations for several ofthe points that were predicted to be promising. Thesefollow-up trials as well as other process constraints led usto choose the following settings for further investigation:

DEEPE= 250, DEEPD= 1.0E+13

MIDE = 0, MIDD = 0, EPI= 4.05

This solution involves dropping the P Mid implant

completely. This is an advantage since it reduces ourprocessing cycle time.

Step 4. Monte Carlo simulations test predicted solution

Using the newly identified settings of our factors, wesought to simulate the effects of natural process varia-tion on our responses. To do this, we used Monte Carlosimulations of 35 process variables. These included im-plants (doses, energies and % de-ionization levels), dif-fusions and oxidations (temperatures and times), deposi-tions (thickness amounts), epi (thickness, concentrationand auto-doping) and deglaze etch rates. We treated allthe process variables as independent and normally dis-tributed. A total of 1000 simulations were run and foreach simulation the responses were recorded.

In Figures5–7the histograms of simulated responsesare shown. These simulated distributions of the RES,CAP and E5DB were judged to be quite acceptable.

Analysis of Monte Carlo data using partial leastsquares (PLS). Using a PC software package formultivariate modelling called SIMCA-P [11], weconstructed a partial least squares [12] model forthe responses in the Monte Carlo simulation. This wasuseful for identifying the process variables that are mostimportant to control to keep the products snapback-free.In Figure8 a Pareto chart of the relative importance ofthe process variables is shown. This is based on the indexof importance called VIP in the SIMCA-P software.From the PLS analysis we found that control of epithickness will be very important, as will control of the PWell implant.

PLS is a statistical regression technique for relatinga matrix of response variables to a matrix of predictorvariables. The matrix of responses can include hundredsof correlated variables. Similarly, the matrix of predictorsmay contain hundreds of correlated variables. Inthis Monte Carlo experiment we had 35 predictorvariables, which were the manufacturing factors thatwere intentionally varied. For our responses we hadthree primary responses shown in Figures5–7 as wellas several other related responses that are not describedherein.

Figure 5. Monte Carlo of P Well capacitance



Figure 6. Monte Carlo of E5DB

Figure 7. Monte Carlo of P Well resistance

Figure 8. Pareto of process variables (indicates those most important to control)



Figure 9. Boxplot of holding voltage: old versus new process

Figure 10. Snapback experimental design projected into all pairs of factors



Step 5. Verification of improvements on a product

Our final step in eliminating snapback was to manu-facture product using the improved process. By improvedprocess, we mean the process modified to use the optimalfactor settings from Step 3. In Figure9 a boxplot ofthe measured HVOLT is shown for the old process andthe improved process. The product from the improvedprocess showed HVOLT readings well above 5 V, whilethe old process did not get above 5 V. Thus, by changingthe settings of our P Well implant and epi thickness, wewere able to eliminate snapback.

FURTHER IMPROVEMENTS

Based on these improved results, additional opportunitiesto improve the holding voltage were determined. Recentmeasurements on product have shown holding voltagesrunning above 7 V. We believe that this performance isacceptable in product designed for 5 V operations.

DISCUSSION

We used our process simulators extensively in this casestudy. This allowed us to experiment quickly and in-expensively. When experimenting with simulators, it isimportant that the process models in the simulator areaccurate. A great deal of effort that is not described inthis case study went into making our process simulatoreffective.

Our experimental design was a type of D-optimal de-sign. While it was sufficient for leading us to a solution,it was not necessarily the best design we could have used.As it turned out, the SLOPE response was only a functionof the EPI factor. Therefore the 32-trial experiment re-turned only five distinct values of SLOPE. In retrospect,it would have been better to have used a design having32 unique values of each factor. These types of uniquefactor value designs, which include randomized orthog-onal arrays and rotated factorial designs, are describedby Owen [5] and Beattie and Lin [6]. Our reason forusing the experimental design that we did choose wasthat it was easily constructed with the software we hadavailable. We chose not to run a central composite design(CCD), because we liked the more dispersed arrangementof points that we got with this D-optimal. In Figure10theexperimental design that we ran is examined in all two-variable projections. Note that more than nine combina-tions are seen in every two-way projection. Compare thatwith the projection of the CCD, also shown in Figure10.Examining the graphs in Figure10 reveals that 18 of the27 points in the CCD are redundant in a two-variableprojection, while our design had 16 redundant points outof 32 for one of the factor pairs (DEEPE versus MIDE).

The running of Monte Carlo simulations has becomequite common in the IC industry. However, our use ofPLS to model the Monte Carlo results demonstrates thatwe can glean more information than just the standard

histogram of outputs.Consider the merits of using statistical methods such

as experimental design, multiple-response optimizationand path of steepest ascent. These methods provide aneffective framework for solving the complex problemsthat occur in semiconductor process architecture. Cou-pling those methods with the use of process simulators,Monte Carlo simulations and PLS enable us to solveour tough problems rapidly and economically. Becausethe techniques we have described are effective, rapidand economical, they will be utilized in many new andcreative ways by the semiconductor industry in the yearsahead.

REFERENCES

1. B. A. Beitman, ‘n-Channel MOSFET breakdown characteristics andmodeling for p-well technologies’,IEEE Trans. Electron Devices,ED-35, 1935–1941 (1988).

2. G. W. Neudeck,The Bipolar Junction Transistor(Modular Serieson Solid State Devices, Vol. III), Addison-Wesley, Reading, MA,(1983).

3. SUPREM-3, Version 9002, Technology Modeling Associates, PaloAlto, CA, 1990.

4. RS/Discover, Release 4, Domain Solutions Corporation, Cambridge,MA, 1996.

5. A. B. Owen, ‘Orthogonal arrays for computer experiments, integra-tion and visualization’,Statist. Sinica, 2, 439–452 (1992).

6. S. D. Beattie and D. K. J. Lin, ‘Designing computer experiments: ro-tated factorial designs’,Technical report #97-06, The PennsylvaniaState University, Department of Statistics.

7. Statistica for Windows (Computer Program Manual), Tulsa, OK,1997.

8. D. Derringer and R. Suich, ‘Simultaneous optimization of severalresponse variables’,J. Qual. Technol., 12, 214–219 (1980).

9. JMP, Version 3.1, SAS Institute, Cary, NC, 1995.10. R. O. Lynch, ‘Defining the path of steepest ascent using

RS/Discover’, Paper 4,SEMATECH 12th Statistical Symp., Austin,TX, 1995.

11. SIMCA-P, Version 3.0, Umetri AB, Umea, 1996.12. S. Wold, K. Esbensen and P. Geladi, ‘Principle components analy-

sis’, Chemometrics Intell. Lab. Syst., 2, 37–52 (1987).

Authors’ biographies:

Mike Church obtained BSEE and MSEE degrees from PurdueUniversity in 1981 and 1982 respectively. He joined the CustomIntegrated Circuits Division of Harris Semiconductor in 1984 asa Device Engineer responsible for developing and characteriz-ing radiation-hardened bipolar and CMOS circuits for militaryand space applications. Since 1989 he has been a TechnologyDevelopment Process Engineer in the Semiconductor ProductsDivision of Harris Semiconductor, engaged in the integrationand development of advanced BiCMOS and linear CMOS pro-cesses for mixed signal design applications.

Richard O. Lynch received a PhD in statistics from the Uni-versity of Florida in 1986. He began at Harris Semiconductorin 1984 as a process engineer in manufacturing. During his 13years at Harris, Dr Lynch has worked in manufacturing, qualitycontrol and technology development. In 1990 he completed a 2year temporary assignment with the Statistical Methods Groupat SEMATECH. Beginning in April 1998 he will leave Harris tostart a private practice in statistical consulting and training.


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