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TRANSCRIPT
Design of a Beta-Multiplier Voltage Reference for Glucose Sensor
Mohd Ishtiaque Ibn Hossain
Department of Electrical Engineering and Computer ScienceUniversity of Tennessee, Knoxville TN, USA
18th April , 2016
Master of Science Project Defense
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Outline
Introduction and Motivation
Design of a Beta-Multiplier Voltage Reference
Changes in Reference Voltage (VREF) with Supply (VDD)
Changes in Reference Voltage (VREF) with Temperature
Changes in Reference Voltage (VREF) with Process Variation
Comparison of Beta-Multiplier Voltage Reference with Bandgap Reference
Beta-Multiplier Reference in a Voltage Regulator
Results and Discussions
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Glucose Monitor
According to World Health Organization, the number of people with diabetes was 422 million in 2014[1]
WHO projects that diabetes will be the 7th leading cause of death in 2030 Preventive treatment costs per person approximately $12000 annually
[1] http://www.who.int/mediacentre/factsheets/fs312/en/[2] http://www.medtronicdiabetes.com/products/continuous-glucose-monitoring
Glucose monitor[2]
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Block Diagram of Glucose Sensor System
Block diagram of the glucose sensor system.
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Voltage Reference
A general-use (ideal) voltage reference is a circuit used to generate a fixed voltage VREF , that is independent of power supply voltage VDD (where VREF < VDD) , temperature and process variation.
Application:Voltage references are used in regulators, which is an integral part of almost all analog and digital devices.
Voltage Reference Design Topologies:• Voltage reference using MOSFETs and resistors
For e.g. Beta Multiplier Reference• Voltage reference using parasitic diodes
Also known as Band-Gap Reference
Voltage References Design Challenges: Generate fixed voltage (VREF), that is independent of the
• Power supply • Temperature• Process variation
In short, an ideal voltage reference is independent of PVT
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Design of Voltage Reference using Beta Multiplier
R. J. Baker, CMOS Circuit Design, Layout, and Simulation, 3rd Edition, 3 edition. Piscataway, NJ : Hoboken, NJ: IEEE Press, 2010.
Voltage Reference using Beta-Multiplier Topology
VGS1 = VGS2 + IREF.Rβ2 = K. β1
IREF
VregVbiasn
VDD
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Voltage Reference using Beta Multiplier (Schematic)
Voltage Reference using Beta-Multiplier
MSU1
MSU2
MSU3
M1 M2
M3 M4
MA1 MA2
MA3 MA4
R
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Simulation Result of Voltage Reference as a function of Supply
Result: Constant VREF for varying power supply
VDD (V)
V REF (
mV)
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Simulation Result of Voltage Reference as a function of Temperature
Result: Constant VREF for varying Temperature
V REF (
mV)
Temperature (C)
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Monte Carlo Simulation of Voltage Reference as a Function of Process
Result: Average = 661.2mV, Standard Deviation = 26.9mV
VDD (V)
V REF (
mV)
VREF (mV)
No. o
f poi
nts
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Voltage Reference using Beta Multiplier (Layout)
Layout area: 33.6 X 47.31 µm2
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Monte Carlo Simulation of Voltage Reference as a Function of Mismatch
Result: Average = 660.9mV, Standard Deviation = 8.9mV VDD (V)
V REF (
mV)
VREF (mV)
No. o
f poi
nts
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Band-Gap Reference Circuit
Schematic of a Bandgap Reference circuit.
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Simulation Result of Voltage Reference as a Function of Supply
Result: Constant VREF for varying power supply
VDD (V)
V REF (
mV)
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Simulation Result of Voltage Reference as a Function of Temperature
Result: Constant VREF for varying temperature
Temperature (C)
V REF (
mV)
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Monte Carlo Simulation of Bandgap Reference as a Function of Process
Result: unstable VREF due to process variation
VDD (V)
V REF (
mV)
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Voltage Regulators Voltage Regulators A voltage regulator generates a fixed output voltage of a preset magnitude that remains constant regardless of changes to its input voltage or load conditions
Voltage Regulator topology A voltage reference is used with an op amp to generate a regulated voltage.
VREG
Schematic of a Voltage regulator circuit.
In ideal condition (op-amp has infinite open loop gain),
VREG = VREF . ( 1 + RA /RB )
Analog VLSI and Devices Laboratory 19
Voltage Regulators
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Schematic of Voltage Regulator
Schematic of a Voltage regulator circuit.
Beta-Multiplier Voltage Reference Op-Amp
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Regulator Output (VREG) Analysis
Result: for 400mV change is Supply voltage, VREG changes by 15mV
VREF
VREG
VDD (V)
V REG (V
)V RE
F (m
V)
VREG
VREF
Regulator Output (VREG) Analysis
Result: for 20°C Change in temperature, VREG changes by 8mV
VREF
VREG
Temperature (C)
V REF (
mV)
V REG (
V)
VREG
VREF
PVT corner Analysis
Result: VREF varies ±9%
VDD (V)
V REF (
mV)
Target simulatedSupply (V) 1.8 1.8VREF (mV) 660 660.7IREF (µA) 6.6
Power Consumption (µW) 11.8ΔIREF (µA) with VDD=10% around nominal value no change
ΔVREF (mV) with VDD=10% around nominal value no changeΔIREF (µA) with R=10% around nominal value 0.07
ΔVREF (mV) with R=10% around nominal value 6TCVREF (ppm/°C) 1000
TCIREF (ppm/°C) 2000Standard Deviation in Monte Carlo Simulation (1000 points) of VREF as a Function of Process (mV) 27
Standard Deviation in Monte Carlo Simulation (1000 points) of VREF as a Function of Mismatch (mV) 9 Regulator Output VREG (V) 1.1 1.11
Regulator Output VREG (V) @37°C 1.1 1.114ΔVREF (%) in PVT Corner Simulation ±9%
Summary
