usb power delivery · 2/20/2019 · usb developer days –october 24 –25, 2017 usb implementers...
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USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
USB Power DeliveryRichard Petrie – Microchip
Bob Dunstan – Renesas(Ed Berrios – ON Semiconductor)
USB Developer Days 2017
Taipei Taiwan
October 24 – 24, 2017
1
USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
Power Delivery Agenda• Introduction • Architectural Overview• Beyond USB-IF
• IEC standardized chargers • Country Codes/Country Info
• USB Type-C Port Controller• Active Cable Support• PD Authentication• PD Firmware Update• PD System Policy Manager and
Bridging• Fast Role Swap
Following the 10am break …
• Programmable Power Supply (PPS)• Protocol• Power Supply
2
Other related sessions:• USB Type-C Active Cables• USB Type-C Authentication/Firmware Update• USB Type-C Battery Charging• Bridging
USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
Introduction
• Our original vision - achieved
• Standards based charging
• Better Cabling
• Authentication
• Firmware Update
• Bridging
• Port Chips
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USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
Our original Vision…
4
65W 100W
USB Power Delivery
SSD
HDD
USB 2.0
USB 3.0
USB BC 1.2
2.5W 4.5W 7.5W
Extend ease of use, reduce clutter, reduce waste
• Power increased to 100W• Concept of universal charging being extended by IEC 63002
USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
…achieved++!• Standards-based charging
• Better Cabling
• Authentication
• Firmware Update
• Bridging
• Port Chips
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USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
Standards based charging • IEC 63002:2016
• Defines universal Chargers
• Covers laptops, tablets and PCs
• Get power from any charger to your battery
• Different charging algorithms• Fixed Voltage
• Sink Directed
• USB-IF certifies• Power adapters, Power banks, UPS’es, Higher power USB ports, Hubs, Docks…
• All can be made compliant and interoperable
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USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
Better Cabling• Discoverable, configurable cables
• Standard Cabling for all types of applications
• Double the USB bandwidth using 2 lanes
• Active cables• Support longer cabling (up to 60 m)
• Provisions for thermal management
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USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
USB Type-C Authentication• PD authentication mechanism using globally recognized techniques
• Certificates: X509v3
• Digital signing: ECDSA using NIST P256
• Hash: SHA256
• Cable authentication• Ensures that the cable’s identity is valid
• Port-to-Port authentication• E.g. Sink-to-Source or Source-to-Sink
• Ensures that the Source or Sink’s identity is valid
• The Authentication specification is included as part of the USB 3.2 release bundle found at http://www.usb.org/developers/docs/
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USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
Firmware Update• Update mechanism over PD
• Similar to USB Device Firmware Update class (DFU)
• No need to support a USB Host/Device in order to update FW
• Enables update of Sources and Sinks as required
• Specification can be found here:http://www.usb.org/developers/powerdelivery/PD_FW_Update_Specification_Rev_1_0_20160915b.pdf
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USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
Bridging
• For Hubs and other products with multiple, independent PD ports
• Enables PD status to be read
• Remote authentication and firmware update over USB via PD
• Compatible with UCSI
• USB based request/response converted to/from PD Messages
• USB Type-C Bridge Class specification can be found here:• http://www.usb.org/developers/docs/devclass_docs/USB_Type-C_Bridge_Spec.zip
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USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
Port Chips
• USB Type-C Port Chip (TCPC)
• Standalone implementation of USB Type-C states and PD Protocol
• TCPC Interface over I2C defined by specification
• Enables standard silicon implementations of the lower layers of the PD stack.
• The TCPC interface specification is included as part of the USB 3.2 release bundle found at http://www.usb.org/developers/docs/
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TCPC Interface (TCPCI)
USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
Architectural Overview
• Terminology
• Attach/Detach Detection
• Physical Layer
• PD System Overview
• Messages
• Alternate Modes
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USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
Terminology• DFP/UFP
• Defines the Port’s position in the USB topology• DFP is equivalent to A-Port/Host, UFP is equivalent to B-Port/Device• Does not imply USB Communication Capability
• Source/Sink• Defines the power role the port is currently operating in
• DRP (Dual-role Power)• Port can operate as either a Source or a Sink
• DRD (Dual-role Data)• Port can operate as either a DFP or a UFP
• USB Communications Capable• Port can send/receive USB traffic – may be asymmetric for DFP/UFP
• SOP*• Start of packet (SOP/SOP’/SOP’’)
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USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
PD SystemOverview
• Power Source/Sink (Chapter 7)• Controls power transitions
• Device Policy (Chapter 8)• Policy Engine
• Drives the Atomic Message Sequences• Device Policy Manager
• Handles PD across multiple ports• Makes decisions on how to allocate power• Talks to Power Source/Sink and Cable
Detection
• USB-C Port Control• USB Type-C state operation
(attach/detach)
• Physical Layer (Chapter 5)• Port to Port over CC wire• Collision Avoidance
• Protocol Layer (Chapter 6)• Handles retries, message construction
and chunking
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Power
Source(s)
Physical
Layer
Protocol
Source Port
Device Policy Manager
Source
Policy
Engine
Power
Sink
Physical
Layer
Protocol
Sink Port
Device Policy Manager
Sink
Policy
Engine
USB-C
Control
USB-C
Control
VBUS USB PortVBUSUSB Port CC CC
BMCBMC
CC
VBUS
USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
Attach/Detach Detection• Source (Rp asserted)
• Presence of Rd indicates port to port attach• Immediately sends Source Capabilities
• Waits for GoodCRC and Request or times out and does a Hard Reset
• Absence of Rd indicates detached state
• Sink (Rd asserted)• Presence of Vbus indicates it is attached to a Source
• Responds with GoodCRC to Source Capabilities and then sends a Request
• When VBUS is removed• During PR_Swap connection is retained
• During Hard Reset if self-powered and can operate connection is retained
• At other times this means detached
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USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
Physical Layer• Signal is DC coupled on USB Type-C CC wire
• 300 kbps half duplex communication system
• Uses Bi-mark phase Coding (BMC)
• CRC-32 used to detect data corruption
• 4b5b K-codes and 4 K-code ordered sets used for markers (SOP, EOP, Hard Reset etc.)
• USB Type-C Current (Rp) used for collision avoidance
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USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
Protocol
• Defines three types of messages:• Control Messages• Data Messages
(data payload up to 28 bytes)• Extended Data Messages
(up to 256 byte payload)
• Every packet is acknowledged with a response (GoodCRC)
• 3 tries and you are out
• Defines message usage:• Negotiating power contracts• Data/Power/VCONN role swapping• Alerts/status/extended
capabilities/identity• Alternate Mode entry/exit• Authentication• Firmware Update• Other vendor defined messages
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USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
Device Policy Manager• One instance per device
• Acts across one or more ports
• Manages bus traffic
• Manages power resources in the device
• Monitors and controls the power supply
• Interacts with the cable detection module
• Causes Policy Engine to enact policy for a given port
• Optional USB interface to System Policy
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Power
Source(s)/
Sink
Physical Layer
Protocol
Source Port
Device Policy Manager
Policy Engine
USB-C Control
System Policy
Manager
PD USB Device
USB Host
USB hub tree
(optional)
USB Interface
(optional)
USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
USB Bridge Class Specification• OSPM includes the System Policy Manager
(SPM) capability
• Provides OS visibility into Power Delivery
• System can overlay a coordinated policy on device policy
• Communication is done over USB
• Devices report capabilities
• Hubs report and allow limited control of their downstream ports
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OSPM OSAMOSFUM
USB Type-C Bridge Class Driver
Core USB Stack
xHCI
USB-C
PDUSB Host
USB-C
USB Hub logicOR
USB Device Logic
USB Type-C Bridge
USB PD Device Policy Manager (DPM)
PPM PAMPFUM
Device Container
USB PD Logic
PD Protocol Layer
PD PHY
PD Policy Engine
USB-C
PD Protocol Layer
PD PHY
PD Policy Engine
USB-C
PD Protocol Layer
PD PHY
PD Policy Engine
USB-C
USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
Bringing it all together• Negotiating power is simple and robust
• Source sends its capabilities
• Sink makes a Request
• Source Accepts and send PS_Ready
• What happens when the Sink needs more power?• Sink can indicate that it needs more power (Capability Mismatch)
• Source can read Sink’s capabilities to determine what it needs to function
• Extended capabilities used to exchange additional information between Source and Sink
• Status provides real-time operational information
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USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
Following the spec is important• Simple things can cause big problems
• Reserved bits / values• Spec requirement: Set to 0 by the sender – to be ignored by the receiver
• Rationale was to allows these bits to be used by future revisions without impacting previous revisions
• Problem seen in the field• Revision 3 APDO used for PPS defined a previously reserved value
• Some Revision 3 Sinks did not ignore the reserved value and could not properly understand the new data object and did Hard Resets
• The result is that they would not get any power from a properly operating PPS charger – Bad User Experience!
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USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
Alternate Modes• Alternate modes reconfigure the connector
• Repurpose pins to support another bus• Change the mode of operation of a bus• Enable sideband signals
• Alternate modes may reconfigure the cable• Change signal conditioning type or direction
• Note: Accessory Mode is not the same
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Full featured cable – configurable pins Direct attach – configurable pins
USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
Alternate Mode Process• Discover SVIDS
• Device/cable returns the SVIDS for which is has modes
• Discover Mode• Device/cable returns the modes is has for
each SVID
• Host evaluates the intersection of the modes it and the device/cable supports
• USB Safe State• Prevent any signaling that appears on data
wires from damaging USB PHY• May be simple isolation (mux/switch)• May be very robust PHY inputs
• Enter mode – SVID + mode
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Initiator (DFP) Responder (UFP or Cable Plug)
Discover SVIDs
List of SVIDs
Discover Modes (SVID)
Modes for SVID
For every DFP supported SVID
Modes Supported?
N Stay in USB
mode
Y
Enter Mode
ACK (Responder switched to Mode)
Initiator and Responder operate using Mode
Return to USB mode
Establish PD Contract
Exit Mode or PD Hard Reset or cable unplugged or power
removed?
Y
N
USB Safe State
USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
Failure to find an Alternate Mode• Alternate mode device does not receive an Enter Alternate Mode
command• Host does not support PD so does not look for alternate mode devices
• Host finds alternate mode devices, but does not support this particular device
• Alternate mode device presents either an ‘equivalent USB function’ and/or USB Billboard Device interface to the USB stack
• BB device provides the OS with information about the alternate mode device that it can use to inform the user that the host does not support the alternate mode
• Billboard applies to alternate mode devices and adapters• Does not apply to cables that support alternate modes.
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USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
E-Marked Cables
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USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
Multi-drop used to access cable
• Multi-drop• Packet structure unchanged• Start of packet is message ‘address’ (SOP’/SOP’’)• Limited access to the new ‘addresses’• Electronically marked cables respond to SOP’
• Only the VCONN Source can reliably talk to the cable
• Source of VCONN controlled via with VCONN_Swap
• Single initiator of multi-drop message sequences
• Cable Plug not allowed to initiate messages• Source allowed to initiate communication
SOP’ prior to an explicit contract• DFP can initiate communication SOP’/SOP’’
within an explicit contract
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DFP UFP
SOP signaling
SOP’signaling
SOP’’signaling
Cable Plug
(SOP’’)Electronically Marked Cable
Cable Plug
(SOP’)VCONN
USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
Electronically Marked Cable
Discover Identity used to get cable information
• HW/FW Version
• VDO Version
• Cable Connectors
• Cable Latency
• VCONN required
• VBUS
• Current capability
• Voltage
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SOP’
VBUS
GND
VCONN
(Not sourced)
CC
VBUS
GND
VCONN
(Sourced)
CC
DFP UFPElectronically Marked Cable
Ra Ra
Iso( )
Iso( )
• USB Support• USB 2 only
• SuperSpeed Gen 1
• SuperSpeed Gen 2
USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
Active Cables• PD Support for Active Cables
• Active Cable VDO
• Active Cable Thermal Management
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USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
PD Support for Active Cables• Active Cable info updated
• Get Status extended to SOP’ and SOP’’ to return • Operating temperature
• Thermal shutdown flag
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USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
Active Cable VDO • HW/FW Version
• VDO Version (1.1)
• USB Type-C cable / Captive cable
• Latency (proxy for length)
• VBUS
• Supported• Voltage• Current carrying capability
• SBU• Supported• Passive/Active
• SOP’’ controller
• Operating temperature
• Shutdown temperature
• USB Support • USB 2.0• USB 3.2• Lanes (one/two)• Gen1/Gen2
30
USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
Active Cable Thermal Management• Half of a plug’s thermal contribution is the result of current
• Sources and/or Sinks may manage the Active Cable’s thermal
• Source• PD Policy Manager
• Periodically reads plugs’ Status (SOP’/SOP’’)
• Compares Operating Temperature to Maximum Operating Temperature from Cable VDO
• As Operating Temperature approaches Maximum Operating Temperature, Source sends out capabilities with reduced current – Sink is required by PD to respond and reduce the current it consumes
• Sink• PD policy manager may do similar by adjusting amount of current Sink
consumes to manage plug temperature
31
USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
Fast Role Swap• Laptop behavior
• Charge-through hub behavior
32
USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
Fast Role Swap• Initial Source (Hub) has power
removed• Maintains power to downstream
peripherals • Stops sourcing power upstream• Needs new power source urgently!• Signals Fast Swap on CC line
• Initial Sink (Laptop) has 5 V Source ready to be applied quickly• Detects Fast Swap• Waits for supply to drop to 5 V• Starts Sourcing 5 V
• In parallel Port Partners start the role swap process• Ensures that Source and Sink roles are aligned
33
Hub
HDD
USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
Fast Role Swap - Laptop• Laptop reads Sink Fixed Supply PDO to see if Fast Role Swap is
supported
• Evaluates the amount of current the Sink requires to support FRS
• If can support the Sink’s requirements, it keeps its 5 V supply up and arms its FRS detection circuit
34
USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
Fast Role Swap - Hub• FRS capable pass-through hub detects removal of power
• Speculatively signals FRS by pulling CC to ground for 60 – 120 µs
• Unpowered, the Hub continues to source VBUS on its downstream ports for at least 150 µs after VBUS falls below vSafe5V
• If Laptop provides VBUS
• Hub uses it to continue powering its downstream ports• Laptop sends FR_Swap message to resynch PD
• If Laptop does not support FRS or Hub fails to Source VBUS on its downstream ports, devices will be dropped and normal USB mechanisms will be used to recover them when VBUS is reapplied
35
Fast Role Swap is a best effort mechanism
USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
Power Delivery Agenda• Introduction • Architectural Overview• Beyond USB-IF
• IEC standardized chargers • Country Codes/Country Info
• USB Type-C Port Controller• Active Cable Support• PD Authentication• PD Firmware Update• PD System Policy Manager and
Bridging• Fast Role Swap
Following the 10am break …
• Programmable Power Supply (PPS)• Protocol• Power Supply
36
USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
Power Supply
• Power Architecture Overview
• Fixed Source Review
• Programmable Power Source Review
• PPS Example
• Fast Role Swap
• Robust Port Considerations
37
USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
Example Source & Sink Configurations
38
Source
VBUSVBUSVBUSVBUS
Legacy
Power
Source
System Power
External Power
BatteryPD
Source Port
Dual-Role Power
VBUSVBUSVBUSVBUS
Legacy
Power
Source
System Power
External Power
BatteryDual-Role
Power Port
* must be self powered
Sources
Sinks
Sink
VBUS
PD
Sink Port
System Power
External Power
Battery
Dual-Role Power
VBUS
System Power
External Power
BatteryDual-Role
Power Port
* must be self powered
USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
Source Positive Transitions
39
• The voltage limits to do not apply to vSafe0V and vSafe5V
Starting voltage
vSrcNew(typ)
t0
vSrcSlewPos
tSrcSettle
vSrcValid(max)
vSrcValid(min)
Upper bound of valid Source range
vSrcNew(max)
vSrcNew(min)
tSrcReady
Lower bound of valid Source range
≈
≈
+0.5 V
105 %
95 %
−0.5 V
275 msec 285 msec
30 mV/usec
USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
Sink Load I1
vSrcNew(typ)
tSrcReady
iLoadStepRate
vSrcValid(max)
vSrcValid(min)
vSrcNew(max)
vSrcNew(min)tSrcTransient window
≈
tSrcTransient windows
≈
≈
iLoadReleaseRate
Sink Load I2
Application of vSrcNew & vSrcValid after tSrcReady
40
+0.5 V
105 %
95 %
−0.5 V
285 msec
5 msec
5 msec
150 mA/usec−150 mA/usec
USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
Transition to Increase Voltage
41
t3t1
t2Source VOLD Source VNEW
Send
Accept
Evaluate
Accept
Send
PS_RDY
Evaluate
PS_RDY
Sink ≤ IOLDSink ≤ IOLD
≤ IOLD ≤ IOLD
I1
Sink to Sink
Standby
Sink pSnkStdby
Sink Standby
to Sink
VOLD
Source
ñ V
4
1
2
3
5
6
7
Source Port
Policy Engine
Sink Port
Policy Engine
Source Port
Device Policy Mgr
Source Port
Power Supply
Sink Port
Device Policy Mgr
Sink Port
Power Supply
Source Port
Voltage
Sink Port
Current
I1 ≤ (pSnkStdby/VBUS) I2 ≤ (pSnkStdby/VBUS) + cSnkBulkPd(DVBUS/Dt)
I2
VNEW
I1
...
8
≈
PSTransitionTimer (running)
tSrcTransition
Port to Port
Messaging
Source Port
Interaction
Sink Port
Interaction
Source
VBUS Voltage
Sink
VBUS Current
USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
Transition to Increase Current
42
Source Port
Policy Engine
Send
Accept
Sink Port
Policy Engine
Evaluate
Accept
Source Port
Device Policy Mgr
Source Port
Power Supply
Sink Port
Device Policy Mgr
Sink Port
Power Supply
Send
PS_RDY
Evaluate
PS_RDY
Sink ≤ INEWt2
Source Port
Voltage
Sink Port
Current
Sink ≤ IOLD
≤ IOLD
≤ INEW
Sink
ñ I
VBUS doesn’t change
Source
ñ I
3
1
2
4
5
6
PSTransitionTimer (running)
...
7
≈
Source VOLD Source VOLD
tSrcTransition
t1
Port to Port
Messaging
Source Port
Interaction
Sink Port
Interaction
Source
VBUS Voltage
Sink
VBUS Current
USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
PPS Capabilities• New PDO Type Augmented PDO (APDO)
• Source Capability• Min/Max Voltage
• Max Current
• New RDO• Voltage between min/max
• Current Limit
• PPS Status• Operating Mode (CV/CL)
• Source voltage/current
43
USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
PPS Operation• Safety first!
• Over Current/Over Temperature protection required
• Periodic communications with Sink required
• Alerts for OC/OT events
• Sink Directed Charging• Sink periodically (at least every 10 seconds) requests Voltage/Current
• Source operates in constant voltage mode or current limit mode depending the on load
• Source provides status (operational mode, voltage and current)
• Source returns to its safe state when communications with the Sink are lost
44
USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
What is Programmable Power Supply (PPS)• Defines a method to adjust the Source output voltage in 20 mV steps
• Defines a method to adjust the Source current limit in 50 mA steps
• Current limit operation only occurs when the Sink attempts to draw more than the negotiated current level
• Current limit mode is for normal operation, not for protection
• Standard PPS voltage ranges are defined in Chapter 10
• Sinks do not transition to Sink Standby during PPS voltage changes
45
USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
Fixed Sources & Programmable Power Sources
46
Aspect Fixed Source Programmable Power Source
Constant Voltage mode(refer to Chapter 10)
5 V9 V15 V20 V
3.0 V to 5.9 V3.0 V to 11.0 V3.0 V to 16.0 V3.0 V to 21.0 V
Step Size None Nominal 20 mV
Current Limit mode None Yes, nominal 50 mA steps
Sink transition to pSnkStdby Yes – between all voltage changes No, not when operating with PPS
Periodic RDOs during operation No – does not apply Yes, needed for PPS operation
Requires Robust Port Design Yes Yes
USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
PPS = Programmable Voltage + Current Limit
• Shaded areas indicate the highest or lowest nominal output voltage or operating current PPS APDO including tolerance
• PPS APDO Min Voltage is the same value across all of the APDOs
• The sloped line during Constant Voltage mode indicates the load regulation characteristic of power converters
47
Current
Volta
ge
PPS APDO
Min Voltage
PPS APDO
Max Voltage
iPpsCLMinPPS APDO
Max Current
vPpsNew
PPS RDO
Operating Current
PPS RDO
Output Voltage
Programmable
Voltage Only
Region
Programmable Voltage &
Programmable Current Limit Region
Valid Current Limit Response
Invalid Current Limit Response
iPpsCLNew
a
Operating Mode Flag set
Operating Mode Flag cleared
iPpsCLOperating
b
c
d
USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
Coming to Terms with PPS• X-axis
• iPpsCLMin = Parameter defined in Table 7-19 as 1 A
• PPS RDO Operating Current = Requested current level Section 6.4.2
• PPS APDO Max Current = Maximum current based on PDP Section 10.2.2
• Y-axis• PPS APDO Min Voltage = Min voltage which is 3.0 V regardless of PDP
• PPS RDO Output Voltage = Requested voltage level Section 6.4.2
• PPS APDO Max Voltage = Max voltage which is defined by PDP
48
USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
Current
Vo
ltag
e
PPS APDOMin Voltage3.0 V
PPS APDOMax Voltage11.0 V
iPpsCLMin1.0 A
PPS APDO Max Current
3 A
PPS RDOOperating Current
50 mA steps
PPS RDOOutput Voltage20 mV steps
Programmable Voltage Only
Region
Programmable Voltage & Programmable Current Limit Region
Axis for PDP = Prog9V, PDP = 27 W• PPS RDO Output Voltage
step size is fixed at 20 mV nominal
• PPS RDO Operating Current step size is fixed at 50 mA nominal
• Min and max PPS range are defined by the PPS APDO
• Output voltage and operating current of the PPS is defined by the PPS RDO
• Current limiting is not defined for PPS APDOs or PPS RDOs below 1 A
49
USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
Current
Vo
ltag
e
PPS APDO
Min Voltage
PPS APDO
Max Voltage
iPpsCLMinPPS APDO
Max Current
vPpsNew
PPS RDO
Operating Current
PPS RDO
Output Voltage
20 mV steps
Programmable
Voltage Only
Region
Programmable Voltage &
Programmable Current Limit Region
a
Operating Mode Flag set
Operating Mode Flag cleared
b
Constant Voltage Segment of the PPS Curve
• The PPS RDO output voltage step size is fixed at 20 mV nominal
• The PPS RDO output voltage can be changed in single-bit or multiple-bit steps
• PPS output voltage regulation occurs to the left of the point designated as (a)
• The vPpsNew tolerance is ± 5%
50
USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
Constant Voltage – Voltage Parameters
51
vPpsCLCvTransient Operating Voltage
x 0.95 – 0.1VOperating Voltage
x 1.05 + 0.1VV
This limit only applies when a load change causes a transition from current limit mode to constant voltage mode.
vPpsCvCLTransientOperating Voltage
– 1.0VOperating Voltage
+ 0.5VV
This limit only applies when a load changes causes a transition from constant voltage mode to current limit mode.
vPpsMaxVoltageAPDO Voltage
x 0.95APDO Voltage
x 1.05V ± 5% constant voltage tolerance for all PPS voltages.
vPpsMinVoltageAPDO Voltage
x 0.95APDO Voltage
x 1.05V ± 5% constant voltage tolerance for all PPS voltages.
vPpsNewRDO Output
Voltage x 0.95RDO Output
VoltageRDO Output
Voltage x 1.05V ± 5% constant voltage tolerance for all PPS voltages.
vPpsSlewNeg −30 mV/µsThis is the same slew rate limit as the fixed supply requirements.
vPpsSlewPos 30 mV/µsThis is the same slew rate limit as the fixed supply requirements.
vPpsStep 20 mVNominal output voltage change for every LSB change of PPS RDO Output Voltage.
vPpsValid −0.1 0.1 VAdditional allowance beyond ± 5% for load step transient response. Only applies to when the PPS is in constant voltage mode before and after the load step.
USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
Constant Voltage Tolerance, Step Size & Monotonicity
• The regulation tolerance is ± 5%
• The Constant Voltage RDO steps size is 20 mV nominal
Example:
• RDO Output voltage = 4.0 V, the valid regulated range is 3.8 V to 4.2 V
• +1 LSB change of RDO increases the output voltage by 20 mV nominal• A non-positive change of the output voltage in response to +1 LSB change of
RDO violates the monotonicity requirement
52
USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
Current
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PPS APDO
Min Voltage
PPS APDO
Max Voltage
iPpsCLMinPPS APDO
Max Current
PPS RDO
Operating Current
PPS RDO
Output Voltage
Programmable
Voltage Only
Region
Programmable Voltage &
Programmable Current Limit Region
a
Operating Mode Flag set
Operating Mode Flag cleared
iPpsCLOperating
b
Current Limit Segment of the PPS Curve
• PPS shall exhibit a current limit response like the one shown in the diagram
• The opposite slope is not allowed
• PPS is not required to provide power for voltages below the PPS APDO Min Voltage, including tolerance
• PPS output current limiting shall occur below the point designated as (b)
53
USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
PPS Current Limit – Current Parameters
54
iPpsCLMin 1 ACurrent Limit mode is only required when the PPS RDO Operating current is above 1 A.
iPpsCLNew−150 +150 mA
Current Limit mode accuracy when the PPS RDO Operating Current is 1 A or greater and 3 A or less.
−5 +5 %Current Limit mode accuracy when the PPS RDO Operating Current is greater than 3 A.
iPpsCLOperating 0 +100 mARange beyond iPpsCLNew over which the current can vary during Current Limit mode.
iPpsCLStep 50 mANominal output current change for every LSB change of PPS RDO Operating Current.
iPpsCLTransient −250 +250 mARange over which the current can vary during a load transient which does not cause a transition out of Current Limit mode.
iPpsCvCLTransient −100 +500 mARange over which the current can vary during a load transient which causes a transition from Constant Voltage mode to Current Limit mode.
USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
Current
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PPS APDO
Min Voltage
PPS APDO
Max Voltage
iPpsCLMinPPS APDO
Max Current
PPS RDO
Operating Current
PPS RDO
Output Voltage
Programmable
Voltage Only
Region
Programmable Voltage &
Programmable Current Limit Region
Valid Current Limit Response
Invalid Current Limit Response
a
Operating Mode Flag set
Operating Mode Flag cleared
iPpsCLOperating
b
Good versus Bad PPS Current Limit Response
• A current limit response that goes outside of the iPpsCLOperating band is not allowed
• A current limit slope where voltage decreases with decreased load current is not allowed
• Current limit responses do not need to span the entire iPpsCLOperating band from left to right
55
USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
Current
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PPS APDO
Min Voltage
PPS APDO
Max Voltage
iPpsCLMinPPS APDO
Max Current
PPS RDO
Operating Current
PPS RDO
Output Voltage
Programmable
Voltage Only
Region
Programmable Voltage &
Programmable Current Limit Region
iPpsCLNew
a
Operating Mode Flag set
Operating Mode Flag cleared
b
Constant Voltage to Current Limit and Back• Left of point (a) the PPS output
current is below the tolerance band for a given PPS RDO Operating Current therefore is in Constant Voltage mode
• Operating Mode Flag is cleared
• Below point (b) the PPS output voltage is below the tolerance band for a given PPS RDO Output Voltage therefore is in Current Limit mode
• Operating Mode Flag is set
• The state of the Operating Mode Flag between points (a) and (b) is not defined and the operational mode is unknown
56
USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
Sink
PPS Adapter
VBUSCC
PPS Charging Example
• Conceptually the Sink controls the PPS to charge its battery
• The Sink sends periodic RDOs to keep-alive the Source ‘you must’
• In practice, the Sink must provide local regulation and battery protection
57
Sink
PPS Adapter
Local voltage & current regulation
Battery Monitoring & Safety
VBUSCC
USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
Safe Charge
58
Current
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PPS APDOMin Voltage
PPS APDOMax Voltage
iPpsCLMinPPS APDO Max Current
PPS RDOOperating Current
PPS RDOOutput Voltage
Programmable Voltage Only
Region
Programmable Voltage & Programmable Current Limit Region
a
Operating Mode Flag set
Operating Mode Flag cleared
b
Bat
tery
Cu
rren
t &
Bat
tery
Vo
ltag
e
(IBAT)
(VBAT)
safe pre constant current constant voltage eoc
PPS RDO Output Voltage
LOW battery current & LOW battery voltagePPS in Constant Voltage modeOperating Mode Flag is cleared
PPS RDO 1
PPS RDO 2
USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
Current
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PPS APDOMin Voltage
PPS APDOMax Voltage
iPpsCLMinPPS APDO Max Current
PPS RDOOperating Current
PPS RDOOutput Voltage
Programmable Voltage Only
Region
Programmable Voltage & Programmable Current Limit Region
a
Operating Mode Flag set
Operating Mode Flag cleared
b
Pre Charge
59
LOW charging current & LOW battery voltagePPS in Constant Voltage modeOperating Mode Flag is cleared
PPS RDO 1
PPS RDO 2
Bat
tery
Cu
rren
t &
Bat
tery
Vo
ltag
e
(IBAT)
(VBAT)
safe pre constant current constant voltage eoc
PPS RDO Output Voltage
USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
Current
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PPS APDO
Min Voltage
PPS APDO
Max Voltage
iPpsCLMinPPS APDO
Max Current
PPS RDO
Operating Current
PPS RDO
Output Voltage
Programmable
Voltage Only
Region
Programmable Voltage &
Programmable Current Limit Region
a
Operating Mode Flag set
Operating Mode Flag cleared
b
Start of CC Charge
60
HIGH charging current & LOW battery voltagePPS in Current Limit modeOperating Mode Flag is set
PPS RDO 1
PPS RDO 2
Bat
tery
Cu
rren
t &
Bat
tery
Vo
ltag
e
(IBAT)
(VBAT)
safe pre constant current constant voltage eoc
PPS RDO Output Voltage
USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
Progressing through CC Charge
61
HIGH charging current & INCREASING battery voltagePPS in Current Limit modeOperating Mode Flag is set
PPS RDO 1
PPS RDO 2
Bat
tery
Cu
rren
t &
Bat
tery
Vo
ltag
e
(IBAT)
(VBAT)
safe pre constant current constant voltage eoc
PPS RDO Output Voltage
Current
Vo
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e
PPS APDO
Min Voltage
PPS APDO
Max Voltage
iPpsCLMinPPS APDO
Max Current
PPS RDO
Operating Current
PPS RDO
Output Voltage
Programmable
Voltage Only
Region
Programmable Voltage &
Programmable Current Limit Region
a
Operating Mode Flag set
Operating Mode Flag cleared
b
USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
Nearing the End of CC Charge
62
HIGH charging current & HIGH battery voltagePPS in Current Limit modeOperating Mode Flag is set
PPS RDO 1
PPS RDO 2
Bat
tery
Cu
rren
t &
Bat
tery
Vo
ltag
e
(IBAT)
(VBAT)
safe pre constant current constant voltage eoc
PPS RDO Output Voltage
Current
Vo
ltag
e
PPS APDO
Min Voltage
PPS APDO
Max Voltage
iPpsCLMinPPS APDO
Max Current
PPS RDO
Operating Current
PPS RDO
Output Voltage
Programmable
Voltage Only
Region
Programmable Voltage &
Programmable Current Limit Region
a
Operating Mode Flag set
Operating Mode Flag cleared
b
USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
Current
Vo
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PPS APDO
Min Voltage
PPS APDO
Max Voltage
iPpsCLMinPPS APDO
Max Current
PPS RDO
Operating Current
PPS RDO
Output Voltage
Programmable
Voltage Only
Region
Programmable Voltage &
Programmable Current Limit Region
a
Operating Mode Flag set
Operating Mode Flag cleared
b
Start of CV Charge
63
HIGH charging current & HIGH battery voltagePPS in Constant Voltage modeOperating Mode Flag is cleared
PPS RDO 1
PPS RDO 2
Bat
tery
Cu
rren
t &
Bat
tery
Vo
ltag
e
(IBAT)
(VBAT)
safe pre constant current constant voltage eoc
PPS RDO Output Voltage
USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
Current
Vo
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e
PPS APDO
Min Voltage
PPS APDO
Max Voltage
iPpsCLMinPPS APDO
Max Current
PPS RDO
Operating Current
PPS RDO
Output Voltage
Programmable
Voltage Only
Region
Programmable Voltage &
Programmable Current Limit Region
a
Operating Mode Flag set
Operating Mode Flag cleared
b
Progressing through CV Charge
64
DECREASING charging current & HIGH battery voltagePPS in Constant Voltage modeOperating Mode Flag is cleared
PPS RDO 1
PPS RDO 2
Bat
tery
Cu
rren
t &
Bat
tery
Vo
ltag
e
(IBAT)
(VBAT)
safe pre constant current constant voltage eoc
PPS RDO Output Voltage
USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
Current
Vo
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e
PPS APDO
Min Voltage
PPS APDO
Max Voltage
iPpsCLMinPPS APDO
Max Current
PPS RDO
Operating Current
PPS RDO
Output Voltage
Programmable
Voltage Only
Region
Programmable Voltage &
Programmable Current Limit Region
a
Operating Mode Flag set
Operating Mode Flag cleared
b
Nearing the End of CV Charge
65
LOW charging current & HIGH battery voltagePPS in Constant Voltage modeOperating Mode Flag is cleared
PPS RDO 1
PPS RDO 2
Bat
tery
Cu
rren
t &
Bat
tery
Vo
ltag
e
(IBAT)
(VBAT)
safe pre constant current constant voltage eoc
PPS RDO Output Voltage
USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
Example PPS Responses
66
Bat
tery
Cu
rren
t &
Bat
tery
Vo
ltag
e
(IBAT)
(VBAT)
safe pre constant current constant voltage eoc
PPS RDO Output Voltage
Bat
tery
Cu
rren
t &
Bat
tery
Vo
ltag
e
(IBAT)
(VBAT)
safe pre constant current constant voltage eoc
PPS RDO Output Voltage
Bat
tery
Cu
rren
t &
Bat
tery
Vo
ltag
e
(IBAT)
(VBAT)
safe pre constant current constant voltage eoc
Bat
tery
Cu
rren
t &
Bat
tery
Vo
ltag
e
(IBAT)
(VBAT)
safe pre constant current constant voltage eoc
PPS RDO Output Voltage
“The Presenter” “The Cooler”
“The Nudge” “The Optimizer”
2 PPS RDOs&
Periodic RDOs
3 PPS RDOs&
Periodic RDOs
4 PPS RDOs&
Periodic RDOs
10 PPS RDOs&
Periodic RDOs
USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
PPS – What can go wrong?• Output voltage did not increment/decrement from previous value
• Output is supposed to be monotonic with 20 mV steps
• Output voltage transition times not met on large voltage changes• Upcoming ECN will relax requirement for large transitions
• Current Limit mode not supported• Required for PPS
• Minimum voltage• 3 V requirement not met• Discussions to raise the minimum voltage are underway
• PPS Status• OMF flag not properly set• Voltage/Current not reported correctly
• Response to Hard Reset• Vbus discharge to vSafe0V• Active discharge or allow to decay – inconsistent behavior
67
USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
Fast Role Swap (FRS)
1. The Notebook discovers if the Charge-thru Hub supports FRS
2. The Notebook arms itself
3. The Charge-thru Hub signals FRS to Notebook on Port 3 when the Adapter is removed
4. (a) The Notebook supplies VBUS through Port 3 when VBUSvoltage reaches vSafe5V
(b) The Port 2 VBUS is held at vSafe5V
5. PD unravels the mess !
68
NotebookAdapter
Charge-thru Hub
Port 3
USB Device
Port 1
Port 2 Hold Cap
USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
NotebookAdapter
Charge-thru Hub
Port 3
USB Device
Port 1
Port 2 Hold Cap
Power Flow during Fast Role Swap (FRS)
• Green arrows indicate progression of FRS
• Black arrows indicate direction of power flow
• FRS Objective is to keep the USB Device powered
69
Source Sink
Sink
Notebook
Charge-thru Hub
Port 3
USB Device
Port 1
Port 2 Hold Cap
Source
Sink
Notebook
Charge-thru Hub
Port 3
USB Device
Port 1
Port 2 Hold Cap
Source
Sink
Adapter Powered
Hold Capacitor Powered
Host Powered
USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
ECRs being discussed
• Increase of PPS APDO Min Voltage• Presently published at 3.0 V
• May be increased to 3.3 V
• Clarify definition of PS_RDY for PPS• 25 ms for PPS APDO voltage changes < 0.5 V
• Longer for PPS APDO voltage changes ≥ 0.5 V
70
Current
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PPS APDOMin Voltage
PPS APDOMax Voltage
iPpsCLMinPPS APDO Max Current
vPpsNew
PPS RDOOperating Current
PPS RDOOutput Voltage
Programmable Voltage Only
Region
Programmable Voltage & Programmable Current Limit Region
Valid Current Limit Response
Invalid Current Limit Response
iPpsCLNew
a
Current Limit Flag set
Current Limit Flag cleared
iPpsCLOperating
b
c
d
USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
Port Robustness Philosophy
• Sources protect themselves
• Sources shall not rely on Sinks for protection
• Sinks protect themselves
• Sinks shall not rely on Sources for protection
71
Robust Source and Sink design does not equateto regulatory safety compliance
USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
Robust Source Port Considerations
• Output Over Current Protection
• Over Temperature Protection
• vSafe5V to vSafe5V Connection
• VBUS Discharge at Detach
• PPS Expects Periodic RDOs from Sink
Note: Sources are required to protect themselves from damage. Source protection mechanisms are not expected to protect Sinks.
72
USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
Robust Sink Port Considerations
• Input Over Voltage Protection
• Over Temperature Protection
• VBUS Discharge at Detach
• Sends Periodic RDOs to PPS
Note: Sinks are required to protect themselves from damage. Sink protection mechanisms are not expected to protect Sources.
73
USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017
Q&A
74