University of Groningen

Transport at low electron density in the two-dimensional electron gas of silicon MOSFETsHeemskerk, Richard

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Chapter 3

Experimental realization

3.1 Split gate technique

In a standard MOSFET the current runs from source to drain, which areimplanted n-doped contacts. From the center of the contact to the areawhere the 2DEG is formed we have a gradual decrease in concentration ofn-type dopants crossing over to the p-type substrate doping. At low electrondensities we nd that the contact resistance increases, which hampers themeasurement of the conductivity of the 2DEG at low electron densities dueto the large changing series resistance of the contacts. Therefore a newtechnique has been developed to maintain a high electron density of the2DEG close to the doped contact areas, while in the conducting part tobe studied the electron density can be controlled independently to very lowelectron densities (ns < 1014m2). A short (narrow) interruption in thegate metallization ( 100nm) is introduced, which splits the gate into twoparts to which the voltage can be applied independently. The spread ofthe electric eld is large enough to guarantee at the interruption a gradualchange in electron density as long as the interruption is narrow.

In Sec. 3.2 the behavior of the contacts at low electron density is discussedfor samples without a split gate. In Sec. 3.4 we demonstrate the in uenceof the split gate and the reduced contact resistance of the samples with thesplit gate. Another benet of the split gate is the alternative strategy toground the measurement set up (see Sec. 3.5). The complete measurementset up is discussed in Sec. 3.6.

43

44 Chapter 3. Experimental realization

Field Oxide

Gate Oxide

Doped Area

Contact Metallization to Substrate

Gate Metallization

Hall Bar

20µm20µm

Cut through Fig. 3.2.

Figure 3.1: Topview of the layout of a doped contact. The layout showsthe gate metallization (thin line), the transition between the eld and gate

oxide (thick line), the doped area (dashed line) and the contact area of the

metallization (dotted line).

3.2 The behavior of the doped contacts

For low electron densities the conduction of the contacts decreases. In prin-ciple a high contact resistance is not a severe problem, but we nd also acurrent independent DC oset voltage between each contact pair. This osetvoltage increases gradually upon lowering the electron density and is dier-ent for each contact pair. Above an electron density of roughly 4 1015m2

this oset disappears and it can be ignored with respect to the measuredvoltage across the 2DEG. As we will show the oset voltage originates fromthe doped contact areas.

The complicated behavior can be understood from the production processand the device lay- out of the doped areas of the MOSFETs. The productionprocess is described in Appendix A. The doped area is constructed as anoverlap between the inversion layer formed below the gate oxide and themetal contact connected to the silicon substrate where the eld oxide isremoved. The distance, as shown in Fig. 3.1, is 20m. This distance istaken large to avoid a mismatch due to poor alignment in the subsequent

3.2. The behavior of the doped contacts 45

fabrication steps. We expect the electrical connection between the 2DEGand the implanted area is the bottleneck, and not this large distance.

The n-type dopant, phosphorus is implanted after the repeated oxidationsteps, but before the eld and gate oxide is grown. After implantation thesample is annealed to allow diusion and activation of the dopants. Alsothe lattice damage is repaired during this anneal. In the next step the eldoxide is grown thermally, also at the doped areas. The silicon used for thethermal oxidation is heavily doped at the contact areas. Hence the eldoxide and the gate oxide of the following growth step will also be heavilypoluted with phosphorus. Although the phosphorus has to diuse out of thesilicon converted into silicon-oxide, the dopant concentration that remainsin the oxide is still high.

In Fig. 3.2 a cut through the interface between the doped area and theinversion layer is shown. The grainness and scattered dots shown in thegure represent the phosphorus, and are meant to visualise the phosphorusconcentration in the layer. At the interface between the inversion layer andthe doped area the phosphorus concentration in the oxide is high, and thecharge in the oxide will be high as well. The phosphorous diuse in all direc-tions and a gradient in the phosphorus concentration in the undoped siliconnear the interface will develop. A similar gradient in the concentration is ex-pected in the gate oxide. The total oxide charge at the interface between thedoped and undoped area is apparently high enough to decrease the electrondensity and the ohmic contact does not function properly. (The increase inoxide charge shifts the atband and the threshold voltage locally followingthe reasoning of Chap. 2.)

The phosphorus concentration in the oxide above the doped area hasbeen calculated with a standard software routine Supreme-3, which can beused to calculate dopant proles in the vertical direction. The program isable to simulate the eects on the phosphorus concentration resulting fromthe MOSFET processing. The total phosphorus concentration in the gateoxide above the doped area is found to be 6:9 1015m2 in the 147nmthick gate oxide with a peak concentration at half the oxide thickness. Theoxide is negatively charged by the phosphorus concentration. This chargewill screen the positive potential on the gate. Hence, the electron density ofthe inversion layer at the interface between the doped area and the inversionlayer is reduced or disappears at low gate voltage completely. Consequently,the overlap between the doped area and the inversion layer has disappearedas well, and a substantial potential drop across the contact may develop.The rst signs of such a contact problem are observed at an electron density

46 Chapter 3. Experimental realization

Figure 3.2: The cut through of a contact at the interface between the doped

area and the inversion layer.

3.2. The behavior of the doped contacts 47

CgcCgcRgcRgc

Rct(Ns)Rct(Ns)

CoxCox

VgVg

VterminalVterminal 2DEG

Figure 3.3: The RC-circuit equivalent of the contact between the doped areaand the inversion layer.

of about 4 1015m2 which is comparable to the phosphorus concentrationin the gate oxide above the doped areas.

Given this contact behavior the oset voltage develops as follows. InFig.3.3 the dierent components are illustrated. Vg is the applied gate volt-age on the aluminium gate (3.2). The 2DEG is formed through the capacitivecoupling, Cox. In parallel there is a capacitive coupling to the contact, Cgc,which is leaky with a resistance Rgc (order of 10

12). In principle the resis-tance between the doped silicon contact and the undoped silicon in whichthe 2DEG is formed is small. However, for low electron density this resis-tance Rc increases and therefore a voltage drop develops due to the currentthat leaks through Rgc to the 2DEG across Rc. Therefore Vterminal indicatesa value dierent from the one expected for the 2DEG, which leads to theobserved oset voltage.

The DC oset voltage can be lowered by changing the processing of thedevices. The doped thermal oxide should be removed, and replaced by e.g.deposited PECVD oxide. This strategy to lower the DC oset voltage hasthe disadvantage that it may be dicult to maintain the quality of the MOS-FETs. As shown in Chap. 2 the quality is very sensitive to changes in theproduction. The risk of a decline in quality has been avoided by develop-ing a new technique which avoids that low electron densities are needed atthe doped areas. The technique also complicates the processing, but in-volves only structuring of the gate metallization after the basic MOSFETsare completed.

48 Chapter 3. Experimental realization

3.3 Submicron gaps to avoid low electron densities

at the doped areas

Low electron densities at the doped contacts are avoided by making an in-terruption in the gate metallization of the voltage and current leads. Anexample of this interruption is shown in Fig. 3.4, where only the gate isinterrupted. The oxide and the silicon is hardly aected by the processingand the MOSFET still works properly. The purpose of the interruption is tosplit the gate in two parts, while the inversion layer at the Si-SiO2 interfaceis continuous. The width of the interruption is small enough to allow theelectric elds of both gates to overlap. When the voltages on both gates areequal, then a small drop in electron density will occur at the interruption.We have also performed measurements at high magnetic elds to check forthe in uence of the split gate. We nd in the regime of the Integer QuantumHall eect that the transmission of the edge channels is not eected by theinterruption in the gate metallization.

In practice we like to use a large dierence in gate voltage, which leadsto a sharp drop in electron density across the interruption. When this dropin electron density is much larger than the small drop, which results fromthe geometrical variation in electric eld, we expect a monotonous changein electron density across the interruption. This is the situation used for theconductivity measurements at low electron density.

A gate split in two parts makes it possible to control the gate voltageand the electron density on each side of the interruption independently. Italso enables the control of the electron density in the leads independent ofthe rest of the device. The density is kept high in the part of the leadswith doped areas, while the center part of the sample can be varied to theextremely low electron densities required for the present experiments.

3.3.1 The processing of the submicron gaps

The interruption is made in the gate by etching a groove in the 25nm thickaluminium layer. The SiO2 layer and the silicon substrate are left unaltered.The electron density at each side of the interuption is completely controlledby the voltage applied to the gate. It is required that the siliconoxide isunaected, because it is a protection layer for the interface. When thewidth of the interruption is smaller than the thickness of the gate oxide, theelectric eld of the gates on each side will be large enough to maintain theelectron density. The thickness of the gate oxide is 147nm the interruptions

3.3. Submicron gaps to avoid low electron densities at the doped areas 49

Metal (Al)

Oxide (SiO2)

Bulk Silicon

Figure 3.4: The top gure shows the schematic top view of a MOSFET; Cur-

rent lead, part of the Hall bar with the interruption, and two side (voltage)

leads. The bottom gure is a cut through of the MOSFET at the interruption

as indicated with the arrows.

50 Chapter 3. Experimental realization

25 nm Al25 nm Al

Bare SiO2Bare SiO2

200 nm200 nm

Submicron GapSubmicron Gap

Figure 3.5: A picture made with a Scanning Electron Microscope of a sub-

micron gap at edge of the aluminium gate.

are submicron gaps with a width of 50nm to 70nm (see Fig. 3.5). Whenthe SiO2 layer and in particular the Si-SiO2 interface is undisturbed thequality of the MOSFET can be guaranteed. Therefore only etching themetal is in principle an ideal stategy. However, the process used to makethese interruptions (electron beam lithography and reactive ion etching) mayproduce charges and radiation damage. These are repaired by annealing thedevice after processing. It is comparable to the radiation damage duringthe evaporation of the aluminium with an electron gun which is also used inthe last step of the MOSFET processing, the metallization. After the gatemetallization the radiation damage is repaired by an anneal as well.

The recipe to make the submicron gaps of 50 to 70nm width in thealuminium gate with reactive ion etching is as follows. A 120nm thicksingle layer resist 4% poly-methyl-methacrylate (PMMA 2041) soaked inchlorobenzene is used for the electron beam lithography. The PMMA layeris exposed at 35 keV with a dose of 21 nC=m. For the exposure an electronbeam pattern generator mounted on a scanning electron microscope (SEM)is used. It enables alignment of the sample by using the SEM facility, afterwhich the beam can be used to write the desired pattern. After exposure thePMMA- layer is developed in a solution of methyl-iso-butyl-ketone (MIBK)and iso-propyl-alcohol (IPA) with a ratio of 3:1 for 30 seconds, followed byrinsing the sample in demiwater (2x) for 100 seconds. The 25nm thick alu-minium layer is etched at Delft Institute of Microelectronics and SubmicronTechnology (DIMES) using a locally developed recipe, which is with a gasmixture of SiCl4 (40:6sccm), Cl2 (7:3sccm), and He (17:2sccm) at a pressure

3.3. Submicron gaps to avoid low electron densities at the doped areas 51

of 10bar in 165 seconds. The ratio between SiCl4 and Cl2 is high to etchthe aluminium oxide as well. It also enhances the anisotropy. On the oth-erhand the selectivity is declined by the high aspect ratio (height : width)of the pattern in the PMMA layer. The aluminium is recrystallized duringthe last anneal step which leads to a further decline in selectivity. The poorselectivity turned out to be the bottleneck in the present processing. Theprocess can be further optimized by choosing a lower aspect ratio, e.g. below2. The etching time will be shorter and the prole of the gaps will be betterdened. After etching an anneal at T = 450oC in forming gas is used torepair damage and to reduce the oxide charge.

The aluminium etching process is based on a single layer resist, whileoften a three layer resist of photo resist, germanium, and an electron resistlayer is used. A single layer of electron resist is used here to make theprocessing easier and shorter. A three layer resist contains more processingsteps and is therefore more risky. The three layer resist is needed for thickerlayers of aluminium. In our case a 25nm thick gate is used, which can beetched easily with a single layer electron resist. As mentioned before theaspect ratio between height and width of the etching pattern should be keptlow enough. Otherwise the etching rate reduces too much. In Fig. 3.5 a50nm wide gap in the aluminium is shown.

3.3.2 The location of the submicron gaps in the devices

In Fig 3.6 a picture of a typical device lay out is shown. In the middle anarrow Hall bar of 10m is visible running from left to right. This is thelocation of the 2DEG inversion layer of which the longitudinal resistance isstudied. The two rows with rectangles above and below are the side contacts(not connected to the Hall bar) and gate bond pads (connected to the Hallbar). The Hall bar is drawn in Fig. 3.6b. The submicron gaps are indicated:there are 6 gaps made in the voltage leads numbered with 2, 3, 6, and 7and 2 gaps across the Hall bar in the current leads. One gap in the voltagelead (7) is positioned further away from the Hall bar, because there is agate connection needed to the central part of the sample. With this gateconnection the electron density in the central part is tuned. The resistanceof this part can be obtained by supplying a current through the Hall barfrom drain to source and measuring the voltage dierence between contacts3 and 2 or between contacts 6 and 7.

We have also made samples with a narrow Hall bar etched next to thesubmicron gaps in the aluminium gate. These narrow samples (2, 1 and

52 Chapter 3. Experimental realization

Drain Source

14 3 2

75 6 8

Submicron Gap Gate

Current & Voltage Leads

Hall- Bar

Figure 3.6: a. A picture which is taken from a 10m sample. b. The Hall

bar with the submicron gaps.

3.4. The in uence of the submicron gaps on the conductance 53

Figure 3.7: Picture of a sample with wide gaps (400nm) which dene a 28Hall bar with 2 current and 4 voltage leads. The leads are interrupted with

submicron gaps.

0:5m wide) are made by writing a narrow pattern in the aluminium gatemetallization. The pattern is made with the same process technology to-gether with the submicron gaps. A picture of a 28m Hall bar is shown inFig. 3.7. The pattern for the narrowest Hall bar is made by making gaps ofthe order of 400nm wide. This is large enough to have no overlap betweenthe inversion layers of both areas. Of course, during normal operation nogate voltage is applied to the areas separated from the gate bond pads. Noinversion layer will be formed, because the MOSFETs are normally o.

3.4 The in uence of the submicron gaps on the

conductance

To evaluate the properties of the submicron gaps in the gate we rst an-alyze the conductance for equal gate voltages applied on both sides of theinterruption. In Fig. 3.8 the resistance of the 2DEG is shown, obtained fromDC-measurements at dierent current values to check the linearity of theresponse. Sample A is a sample without submicron gaps, which shows alinear response to the current. It is measured until an electron density of

54 Chapter 3. Experimental realization

106

106

105

105

104

104

103

103

102

102

0 0.2 0.4 0.6

ns (1016

m-2)ns (10

16m

-2)

0.8 1.0 1.2 1.4

R (Ω

)R

(Ω)

Resistance sample:BA∆(B-A)B - R2DEG

BA∆(B-A)B - R2DEG

Figure 3.8: The resistance of the 2DEG in a MOSFET (48050 m) with(B) and without submicron gaps (A) in the voltage and current leads at

a temperature of 4.2 Kelvin. The dierence between the resistance in the

two samples is (B-A). This value corresponds to the contribution of the

submicron gaps to the resistance. This can also be calculated by subtracting

the resistance of the 2DEG based on a measurement next to the submicron

gaps from the total resistance in sample B (B-R2DEG).

8:6 1014 m2 at T = 4:2 K is reached the lowest value at which the re-sistance still showed a linear response. Sample B has submicron gaps. Thelayout is as shown in Fig. 3.6. Sample B and A are both measured with thesame four terminal DC technique, while the applied gate voltage is equal onall gates. The dierence between the measurements of sample B and A in-dicate the in uence of the submicron gaps on the resistance, shown as curve(B-A) in Fig. 3.8.

Another way to derive the in uence of the submicron gaps on the resis-tance is to subtract from the total resistance including the gaps, the resis-tance of the 2DEG which is calculated from a measurement on another partof sample B without the submicron gaps. The result is curve (B-R2DEG),which gives a comparable value as for (B-A).

3.5. Grounding of the electron gas 55

Although the measurements still show an increasing contact resistanceit is always an order of magnitude smaller than the 2DEG resistance. Thecontact resistance is further reduced to several kilo ohm when the electrondensity in the leads is set at 1016m2 and only the electron density in thecentral part is lowered. Secondly the results shown here are obtained atT = 4:2 K. Below 1 K the dierence between samples with gaps andplain MOSFETs becomes much larger. For plain MOSFETs it is dicult tomeasure at an electron density of 1 1015 m2, while for samples with gapsno dierence is found with higher temperatures.

We have not found any DC oset voltage between the dierent contactpairs, indicating that the oset voltage is indeed created at the connectionof the doped area with the 2DEG.

In passing we like to make the following comment on results reportedpreviously. Wang et al. [1] have made submicron gaps of about 100nm in atungsten gate, for a gate oxide thickness of 100nm instead of 150nm. Theyshowed conductance measurements with a submicron gap and without a sub-micron gap in zero magnetic eld. They made a correction for the dierencein the number of square resistances, but did not report any correction madefor the contact resistance between the doped area and the 2DEG. In fact thecontact resistance between the doped area and the 2DEG must dominateover the resistance of the 2DEG. Their conductance measurements Gs2 andGsd show clearly a problem with the doped contacts as well. The contactshave a higher threshold voltage for conduction than the 2DEG of about 1:7Vvs. 1:2V . The measurements show that the eect of the submicron gap hasless in uence on the conductance than the doped contacts. The dierencebetween both measurements is more likely to reveal the dierence in contactresistance than the eect of the submicron gap. Our four terminal mea-surements also show that the in uence of the gap on the resistance is muchsmaller than the resistance of the 2DEG (Fig. 3.8).

3.5 Grounding of the electron gas

The grounding of the electron gas often leads to contradictory requirements.The grounding for the gate voltage is preferred to be at one of the voltageleads, which carries no current, hence the potential in the contact is equal tothe potential of the electron gas to be measured. The gate voltage is givenby the dierence in Fermi-energy between the gate and the 2DEG, and theelectron density is well dened. On the other hand it is experimentally

56 Chapter 3. Experimental realization

Usage of gaps:Gaps not usedGaps used

Usage of gaps:Gaps not usedGaps used

108

108

107

107

106

106

105

105

104

104

0 0.2 0.4 0.6 0.8 1.0

ns (1015

m-2)ns (10

15m

-2)

R (Ω

)R

(Ω)

Figure 3.9: The two terminal resistance between drain and source in a samplewithout submicron gaps and a sample with submicron gaps of which only the

central part is lowered in electron density. The dierence in resistance is a

measure for the dierence in potential drop across the samples.

preferred to ground the current source for stability, which means that oneof the current leads is grounded.

However, when the two preferences are combined, and a current lead isgrounded and the gate voltage is applied with respect to that lead, then therewill be a voltage drop across that contact depending on the current and thecontact resistance. A sample without submicron gaps has a high contactresistance at low electron density which will change the electron density inthe 2DEG considerably, when it is grounded in this way. In a sample withgaps the total potential drop over the sample can be reduced by lowering onlythe central part of the 2DEG instead of all gates, so the contact resistanceis much lower. The dierence in total potential drop across the sample isillustrated in Fig. 3.9 .

The threshold voltage in this sample is 0:4V and an increase of 1V ingate voltage corresponds to an increase of 1:441015m2 in electron densityas follows from Eq. 2.12. At low electron density the total potential drop is

3.6. Measurement set-up for samples with submicron gaps 57

reduced by a factor of 40. Therefore we will use one of the current contactsas a grounding point for both the current source and the gate voltage. Theadvantage of one grounding point is noise reduction in the measurements.

3.6 Measurement set-up for samples with submi-

cron gaps

A complete measurement set-up is shown in Fig 3.10, only the groundingpoint has been discussed in Sec. 3.5. The Si MOSFET is placed in a cryostatwhich serves as a grounded shield. The MOSFET is not in direct contactwith the cryostat and the ground. An operational amplier with a highinput resistance is used to stabilize the potential of one of the current leadsto ground. The reason is that there is no direct connection between thesample and ground to allow for ltering of all the connections to the samplewhen the leads enter the cryostat. If a direct connection to ground wasmade for the current leads to serve as reference contact, the transit lterswould have been shortcut. This way of grounding is called virtual or activegrounding, the potential of the contact is equal to ground, but there is ahigh ohmic connection to ground. It is useful to reduce extraneous noise.

All the other leads to the sample are ltered with transit lters and alow pass lter is inserted which uses the capacitor of the transit lter. Thecuto frequency of the low pass lter is between 1kHz and 5kHz, while thetransit lters are eective beyond 1MHz. The ltering decreases the signalspicked up by the cables and the equipment outside the cryostat. When highfrequency noise enters the cryostat and enters the sample, the two dimen-sional electron gas (2DEG) will be heated and the electron temperature maybe higher than the phonon temperature. Without ltering the temperatureof the electrons in the 2DEG increases to T > 4:2K.

In Fig. 3.11 the longitudinal resistance is shown for a sample with andwithout ltering. Clearly, the ltering has a dramatic eect on the highresistance part at low electron density and hardly any eect on the lowresistance at high electron density. As will be shown in Sec. 4.3, the highresistance part depends more on temperature than the low resistance partat high electron density.

The equipment used is selected for high resistance measurements. Itconsists of a voltage source to dene the gate voltage to set the electrondensity (Sec. 4.4). A current source and a voltage meter is used to measurethe resistance in a four terminal arrangement.

58 Chapter 3. Experimental realization

Cryostat

Sample

Voltage Source

Transconductance Amp.Differential Amp.

1 2 3 4 5

Sample contacts:1. Source2. Drain3. Gate contact4. Voltage lead5. Voltage lead

Sample contacts:1. Source2. Drain3. Gate contact4. Voltage lead5. Voltage lead

Input Output

Figure 3.10: Measurement set-up as used for low electron density measure-

ments

3.6. Measurement set-up for samples with submicron gaps 59

0.4 0.6 0.8 1.0 1.2 1.4 1.6

103

104

105

106

107

Ns (1015m-2)Ns (1015m-2)

withwithout

Filter:

R(Ω)

Figure 3.11: Measurement with and without ltering at a temperature T =4:2K.

60 Chapter 3. Experimental realization

The voltage source for the gate voltage should have low noise to obtain astable gate voltage, and it should be oating. The accuracy in gate voltageneeded is about 0:5 mV . Then the noise at the output of the voltage sourceis at least one order of magnitude lower than the dierence in gate voltageused to measure the electron density. The voltage source used is a homemade programmable voltage source. It fullls both restrictions, the noiselevel is less than 0:1 mV .

The current source consists of two instruments, a programmable voltagesource and a transconductance amplier. The output noise of the transcon-ductance amplier should be very low, because the noise on the current di-rectly in uences the measured values. The noise averages a current-voltagemeasurement over the current range of the amplitude of the noise. When themeasured resistance changes strongly in the pA range the noise should be lessthan 1pA. Therefore the transconductance amplier is fed with batteries,and the input voltage of the programmable voltage source is isolated withan optocoupler to reduce the output noise. The noise of the transconduc-tance amplier arises from the output of the optocoupler (ISO122P) and theinput bias current of the amplier that controls the current (OPA121KP).The noise is typical 2pA and maximal 5pA, and is further reduced by theltering at the cryostat.

The voltage is measured after amplication with a programmable mul-timeter. Two dierential ampliers are used one at the time. The amplierused for low resistance measurements (R < 106) has an input resistanceof > 108. The high frequency noise is 1:2nV=

pHz. It is not suitable for

high resistance measurements, because of the low input resistance. There-fore a second amplier, which is home made, is used for the high resistancemeasurements. This dierential amplier is fed with batteries and has twoelectrometer inputs which are both one of the inputs of an AD549J amplierwith an inputresistance (> 1014), but a noise of 35nV=

pHz. Although the

inputresistance is high enough to measure large resistance values the signalto noise ratio is poor for low resistance measurements. E.g. for a resistance,R < 104 which is usually measured with a current in the range of 10 to100pA the noise is as large as the measured signal.

For low temperature measurement a dilution refrigerator is used witha base temperature of about 50mK. The germanium resistor, used as athermometer, is connected to a copper block in a vacuum chamber; thecopper block is cooled by the mixing liquid. The sample holder is connectedto the copper block as well, but is made of plastic to electrically isolate thesample. The wires connected to the holder which have only a thin isolation

3.7. Conclusions 61

and the wires from the sampleholder to the sample are used to transfer theheat produced in the sample to the sample holder and to the copper block.The temperature gradient over the copper block is expected to be negligible.The connection between the sampleholder and the sample is through thethin wires and the bad conducting sampleholder, which may cause a slightlyelevated temperature. The measurements at low electron densities are alltaken above T = 100mK to be sure that the temperature is not saturated.

3.7 Conclusions

The devices with submicron gaps have the benet of a small contact re-sistance, which allow us to measure at electron densities, ns < 1014m2.The low contact resistance has the additional benet that the current sourceand gate voltage can be grounded at the same point, which stabilizes themeasurement and gives noise reduction. The only signicant voltage dropalong the sample occurs when the resistance of the 2DEG is high. Then thevoltage along the sample can be of the order of 1mV and a small dierencein electron density across the sample will appear.

The measurement set up is suitable for low temperature measurementsT > 100mK. The noise is reduced by ltering of the input terminalson the cryostat with transit lters and low pass lters (cuto frequency= 1kHz to 5kHz) and by selecting the right equipment such as a low noisetransconductance amplier which is battery fed. The high resistance is mea-sured with a suitable dierential amplier. The limitation of the set up isaround R > 108 at low temperatures T < 1K. This is due to the noise ofthe transconductance amplier compared to the rapid change in resistancearound zero bias current.

References

[1] S-L. Wang, P.C. Van Son, S. Bakker, and T.M. Klapwijk. Selectivepopulation of edge states in Si-MOSFETs in the quantum Hall regimeJ. Phys : Cond.Matt., 3:4297, 1991.

62 Chapter 3. Experimental realization