united states patentcmosedu.com/jbaker/patents/us8117520.pdfconverters,” 1997, 12 pgs. (continued)...

(12) United States Patent Baker

US008117520B2

US 8,117,520 B2 Feb. 14, 2012

(10) Patent N0.: (45) Date of Patent:

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ERROR DETECTION FOR MULTI-BIT MEMORY

Inventor: R. Jacob Baker, Boise, ID (US)

Assignee: Micron Technology, Inc., Boise, ID (Us)

Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 1278 days.

Appl.No.: 11/819,000

Filed: Jun. 15, 2007

Prior Publication Data

US 2008/0313525 A1 Dec. 18, 2008

Int. Cl. H03M13/00 (2006.01) US. Cl. ..................................................... .. 714/781

Field of Classi?cation Search ................. .. 714/781

See application ?le for complete search history.

6,781,906 B2 8/2004 Perner et al. 6,785,156 B2 8/2004 Baker 6,795,359 B1 9/2004 Baker 6,798,705 B2 9/2004 Baker 6,807,403 B2 10/2004 Tanaka 6,813,208 B2 11/2004 Baker 6,822,892 B2 11/2004 Baker 6,826,102 B2 11/2004 Baker 6,829,188 B2 12/2004 Baker 6,847,234 B2 1/2005 Choi 6,850,441 B2 2/2005 Mokhlesi et al. 6,856,564 B2 2/2005 Baker 6,870,784 B2 3/2005 Baker 6,901,020 B2 5/2005 Baker 6,914,838 B2 7/2005 Baker 6,930,942 B2 8/2005 Baker 6,954,390 B2 10/2005 Baker 6,954,391 B2 10/2005 Baker 6,977,601 B1 12/2005 Fletcher et a1. 6,985,375 B2 1/2006 Baker

(Continued)

OTHER PUBLICATIONS

Rane Corporation, RaneNote 137, “Digital Charma of Audio A/D Converters,” 1997, 12 pgs.

(Continued)

Primary Examiner * Scott Baderman References Cited

Assistant Examiner * Enam Ahmed

U_S_ PATENT DOCUMENTS (74) Attorney, Agent, or Firm * Fletcher Yoder

5,600,319 A 2/1997 Ginetti 5,614,856 A 3/1997 Wilson et a1. (57) ABSTRACT 5,805,302 A * 9/1998 Enam et a1~ ~~~~~~~~~~~~~ ~~ 358/4260 Systems, methods, and devices are disclosed, including a 5 953276 A 9/1999 Baker device that includes a plurality of data locations, a quantiZing 6,044,019 A 3/2000 Cernea et al. . . . . 6,188,340 B1 2/2001 Matsumoto et a1‘ c1rcu1t coupled to the plurality of data locations, and an error 6,282,120 B1 8/2001 Cernea et a1, detection module coupled to the quantiZing circuit. In some 6,490,200 B2 12/2002 Cernea et al~ embodiments, the error detection module includes an encoder 6,504,750 B1 1/ 2003 Baker con?gured to encode incoming data With redundant data 6,567,297 B2 5/2003 Baker d - d f h - - d d d d n? d 6,661,708 B2 120003 Cernea et a1‘ er1ve rom~t e mcommg ata an a eco er co gure to 6,664,708 B2 12/2003 Shlimak et a1‘ detect errors in stored data based on the redundant data. 6,665,013 B1 12/2003 Fossum et al. 6,741,502 B1 5/2004 Cernea 21 Claims, 17 Drawing Sheets

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US 8,117,520 B2

US. PATENT DOCUMENTS

7,002,833 B2 2/2006 Hush et al. 7,009,901 B2 3/2006 Baker 7,095,667 B2 8/2006 Baker 7,102,932 B2 9/2006 Baker 7,133,307 B2 11/2006 Baker 7,366,021 B2 4/2008 Tayloret al. 7,519,898 B2* 4/2009 Narayanan et al. ......... .. 714/801

2002/0101758 A1 8/2002 Baker 2002/0194557 A1 12/2002 Park 2003/0039162 A1 2/2003 Baker 2003/0043616 A1 3/2003 Baker 2003/0067797 A1 4/2003 Baker 2003/0198078 A1 2003/0214868 A1

10/2003 Baker 11/2003 Baker

2004/0008555 A1 1/2004 Baker 2004/0032760 A1 2/2004 Baker 2004/0062100 A1 4/2004 Baker 2004/0076052 A1 4/2004 Baker 2004/0095839 A1 5/2004 Baker 2004/0151244 A1* 8/2004 Kim et al. .............. .. 375/240.03

2004/0190327 A1 9/2004 Baker 2004/0190334 A1 9/2004 Baker 2004/0199710 A1 2004/0240294 A1

10/2004 Baker 12/2004 Baker

2005/0002249 A1 1/2005 Baker 2005/0007803 A1 1/2005 Baker 2005/0007850 A1 1/2005 Baker 2005/0013184 A1 1/2005 Baker 2005/0018477 A1 1/2005 Baker 2005/0018512 A1 1/2005 Baker 2005/0041128 A1 2/2005 Baker 2005/0088892 A1 4/2005 Baker 2005/0088893 A1 4/2005 Baker 2005/0201145 A1 9/2005 Baker 2006/0013040 A1 1/2006 Baker 2006/0062062 A1 3/2006 Baker 2006/0221696 A1 10/2006 Li 2006/0227641 A1 2006/0250853 A1 2006/0291291 A1 2008/0309530 A1 2009/0172500 A1*

10/2006 Baker 11/2006 Tayloret al. 12/2006 Hosono et al. 12/2008 Baker 7/2009 Vityaev ....................... .. 714/780

OTHER PUBLICATIONS

Baker, R.J., (2001-2006) Sensing Circuits for Resistive Memory, presented at various universities and companies.

Baker, “CMOS Mixed Signal Circuit Design,” IEEE Press, A. John Wiley & Sons, Inc.; Copyright 2003, Figures 30.63, 31.82, 32.6, 32.7, 32.24, 32.51, 33.34, 33.47, 33.51, 34.18, 3424; located at http:// cmosedu.com/cmos2/book2.htrn. Dallas Semiconductor, Maxim Application Note 1870, “Demystify ing Sigma-Delta ADCs,” (Jan. 31, 2003), 15 pgs. Baker, R.J., (2003) Mixed-Signal Design in the Microelectronics Curriculum, IEEE University/Government/Industry Microelectron ics (UGIM) Symposium, Jun. 30-Jul. 2, 2003. Baker, R]. (2004) Delta-Sigma Modulation for Sensing, IEEE/EDS Workshop on Microelectronics and Electron Devices (WMED), Apr. 2004. Baker, “CMOS Circuit Design, Layout, and Simulation,” Second Edition, IEEE Press, A. John Wiley & Sons, Inc.; Copyright 2005; Chapters 13, 16, 17, 20, 22-24, 28-29; pp. 375-396, 433-522, 613 656, 711-828, 931-1022. Hadrick, M. and Baker, R.J., (2005) Sensing in CMOSImagers using Delta-Sigma Modulation, a general presentation of our Work in this area.

Baker, R]. (2005) Design ofHigh-Speed CMOS Op-Amps for Signal Processing, IEEE/EDS Workshop on Microelectronics and Electron Devices (WMED), Apr. 2005. Leslie, M.B., and Baker, R.J., (2006) “Noise-Shaping Sense Ampli ?er for MRAM Cross-Point Arrays,” IEEE Journal of Solid State Circuits, vol. 41, No. 3, pp. 699-704. Duvvada, K., Saxena, V., and Baker, R. J ., (2006) High Speed Digital Input Bu?er Circuits, proceedings of the IEEE/EDS Workshop on Microelectronics and Electron Devices (WMED), pp. 11-12, Apr. 2006.

Saxena, V., Plum, T.J., Jessing, J.R., and Baker, R. J., (2006) Design and Fabrication of a MEMS Capacitive Chemical Sensor System, proceedings of the IEEE/EDS Workshop on Microelectronics and Electron Devices (WMED), pp. 17-18, Apr. 2006. Baker, R]. and Saxena, V., (2007) Design of Bandpass Delta Sigma Modulators.‘ Avoiding Common Mistakes, presented at various uni versities and companies. Wikipedia4de?nition of “Error detection and correction”, pulled from Website Jun. 1, 2007, 9 pgs. Wikipedia4de?nition of‘Hamming code”, pulled from Website Jun. 1,2007, 8 pgs. Wikipedia4de?nition of‘Linear feedback shift register (LFSR),” pulled from Website Jun. 1, 2007, 4 pgs. Park, “Motorola Digital Signal ProcessorsiPrinciples of Sigma Delta Modulation forAnalog-to-Digital Converters,”(Undated).

* cited by examiner

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US 8,117,520 B2 1

ERROR DETECTION FOR MULTI-BIT MEMORY

BACKGROUND

1. Field of Invention Embodiments of the present invention relate generally to

error detection and, more speci?cally, in one embodiment, to error detection for a multi-bit memory.

2. Description of Related Art Generally, memory devices include an array of memory

elements and associated sense ampli?ers. The memory ele ments store data, and the sense ampli?ers read the data from the memory elements. To read data, for example, a current is passed through the memory element, and the current or a resulting voltage is measured by the sense ampli?er. Conven tionally, the sense ampli?er measures the current or voltage by comparing it to a reference current or voltage. Depending on Whether the current or voltage is greater than the reference, the sense ampli?er outputs a value of one or Zero. That is, the sense ampli?er quantiZes (e.g., digitiZes) the analog signal from the memory element into one of tWo logic states. Many types of memory elements are capable of assuming

more than just tWo states. For example, some memory ele ments are capable of muti-bit (e.g., more than tWo state) storage. For instance, rather than outputting either a high or loW voltage, the memory element may output four or eight different voltage levels, each level corresponding to a differ ent data value. HoWever, conventional sense ampli?ers often fail to distinguish accurately betWeen the additional levels because the difference betWeen the levels (e.g., a voltage difference) in a multi-bit memory element is often smaller than the difference betWeen the levels in a single-bit (i.e., tWo state) memory element. Thus, conventional sense ampli?ers often cannot read multi-bit memory elements. This problem may be increased as high performance multi-bit memory elements become increasingly dense, thereby reducing the siZe of the memory elements and the difference betWeen the levels (e.g., voltage) to be sensed by the sense ampli?ers. A variety of factors may tend to prevent the sense ampli?er

from discerning small differences in the levels of a multi-bit memory element. For instance, noise in the poWer supply, ground, and reference voltage may cause an inaccurate read ing of the memory element. The noise may have a variety of sources, such as temperature variations, parasitic signals, data dependent effects, and manufacturing process variations. This susceptibility to noise often leads a designer to reduce the number of readable states of the memory element, Which tends to reduce memory density and increase the cost of memory.

Conventional sense ampli?ers present similar problems in imaging devices. In these devices, an array of light sensors output a current or voltage in response to light impinging upon the sensor. The magnitude of the current or voltage typically depends upon the intensity of the light. Thus, the capacity of the sense ampli?er to accurately convert the cur rent or voltage into a digital signal may determine, in part, the ?delity of the captured image. Consequently, noise affecting the sense ampli?er may diminish the performance of imaging devices.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 illustrates an electronic device in accordance With an embodiment of the present invention;

FIG. 2 illustrates a memory device in accordance With an embodiment of the present invention;

20

25

30

35

40

45

50

55

60

65

2 FIG. 3 illustrates a memory array in accordance With an

embodiment of the present invention; FIG. 4 illustrates a memory element in accordance With an

embodiment of the present invention; FIG. 5 illustrates I-V traces of memory elements storing

different values, in accordance With an embodiment of the present invention;

FIG. 6 illustrates noise in the bit-line current during a read operation;

FIG. 7 illustrates a quantiZing circuit in accordance With an embodiment of the present invention;

FIG. 8 illustrates a delta-sigma sensing circuit in accor dance With an embodiment of the present invention;

FIGS. 9 and 10 illustrate current ?oW during operation of the quantiZing circuit of FIG. 8;

FIGS. 11-13 illustrate voltages in the quantiZing circuit of FIG. 8 When sensing small, medium, and large currents, respectively;

FIG. 14 is a graph of bit-line current versus counter output for the quantiZing circuit of FIG. 8;

FIG. 15 is a graph of count versus quantiZing circuit output in accordance With an embodiment of the present invention;

FIG. 16 illustrates an example of an error detection module in accordance With an embodiment of the present invention;

FIG. 17 is a ?owchart illustrating the operation of the error detection module of FIG. 16;

FIG. 18 illustrates an example of an error correction mod ule in accordance With an embodiment of the present inven tion;

FIG. 19 is a ?owchart illustrating the operation of the error correction module of FIG. 18; and

FIG. 20 illustrates an example of a system that includes the electronic device of FIG. 2.

DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS

Various embodiments of the present invention are described beloW. In an effort to provide a concise description of these embodiments, not all features of an actual implemen tation are described in the speci?cation. It should be appre ciated that in the development of any such actual implemen tation, as in any engineering or design project, numerous implementation-speci?c decisions must be made to achieve the developers’ speci?c goals, such as compliance With sys tem-related and business-related constraints, Which may vary from one implementation to another. Moreover, it should be appreciated that such a development effort might be complex and time consuming but Would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill having the bene?t of this disclosure. Some of the subsequently described embodiments may

address one or more of the problems With conventional sense ampli?ers discussed above. Some embodiments include a quantiZing circuit con?gured to detect small differences in voltages and/or currents. As explained beloW, the quantiZing circuit may sample the measured electrical parameter on mul tiple occasions and ?lter, e.g., average or sum, the samples to reduce the impact of noise. As a result, in some embodiments, the quantiZing circuit may resolve small differences betWeen voltage or current levels in multi-bit memory elements and/or light sensors, Which may alloW circuit designers to increase the number of bits stored per memory element and/ or the sensitivity of an imaging device. Some of the embodiments described herein are con?gured

to detect errors that may arise When Writing to or reading from a memory element. Speci?cally, the FIG. 16 illustrates a

united states patentcmosedu.com/jbaker/patents/us8117520.pdfconverters,” 1997, 12 pgs. (continued)...

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