unit – ii interfacing

8/3/2019 UNIT II Interfacing

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UNIT II Interfacing


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Programmable Peripheral interface -8255

Features:` Designed by Intel to interface with 8,16 bit & higher capability

microprocessor with I/O peripherals

` It has 24 i/o lines which may be programmed in to two groups of

12 lines or three groups of 8 lines` The two group i/o pins named as GROUP A and GROUP B

` Each group contains a two sub group of 8 bit i/o lines & 4 bit i/o

lines

` Group A contains an 8 bit port A along with a 4 bit port C called

Cupper

` Group B contains an 8 bit port B along with a bit port C called

Clower


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8255 Pin diagram

` PA7-PA0 buffered/latched i/o 8 bit PORT A

` PB7-PB0 buffered/latched i/o 8 bit PORT B

` PC7-PC4 Upper nibble of PORT C

` PC3-PC0 Lower nibble of PORT C

` RD Read` WR-Write

` CS-Chip Select

` A0-A1 Address Lines

` D0-D7 Data Lines carries DATA or ControlWord to/from processor

` RESET Clears control word registers


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8255 internal Architecture


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` Data Bus Buffer This bi-directional 8-bit buffer is used to interface the 8255 to the

system data bus.

Data is transmitted or received by the buffer upon execution of

input or output instructions by the CPU. Control words information is transferred through the data bus

buffer.

` Read/Write and Control Logic

This block is to manage all of the internal and external transfers ofboth Data and Control words

It accepts inputs from the CPU Address and Control busses and in

turn, issues commands to both of the Control Groups


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` (CS) Chip Select A "low" on this input pin enables the communication between

the 8255 and the CPU

` (RD) Read

A "low" on this input pin enables 8255 to send the data or

status information to the CPU on the data bus

` (WR) Write

A "low" on this input pin enables the CPU to write data or

control words into the 8255


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` (A0 andA1) Port Select 0 and Port Select 1

These input signals, in conjunction with the RD and

WR inputs, control the selection of one of the three

ports or the control word register


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Control Word Register


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` Group A and Group B Controls The CPU "outputs" a control word to the 8255

The control word contains information such as "mode", "bit set",

"bit reset", etc.

Each of the Control blocks (Group A and Group B) accepts"commands" from the Read/Write Control logic, receives "control

words" from the internal data bus and issues the proper commands

to its associated ports

` There are 2 basic modes of operations

I/O Mode (Mode 0,Mode1 & Mode2)

Bit Set Reset mode (BSR)


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BSR Mode

` In this mode any of the 8 bit of port C can be set orreset depending on D0 of the control word

` The bit to be set or reset is selected by D1,D2 & D3 of

the control word register


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` Eg: If the 5th bit (PC5) of port C has to be "SET", then what is thecontrol word?

1. Since it is BSR mode, D7 = '0'.

2. Since D4,D5,D6 are not used, assume them to be '0'.

3. PC5 has to be selected, hence, D3 = '1', D2 = '0', D1 = '1'.4. PC5 has to be set, hence, D0 = '1'.

Applying the above values to the format for BSR mode, we get the

control word as "0B (hex)".


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Mode 0(Basic I/O mode)

` Features of this mode

Two 8-bit ports ( port A and port B )and two 4-bit ports (port C upperand lower ) are available. The two 4-bit ports can be combinedly used as athird 8-bit port.

Any port can be used as an input or output port

Output ports are latched. Input ports are not latched

A maximum of four ports are available so that overall 16 I/O configuration

are possible.

All these modes can be selected by programming the Control wordregister. CWR has two formats one for BSR mode and I/O modes


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Mode 1 (Strobed I/O mode)

` In this mode hand shaking signals controls the i/o operation` Port C lines PC0,PC1 & PC2 provides the handshake signals for

port B

` Port C lines P3,PC6 & PC7 provides the handshake signals for port

A

` PC4 & PC5 can be used as independent I/O lines

Input Control Signal Definitions

` STB(Strobe input) : when it is low, data from the data lines are

loaded into the latches

` IBF (Input buffer full):if it rises high, indicates data loaded into

latches ( Acknowledgement )


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` INTR (Interrupt Request ):used to interrupt the CPU and to get theservice by the input device

` INTE is the internal flag controlled by the bit set/reset mode either

PC4 or PC2 as below


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Mode 1 Strobed Input Data Transfer


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Output control signal definition OBF(output buffer full):if low, indicates that CPU has written data to

output

ACK:acts as ack given by the output device

INTR (Interrupt request ):used to interrupt the CPU when outputdevice ack the data receipt.


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Control word of A & Control word ofB


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Mode 1 Strobed output data transfer


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Mode 2(Strobed bi directional I/O)

` Only 8 bit in group A is available` The 8 bit port A is bidirectional & have 5 bit port control

lines(PC3-PC7)

` 3 I/O lines are available at port C (PC2-PC0)

` Inputs and outputs are both latched


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Control signal definition in mode 2

` INTR(Interrupt request):used to interrupt the CPU to ask for data

transfer

Control signal for output operations

` OBF(output buffer full):If it is low ,indicates CPU has written data to

port A

` ACK:If it is low ,indicates the ack for the received byte

` INTE1(Flag associated with OBF):controlled by PC6


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Control signal for input operations` STB(strobe input) :if Low, indicates the data into the input latches

` IBF(Input buffer full):when data is loaded into input buffer, raises to 1

indicates data has been received by the receiver.

Note: WR must occur before ACK and STB must be activated beforeRD.


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Mode 2 control word & Pins


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Serial I/O Interface -8251

` Introduction To begin with serial I/O there are certain terms and acronyms has

to be explained they are

Simple ,Half duplex and full duplex

Synchronous or asynchronous In synchronous transmission data is sent in blocks at constant rates,

start and the end of blocks are identified with specific bytes or bit

pattern

In asynchronous transmission each data character has a bit which

identifies its start and 1 or 2 bits which identity its end


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` Baud Rate- indicates the rate at which serial data is beingtransferred. Given as 1/(time between signal transmission)

` Serial data transmission are slow when compared to parallel data

transmission

` Parallel data transmission requires more wires which makes difficult

for transmitting data over a long distance

` Intel introduced 8251 a programmable synchronous orasynchronous communication offen called as universal synchronous

asynchronous receiver and transmitter or USART


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` Microcomputer always deals with parallel data, Hence before doingserial communication the data has to converted into serial data

` For sending serial data over a long distance, telephone lines were

used

` For this the digital data has to converted into audio frequency

signal which can transmit through phone lines

` The device used for conversion is called a modem


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` Data and handshaking signals in sequence When the terminal is switched on, It assertsData-Terminal-Ready(DTR)

to tell the modem it is ready

Modem asserts Data-Set-Ready (DSR) to the terminal

Modem dials the remote computer ,if it is available. Terminal has acharacter ready to send, it will assert Request-To-Send (RTS) signal

The modem will send Carrier-Detect signal to the terminal indicating aconnection establishment

The modem will assert a Clear-To Send signal (CTS) back to the terminal


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8251 block diagram


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PIN Description

` D7-D0 connect system bus to device` CS-used for address decoding

` 8251 has two internal addresses, a control address(FFF2H) which is

selected when C/D is high and a data address (FFF0H)when the C/D

is low

` RD,WR,RD & RESET are connected to the system signals

` TXC,RXC transmitter clock and receiver clock for shifting the data,

used to select the frequency signal 1,16 or 64 times the baud rate

` CLK system clock signal

` TXD- indicates serial-data output

` RXD-indicates serial-data input


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` TXE-Transmitter buffer empty` TXRDY Transmitter ready (ready for char from CPU)

` RXRDY-Receiver ready (has a character for CPU)

` SYNDET/BD-Sync detect /Break detect

CONTROL WORDS

There are two types of control word and a status word

1. Mode word

2. Command word3.Status word

It is possible to see the internal status of the 8251 by reading the

Status word


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Mode Word-Asynchronous


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Mode Word Synchronous


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Command Word


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Status Word

` D0-Indicates USART is ready to accept a data character orcommand

` D1-indicates USART has received the Character and ready totransfer it to the CPU

` D2-indicates parallel to serial converter is empty

` D3-Parity error

` D4-Over Run error-Indicates CPU does not read a character beforethe next one becomes available

` D5-Framing Error-Set when valid stop is not detected

` D6-Sync Detect-Indicates that the character sync has been achieved

` D7-used to test modem condition


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DMA controller 8257

` Direct Memory Access--the ability of an I/O subsystem totransfer data to and from a memory subsystem without

processor intervention.

` DMA Controller--a device that can control data transfersbetween an I/O subsystem and a memory subsystem in

the same manner that a processor can control such

transfers


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DMA Controller Interfaced with the CPU


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Features of 8257

` It is programmable,4 channel direct memory access controller

` Each channel can programmed individually

` Each channel has a pair of 16 bit registers viz DMA address register

and terminal counter registers

` Address register gives the address of the memory location &counter specifies the number DMA cycles to be performed

` It maintains a DMA cycle count for each channel and activates theTC signal to indicate the peripheral that specified DMA cycles arecompleted


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Pin Configuration`

It has priority logic that resolves theperipheral request. Can be programmed

in two modes either fixed or rotating mode

` D0-D7( Bidirectional pins connected

to system bus

` Address Bus(A0-A3 & A4-A7)

` Address Strobe (ADSTB)-used to

demultiplex higher byte address and

data using external latch


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` Address Enable (AEN)-indicates available of higher address on the latches

` Memory Read/Memory Write(MEMR,MEMW)

` I/O Read / I/O Write (IOR,IOW)

` Chip Select(CS)

` Hold Request-it is used for requesting the CPU to get the control of the

system bus

` Hold Ack(HLDA) -indicates that CPU has granted the system bus


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` DREQ0 DREQ3 -these are DMA request

` DACK0-DACK3 these are the ack for DMA request

` Terminal Count it indicates the completion ofDMA cycle

` MARK notifies the peripherals that current DMA cycle is 128th

cycle since the previous MARK.


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Architecture of 8257


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` Data buffers-there is a 8 bit buffer which interface the 8257 tosystem bus.

In slave mode, it is used to transfer data between CPU and internal

registers of 8257

In master mode, it is used to send higher byte address on the data

bus

` DMA Channels:

8257 has 4 separate channels CH0 to CH1.each channel has a pair

of 2 16 bit registers.

Also there are two common register for all the channels namelymode set & status registers

CPU selects one of these 10 registers using address lines A0-A3


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` DMA address register- used to store the starting address of thememory location

` Terminal Count registers lower 14 bits are used count

the required number ofDMA cycles


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` T1 & T2 indicates the type ofDMA operation

` Mode Register


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` B0-B3 bits enable one of the four DMA channels

` B4(Rotating priority) - is set enables rotating priority otherwise

normal

` B6 (TC) -bit is set selected channel is disabled after the terminal

count condition is reached & further prevents any DMA cycle on

the channel

` If the TC stop bit is set to zero the channel is not disabled evenafter the count reaches zero


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` B7- auto load bit is set enables channel 2 for repeat block chainingoperation.

` Channel 2 register are reloaded with the corresponding channel 3

register for the next block transfer

` B6 (Extended write)- if set then extends the duration of MEMW

and IOW.used while interfacing with slow devices.


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Status Register

unit – ii interfacing

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