Anurag Sharma

Basics Of MP &

8085 Microprocessor Architecture

Basics of registers and counters Introduction to MP Internal data operations and

registers Pins and signals Peripheral devices Memory organization Interrupts

Contents

BASICS OF REGISTERS AND COUNTERS

Digital Logic

Combinational Logic

Sequential Logic

Combinational logic (sometimes also referred to as time-independent logic) is a type of digital logic which is implemented by Boolean circuits, where the output is a pure function of the present input only.

Sequential logic, in which the output depends not only on the present input but also on the history of the input. In other words, sequential logic has memory while combinational logic does not.

Combinational and Sequential Circuits

Sequential Logic/Circuits

We now turn to digital circuits which have states which change in time, usually according to an external clock. The flip-flop is an important element of such circuits. It has the interesting property of memory: It can be set to a state which is retained until explicitly reset.

These Logic Circuits are:1. Flip Flop2. Registers3. Counters

Latch and Flip Flop

A latch is a device with exactly two stable states. These states are high-output and low-output.

A latch has a feedback path, so information can be retained by the device. Therefore latches can be memory devices, and can store one bit of data for as long as the device is powered.

As the name suggests, latches are used to "latch onto" information and hold in place.

Latches are very similar to flip-flops, and do not operate on clock edges as flip-flops do.

RS Latch

S R Qn Qn+1

0 0 0 0

0 0 1 1

0 1 0 0

0 1 1 0

1 0 0 1

1 0 1 1

1 1 0 Meta-StableState1 1 1

Flip-flops can be either simple (transparent or opaque) or clocked (synchronous or edge-triggered); the simple ones are commonly called latches. The word latch is mainly used for storage elements, while clocked devices are described as flip-flops.

A latch is level-sensitive, whereas a flip-flop is edge-sensitive. That is, when a latch is enabled it becomes transparent, while a flip flop's output only changes on a single type (positive going or negative going) of clock edge.

R

S

CLK

Qn

Qn+1

Registers

All data must be represented in a register before it can be processed. For example, if two numbers are to be multiplied, both numbers must be in registers, and the result is also placed in a register. (The register can contain the address of a memory location where data is stored rather than the actual data itself.)

The number of registers that a CPU has and the size of each (number of bits) help determine the power and speed of a CPU. For example a 32-bit CPU is one in which each register is 32 bits wide. Therefore, each CPU instruction can manipulate 32 bits of data.

4-bit Serial Input Parallel Out Shift Register

Book

Ramesh S. Goankar, “Microprocessor Architecture, Programming and

Applications with 8085”, 5thEdition, Prentice Hall

Microcomputer – a computer with a microprocessor as its CPU. Includes memory, I/O etc.

Microprocessor – silicon chip which includes ALU, register circuits & control circuits

Microcontroller – silicon chip which includes microprocessor, memory & I/O in a single package.

What is a Microprocessor?

The word comes from the combination micro and processor.

Processor means a device that processes whatever. In this context processor means a device that processes numbers, specifically binary numbers, 0’s and 1’s.To process means to manipulate. It is a general term that describes all manipulation.

Again in this content, it means to perform certain operations on the numbers that depend on the microprocessor’s design.

Was there ever a “mini”-processor?

No.

It went directly from discrete elements to a single chip. However, comparing today’s microprocessors to the ones built in the early 1970’s you find an extreme increase in the amount of integration.

So, What is a microprocessor?

Definition of the Microprocessor

The microprocessor is a programmable device that takes in numbers, performs on them arithmetic or logical operations according to the program stored in memory and then produces other numbers as a result.

Programmable device: The microprocessor can perform different sets of operations on the data it receives depending on the sequence of instructions supplied in the given program. By changing the program, the microprocessor manipulates the data in different ways.

Instructions: Each microprocessor is designed to execute a specific group of operations. This group of operations is called an instruction set. This instruction set defines what the microprocessor can and cannot do.

What is memory?

Memory is the location where information is kept while not in current use.

Memory is a collection of storage devices. Usually, each storage device holds one bit. Also, in most kinds of memory, these storage devices are grouped into groups of 8. These 8 storage locations can only be accessed together. So, one can only read or write in terms of bytes to and from memory.

Memory is usually measured by the number of bytes it can hold. It is measured in Kilos, Megas and lately Gigas. A Kilo in computer language is 210 =1024. So, a KB (KiloByte) is 1024 bytes. Mega is 1024 Kilos and Giga is 1024 Mega.

A Microprocessor-based system

From the above description, we can draw the following block diagram to represent a microprocessor-based system:

Processor Transistor count

Date of introduction

Manufacturer Process Area

Intel 4004 2,300 1971 Intel 10 µm 12 mm²

Intel 8008 3,500 1972 Intel 10 µm 14 mm²

MOS Technology 6502

3,510 1975 MOS Technology 8 μm 21 mm²

Motorola 6800

4,100 1974 Motorola 6 μm 16 mm²

Intel 8080 4,500 1974 Intel 6 μm 20 mm²

RCA 1802 5,000 1974 RCA 5 μm 27 mm²

Intel 8085 6,500 1976 Intel 3 μm 20 mm²

An Intel 8085AH processor.

Produced From 1977 to 1990s

Common manufacturer(s) • Intel and several others

Max. CPU clock rate 3, 5 and 6 MHz

Min. feature size 3 μm

Instruction set 8080

Predecessor Intel 8080

Successor Intel 8086

Package(s) • 40 pin

Data Transfer Operation

• Load given data into register• Copy data from register to register• Copy data from register to memory• Copy data from memory location to register

• Source to Destination• Do not affect Flag Register Content?

Arithmetic Operation

• Addition: 8 bit number (content of memory location or register) can be added to accumulator and result stored in accumulator. Carry in carry flag. Two 16 bit numbers can be added using HL pair.(DAD)

• Subtraction: Same as Addition. Borrow can be stored in carry flag.

• Increment/Decrement: Content of any register, memory location, or register pair is incremented or decremented by 1 with these instructions.

Logical Operation

• Logical: ANDed, ORed, or Exclusively ORed, with the content of accumulator. Flags are affected.

• Rotate: Shifting of each bit in the accumulator either in left or right by 1 bit position.

• Compare: Comparison for equality with contents of accumulator.• Complement: Accumulator contents can be complemented.

Branching Operation

• Changes the sequence of program either conditionally or under certain test condition. Branch Instructions, subroutine calls and return instructions and restart instructions.

Stack. I/O and Machine control Operations

• Controls the stack operation, I/O operations and M/C operations.

Instruction Format

Instructions set of 8085 consists of one, two and three byte instructions. The first byte is always the opcode; in two byte instruction the second byte is usually data; in three byte instructions the last two bytes present address or 16 bit data.

Opcode Format

Opcode is unique for each instruction.

How these opcodes are written?“DDD defines the destination address, SSS defines the source register and DD defines the register pair.”

FunctionOperation Code

B7 B6 B5 B4 B3 B2 B1 B0

MVI r, Data 0 0 D D D 1 1 0

LXI rp, data 0 0 D D 0 0 0 1

MOV rd, rs 0 1 D D D S S S

Register Code

B 0 0 0

C 0 0 1

D 0 1 0

E 0 1 1

H 1 0 0

L 1 0 1

M 1 1 0

A 1 1 1

Reg. Pair Code

BC 0 0

DE 0 1

HL 1 0

AF or SP 1 1

Move Immediate 8-bit data

Instructions MVI B

Operation Code 00 DDD 110

Register Code 000

Opcode 00 000 110 06H

Move Immediate 8-bit data

Instructions MVI A

Operation Code 00 DDD 110

Register Code 111

Opcode 00 111 110 3EH

Load Immediate 16-bit data

Instructions LXI B

Operation Code 00 DD 0001

Register Code 00 0001

Opcode 00 00 0001 01H

Data Format

The operand is another name for data. It may appear in different forms:

• Addresses• Numbers/Logical data and• Character

Addresses: The address is a 16-bit unsigned integer number used to refer a memory location.

Numbers/Data: The 8085 supports following numeric data types.Signed Integer: A singed integer number is either a positive number or a negative number. In 8085, 8-bits are assigned for signed integer, in which most significant bit is used for sign and remaining seven bits are used for magnitude. Sign bit 0 indicates positive number whereas sign bit 1 indicates negative numbers.

Unsigned Numbers: The 8085 MP supports 8-bit unsigned integers too.

BCD: Registers can store 2 digit BCD numbers.

Write an assembly program to add two numbers.

Step:1 Load two Hex NumbersStep:2 Add NumbersStep:3 Store the result in memory

Start

Load two Numbers

Add Numbers

Store Result

Stop

MVI A, 20H Load 20H as a first number in registers A

MVI B, 40H Load 40H as a second number in register B

ADD B Add two numbers and save result in register A

STA 2200H Store the result in memory location 2200H

HLT Stop the program execution

Mnemonics Hex Code

MVI A, 20H 3EH Opcode

20H Operand

MVI B, 40H 06H Opcode

40H Operand

ADD B 80H Opcode

STA 2200H 32H Opcode

00H Operand(Lower Byte of Instruction)

22H Operand(Higher byte of instruction)

HLT 76H Opcode

Addressing Modes in 8085

In each instruction, programmer has to specify 3 things:◦ Operation to be performed.◦ Address of source of data.◦ Address of destination of result

The method by which the address of source of data or the address of destination of result is given in the instruction is called Addressing Modes.

The term addressing mode refers to the way in which the operand of the instruction is specified.

Intel 8085 uses the following addressing modes:

1. Direct Addressing Mode2. Register Addressing Mode3. Register Indirect Addressing Mode4. Immediate Addressing Mode5. Implicit Addressing Mode

Direct Addressing:

In direct addressing mode, effective address of the operand is given in the address field of the instruction. It requires one memory reference to read the operand from the given location and provides only a limited address space. Length of the address field is usually less than the word length. Ex : Move P, Ro, Add Q, Ro P and Q are the address of operand

LDA is the operation.2500 H is the address of source.Accumulator is the destination.

Register Addressing

Register addressing mode is similar to direct addressing. The only difference is that the address field of the instruction refers to a register rather than a memory location 3 or 4 bits are used as address field to reference 8 to 16 generate purpose registers. The advantages of register addressing are Small address field is needed in the instruction.

• In this mode, the operand is in general purpose register.• MOV is the operation.• B is the source of data.• A is the destination.

Register Indirect Addressing

This mode is similar to indirect addressing. The address field of the instruction refers to a register. The register contains the effective address of the operand. This mode uses one memory reference to obtain the operand. The address space is limited to the width of the registers available to store the effective address.

MOV is the operation.M is the memory location specified by H-L register pair.A is the destination.

Immediate Addressing

This is the simplest form of addressing. Here, the operand is given in the instruction itself. This mode is used to define a constant or set initial values of variables. The advantage of this mode is that no memory reference other than instruction fetch is required to obtain operand. The disadvantage is that the size of the number is limited to the size of the address field, which most instruction sets is small compared to word length.

MVI is the operation.05 H is the immediate data (source).A is the destination.

MVI A, 05 H Move 05 H in accumulator.

Implicit Addressing Mode

If address of source of data as well as address of destination of result is fixed, then there is no need to give any operand along with the instruction.

CMA Complement accumulator.

CMA is the operation.A is the source.A is the destination.

Instruction Sets : 8085

Various Notations:

M: Memory location pointed by HL pairr: 8 bit registerrp:16 bit register pairrs: source registerrd: destination registeraddr:16 bit address register

Data transfer instructions->

• Loads the given data into register

• Copy data from register to register

• Copy data from register to memory and vice versa

• Never affects any flag

MVI r, data(8-bit)

MVI M, data(8-bit)

MOV rd, rs

MOV M, rs

MOV rd, M

LXI rp, data(16 bit)

STA addr

LDA addr

SHLD addr

LHLD addr

STAX rp

LDAX rp

XCHG

MVI r, data(8) Move 8 bit immediate data to register r

Operation r <- 8 bit data

Description This instruction directly loads a specified register with an 8 bit data given within the instruction. The register r is an 8 bit general purpose register such as A, B, C, D, E, H, and L.

No of bytes 2 bytes

First byte: opcode of MVI r

Second byte: 8 bit data

Addressing mode

Immediate addressing mode

Flags Not affected

Example: MVI B, 60H : Instruction will load 60H directly into the B register

Before Execution

A F

B C

D E

H L

After Execution

A F

B 60 C

D E

H L

MVI M, data(8) Move 8 bit immediate data to memory whose address is in HL register pair

Operation M <- byte or (HL) <- byte

Description This instruction directly loads an 8 bit data given within the instruction into a memory location. The memory location is specified by the content of HL register pair.

No of bytes 2 bytes

First byte: opcode of MVI M

Second byte: 8 bit data

Addressing mode

Immediate and indirect addressing mode

Flags Not affected

Example: H = 20H and L = 50HMVI M, 40H

Before execution

204FH

2050H

2051H

Before execution

204FH

2050H 40

2051H

MOV rd, rs Move data from source register(rs) to destination register(rd).

Operation rd <- rs

Description This instruction copies data from the source register into destination register. The content of source register remains unchanged after execution of this instruction.

No of bytes 1 byte

First byte: opcode of MOV rd, rs

Addressing mode

Register Addressing

Flags Not affected

Example: A = 20HMOV B, A

Before Execution

A 20 B

After Execution

A 20 B 20

MOV M, rs Move data from source register(rs) to memory whose address is in HL pair.

Operation HL <- rs

Description This instruction copies data from the source register into memory location pointed by register pair HL. The content of source register remains unchanged after execution of this instruction.

No of bytes 1 byte

First byte: opcode of MOV M, rs

Addressing mode

Indirect Addressing

Flags Not affected

Example:HL = 2050H, B = 30HMOV M, B

Before Execution

A F 204DH

B 30 C 204EH

D E 204FH

H 20 L 50 2050H

After Execution

A F 204DH

B 30 C 204EH

D E 204FH

H 20 L 50 2050H 30

MOV rd, M Move data from memory location specified by HL pair to the destination register.

Operation rd <- HL

Description This instruction copies data from memory location whose address is specified by HL pair into destination register.

No of bytes 1 byte

First byte: opcode of MOV rd, M

Addressing mode

Indirect Addressing

Flags Not affected

Example MOV C, M

LXI rp, data(16)

Load 16 bit immediate data to specified register pair

Operation rp <- data(16)

Description This instruction loads immediate data specified within the instruction into register pair or stack pointer.

No of bytes 3 byte

First byte: opcode of LXI rp

Second Byte: low order byte of 16 bit data

Third Byte: higher order byte of 16 bit data

Addressing mode

Immediate Addressing

Flags Not affected

Example LXI B, 1020H

STA addr Store the content of A register at address given within the instruction.

Operation addr <- A

Description This instruction stores the content of A into the memory location whose address is directly specified within the instruction. The content of A remains unchanged.

No of bytes 3 byte

First byte: opcode of STA

Second Byte: low order byte of address

Third Byte: higher order byte of address

Addressing mode

Direct addressing

Flags Not affected

Example STA 2000H

LDA addr Load data into A register directly from the address given within the instruction.

Operation A <- addr

Description This instruction copies the content of the memory location whose address is given within the instruction into the accumulator. The content of memory remains unchanged.

No of bytes 3 byte

First byte: opcode of LDA

Second Byte: low order byte of address

Third Byte: higher order byte of address

Addressing mode

Direct addressing

Flags Not affected

Example LDA 2000H

SHLD addr Store HL register pair in memory

Operation addr <- L and (addr+1) <- H

Description This stores the content of L register in the memory location given within the instruction and content of H register at address next to it. HL content remains unchanged.

No of bytes 3 byte

First byte: opcode of SHLD

Second Byte: low order byte of address

Third Byte: higher order byte of address

Addressing mode

Direct addressing

Flags Not affected

Example SHLD 2500H

LHLD addr Load HL register pair from memory

Operation L <- addr and H <- addr+1

Description This copies the content of the memory location given within the instruction into the L register and the content of the next memory location into H register.

No of bytes 3 byte

First byte: opcode of LHLD

Second Byte: low order byte of address

Third Byte: higher order byte of address

Addressing mode

Direct addressing

Flags Not affected

Example LHLD 2500H

STAX rp Store the content of A register in memory location whose address is specified by BC or DE register pair.

Operation rp <- A

Description This instruction copies the content of the accumulator into the memory location whose address is specified by the specified register pair. The content of A remains unchanged.

No of bytes 1 Byte

First byte: opcode of STAX rp

Addressing mode

Register Indirect addressing

Flags Not affected

Example STAX B

LDAX rp Load A register with the content of memory location whose address is specified by BC or DE register pair.

Operation A <- rp

Description Copies the content of memory location whose address is specified by the register pair into the accumulator.

No of bytes 1 byte

First byte: opcode of LDAX rp

Addressing mode

Register Indirect Addressing

Flags Not affected

Example LDAX D

XCHG Exchange the content of H with D and L with E.

Operation H <-> D and L <-> E

Description Exchange the content of HL with DE

No of bytes 1 byte

First byte: opcode of XCHG

Addressing mode

Register addressing

Flags Not affected

Example XCHG

Arithmetic Group

ADD SUBTRACT DAA

INCREMENT &

DECREMENT

ADD

ADD r

ADD M

ADI data(8)ADC r

ADC M

ACI data(8)

DAD rp

ADD r Add Register r to accumulator.

Operation A<- A + r

No of bytes 1 byte

First byte: opcode of ADD r

Addressing mode

Register addressing

Flags All flags are affected

Example ADD B

ADD M Add data in memory to accumulator

Operation A<- A+M

No of bytes 1 byte

First byte: opcode of ADD M

Addressing mode

Register indirect addressing

Flags All flags are affected

Example ADD M

ADI data(8) Add immediate 8 bit data to accumulator

Operation A<- A+ data(8)

No of bytes 2 byte

First byte: opcode of ADD M

Second Byte: Data(8) bit

Addressing mode

Immediate Addressing

Flags All flags are affected

Example ADI 70H

ADC r Add register r with carry to register A

Operation A<- A+r+CY

No of bytes 1 byte

First byte: opcode of ADC r

Addressing mode

Register Addressing

Flags All flags are affected

Example ADC C

ADC M Add data in memory to accumulator with carry.

Operation A<- A+M+ CY

No of bytes 1 byte

First byte: opcode of ADC M

Addressing mode

Register Indirect Addressing

Flags All flags are affected

Example ADC M

ACI data(8) Add 8 bit immediate data to accumulator with carry.

Operation A<- A+ Data(8) + CY

No of bytes 2 byte

First byte: opcode of ADC r

Second Byte: Data(8)

Addressing mode

Immediate Addressing

Flags All flags are affected

Example ACI 20H

DAD rp Add register pair rp to HL register pair

Operation HL<- HL+ rp

No of bytes 1 byte

First byte: opcode of DAD rp

Addressing mode

Register Addressing

Flags Only carry flag is affected.

Example DAD D

SUBTRACT

SUB R

SUB M

SUI Data

SBB r

SBB M

SBI Data

SUB r Subtract specified register from Accumulator

Operation A<- A- r

No of bytes 1 byte

First byte: opcode of SUB r

Addressing mode Register Addressing

Flags All Flags are affected

Example SUB B

SUB M Subtract data in memory from accumulator.

Operation A<- A- M

No of bytes 1 byte

First byte: opcode of SUB M

Addressing mode Register Indirect Addressing

Flags All Flags are affected

Example SUB M

SUI data(8) Subtract 8 bit immediate data from the accumulator.

Operation A<- A- data(8)

No of bytes 2 byte

First byte: opcode of SUI

Second Byte: Data 8 Bit

Addressing mode Immediate Addressing

Flags All Flags are affected

Example SUI 40H

SBB r Subtract specified register and borrow flag from accumulator.

Operation A<- A- r-CY

No of bytes 1 byte

First byte: opcode of SBB r

Addressing mode Register Addressing

Flags All Flags are affected

Example SBB C

SBB M Subtract memory data and borrow flag from accumulator.

Operation A<- A-M-CY

No of bytes 1 byte

First byte: opcode of SUB M

Addressing mode Register Indirect Addressing

Flags All Flags are affected

Example SBB M

SBI data(8) Subtract 8 bit immediate data and borrow flag from accumulator

Operation A<- A- Data(8)-CY

No of bytes 2 byte

First byte: opcode of SUB r

Second Byte: Data 8 bit

Addressing mode Immediate Addressing

Flags All Flags are affected

Example SBI 20H

DAA This instruction adjusts accumulator to packed BCD after adding two BCD Numbers.

Instruction works as follow: 1. If the value of the low order four bits in the A is greater than 9 or if

auxiliary carry flag is set, the instruction adds 6(06) to the low order four bits.

2. If the value of the high order four bits in the A is greater than 9 or if carry flag is set, the instruction adds 6 to the high order four bits.

Example: if A = 0011 1001 = 39 BCDAnd C = 0001 0010 = 12 BCD thenADD C; gives A = 0100 1011 = 4BHDAA; adds 0110 because 1011 > 9, A = 0101 0001 = 51 BCD

No of Bytes 1 Bytes

First Byte: Opcode of DAA

Addressing mode Immediate Addressing

Increment &

Decrement

INR r Increment specified register

Operation r <- r + 1

No of bytes 1 byte

First byte: opcode of INR r

Addressing mode Register Addressing

Flags All Flags except carry flag are affected

Example INR B

INR M Increment data in memory.

Operation M <- M + 1

No of bytes 1 byte

First byte: opcode of INR M

Addressing mode Register Indirect Addressing

Flags All Flags except carry flag are affected

Example INR M

INX rp Increment specified register pair

Operation rp <- rp + 1

No of bytes 1 byte

First byte: opcode of INX rp

Addressing mode Register Addressing

Flags No flags are affected

Example INX H

DCR r Decrement specified register

Operation r <- r – 1

No of bytes 1 byte

First byte: opcode of DCR r

Addressing mode Register Addressing

Flags All Flags except carry flag are affected

Example DCR B

DCR M Decrement data in memory

Operation M <- M-1

No of bytes 1 byte

First byte: opcode of DCR M

Addressing mode Register Indirect Addressing

Flags All Flags except carry flag are affected

Example DCR M

DCX rp Decrement specified register pair

Operation rp<- rp-1

No of bytes 1 byte

First byte: opcode of DCX rp

Addressing mode Register Addressing

Flags No flags are affected

Example DCX D

Branching Instructions

• The branching instruction alter the normal sequential flow.

• These instructions alter either unconditionally or conditionally.

Branch Instruction

Jump Instructions

Call & Return Instruction

Restart Instruction

JMP addr Jump unconditionally to the address

Operation PC<- addr

No of bytes 3 byte

First byte: opcode of JMP addr

Second Byte: Address lower byte

Third Byte: Address higher Byte

Addressing mode Immediate Addressing

Flags No flags are affected

Example JMP2000H

Jcondition addr: Jump conditionally to address.Operation: if condition is true PC<- addr else PC<- PC+3Instruction code Description Condition for jump

JC Jump on carry CY=0

JNC Jump on not carry CY != 0

JP Jump on positive S=0

JM Jump on minus S=1

JPE Jump on parity even P=1

JPO Jump on parity odd P=0

JZ Jump on zero Z=1

JNZ Jump on not zero Z=0

No of bytes: 3 bytesAddressing mode: immediate addressing modeFlags are not affectedE.g. JC 2000H

PCHL Load HL content into program counter

Operation PC<- HL

No of bytes 1 byte

First byte: opcode of PCHL

Addressing mode Register Addressing

Flags No flags are affected

Example PCHL

Unconditional subroutine call

CALL 16-bit address The program sequence is transferred to the memory location specified by the 16-bit address given in the operand. Before the transfer, the address of the next instruction after CALL (the contents of the program counter) is pushed onto the stack.

Example: CALL 2034H or CALL XYZ

Opcode Operand DescriptionCx 16-bit address Call conditionally

The program sequence is transferred to the memory location specified by the 16-bit address given in the operand based on the specified flag of the PSW.

Before the transfer, the address of the next instruction after the call (the contents of the program counter) is pushed onto the stack.

Example: CZ 2034 H.

Logic •1 bit logical operations

Rotate •Rotate the content of Register

Logic Instructions

Instruction Operation No of

BytesAddr. Mode Flags Example

ANA r A<-a^r 1 Register All affected ANA B

ANA M A<-A^M 1 Reg. Indirect

All Affected ANA M

ANI Data A<-A^data 2 Immediate All Affected ANI 3FH

XRA r A<-A r 1 Register All Affected XRA C

XRA M A<- A M 1 Reg. Indirect

All Affected XRA M

XRI data A <-A data 2 Immediate All Affected XRI BA H

ORA r A<- A v r 1 Register All Affected ORA D

ORA M A<- A v M 1 Reg. Indirect

All Affected ORA M

ORI Data A<- A v Data

2 Immediate All Affected ORI 4CH

CMP r A – r 1 Register All Affected CMP D

If A>r CY=0, Z=0; A=r, CY=0, Z=1; A<r, CY=1, Z=0

CMP M A-M 1 Reg. Indirect

All Affected CMP M

CPI Data A-data 2 Immediate All Affected CPI 40H

STC CY<-1 1 CY Flag STC

CMC CY<-CY’ 1 CY Flag CMC

CMA A<-A’ 1 Implied Not Affected

CMA

Instruction Operation No of

BytesAddr. Mode Flags Exampl

e

RLC Rotate A Left 1 Implied CY Affected RLC

RRC Rotate A Right

1 Implied CY Affected RRC

RAL Rotate A Left Through Carry

1 Implied CY Affected RAL

RAR Rotate A Right Through Carry

1 Implied CY Affected RAR

Stack Operations, I/O and

Machine Control Group

LXI SP, data Before execution of any stack related instruction, stack pointer must be initialized with a valid memory address.

There are two ways to initialize the SP.

Direct Way LXI SP, data(16); load 16 bit data into SP

Indirect Way LXI H, data(16); load 16 bit data into HL

SPHL Load the content of HL into SP.

Since the 8085’s stack pointer is decremented before data is written to the stack, the stack pointer can actually be initialized to a value one higher than the highest read/write memory.

Software Delay

In real time applications like traffic light control, digital clock etc. its important to keep track with time. In MP its necessary to give a delay between execution of two instructions.

The MP consists of two basic areas Software and Hardware. Software is essential to control and operate the hardware to get the desired output in time. Each instruction requires fix time to be executed.

Each instruction passes through different combinations of Fetch, Memory Read, and Memory Write cycles. Knowing the combinations of cycles, one can calculate how long such an instruction would require to complete.

The table in Appendix F of the book contains a column with the title B/M/T.B for Number of BytesM for Number of Machine CyclesT for Number of T-State.

Knowing how many T-States an instruction requires, and keeping in mind that a T-State is one clock cycle long, we can calculate the time using the following formula:

Delay = No. of T-States / Frequency

For example a “MVI” instruction uses 7 T-States. Therefore, if the Microprocessor is running at 2 MHz, the instruction would require 3.5 μ Seconds to complete.

Delay Using NOP Instruction

NOP instruction does nothing but takes 4T states processor time to execute. So by executing NOP between two instructions we can get a time delay of 4T states.

Delay using counters

Counting can create time delay. Since the execution time of instructions is known, the initial value of the counter, required to get specific time delay can be determined.

Using 8 Bit Counter:

Instructions

T States

MVI C, count

Load Count 7

Back: DCR C Decrement Count 4

JNZ Back Jump Back if Count not equals to Zero.

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