unit i mos transistor theory and process technology
TRANSCRIPT
![Page 1: UNIT I MOS TRANSISTOR THEORY AND PROCESS TECHNOLOGY](https://reader035.vdocuments.mx/reader035/viewer/2022062309/56649f355503460f94c527de/html5/thumbnails/1.jpg)
UNIT IMOS TRANSISTOR THEORY
AND PROCESS TECHNOLOGY
![Page 2: UNIT I MOS TRANSISTOR THEORY AND PROCESS TECHNOLOGY](https://reader035.vdocuments.mx/reader035/viewer/2022062309/56649f355503460f94c527de/html5/thumbnails/2.jpg)
TOPICS
• NMOS and PMOS transistors • Threshold voltage • Body effect • Design equations• Second order effects • MOS models• Small signal AC characteristics • Basic CMOS technology
![Page 3: UNIT I MOS TRANSISTOR THEORY AND PROCESS TECHNOLOGY](https://reader035.vdocuments.mx/reader035/viewer/2022062309/56649f355503460f94c527de/html5/thumbnails/3.jpg)
MOS TRANSISTOR• MOS Metal Oxide Semiconductor• MOS transistor is a majority carrier device,
current is the conducting channel b/w source & drain.
• 2 types of MOS transistor:n-MOS transistorp-MOS transistor
• Various symbol representation for n-MOS & p-MOS
![Page 4: UNIT I MOS TRANSISTOR THEORY AND PROCESS TECHNOLOGY](https://reader035.vdocuments.mx/reader035/viewer/2022062309/56649f355503460f94c527de/html5/thumbnails/4.jpg)
n-MOS
![Page 5: UNIT I MOS TRANSISTOR THEORY AND PROCESS TECHNOLOGY](https://reader035.vdocuments.mx/reader035/viewer/2022062309/56649f355503460f94c527de/html5/thumbnails/5.jpg)
n-MOS
• Majority carriers electrons• When +ive voltage is applied on gate, no. of
electrons will be increased.• So, conductivity of channel is increased.• If Vg < Vt ,Then the channel is cutoff.
• Threshold voltage is the voltage at which MOS device starts to conduct.
![Page 6: UNIT I MOS TRANSISTOR THEORY AND PROCESS TECHNOLOGY](https://reader035.vdocuments.mx/reader035/viewer/2022062309/56649f355503460f94c527de/html5/thumbnails/6.jpg)
p-MOS
• Majority carriers holes
![Page 7: UNIT I MOS TRANSISTOR THEORY AND PROCESS TECHNOLOGY](https://reader035.vdocuments.mx/reader035/viewer/2022062309/56649f355503460f94c527de/html5/thumbnails/7.jpg)
• 2 types of modes in n-MOS & p-MOS:– Enhancement mode– Depletion mode.
• n-MOS Enhancement mode:– Device will be cut off when Vgs= 0
• n-MOS Depletion mode:– Device will conduct even if Vgs= 0
• p-MOS Enhancement mode:– Above Vtp, device will start to conduct.
• p-MOS Depletion mode:– Device will be in conducting state even if Vgs= 0
![Page 8: UNIT I MOS TRANSISTOR THEORY AND PROCESS TECHNOLOGY](https://reader035.vdocuments.mx/reader035/viewer/2022062309/56649f355503460f94c527de/html5/thumbnails/8.jpg)
Conduction characteristics
![Page 9: UNIT I MOS TRANSISTOR THEORY AND PROCESS TECHNOLOGY](https://reader035.vdocuments.mx/reader035/viewer/2022062309/56649f355503460f94c527de/html5/thumbnails/9.jpg)
n-MOS ENHANCEMENT TRANSISTOR
• It has Moderately doped p - type silicon substrate
• In that p-substrate, Heavily doped n + source and drain.
• Channel – a thin insulating layer made up of Silicon dioxide (SiO 2)
• Gate –polycrystaline silicon (polysilicon)
![Page 10: UNIT I MOS TRANSISTOR THEORY AND PROCESS TECHNOLOGY](https://reader035.vdocuments.mx/reader035/viewer/2022062309/56649f355503460f94c527de/html5/thumbnails/10.jpg)
Working principle• When Vgs= 0, Vds is applied.
• There is no current flow b/w source & drain.• When positive voltage is applied to gate,
electric field is produced across p-substrate.• It attracts electrons towards the channel.• It is continued when gate voltage is increased
further, the region below gate will be converted from p-type to n-type.
• So the channel becomes n-type(n-channel).
![Page 11: UNIT I MOS TRANSISTOR THEORY AND PROCESS TECHNOLOGY](https://reader035.vdocuments.mx/reader035/viewer/2022062309/56649f355503460f94c527de/html5/thumbnails/11.jpg)
• Three types of modes of MOS transistor:– Accumulation mode– Depletion mode– Inversion mode
![Page 12: UNIT I MOS TRANSISTOR THEORY AND PROCESS TECHNOLOGY](https://reader035.vdocuments.mx/reader035/viewer/2022062309/56649f355503460f94c527de/html5/thumbnails/12.jpg)
Accumulation mode
• In this mode Vgs < Vt
• Initially p-substrate is having holes only.
![Page 13: UNIT I MOS TRANSISTOR THEORY AND PROCESS TECHNOLOGY](https://reader035.vdocuments.mx/reader035/viewer/2022062309/56649f355503460f94c527de/html5/thumbnails/13.jpg)
Depletion mode
• In this mode Vgs =Vt
• Depletion region is created in this mode .
• Vgs is increased and reach Vt
• So holes are repelled from the channel.
• Because of this, depletion region is created.
![Page 14: UNIT I MOS TRANSISTOR THEORY AND PROCESS TECHNOLOGY](https://reader035.vdocuments.mx/reader035/viewer/2022062309/56649f355503460f94c527de/html5/thumbnails/14.jpg)
Inversion mode
• In this mode Vgs > Vt
• Voltage increased further, so electrons are attracted towards the region below gate.
• So, the layers of electrons will be formed below the gate.
• Bcoz of this layer, this mode is known as inversion mode.
![Page 15: UNIT I MOS TRANSISTOR THEORY AND PROCESS TECHNOLOGY](https://reader035.vdocuments.mx/reader035/viewer/2022062309/56649f355503460f94c527de/html5/thumbnails/15.jpg)
Operation regions of MOS transistor
• Cut-off mode• Non-saturated mode(linear or resistive or
unsaturated mode)• Saturated mode
![Page 16: UNIT I MOS TRANSISTOR THEORY AND PROCESS TECHNOLOGY](https://reader035.vdocuments.mx/reader035/viewer/2022062309/56649f355503460f94c527de/html5/thumbnails/16.jpg)
Cut-off mode
• When Vgs > Vt and Vds = 0.
• Depletion layer is created.• So the region is completely cut-off.
![Page 17: UNIT I MOS TRANSISTOR THEORY AND PROCESS TECHNOLOGY](https://reader035.vdocuments.mx/reader035/viewer/2022062309/56649f355503460f94c527de/html5/thumbnails/17.jpg)
Non-saturated mode
• When Vds < Vgs - Vt
• Deep channel is created in this mode.• Inversion region is weak in this region.
![Page 18: UNIT I MOS TRANSISTOR THEORY AND PROCESS TECHNOLOGY](https://reader035.vdocuments.mx/reader035/viewer/2022062309/56649f355503460f94c527de/html5/thumbnails/18.jpg)
Saturated mode
• Here, Vds > Vgs - Vt and Vgd < Vt
• The channel becomes pinched off.
• Inversion is strong.• Channel current is
controlled by gate voltage & it is independent of drain voltage
![Page 19: UNIT I MOS TRANSISTOR THEORY AND PROCESS TECHNOLOGY](https://reader035.vdocuments.mx/reader035/viewer/2022062309/56649f355503460f94c527de/html5/thumbnails/19.jpg)
• Ids depends following:– Distance b/w source & drain– Channel width– Threshold voltage– Thickness of oxide layer– Dielectric constant of gate insulator– Carrier mobility(μ)
![Page 20: UNIT I MOS TRANSISTOR THEORY AND PROCESS TECHNOLOGY](https://reader035.vdocuments.mx/reader035/viewer/2022062309/56649f355503460f94c527de/html5/thumbnails/20.jpg)
Conclusion
• Three conduction regions are available in nMOS enhancement transistor.
Cut-off region (no current flow)Non-saturated (Id depends Vg and Vd)
Saturated mode (Id independent of Vds )
![Page 21: UNIT I MOS TRANSISTOR THEORY AND PROCESS TECHNOLOGY](https://reader035.vdocuments.mx/reader035/viewer/2022062309/56649f355503460f94c527de/html5/thumbnails/21.jpg)
p-MOS ENHANCEMENT TRANSISTOR