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Unconventional Inorganic-Based Memristive Devices for Advanced Intelligent Systems

Sang Hyun Sung, Do Hyun Kim, Tae Jin Kim, Il-Suk Kang, and Keon Jae Lee*

DOI: 10.1002/admt.201900080

1. Introduction

Since Deepmind’s AlphaGo trounced one of the world’s best human Go players in 2016,[1–3] there has been explosive interest in the field of advanced intelligent systems (AIS), which have the ability to deal with intellectual tasks of real life problems.[4–6] For example, a variety of concepts including autonomous vehicles,[5,7,8] digital assistants,[9–12] humanoid robots,[13–16] and brain-like computers,[17–20] as listed in Figure 1a, are actively being introduced for state-of-the-art AIS demonstration. To realize a human-like AIS that is interactive

The latest progresses in software engineering such as cloud computing, big data analysis, and machine learning have accelerated the emergence of advanced intelligent systems (AIS). However, the current computing system has significant challenges in dealing with unstructured data (e.g., image, voice, physiological signals) because the von-Neumann bottleneck induces latency and power consumption issues. Neuromorphic computing, which imitates the behaviors of neuron and synapse within the biological neural net-work, is considered a promising solution beyond von-Neumann architecture, since its collocated structure of processor and memory enables parallel pro-cessing of unstructured data with remarkable efficiency. Memristors are con-sidered as next-generation nonvolatile memory devices due to fast speed, low power, and excellent scalability. However, a low reliability and leakage current issues remain as obstacle to the commercialization of memristors. Memris-tive devices have been widely investigated as a strong candidate for artificial synapses since their resistance modulation characteristics under electrical stimulus are analogous to the plasticity of the brain synapse. Although emu-lation of synaptic behavior by single memristor cells is demonstrated by many researchers, the development of fully functional memristive neural network requires further investigations. This paper introduces the recent advances and developments in the field of inorganic-based unconventional memristive devices for future AIS applications.

Memristors

The ORCID identification number(s) for the author(s) of this article can be found under https://doi.org/10.1002/admt.201900080.

S. H. Sung, Dr. D. H. Kim, T. J. Kim, Prof. K. J. LeeDepartment of Materials Science and EngineeringKorea Advanced Institute of Science and Technology (KAIST)291 Daehak-ro, Yuseong-gu, Daejeon 34141, Republic of KoreaE-mail: [email protected]. I.-S. KangNational Nanofab CenterKorea Advanced Institute of Science and Technology (KAIST)291, Daehak-ro, Yuseong-gu, Daejeon 34141, Republic of Korea

with our environments, it is important to implement capabilities of cognizing and learning unstructured data (e.g., visual information, natural language, human emotion, and physiological sig-nals) utilizing artificial intelligence (AI) technology.[21–23]

Neuromorphic computing, based on brain-inspired non-von-Neumann archi-tecture, is considered a promising solution for AI application since the processor/memory collocated structure enables parallel processing of massive nonstand-ardized data with extremely high power efficiency.[24–26] In our biological nerve system consisting of a reticular network of 1012 neurons and 1015 synapses,[27] compli-cated intellectual functions are performed at ultralow power of a few tens of watts compared to megawatts of supercom-puters through the neuronal communica-tion process called neurotransmission.[28] When stimuli accumulate over a threshold value, an action potential is generated at the neuronal cell body which propagates through the axon. This nerve impulse is subsequently delivered to the dendrite of the following neuron by the diffusion

of signal transmitters (e.g., positive ions or neurotransmit-ters) across the synaptic cleft. During this dynamic process, the transmission efficiency of the synapse is also strengthened or weakened due to its programmable property (i.e., synaptic plasticity), finally modifying the particular synaptic connec-tivity within the neural network.[29–31] In 2014, researchers at IBM developed a transistor-based neuromorphic TrueNorth chip operated by neurosynaptic cores and static random access memory (SRAM) synapses to demonstrate real time multi-object detection and classification with only 63 mW within their intrachip network.[32] This is 176 000 times smaller energy per synaptic event compared to general-purpose microprocessor, indicating the superior performance of the neuromorphic device for the processing of unstructured data. Moreover, next-generation nonvolatile memories with fast speed, high power efficiency, and low cost could advance the performance of the neuromorphic chip.[33–36] Nevertheless, there remains strong demand for novel artificial synaptic devices that fully imitate the scalable and plastic characteristics of the biological synapse.

A memristor is a two-terminal passive electrical component garnered attention in the neuromorphic computing field since its hysteretic resistance switching behavior is analogous to the synaptic plasticity of the biological synapse, as illustrated in

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Figure 1b.[37–39] In 1971, Chua first introduced the concept of the memristor as a fourth fundamental circuit element that defines the nonlinear relationship between electrical charge and magnetic flux.[40] Generalized properties of memristive systems including zero-crossing current–voltage (I–V) charac-teristics were presented by Chua and Kang in 1976.[41] In 2008, a physical model of the memristor was experimentally demon-strated by researchers at the Hewlett-Packard (HP) laboratory using a TiO2 active layer, the resistance of which was reversibly switched by the applied electrical stimulus.[42] Since then a number of studies on memristive devices related to resistive switching (RS) materials,[43–45] operation mechanisms,[46–50] integration methods,[51–54] and their neuromorphic applications have been widely reported.[55–62]

Herein, we review recent research on inorganic-based unconventional memories ranging from a single memristive cell to memristor-based flexible neuromorphic devices for AIS realization. An overview of representative studies of resistive switching memory and phase-change memory (PCM) is pre-sented from the perspectives of reliability, reproducibility, and integration. The key parameters of resistive switching memo-ries and phase change memories described in this review are summarized as tables (Tables 1 and 2). Flexible memristive devices with an adaptable surface for wearable electronics and brain–machine interface (BMI) applications are discussed. Memristors emulating the properties of the biological syn-apse (e.g., spike-timing-dependent plasticity(STDP), long-term potentiation/depression (LTP/LTD), paired-pulse facilitation/inhibition) are introduced as a fundamental building block for brain-inspired computing. This review will provide a broad outlook on synaptic memristors and their neuromorphic appli-cations for future AIS. The development of fully functional memristive neural network can impact not only the current computing paradigm, but also neuroscience and biomedical engineering, such as reverse engineering of the brain and development of brain–machine interface.

2. Inorganic Resistive Switching Memories

RS memory has attracted significant attention as a strong candidate for artificial synaptic devices based on its advan-tages of fast and low power operation, a hysteretic I–V char-acteristic, semiconductor process compatibility, and high scalability of crossbar-type parallel integration.[63–65] A number of research groups have explored RS memory cells utilizing several kinds of active layers, including oxides (e.g., NiO, TiO2, Cu2O, Nb2O5, HfO2, Ta2O5, WO3, ZnO, ZrO2, Al2O3, SiO2, and CeO2),[66–77] solid-state electrolytes (e.g., GeS, GeSe, Cu2S, and (Zn,Cd)S),[78–81] perovskites (e.g., SrTiO3, SrZrO3, BiFeO3, and Pr1−xCaxMnO3),[82–85] chalcogenides (e.g., Ge2Sb2Te5 and AgInSbTe),[86,87] and 2D materials (e.g., hexagonal-BN).[88] The resistance of the RS memory reversibly switches between the high resistance state (HRS) and the low resistance state (LRS) by applying a particular electrical stimulus at electrodes. This RS phenomenon is mainly explained by various mechanisms, including formation/rupture of the nanoscale conducting fila-ment, variation of the Schottky barrier, electrochemical atomic diffusion, and crystal structure transition.[89–92] Figure 2a shows

the transmission electron microscopy (TEM) image of as-fabri-cated Ag/SiO2/Pt memristor which is representative example of resistive switching by cation diffusion.[93] The resistance state of the SiO2-based memristor can be reversibly switched between HRS and LRS, by the formation and the dissolution of conduc-tive Ag filaments as shown in Figure 2b,c. By applying electric field, the Ag cations from Ag electrode migrate to inert Pt elec-trode and reduced into Ag atoms resulting in the formation of the Ag filament. The RS memory can be categorized into

Sang Hyun Sung is a Ph.D. candidate in Materials Science and Engineering (MSE) from KAIST, under the supervision of Prof. Keon Jae Lee. He received his B.S. degree and M.S. degree from KAIST. His doctoral research topic includes the next-generation memory devices (ferroelectric memory, resistive switching

memory, and phase-change memory) for neuromorphic applications.

Do Hyun Kim received his Ph.D. in Materials Science and Engineering (MSE) from KAIST. He received his B.S. degree in MSE from Kyungpook National University (KNU) in 2013 and M.S. degree from KAIST in 2015. His research interests include flexible electronics (large-scale integration, f-LSI) and next-generation memory

devices (resistive switching memory, phase-change memory, and ferroelectric memory).

Keon Jae Lee received his Ph.D. in Materials Science and Engineering (MSE) from the University of Illinois, Urbana-Champaign (UIUC). During his Ph.D. at UIUC, he was involved in the first co-invention of “flexible single-crystalline inorganic electronics,” using top-down semiconductors and soft lithographic transfer. Since

2009, he has been a professor in MSE at KAIST. His cur-rent research topics are self-powered flexible electronic systems including energy-harvesting/storage devices, LEDs, large-scale integration (LSI), high-density memory, and laser–material interaction for in vivo biomedical and flexible applications.





unipolar and bipolar switching depending on whether the set (switching from HRS to LRS) and reset (switching from LRS to HRS) operation occurs at equal voltage polarity or at the oppo-site voltage polarity, respectively. To implement high perfor-mance RS memory, various properties such as cell parameters (e.g., set/reset/read voltage, HRS/LRS resistance ratio, opera-tion power, switching speed, endurance, and retention), cycle-to-cycle/device-to-device uniformity, selection device, inte-gration method, and operating scheme have to be optimized.

One important area of improvement for RS memory utili-zation is minimizing the switching parameter distribution by decreasing the randomness of the RS phenomena. You et al.[94] demonstrated a highly reliable and reproducible RS memory by incorporating self-assembled nanoinsulators at the inter-face between the NiO RS layer and the top electrode, as shown in Figure 2d. By oxidizing poly(styrene-b-dimethylsiloxane) (PS-b-PDMS) block copolymers (BCPs) containing Si through plasma treatment, insulating SiOx nanodots (SiOx NDs) were uniformly formed on NiO as an electric field concentrator to localize the forming site of the conductive filament (CF). Due to the diminished randomness of the CF formation, the dis-tribution of set and reset voltage was decreased by 76.9% and

59.4% in standard deviation (SD), respectively, as presented in Figure 2e. In addition, the SD of the off-state (HRS) cell resistance also declined from 6.3 × 107 Ω to 5.4 × 104 Ω. Lee et al.[95] successfully improved the switching properties of the Ta2O5-based memristive device (Pd/Ta/Ta2O5/Pd) by inserting a graphene layer with engineered nanopores between the top electrode (Pd/Ta) and the RS layer (Ta2O5) to restrict the ionic reactions required for RS at the nanoscale. Insertion of the monolayer graphene (MLG) decreased the programming and reset currents from ≈4 to ≈0.6 mA while improving the device-to-device uniformity in terms of HRS and LRS cell current. Similarly, Zhao et al.[96] proposed a strategy for centralizing the cation injecting path within the RS memory (Ag/SiO2/Pt) by inserting a concentrated defect graphene (CDG) between the top electrode (Ag) and the RS layer (SiO2). The memory tuned with CDG presented low power consumption (<1.5 µW), fast operation speed (set operation of <100 ns and reset operation of <200 ns), excellent endurance (>107), and multilevel proper-ties due to the localized formation of the Kwon et al.[97] reported a fast-switching and scalable single truncated conical nanopore (StcNP) structured RS memory cell employing a confined ver-tical nanoscale gap. Au nanoparticles (NPs), which were initially


Figure 1. a) Representative examples and related technologies of advanced intelligent system. b) Schematic illustration of neuromorphic (brain-like) computing, presenting the analogous relationship between a biological synapse and a memristive device.

Table 1. Summary of main parameters in resistive switching memories.

[94] [95] [96] [97] [98] [109] [110] [115] [51] [119]

Memory

Structure

Pt/Ti/SiOx-NDs/

NiO/Ni

Pd/Ta/

Graphene/

Ta2O5/Pd

Pt/Ag/DGa)/

SiO2/Pt

Au/StcNPb)

SiOx/Au

Pt/Al2O3/Ag W/SiO2/P+Si/

N+Si/N+Si

Pt/TiO2/Ti/Pt/

TiO2/Pt

p-Si/

SiO2/n-Si

Pt/NbOx/TiOy /

NbOx/TiN

IrOx//Al2O3/

TiOx/TiN

Selection

device

– – Selector – – Diode Diode Self-rectifying Self-rectifying –

RON/OFF <103 (@ Vread =

0.3 V)

<40 (@

Vread = 0.2 V)

≈109 (@

Vread = 0.2 V)

>107 (@

Vread = 1 V)

>105 (@ Vread =

0.05 V)

50

(@ Vread = 1 V)≈103 (@ Vread =

1.5 V)

104 (@

Vread = 2 V)<100

(@ Vread = 3 V)

≈55c)

(@ Vread = 1 V)

Operation

voltage0.77 V ≈1.6 V −1.5–1 V −1.5–1.5 V 4–9 V 0.02–0.03 V 4–8 V −2−4 V 4.5–7.5 V 12 to −12 V >3.2 V

Endurance 500 2 × 106 106 103 103 104 200–300 100 5 × 103 –

Retention (s) 104 – 107 104 105 104 104 2 × 105 106 104

a)DG: Defective graphene; b)StcNP: single truncated conical nanopore; c)This value is 50% of the distribution.




formed on a SiOx/Pt/Ta substrate by dewetting and agglom-eration of an Au patch, penetrated the SiOx layer and finally reached the underlying Pt/Ta electrode through an annealing process to construct the StcNP structure. After deposition of the top electrode (Au) and initial electric breakdown, a vertical nanogap with an RS property was generated, presenting a high HRS/LRS resistance ratio (>107), sub-10 ns switching speed, and multistate storage ability, as shown in Figure 2f,g. Shin et al.[98] adopted a pyramid-shaped Ag array as an electrode of the RS memory (Pt/Al2O3/Ag), achieving low set voltage of 0.48 V ± 0.02 V and reset voltage of 0.15 V ± 0.06 V with min-imized deviations. Kim et al.[99] also reported an RS memory (TiN/TiO2/Cu cone/TiN) embedding a cone-structured Cu cation source, showing improved RS properties compared to the conventional device with a planar bottom electrode. The RS performance of these memories could be enhanced since the conical electrode concentrated the electric field at the sharp tip to localize the forming site of the conductive filament to tens of nanometers. Rosa et al.[100] introduced indium–gallium–zinc oxide nanoparticle (IGZOnp)-based memristive device using solution process.[101] The solution-based deposition provides more defective film with low cost compared to a film deposited by vacuum process, which can be promising for the fabrication of RS memory. The Al/IGZOnp/Ti memristor showed HRS/LRS resistance ratio of 10, retention of 104 s, and endurance cycle of 100. In addition, the RS memory was fabricated under 200 °C, which is capable of application in flexible substrate.

Unit RS memory cells should be integrated in a crossbar-structured parallel matrix with bit and word line interconnec-tions to realize a resistive random access memory (RRAM) for fully functional memory operations.[102–104] In this case, it is crucial to minimize the leakage current flowing through neighboring cells since this causes undesirable electrical inter-ference, readout margin degradation, and additional power consumption.[105–107] Merced-Grafals et al.[108] demonstrated the 1 transistor-1 resistor (1 T-1 R) array of TaOx-based mem-ristors. The conventional CMOS transistors were utilized for the random access operations with high accuracy owing to its well-established characteristics. The proposed 1 T-1 R array per-formed matrix multiplication with high power efficiency, which is 1000–10 000 times higher than that of the custom digital ASIC. However, transistor is three-terminal device which has

disadvantages in scaling compared to the two-terminal selec-tion device such a nonlinear resistor or a rectifying diode. Ji et al.[109] demonstrated a 1 diode-1 resistor (1 D-1 R) nanopillar RS memory presenting a nonlinear I–V characteristic and low reverse-bias current for high-density crossbar-array applications. The SiOx RS layer with underlying P2+/N+/N2+ epitaxial Si was patterned through a Bosch deep Si etch process using a nano-sphere lithography (NSL) technique, as shown in Figure 2h. The 1 D-1 R nanopillar memory demonstrated a low reverse current under 1 × 10−12 A at −3 V, excellent retention over 104 s, stable multilevel operation, sub-50 ns switching speed, and unidirectional RS operation enabling a 1 Gbit crossbar array at a 10% readout margin, as presented in Figure 2i. Kim et al.[110] reported a 32 × 32 crossbar-structured 1 D-1 R array employing an oxide-based Schottky diode (Pt/TiO2/Ti) selection device and a RS storage node (Pt/TiO2/Pt), as shown in Figure 2j. The 1 D-1 R memory cell within the 32 × 32 parallel array operated without electrical interference during random access operation based on its high HRS/LRS resistance ratio (≈103 at 1.5 V) and large rectifying ratio (≈105) between LRS and reverse-biased rectifying state, as presented in Figure 2k. Although 1 D-1 R structure can prevent leakage current issue for unipolar RS memory, the bipolar RS memory requires bidirectional selector for the RS operations, such as Schottky selector, Mott switch, and Ovonic threshold switch (OTS). Kim et al.[111] demonstrated 1 selector-1 resistor (1 S-1 R) array using TiOx/TaOx-based memristor and NbO2-based selector. A TiAlN electrode with high resistance and barrier layers at the NbO2 interface were utilized to minimize the leakage current. The NbO2 selector-based 1 S-1 R array showed sneak current of 1.5 µA with low operation current of 30 µA.

Instead of selection device integration, there have been efforts to implement both the RS and rectifying properties in a single metal–insulator–metal (MIM) structure for a simple device fabrication and vertical memory applications.[112–114] Li et al.[115] developed a crossbar-structured array of all Si-based p-Si/SiO2/n-Si self-rectifying memristor cells, presenting a high HRS/LRS resistance ratio (≈104), long retention (>2 × 105 s at 300 °C), and large rectifying ratio (≈105) for parallel-structured cell integration, as shown in Figure 2l,m. Furthermore, a 3D stacked self-rectifying memristor array was realized using a fluid-supported Si membrane technique. Kim et al.[51] reported


Table 2. Summary of main parameters in phase change memories.

[146] [149] [150] [154] [155] [156] [157] [175]

Structure TiW/TiN/SiOx/

GSTa)/TiW

TiW/GST/NiO/Ni CNTb)/GST/CNT TaN/Ga2Te3Sb5

/TiN

Au/Cr/In2Se3/

Graphene

GeSbCx Al/TiN/

SiC-GST/W/Al

AgInSbIe/TiNor

GeTe/TiN

TPhase transition (K) 888 888 – 836 >623 450–500 513 900

RON/OFF <102 (@ Vread =

0.5 V)

<103 (@ Vread =

0.3 V)

<102 28 50 (@ Vread =

0.3 V)

– ≈20 ≈2 (@ Vread =

0.1 V)

Operation voltage

(or current)Vset = 3 V, 1 µs

Vreset = 10 V,

150 ns

Iset = 1.1 mA

Ireset = 3.2 mA

Iset = 1 µa Ireset =

5 µA

Vset = 4 V, 500 ns

Vreset = 6 V, 100 ns

Vset = 0.7 V, 70 µs

Vreset = 3 V, 50 ns

– Vreset = 3 V, 20 ns Iset >500 µA,

350 ns Ireset >400

µA, 100 ns

Endurance 200 200 200 2 × 105 100 – <105 105

Retention (s) 104 104 – – 1200 – >8 × 103

a)GST: Ge2Sb2Te5; b)CNT: carbon nanotube.




a Pt/NbOx/TiOy/NbOx/TiN (P-NTN) memristor with a high self-rectifying property (≈105) by employing a Pt/NbOx Schottky contact within the cell stack. High cell-to-cell uniformity could

be achieved because the RS was accomplished by the trap-ping and detrapping of electrons at the TiOy/NbOx interface, excluding the randomness of CFs formation, which enlarges


Figure 2. TEM image of Ag/SiO2/Pt memristor in a) as-fabricated state, b) low resistance state, and c) high resistance state. d) Illustration describing the (top) Pt/Ti/NiO/Ni (bottom) RS memory with self-assembled SiOx-NDs inserted between the top electrode (Pt/Ti) and the RS layer (NiO) as an electric field concentrator. e) Cumulative probability graph plotting the set and reset voltages of the NiO memory with and without the incorporated SiOx-NDs. f) Electrical behavior during initial breakdown process for vertical nanogap formation of StcNP SiOx RS memory. g) I–V curves of the StcNP SiOx RS memory (pore diameter of ≈75 nm) showing a large on-off ratio of ≈107 at a read voltage of 1 V. h) Secondary electron microscopy (SEM) image of the SiOx/P2+/N+/N2+ 1 D-1 R nanopillar RS memory. i) I–V characteristics of the 1 D-1 R nanopillar RS memory during 30 cycles of RS opera-tion. The inset shows the HRS and LRS cell readout current with varying reset stop voltage. j) SEM image of a 32 × 32 crossbar-structured 1 D-1 R array with 10 µm width line interconnections. k) Representative I–V characteristic of the selected 1 D-1 R cell while all the adjacent 20 × 20 cells were switched to LRS. l) Magnified image of a 64 × 64 crossbar-structured array consisting of p-Si/SiO2/n-Si self-rectifying memristor cells. m) Measured I–V plot of a p-Si/SiO2/n-Si memristor cell showing unipolar and self-rectifying properties. n) Bright field scanning transmission electron microscopy (STEM) images of the 3D-VRRAM structure. o,p) I–V curves of the 3D-VRRAM operated in o) RS mode and p) CRS mode. a–c) Reproduced with permission.[93] Copyright 2012, Springer Nature. d,e) Reproduced with permission.[94] Copyright 2014, American Chemical Society. f,g) Reproduced with permission.[97] Copyright 2017, American Chemical Society. h,i) Reproduced with permission.[109] Copyright 2014, American Chemical Society. j,k) Reproduced with permission.[110] Copyright 2013, John Wiley & Sons. l,m) Reproduced with permission.[115] Copyright 2017, the authors, published by Springer Nature under the terms of the CC-BY Creative Commons Attribution 4.0 International License. n–p) Reproduced with permission.[119] Copyright 2017, John Wiley & Sons.




the cell property distribution. Furthermore, the RS memory presented a forming-free property, low switching current of 10 nA, and stable endurance up to 5000 cycles.

Vertical-structured RRAM has attracted significant interest owing to its feasibility to dramatically increase the integration density and lower the cost-per-bit compared to the conventional planar-structured memory.[116–118] Banerjee et al.[119] reported a 3D vertical crossbar RRAM (3D-VRRAM) based on a TiO2/Al2O3 hybrid RS bilayer, as shown in Figure 2n. The memory presented reliable switching in RS mode by the formation and rupture of a conductive Ti5O9 (i.e., Magnéli phase) nanofilament with stable resistance ratio levels of 55 and good retention of 104 s, as presented in Figure 2o. In addition, high nonlinearity of ≈33 was achieved in complementary RS (CRS) mode, which enables high-density 1 Mb array, as shown in Figure 2p.

3. Inorganic Phase-Change Memories

PCM has shown potential for a next-generation memris-tive device based on its advantages of a well-known switching mechanism, reliable operation, and high scalability.[120–122] The resistance of PCM is changed by switching the crystal struc-ture of the phase change material (i.e., mainly chalcogenide Ge2Sb2Te5 (GST)) between crystalline and amorphous state, which correspond to LRS and HRS, respectively. To switch the LRS cell to HRS (i.e., reset operation), a short and intense elec-tric pulse is required to instantaneously heat and quench the GST layer for amorphization. In contrast, to switch the HRS cell to LRS (i.e., set operation), a relatively long and moderate pulse is required to heat the GST between the temperature for crystallization (≈350 °C) and melting (≈610 °C). The PCM can also be operated as an analog memory with continuous con-ductance states to imitate the synaptic plasticity for neuromor-phic applications.[123–128]

To implement a high-performance operational PCM, a variety of factors should be considered such as scaling methods,[129–132] cell design optimization,[133–135] thermal engi-neering,[136–138] material exploration,[139–143] and selection device integration.[144,145] Park et al.[146] proposed a strategy for reducing the switching power of the PCM by incorporating PS-b-PDMS BCP-based nanostructured SiOx between the GST chalcogenide material and the TiN heater, as illustrated in Figure 3a.[147,148] The phase transition volume of the GST was shrunk by operation current concentration, resulting in a sig-nificant reduction of the writing power by 1/20 when the fill factor increased from 9.1% to 63.6%, as shown in Figure 3b. You et al.[149] reported an ultralow-power PCM operated by a self-structured nanoscale filament heating electrode. A conduc-tive nanoscale Ni filament was generated by electrical stimula-tion within the insulating NiOx layer, which concentrates the current flow at the filament tip to minimize the volume of GST phase transition, as shown in Figure 3c. A reset current of 593 µA was achieved for 2 × 2 µm2 cell size, as shown in Figure 3d, which is a significantly reduced value compared to the typical reset current of 75 mA for a 2 µm diameter con-tact. In the case of the PCM operated by a single Ni filament generated by a conductive atomic force microscopy (CAFM) tip, an ultralow reset current of 20 µA was realized. Xiong et al.[150]

reported a phase transition of the chalcogenide GST between the nanogap-separated carbon nanotubes (CNTs), which were formed by electrical breakdown of a single CNT. Since a high electric field was generated across the nanogap, the GST could be switched between the amorphous and crystalline state with an extremely low set current of 0.5 µA and a reset current of 5 µA.

The operation properties of the PCM have been improved through the introduction of new phase switching materials,[151] impurity doping, defect control,[152] and strain engineering.[153] Kao et al.[154] reported fast switching and long retention prop-erties of the PCM device based on Ga2Te3Sb5. The high speed operation was accomplished because the phase transition was based on the growth-dominated crystallization and melting/solidification of amorphous phase at the grain boundary as shown in Figure 3e. The PCM presented a low reset current of 2.6 ± 0.2 mA, fast switching time of 20 ns, excellent endur-ance exceeding 2 × 105 cycles, and a long retention property extrapolated to 10 years (at 160 °C), as shown in Figure 3f. Choi et al.[155] demonstrated a PCM (Au/Cr/In2Se3/graphene) uti-lizing a layered In2Se3 material, the crystal structure of which switches between the crystalline β phase (LRS) and the crystal-line γ phase (HRS). The LRS/HRS resistance were explained by the periodic formation/annihilation of the van der Waals’ gap and simultaneous In and Se atom reconfiguration within the atomic layers. Wu et al.[156] reported that a carbon-incorporated Ge–Sb chalcogen-free film (GeSbC) showed a highly reduced mass density difference (Δρ) between its crystalline and amor-phous phases (Δρ = 3.29% at carbon% = 5.75%) that improved the retention property of the PCM. The Te atoms within the Ge2Sb2Te5 materials are known to reduce the stability and the lift-time of the PCM device. It is because of not only agglomer-ated Te atoms in grain boundaries causing residual stress, but also the large density difference (Δρ = 6–8%) between amor-phous and crystalline GST. In contrast, carbon-incorporated GeSbC presents a reduced Δρ since the atomic packing effi-ciency of its amorphous phase is improved due to the increased number of short tetrahedral bonds by carbon atoms, as shown in the atomic models of Figure 3g,h. In terms of a doping effect, Guo et al.[157] demonstrated that SiC doping within a Ge2Sb2Te5 material presented enhanced thermal reliability (retention of 10 years above 120 °C), reduced reset voltage (3.0 V at 20 ns pulse), and lowered volume change (lower than 3.0%). Skelton et al.[158] reported that the Bi doping improves the crystallization speed and n-type conductivity of Ge2Sb2Te5. Other dopants such as O2,[159] N2,[160,161] Si,[162] In,[163] Sn,[164] SiO2,[165] Ag,[166] Al,[167] Cr,[168] and Mg[169] were also adopted to enhance the switching properties of phase switchable chalcogenide materials.

Optimizing the cell structure is an important issue since it is closely related to the programming power, thermal crosstalk issue, and packing density. Several different PCM cell struc-tures have been demonstrated including mushroom,[170] con-fined,[171] µ-trench,[172] cross-spacer,[134] and transistor chain structures.[173] Recently, Giusca et al.[174] reported a phase switching phenomena of a GeTe crystal confined within the cavity of a carbon nanotube with a diameter as low as 1.3 nm, showing the feasibility of the ultradense PCM integration. The encapsulated GeTe with extremely small volume showed a lowered melting point compared to its bulk material, which





has beneficial effects of reducing the programming current of GeTe phase switching. Koelmans et al.[175] presented a unique PCM cell design, called projected PCM, composed of parallel domains of noninsulating projection and phase-switching

segment in a single cell, as shown in Figure 3i,j. The proper-ties of high disorder and defect density of the phase switching material are known to result in a high noise level and resistance drift during the PCM operation. By decoupling the resistance


Figure 3. a) Schematic illustration describing the cell structure of the nanostructured SiOx incorporated PCM. b) The PCM power consumption as a function of varying fill factor of the nanostructured SiOx. c) Operation mechanism of the conductive filament PCM. d) Resistance–pulse current (R–I) curve during reset operation depending on the device area and the compliance current (CC). e) The RS mechanism of the Ga2Te3Sb5 showing the phase change by applied current from 1.6 to 2.4 mA. i) Crystalline phase (LRS), ii) beginning of melting and some amorphous phase in grain boundary, iii) melting and solidification stage, and iv) amorphous phase (HRS). f) R–I curves with different pulse durations from 20 to 500 ns. The inset shows resistance ratio-pulse width curve. g,h) Atomic models of g) crystalline h) amorphous GeSbC5 presenting the distortions and tetrahedral bonds formed by carbon atoms, respectively, leading to the reduced density difference (Δρ) between the crystalline and amorphous phases. i) The schematic of (left) conventional PCM and (right) projected PCM cell. j) The ideal I–V curve of projected PCM cell and illustrations of corresponding current paths. The amorphous phase, crystalline phase, and projection material are denoted as AMOR, CRYST, and PROJ, respectively. k) Current noise result of the pro-jected PCM cell and conventional PCM cell. The dashed lines presents the thermal noise floors. a,b) Reproduced with permission.[146] Copyright 2013, American Chemical Society. c,d) Reproduced with permission.[149] Copyright 2015, American Chemical Society. e,f) Reproduced with permission.[154] Copyright 2009, John Wiley & Sons. g,h) Reproduced with permission.[156] Copyright 2018, John Wiley & Sons. i–k) Reproduced with permission.[175] Copyright 2015, the authors, published by Springer Nature under the terms of the CC-BY Creative Commons Attribution 4.0 International License.




writing and readout operations, both the temporal resistance drift and the current noise could be significantly reduced com-pared to conventional PCM devices, as shown in Figure 3k.

4. Flexible Memristive Devices

In recent years, flexible electronics have been extensively investigated to break through the intrinsic limitations of rigid electronics, leading to the realization of unprecedented form factors for unconventional user experiences.[176–186] This is because of the lightweight, portable, and human-friendly interface characteristics of the flexible devices. The flexibility presents the realization of wearable, skin-attachable, and bio-implantable electronics for the hyper connected society.[187–191] In particular, flexible memory is regarded as a vital compo-nent for high-performance flexible electronics considering its fundamental functions in signal processing, data storage, and interdevice communication. Furthermore, a flexible artificial synapse can be employed in an implantable BMI, providing a valuable route to restore damaged neural functions such as vision, hearing,[192–194] movement,[195,196] and even complex cog-nitive behaviors.[197,198]

A variety of researchers have studied direct fabrication methods of flexible memories on a plastic substrate utilizing low temperature processes such as vacuum deposition, wet processing, and printing methods.[199–204] Jang et al.[205] fabri-cated a Ag/Ag2Se/Au RS memory on a flexible poly-ethylene-naphthalate (PEN) substrate using a wet method, as shown in Figure 4a,b. By spin coating the Ag2Se NPs solution followed by low temperature (under 200 °C) sintering, RS memory with a HRS/LRS resistance ratio of ≈30, endurance of 104 cycles, and retention of ≈105 s could be achieved. Wang et al.[206] fabri-cated a SiOx-based RS memory (Pt/SiOx/Pt) directly on a poly-imide (PI) substrate using simple deposition methods such as electron beam evaporation and sputtering. Pd interlayers were inserted within the RS SiOx layer to lower the electroforming voltage and the threshold voltage to 8.3 and 3.7 V, respectively, while maintaining the HRS/LRS ratio and endurance property of the pure SiOx memory without Pd interlayers, as shown in Figure 4c,d. In addition, the memory presented a low forming voltage and stable RS behavior after 100 iterations of bending. Yoon et al.[207] also utilized the direct deposition method to fab-ricate a crossbar-structured 1 D-1 R memory array on a polymer substrate. The unipolar RS memory (Pt/Ti/SiOx/Pt) integrated with a rectifying Schottky diode (Ti/TiO2/Pt) presented a large rectifying ratio (>106) and a high HRS/LRS resistance ratio (>104), which are required for random access operation in a parallel array. In particular, a sputter-deposited nano porous SiOx RS layer with low packing density provided facile sites for local conduction path formation and disconnection, thereby decreasing the forming voltage and the power consumption. Ji et al.[208] reported a flexible Cu/WO3−x/indium tin oxide (ITO) RS memory on a poly(ethylene terephthalate) (PET) substrate utilizing electrochemical anodic treatment to form a nano porous WO3−x switching layer, as shown in Figure 4e. Because the nanopores in WO3−x provided an easy route for Cu ion migration, the flexible RS memory presented an excellent HRS/LRS resistance ratio of ≈105, stable retention of 5 × 105 s,

and retention of 103 cycles. Furthermore, the WO3−x memristor showed negligible degradation at a bending radius of 5.53 mm, as presented in Figure 4f.

One of the obstacles to direct fabrication is the thermal insta-bility of the polymer substrate since it restricts high tempera-ture processing required for annealing, ion implantation, and crystallization. Therefore, to realize high-performance memris-tive devices on polymers without these issues, innovative meth-odologies, including laser-processing and transfer techniques have been widely studied by several researchers.[209–213] As illus-trated in Figure 4g, Tian et al.[214] demonstrated a reduced gra-phene oxide (rGO)-based flexible RS memory (Ag/HfOx/rGO) on a PET substrate utilizing a one-step laser-scribing technique, which enabled direct growth and simultaneous patterning of the rGO from the graphene oxide (GO) without thermal deg-radation of polymers. The fabricated RS memory presented reliable switching properties with forming-free behavior, stable endurance up to 100 cycles, and multi-bit storage capability, as shown in Figure 4h. Kim et al.[215] reported a flexible 1 T-1 R array employing Si-based transistors and Al/amorphous-TiO2 (α-TiO2)/Al memristors, as shown in Figure 4i. High tempera-ture processed single crystal Si was transferred from the bulk wafer to a polymer substrate to implement a Si-based high performance flexible transistor, which enabled random access operation within an 8 × 8 NOR type memristive memory array without electrical interference. As in the drain current–voltage (ID–VD) plot in Figure 4j, flexible 1 T-1 R memory presented excellent RS characteristics with mechanical endurance during 1000 iterations of bending. Mun et al.[216] also reported a flex-ible 1 PN diode-1 PCM (1 D-1 P) array on a PI substrate using the Si transfer method. In particular, Si-containing PS-b-PDMS BCPs were adopted to introduce a SiOx nanostructure between the GST (i.e., phase change material) and the TiN (i.e., heating electrode) reducing the reset power down to a 1/4 level and pre-venting thermal damage of polymers. The flexible 1 D-1 P cell showed unipolar switching operation due to the rectifying prop-erty of the Si-based PN diode with excellent flexibility evaluated by 1000 iterations of bending cycles.

Another approach to transfer a high temperature processed device was introduced by Qian et al.[217] using an Ag/hexag-onal-BN (hBN)/Cu/PET RS memory, as shown in Figure 4k,l. The hBN RS layer was initially grown on a flexible Cu foil at 1020 °C, followed by transfer of the Cu foil to a PET substrate. The strong covalent BN bonds in the hBN RS layer provided high mechanical strength, resulting in steady operation during a bending test of 750 cycles with a 7 mm bending radius. Sub-sequently, they reported a transparent and flexible ITO/hBN/graphene RS memory on a poly(dimethylsiloxane) substrate utilizing the conventional wet transfer technique.[218] The RS memory with In-based CF, confirmed by an ex situ TEM anal-ysis, showed a HRS/LRS resistance ratio of ≈480 and retention of 5 × 104 s. Due to the outstanding flexibility and high inter-facial adhesion strength of graphene, the ITO/hBN/graphene RS memory demonstrated stable operation up to 850 bending iterations at a bending radius of 14 mm.

Several research groups have sought to transfer the entire memory fabricated on a rigid wafer at high temperature onto a flexible substrate to overcome the restrictions of polymers such as limited thermal budget, inaccurate nano-alignment and





multilayer metallization, and incompatibility with the state-of-the-art semiconductor process.[219–221] As shown in Figure 4m, Kim et al.[221] realized a crossbar-structured 1 S-1 R array on polymers by adopting the inorganic-based laser lift-off (ILLO) transfer method. A 32 × 32 memory array of 1 S-1 R cells was first fabricated on a rigid substrate by a high temperature pro-cess. After irradiating an XeCl laser on a laser-reactive exfolia-tion layer (i.e., amorphous Si), the device could be transferred to a PET substrate by weakening the adhesion between the device and the substrate, which is mainly explained by localized

melting, vaporizing, or dissociating of the exfoliation layer. As illustrated in Figure 4n, the selector (Ni/TiO2/Ni) with a non-linearity factor of >500 decreased the leakage current in a cross-point structure for the random access operations. In addition, the 1 S-1 R memory demonstrated excellent mechanical reli-ability during bending stability (7.5 mm bending radius) and fatigue (1000 iterations of bending) tests.

Recently, Kim et al.[220] developed a Mo-based interfacial physical lift-off (IPLO) method to demonstrate a highly flexible 1 Schottky diode (SD)-1 PCM (1 SD-1 PCM) array on a polymer


Figure 4. a) I–V curves of Ag/AgSe2/Au RS memory on flexible PEN substrate. The insets present the schematic of the AgSe2-based memristor and optical image of the dendrite formation inside the RS memory cell. b) Retention properties of AgSe2 RS memory with read voltage of 0.1 V. c) Illustration of a SiOx-based flexible RS memory device with inserted Pd interlayers within the SiOx RS layer. d) Operational I–V plots for different numbers of inserted Pd interlayers. e) Memory structure of a flexible RS memory fabricated by anodic treatment method. f) Representative I–V plot of the flexible Cu/WO3−x/ITO RS memory with flat state (blue) and bent state (red). g) Schematic image of an rGO-based flexible RS memory. The inset shows the photograph of the rGO-based memory on PET substrate. h) I–V curve of rGO-based memristor at 1, 50, and 100 cycle i) Image of an 8 × 8 NOR type 1 T-1 R array on a plastic substrate. j) Drain current–voltage (ID–VD) plot of the flexible 1 T-1 R cell. k) Schematic illustration of an Ag/hBN/Cu RS memory on a flexible PET substrate. l) I–V curve of hBN RS memory after electroforming process. m) Photograph of a flexible crossbar-structured 1 S-1 R array transferred on PET substrate. n) Representative I–V plot of the integrated 1 S-1 R cell. o) Photograph and optical microscopy (OM) image of a crossbar-structured 1 SD-1 CFPCM array on a PET substrate. p) Representative R–V plot of an integrated 1 SD-1 CFPCM cell. a,b) Reproduced with permission.[205] Copy-right 2012, John Wiley & Sons. c,d) Reproduced with permission.[206] Copyright 2014, American Chemical Society. e,f) Reproduced with permission.[208] Copyright 2016, American Chemical Society. g,h) Reproduced with permission.[214] Copyright 2014, American Chemical Society. i,j) Reproduced with permission.[215] Copyright 2011, American Chemical Society. k,l) Reproduced with permission.[217] Copyright 2016, John Wiley & Sons. m,n) Reproduced with permission.[221] Copyright 2014, John Wiley & Sons. o,p) Reproduced with permission.[220] Copyright 2018, John Wiley & Sons.




substrate. As presented in Figure 4o, the crossbar-structured interconnection of 32 × 32 1 SD-1 PCM cells for 1 kbit data storage was fabricated on an IPLO substrate, which incorpo-rates a FCC/BCC Mo exfoliation interface with weak adhesion energy. The device was subsequently transferred onto a PET substrate without physical degradation. As shown in Figure 4p, the PCM (TiW/Ge2Sb2Te5/NiO/Ni) stably operated on polymers with low reset current because the Ni nanofilament heater con-fined the current flow at the filament tip to minimize the phase switching volume of the GST. The integrated rectifying SD (Pt/TiO2/Ti) selection device effectively suppressed the leakage current through the adjacent cells, which enabled random access operations in a worst case scenario. Furthermore, the physical stability of the f-PRAM was confirmed by harsh and repetitive bending tests of 2000 iterations.

Selection of substrate material is another issue in the fab-rication of flexible memory devices. PET is mainly used for the flexible substrate due to low cost, outstanding flexibility, and excellent chemical resistance. PEN is also widely adopted for the fabrication of flexible devices owing to similar charac-teristics to PET. However, PET and PEN show degradations above ≈150 °C, restricting the process window.[222] PI has better thermal stability over ≈250 °C with high flexibility and excel-lent chemical resistance, while it shows low optical transmit-tance which hinders its application on transparent devices.[223] Mica substrate is another candidate for the flexible electronics due to its outstanding thermal stability up to 600 °C, while high manufacturing cost limits its applications.[224] Recently, cellulose paper as flexible substrate is studied with the rise of single-use disposable electronic devices that requires low cost and recyclable substrate.[225–227] For the realization of flexible electronic system, the substrate materials should be adopted in consideration of the purpose and required characteristics such as mechanical stability, thermal stability, chemical resistance, optical transmittance, and recyclability.

5. Memristors for Neuromorphic System

The research on neuromorphic computing was firstly started by imitating the features of biological neural network for the reverse-engineering of brain, which is expanded to not only neuromorphic hardware devices such as artificial synaptic devices, but also neuromorphic software systems and algo-rithms including artificial neural network, deep learning, and many other approaches. The neuromorphic software spread throughout our daily lives, while neuromorphic hardware emulating the synaptic behaviors of biological brain is still under developments. Many researchers have devoted efforts to realize memristive devices that emulate the operation mecha-nism of the biological synapse for the neuromorphic appli-cations.[19,77,82,126] One of the basic features required for the artificial synapse is LTP/LTD of the synaptic weight, which is analogous to nonvolatile multilevel resistance switching by electric stimulation.[228] Reliable multilevel cell (MLC) opera-tion of nanomesh-patterned memristor was reported by You et al.,[229] as illustrated in Figure 5a. The Ag nanocone array formed by a SiO2 nanomesh, as shown in Figure 5b, concen-trated the electric field at the tip of the nanocone structure,

leading to the control of the Ag filament formations. Owing to this guided growth of the CF, three distinctive HRS levels were achieved by changing the reset voltages, as presented in Figure 5c,d. To fully emulate the LTP/LTD of a synapse, how-ever, the resistance state of the memristor should be gradu-ally modulated (i.e., analog resistive switching) with respect to increasing/decreasing voltages. Figure 5e illustrates the TiOx-based memristor reported by Gupta et al.,[230] which shows gradual resistance changes depending on the voltage or the number of input pulses. As presented in Figure 5f,g, the resistance state remained constant below the threshold voltage (1.45 V for set operation, −1.65 V for reset operation), and grad-ually increased/decreased with a gradual increase/decrease of the input voltage amplitude above the threshold. Figure 5h,i further show that the resistance state could be modulated by the number of input pulses, as the resistance decreases with an increasing number of positive input pulses (potentiation) and the resistance increases with an increasing number of negative input pulses (depression). Jo et al.[37] introduced the emulation of the STDP, which is another type of long-term synaptic plas-ticity, using an Ag doped Si memristor. The STDP operation of the proposed nanoscale memristor is presented in Figure 5j, indicating that the synaptic weight changes with respect to the relative timing of the presynaptic spike and the postsynaptic spike, analogous to a biological synapse. The synaptic weight (resistance state) of the device increased/decreased when a pre-synaptic pulse was applied before/after the postsynaptic pulse, and the amount of synaptic weight change increased with the a decrease of the timing difference.

In contrast to long-term plasticity, short-term plasticity indicates the temporary change (tens of milliseconds) of syn-aptic weight,[231] depending on the history of the applied neu-ronal spikes. Wang et al.[232] reported a diffusive memristor, which showed threshold switching (volatile resistive switching) by doping a small amount of Ag in an oxide matrix (e.g., Ag:SiOxNy, Ag:HfOx, or Ag:MgOx). Because of the Ostwald rip-ening, the Ag filament formed by the electric field immediately diffused into the oxide matrix after the removing the electric field, leading to a significant decay of the current level and a return to the HRS in tens of milliseconds. Due to the analo-gous behavior of a diffusion induced volatile RS to short-term plasticity, the diffusive memristor could emulate the paired-pulse facilitation/depression (PPF/PPD) of biological synapse, showing a temporary change in the synaptic strength by paired neuronal spikes. If the second pulse was applied before com-plete diffusion of the filament, which was formed by the first spike, it would induce the formation of the Ag CF with an increased radius, resulting in decreased resistance (synaptic weight increase, PPF). If the interval between two pulses were sufficiently large, on the contrary, the Ag filament would dif-fuse into the oxide matrix before the arrival of the second spike. The diffused Ag particles would be accumulated in one side of the electrode due to the electric field, leading to an increase in resistance (synaptic weight decrease, PPD). In addition to the emulation of PPF/PPD, the frequency dependent long-term plasticity, called spike-rate-dependent plasticity (SRDP) was demonstrated by the integrated circuit of diffusive memristor and nonvolatile TaOx memristor. The resistance of the TaOx-based memristor decreases with higher pulse frequency due to






Figure 5. a) Schematic of SiO2 nanomesh-patterned memristor device and b) its resistive switching mechanism showing guided growth of an Ag filament at the tip of the Ag nanocone array. c) I–V curves for MLC operations of nanomesh-patterned memristor with different reset voltage. d) Endurance test results of the SiO2 nanomesh memristor with four distinctive resistance states. e) Illustration of TiOx-based RS memory and atomic force microscopy (AFM) image of a crossbar-structured array. f,g) Gradual resistance modulation using TiOx-based RS memory. The f ) input voltage pulses with increasing voltage amplitude and alternating polarity induces g) continuous resistance changes after the threshold value, +1.45 V for positive bias and −1.65 V for negative bias. h,i) Analog resistive switching depending on the increasing number of h) negative and i) positive pulses. The continuous lines show the fitted curve of the device response using a second-order exponential function. j) STDP operation by an Ag doped Si memristor presenting the synaptic weight change depending on the relative timing of the presynaptic and post-synaptic spikes. The inset shows a scanning electron microscopy (SEM) image of the crossbar-structured memristor array. k) I–V curve of the diffusive memristor indicating the volatile resistive switching behavior. l,m) I–V curve with different preceding voltage pulses in l) log scale and m) linear scale, indicating the emulation of allodynia and hyperalgesia, respectively. n) Frequency dependent synaptic weight change with different prestimulation frequency of 10 and 25 Hz. The synaptic weight change curve slides to positive direction with increasing prestimulation frequency showing the experience-dependent plasticity. o) Examples of grey scale face images with 100 random noise patterns. p) The image classification results of 1 T-1 R memristive network with (blue) and without (red) a write-verify scheme for an increasing noise proportion. q) The conduct-ance change of the flexible memristor with increasing pulse intervals showing PPF/PPD-like behavior. The change in synaptic weight decreases as the pulse interval increases, and finally becomes negative at a 50 ms pulse interval. r) STDP emulation by a flexible ZHO-based memristive device. The solid line indicates the asymmetric Hebbian learning rule. a–d) Reproduced with permission.[229] Copyright 2016, American Chemical Society. e–i) Reproduced with permission.[230] Copyright 2016, the authors, published by Springer Nature under the terms of the CC-BY Creative Commons Attribution 4.0 International License. j) Reproduced with permission.[37] Copyright 2010, American Chemical Society. k–m) Reproduced with permission.[233] Copyright 2018, the authors, published by Springer Nature under the terms of the CC-BY Creative Commons Attribution 4.0 International License. n) Reproduced with permission.[237] Copyright 2018, John Wiley & Sons. o,p) Reproduced with permission.[252] Copy-right 2017, the authors, published by Springer Nature under the terms of the CC-BY Creative Commons Attribution 4.0 International License. q,r) Reproduced with permission.[259] Copyright 2018, Springer Nature.




the PPF/PPD-like behavior of the diffusive memristor, and vice versa emulating the SRDP behavior of neuron.

Using the PPF/PPD-like behavior of the diffusive memristor, Yoon et al.[233] further demonstrated the emulation of a sensory neuron, called a nociceptor, which reacts to a noxious stimulus by sending warning signals to the brain, thereby preventing critical injuries. The same SiOx-based diffusive memristor showing the threshold switching, as presented in Figure 5k, was utilized for the artificial nociceptor. The mechanism of the bio-logical nociceptor, called sensitization, can be described by two different reactions, named allodynia and hyperalgesia.[234,235] When noxious stimulations come to the nociceptor, the nocice-ptor is sensitized, result in the decrease of the pain threshold to feel the pain by normally harmless stimuli (allodynia) and the increased amount of pain by the same noxious stimuli (hyper-algesia). Figure 5l shows the threshold voltage lowering of the diffusive memristor (decreasing pain threshold) with respect to increasing voltage of previous pulses (more noxious preceding stimulus), which is analogous to allodynia of a biological noci-ceptor. Simultaneously, the current output increased (increased amount of pain) with higher amplitude of the previous signals, as demonstrated in Figure 5m, presenting similar behavior to hyperalgesia of the nociceptor. In addition to the emulation of sensitization behavior of a nociceptor, a memristive thermal nociceptor was implemented by coupling the thermoelec-tric module with the diffusive memristor. The thermoelectric plate converted the external heat signal into a voltage spike which was subsequently applied to the artificial nociceptor. The thermal nociceptor emulated by the diffusive memristor demonstrated similar characteristics to those of the human body, showing ON-switching temperature of 40 °C compared to 45 °C of a biological thermal nociceptor.

Milano et al.[236] reported an artificial synaptic device that emulates short-term plasticity using a single nanowire (NW)-based memristor that operates by redox reaction and transpor-tation of diffusive Ag ions. The single crystal ZnO NWs, grown by the chemical vapor deposition (CVD) method, were attached to Ag and Pt electrodes to form a MIM structure. A conductive Ag filament was developed by applying positive voltage to the Ag electrode, which decayed into a number of Ag nanoclusters. Emulation of PPF and PPD using the single NW-based mem-ristor were demonstrated, owing to the electric field driven CF formation and its physicochemical dissolution. A synaptic weight enhancement was observed with high frequency pulse input (PPF), in contrast to a synaptic weight decrease with low frequency pulses (PPD).

Yin et al.[237] demonstrated the emulation of SRDP with sliding threshold, defined as experience-dependent plasticity in Bienenstock, Cooper, and Munro (BCM) theory.[238] Hafnium oxide bilayer (HfOy/HfOx), deposited by changing the oxygen partial pressure in sputtering process, was used as RS medium. Figure 5n presents the emulation of experience-dependent plasticity by the W/HfOy/HfOx/Pt memristor. By increasing the frequency of the prestimulation (experienced pulse train) from 10 to 25 Hz, the synaptic weight function slides to posi-tive direction, showing the lowered average synaptic weight and increased threshold similar to the frequency-response of bio-logical visual cortex.[239] In addition, the metaplasticity, known as plasticity of synaptic plasticity, was imitated by the bilayer

RS memory.[240–242] For the conventional long-term plasticity, the synaptic weight increases by the stimulations above the threshold with same amount of weight change regardless of any prestimulations below the threshold. In case of metaplasticity, the prestimulation affects to the synaptic weight by increasing the amount of weight change induced by the stimulation above threshold, while prestimulation itself does not promote the syn-aptic weight change. The hafnium oxide bilayer RS memory with metaplasticity demonstrated the enhanced synaptic weight change by ≈35% for potentiation and ≈15% for depression.

Ohno et al.[243] demonstrated a Ag2S memristive device that can emulate both the long-term and short-term plasticities by modulating the input pulse intervals. The volatile RS was observed for a longer intervals (20 s), whereas nonvolatile RS was observed for the shorter intervals (2 s). Besides the simple emulation of synaptic plasticities, image memorization was conducted using a 7 × 7 array of Ag2S RS memory cells. Two images of the digits 1 and 2 were simultaneously programmed to an artificial synaptic network with input pulse intervals of 2 s (long-term mode) and 20 s (short-term mode), respectively. The two images were memorized in the Ag2S memristor array with different conductance levels, enabling identification of the two digits. On the contrary, the conventional memory would store the two images as the same conductance incapable of distinc-tions between the images.

Beyond the emulation of synaptic plasticity, several researchers reported innovative learning operations using neu-romorphic memristive devices.[61,244,245] Li et al.[246] proposed a neuromorphic circuit for associative learning, indicating the training of the relationship between events (e.g., Pavlovian con-ditioning) based on an AgInSbTe (AIST) memristor. In Pavlov’s classical conditioning experiment,[247–249] for example, a neu-tral stimulus (NS, bell) accompanied with an unconditioned stimulus (US, food), that induces an unconditioned response (UR, salivation), result in the response of the subject (dog) to the NS. This indicates that the association between the NS and US can be trained by temporally contiguous input of NS and US. The NS after the training process is called the conditioned stimulus (CS) while the corresponding response is called the conditioned response (CR). To demonstrate this timing-related learning, an Ag/AIST/Ta-based memristor was integrated with a series of resistors to build an associative learning circuit. For the training process, high voltage pulses (above ON-voltage, US) were applied simultaneously with the low voltage (below ON-voltage, NS) pulses. The US and NS were associated after the learning process, showing the transition from NS to CS. This association was realized by the STDP-like behavior of the artificial synapse, presenting the synaptic increase with respect to the time interval between the US and NS.

Recently, visual pattern recognition using a memristive neural network was introduced by several researchers as a repre-sentative example of network-level learning.[250,251] Yao et al.[252] demonstrated a 128 × 8 memory array of 1 T-1 R cells employing a Si-based transistor and an Al/TiN/TaOx/HfAlyOx/TiN mem-ristor, which was capable of image classification. As presented in Figure 5o, gray scale images from Yale Face Database with a randomly generated noise patterns were classified by the 1 T-1 R memristive network after training processes with or without write-verify operations. Both learning process are based on the





gradient descent (GD) algorithm, which utilizes gradient of the error between reference and calculation result for the weight update. The difference between with and without write-verify function is the weight update function, whether the error gra-dient is directly reflected to weight update or just indicate the update direction (positive or negative). In the case of face images without noise patterns, the proposed electronic synapse correctly classified 22 out of 24 images, similar to the recognition rate of a classical computing system. Figure 5p shows the classifica-tion rate with (blue) and without (red) the write-verify operation depending on the increasing noise proportion in the image. The average classification rates of noisy images were 88.08% (with write-verify) and 85.04% (without write-verify), showing slightly lower values with much higher power efficiency compared to a Si circuit-based system. Furthermore, Li et al.[253] introduced self-adaptive in situ learning by a two-layer memristive neural network, using a 128 × 64 array of 1 T-1 R cells employing a Si-based transistor and a Ta/HfO2/Pt memristor. For the training process, 80 000 gray scale images of hand-written digits were utilized with the stochastic gradient descent (SGD) algorithm. In contrast to GD algorithm, which calculates error gradient from every data point, SGD algorithm calculates error gradient from small subset of data to decrease the amount of calculation and faster result. 10 000 digit images from separate sets were classified by the 1 T-1 R neural network with a recognition rate of 91.71%. Despite a hardware defect rate of 11%, the recogni-tion rate was only slightly lower than the ideal classification rate (by 2.4%), thus demonstrating the potential of fault-tolerant computations by a memristive neural network.

Although memristive neural network based on GD and SGD algorithm showed excellent learning capability, both algorithm have inherent limitations of slow speed and inaccuracy. A gra-dient descent optimizer such as adaptive gradient (AdaGrad),[254] root-mean-square propagation (RMSProp),[255] and momentum can be used to overcome such limitations.[256] However, only a few reports demonstrated the memristive neural network with the advanced learning algorithm, while simulation studies of learning algorithm with memristor network model have been presented by many researchers recently. Li et al.[257] reported memristive neural network called long short-term memory (LSTM) with momentum and RMSProp optimizer.[258] The SGD with momentum (SGDM) algorithm was used for the prediction of airline passenger problem, showing exact pre-diction of passenger numbers after 800 epochs of training. The gait classification was also conducted by LSTM memory with RMSProp algorithm, presenting 79.1% accuracy after 50 epochs of training. It is noteworthy that aforementioned works utilizes external software to calculate the learning algo-rithms such as GD, SGD, SGDM, and RMSProp, which should be implemented in circuit-level or auxiliary memory for the future application of memristive neural networks.

A flexible neuromorphic memristor was demonstrated by Yan et al.[259] using a TiN/ZHO/IGZO memristor and a mica substrate in 2018. The presented flexible memristive device showed stable threshold switching after bending iterations of 1000 cycles at a 15 mm bending radius, due to the high mechanical flexibility of the mica substrate. Figure 5q illustrates the PPF/PPD operation of the ZHO-based flexible memristor with different pulse intervals. The increment of synaptic weight

decreased with increasing pulse intervals, and even reversed from a 50 ms interval, indicating the transition from PPF to PPD. Furthermore, the asymmetric Hebbian learning rule, the most followed STDP rule in the neocortex,[260] was imitated by the flexible memristive device, as demonstrated in Figure 5r. Although the proposed device successfully emulated the syn-aptic plasticity at the device level, network-level studies (e.g., associative learning, pattern recognition, and fault-tolerant computation) using flexible memristive device should be fur-ther investigated for the realization of the BMI and AIS.

6. Conclusion

In this review, we discussed the recent advances in memris-tive devices, including RS memories, PCMs, flexible memories, and artificial synapses in terms of performance and integration. Innovative methodologies have been exploited to improve the cell reliability, reproducibility, and scalability for high-perfor-mance memristive operations. Selection devices have been inte-grated with memristive cells to enable random access operation in a crossbar-structured parallel array. These memristors were implemented in a flexible form for potential wearable electronics and BMI. Lastly, brain-inspired memristive devices emulating the operation mechanism of the neuronal network were studied for upcoming AI applications. As artificial synapses, memristors have provided significant advances in the field of brain-inspired neuromorphic computing and can potentially provide a signifi-cant breakthrough in the development of future AIS.

AcknowledgementsS.H.S. and D.H.K. contributed equally to this work. This work was supported by the Wearable Platform Materials Technology Center (WMC) (NRF-2016R1A5A1009926), Nano·Material Technology Development Program (NRF-2016M3A7B4910636) through the National Research Foundation of Korea (NRF) funded by the Ministry of Science, ICT and Future Planning. This work was supported by the National Research Foundation (NRF) of Korea funded by the Ministry of Science, ICT and Future Planning (Grant No. NRF-2017R1A2A1A18071765).

Conflict of InterestThe authors declare no conflict of interest.

Keywordsadvanced intelligent systems, artificial synapses, flexible memory, memristors, neuromorphic computing

Received: January 23, 2019Revised: February 12, 2019

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