Thin Solid Films 520 (2012) 3149–3154

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Ultra-low resistivity in-situ phosphorus doped Si and SiC epitaxy for source/drainformation in advanced 20 nm n-type field effect transistor devices

Nicolas Loubet a,⁎, Thomas Adam b, Mark Raymond c, Qing Liu a, Kangguo Cheng b,Raghavasimhan Sreenivasan b, Alexander Reznicek b, Prasanna Khare a, Walter Kleemeier a,Vamsi Paruchuri b, Bruce Doris b, Ron Sampson a

a STMicroelectronics, Albany NanoTech, 257 Fuller Road, Albany, NY 12203 USAb IBM, Albany NanoTech, 257 Fuller Road, Albany, NY 12203 USAc GLOBALFOUNDRIES, Albany NanoTech, 257 Fuller Road, Albany, NY 12203 USA

⁎ Corresponding author. Tel.: +1 518 292 7220.E-mail address: nloub@us.ibm.com (N. Loubet).

0040-6090/$ – see front matter © 2011 Elsevier B.V. Alldoi:10.1016/j.tsf.2011.10.106

a b s t r a c t

a r t i c l e i n f o

Available online 29 October 2011

Keywords:EpitaxySiCPhosphorusIn-situ dopedLaserActivation anneal

We present an effective epitaxy process based on a cyclical deposition-etch (CDE) technique to obtain ultra-lowresistivity in situ phosphorus-doped silicon carbon (SiCP) layers for raised source/drain applications. Thecombined low process temperature and high growth rate of the CDE technique is shown to maximize theincorporation of phosphorus and carbon into the crystal. We also present a complementary procedurebased uponhigh-temperature annealing to further improve the phosphorus activation. This process andprocedureenable the formation of raised SiCP source/drains on advanced 20 nm fully-depleted-silicon-on-insulator deviceswith a carrier density up to 3×1020 cm−3 for 5×1020 cm−3 total P, and with fully-substitutional carbon in therange from 0% to 2%. It was found that a 1250 °C millisecond laser anneal improves resistivity by 30% and 42%for SiP and SiC2.1%P, respectively. This result is in contrast with a 1060 °C spike anneal, where the gain in activatedP is shown to be insignificant for SiCP. It is shown that the formation of C clusters or precipitates during spike annealadversely affects P activation. With an optimized annealing process, resistivity values as low as 0.46 MΩ cm forSiC2.1%P and 0.3 MΩ cm for SiP were obtained.

© 2011 Elsevier B.V. All rights reserved.

1. Introduction

In today's advanced silicon devices, in-situ phosphorus doped siliconcarbon (SiCP) can be used in either recessed source/drain [1–4] orraised source/drain (RSD) [5,6] applications to induce strain in thechannel of n-typefield effect transistor (nFET) devices and consequentlyincrease its channel electron mobility. The application of in-situ dopedepitaxy to form the RSD junctions of thin-film devices has an addedbenefit in that it also does not require damaging implant steps andenables the construction of very abrupt dopant profiles [7]. Thispaper describes a SiCP selective epitaxy process which was developedto achieve ultra-low resistivity values with high carrier density. Thisselective epitaxy process, defined using the cyclical deposition-etch(CDE) technique [8,9], was then applied to form a RSD structure andcharacterized on 20 nm fully-depleted-silicon-on-insulator (FDSOI)devices [10,11]. In the first part, we will describe the capabilities ofthe gas mixture based on commercially available Si2H6. It enableshigh substitutional C and P as well as the realization of a faceted in-situP doped RSD SiC structure in 100 nm gate pitch devices. In the last

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part, we will show the important improvement in sheet resistivitymeasured after the application of various dopant-activation anneals.

2. Experimental details

All deposition stepswere carried out in a 300 mmstandard industrialRapid Thermal Chemical Vapor Deposition reactor, including the lowtemperature (b600 °C) cyclic epitaxy process. A Si2H6-based gas mixfor Si deposition was used, combined with SiH3CH3 (MMS) and PH3 forcarbon and phosphorus incorporation, respectively. Finally, HCl wasused as the gas-phase etchant. Fig. 1 describes the CDE process, whichconsists of a two-step sequence: 1) a non-selective deposition stepwith a Si2H6-based gas mixture which results in the deposition ofcrystalline, poly-crystalline and amorphous films, followed by 2) anetch-back of the amorphous Si:C:P (α-SiC) and defective crystallineSi:C (c-SiC) films using HCl gas. Due to the higher etch rate of theamorphous or poly silicon films compared to its mono-crystallinephase [12], and a conformal α-Si:C deposition at low temperatures,net growth with this cyclic process occurs only on the exposed silicon(active device area) where the mono-crystalline phase is present.Scanning electron microscope (SEM) cross-sections in Fig. 1 illustratethe morphology of the deposited material on wafers after thenon selective deposition step and after the selective etch of α-SiC

Fig. 1. Description of the cyclical deposition-etch (CDE) epitaxy process using silanes. Each deposition step (step ①) is followed by HCl etch-back of the amorphous α-SiCP ondielectrics (step ②). Included are SEM micrographs after non selective deposition of SiCP and after selective etch of the amorphous layer α-SiCP. After n cycles, a raised sourcedrain structure is obtained. The junctions are formed by a dopant activation step following the epitaxy.

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and defective c-SiC. Using this cyclic process, high quality SiCPfilms were grown in the source/drain regions of nFETs where thefinal thickness was controlled by the number of deposition/etchcycles (n). When integrated as part of a transistor architecture definedwith thin spacers between the gate and RSD, an effective electricalconnection can be made between the SiCP RSD and channel suchthat efficient transistor operation is obtained.

In order to enable sufficient incorporation of phosphorus and carboninto the SiCP film, a combination of low process temperature and fastgrowth rate is required to ensure substitutional occupancy, a keyrequirement for strain-enhanced mobility and low resistivityRSDs [13,14]. Just as important for the function of the CDE processdescribed in this work, a non selective epitaxial deposition at lowtemperature results in a smooth conformal deposition of α-SiC ondielectric surfaces without the formation of discontinuous poly SiCPgrains [15]. This conformal deposition ensures a maximum efficiency ofthe subsequent etch step of the CDE process. In this work, temperaturesbelow 600 °C were used for SiCP deposition. To improve the depositionrate at low temperature and assure a high-level of P incorporation intothe film, an optimized mixture of PH3 and MMS co-injected with Si2H6

was chosen. Although not reported in this work, the use of higherorder silanes such as Si3H8 can represent a potential alternative, as theyhave the capability to decompose at very low temperatures down to550 °C [16,17]. Other alternatives, such as dichlorosilane SiH2Cl2 (DCS)or SiH4, lead to unacceptably slow SiCP growth rates at temperaturesbelow 650 °C. The addition of PH3 also lowers the growth rate due to astrong surface segregation [18], but this effect can be compensatedto recover the growth rate when N2 gas is used as a carrier insteadof H2. For the HCl etch step, very low etch rates of α-SiCP werereported previously [19]. It is reported here that an etch process athigher pressure can lead to more acceptable etch rates even at verylow working temperatures. Cl2 as an alternative etchant to HCl is notpreferred as Cl2 reacts with silicon and exhibits poor α-SiCP/c-SiCPselectivity [20]. Finally, when combined with a good separation in etchrate between α-SiCP and c-SiCP phases, a net deposition only on the

active areas of the devices is achieved. In the CDE process optimized inthis work, the total duration of an individual cycle was approximatelyone minute, where each cycle includes gas, temperature, and pressurestabilization, as well as the main deposition and etch steps. Corre-sponding net growth rates in the range 2 nm/min–4 nm/min weredemonstrated, which is consistentwith the process throughput requiredfor industrial applications.

For electrical and physical characterization, epitaxial layers weregrown on 300 mm un-patterned p-type silicon (100) wafers. An insitu high-temperature anneal in a hydrogen ambient for surfacecleaning was applied immediately prior to deposition. Resistivityvalues before and after various activation-anneals were extracted bymultiplying the sheet resistance measured using an industrialfour-point probe full wafer map in combination with the thicknessof the layer given by X-ray diffraction (XRD) using a BedeMetrix-Lin triple-axis mode with a sealed Cu-Ka tube. The primary beamwas conditioned using a multilayer X-ray mirror, 2-bounce Ge (004)beam conditioner, and motorized anti-scattering slits. XRD was alsoemployed to determine the amount of incorporated carbon in substitu-tional sites using the relationship between lattice constant and carbonconcentration identified by Kelires [21]. Finally, the samples wereanalyzed by secondary ion-mass spectroscopy (SIMS) to quantify thetotal amount of carbon and phosphorus atoms present in the crystal.For the SIMS, a model Cameca IMS-Wf with 500 eV Cs-ion sputteringat 48° was used. Ion-implanted standards were used to convert theraw SIMS signals into corresponding concentrations of P and C.

For patterned wafers used to demonstrate FDSOI device integration,an in situ pre-clean plus low-temperature in situ anneal was added tothe CDE process. Within the CDE steps itself, only the HCl etch timewas adjusted in order to enable a net growth rate per cycle of thesame order of magnitude as achieved using un-patterned wafers. Afterdeposition, a dopant drive-in anneal was performed on the fabricateddevices, including a spike anneal for junction formationwith an optionalmillisecond laser activation (DSA) to define the electrical connection ofthe fabricated RSD to the device channel. A spike anneal temperature

Fig. 3. Apparent substitutional C measured with XRD for increasing MMS and PH3 partialpressures (a). A comparison with the total carbon concentration is also reported showinga linear trend (b).

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of 1060 °C was selected for the devices and spacer widths reported inthis work. Reference blanket wafers were also processed under thesame epitaxy conditions and measured by SIMS before and after spikeanneal.

3. Results and discussion

3.1. Process characterization on blanket wafers

In Fig. 2, XRD results are reported for layers deposited using a partialpressure of PH3=5×10−2 Pa and varying amounts of MMS showingthe good epitaxy quality maintained even at high doping and substitu-tional C. A change in lattice parameter of silicon due to the presence ofphosphorus in the crystal matrix was also observed. For this SiP case,the measured tensile strain due to substitutional P was equivalent to[C]sub≈0.21%. The apparent substitutional carbon ([C]sub) measuredwith XRD plotted as a function of the MMS partial pressure (PMMS) forvarious PH3 partial pressures was compared in Fig. 3 with the totalcarbon concentration ([C]total) given by SIMS. It can be seen that thecarbon incorporation is following a linear trendwith PMMS independentof the partial pressure of PH3 at first order. In addition, due to the lowdeposition temperature, [C]sub=[C]total for the lowest doping levels.Fig. 3a also shows that at higher partial pressures of PH3 the amountof C present in a substitutional site in the crystal is reduced even though[C]total remains constant (Fig. 3b).

Fig. 4a and b plot resistivity as a measure of substitutional Pconcentration and total P concentration from SIMS both as a functionof [C]total. It was found that increased carbon incorporation dramaticallyincreased the film resistivity. Since carbon and phosphorous competefor substitutional sites, an inverse relationship between substitutionalcarbon concentration and free carrier density results. From Fig. 4a, thelowest resistivity values were obtained for SiP without carbonwith an ‘as deposited’ resistivity of 0.39 MΩ cm measured on blanketwafers, which is equivalent to 2×1020 cm−3 free carriers. This carrierconcentrationwas found to be a higher value versus what was reportedpreviously with DCS [22,23] or SiH4 [24], and comparable to valuesalready reported using high-order silanes such as trisilane Si3H8

[25,26]. The corresponding total P incorporation was 5×1020 cm−3.

3.2. Realization on FDSOI device in 20 nm technology

Fig. 5a and b, respectively, show scanning electron microscope(SEM) cross sections of 20 nm design-rule compliant FDSOI devices

Fig. 2. Omega-2Theta scans around the (004) XRD order (3600 arc sec=1°) for SiC filmsfor a constant dopant injection PPH3=5×10−2 Pa and various PMMS. Without carbon, aSi–P peak is visible showing the strain induced by P inclusion in the silicon crystalequivalent to 0.21% substitutional C.

fabricated using CDE-deposited SiP and SiC1.5%P. Before imaging, thesamples were covered with a thin Cr layer and observed with a HitachiS5500 SEMapparatus at an operating voltage of 4 kV. Both cross sectionsexhibit the targeted 25 nm RSD. Spacers and SiN hard-masks were

Fig. 4. Resistivity as a function of the total C concentration for increasing PH3 (a). Thetotal phosphorus concentration measured with SIMS is also reported in (b) showinga slightly better incorporation of P with lower C.

Fig. 7. Resistivity as a function of the total carbon concentration measured after differentlaser anneals (DSA) for temperatures from 950 °C up to 1250 °C. A strong improvement inthe phosphorus incorporation can be observed at temperatures above 1150 °C.

Fig. 5. SEMcross sections of planar FDSOI deviceswith (a) SiP and (b) SiCPRSDs fabricatedusing the CDE process.

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preserved during selective removal of α-SiCP. Through additionaloptimization of the CDE process a facet was formed next to thespacer sidewalls [27] which results in a lower measured parasiticsource/drain to gate capacitance during dynamic transistor operation

Fig. 6. SIMS data of SiCP layers before/after spike anneal at 1060 °C. The thicknessextracted from XRD measurement is indicated with dotted lines for each layer andthe effect of carbon attenuating the phosphorus diffusion is highlighted with arrows.

[28]. Corresponding SIMS results on the un-patternedwafers processedbefore and after the 1060 °C spike anneal are reported in Fig. 6. Layerthicknesses are different on these un-patterned wafers due to the useof the CDE process which was optimized for patterned wafers. Withoutcarbon, P diffusion is observed after annealing at high temperaturewhile the presence of a small amount of carbon in the crystal latticedramatically suppresses the diffusion of phosphorous. Themore carbonincorporated in thefilm, the less diffusion into the substrate is observed.A small amount of phosphorus out-diffusion was measured at thesample surface. However, the overall total [P] and [C] in the crystalwas not significantly modified after thermal anneal.

3.3. Resistivity improvement after various dopant activations

Of particular interest to the CMOS community is the effect of a‘diffusion-less’ process, such as amillisecond laser annealing treatment,on dopant activation and hence, film resistivity. As-deposited sampleswere subjected to laser anneals with peak temperatures ranging from950 °C to 1250 °C to determine the threshold “dynamic” wafer surfacetemperature (or threshold laser power/dose) at which activation ofthe phosphorus dopant atoms initiated. These results are reported inFig. 7, where the ‘as deposited’ resistivity is included as referencecompared to the resistivity measured after various laser annealingconditions. Note that below 1150 °C no significant improvement inresistivity was detected. However, above this temperature, the resistivityof the film is reduced. The improvement obtained after laser annealing

Fig. 8. Resistivity as a function of the total carbon concentration measured after differentthermal treatments for dopant activation: 1250 °C laser annealing (DSA) and 1060 °Cspike only, and with added 1250 °C DSA before or after spike.

Fig. 9. Apparent [C]sub measured with XRD as a function of carbon concentration aftervarious thermal treatments: using 1250 °C laser annealing (DSA) and 1060 °C spikealone, or with added 1250 °C DSA before or after spike.

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strongly depends on the carbon concentration. For higher temperatures,the variation of the resistivity as a function of the total carbon concentra-tion becomes linear. Best measured resistivity improvements were 30%for SiP and 42% for SiC2.1%P after a laser annealing at 1250 °C.

Finally, the resistivity of the films after various anneals used fordopant activation and drive-in was measured (Fig. 8). As a reference,the best activation results with 1250 °C laser annealing are reportedand compared with a conventional spike 1060 °C as well as differentcombinations of laser and spike annealing. Lowest film resistivities wereobtained for samples subjected to laser annealing only, independent ofthe carbon concentration in the layer. Without carbon, the resistivity ofSiP is always improved after activation anneal. This result suggests thatthe presence of carbon in the film is impeding P activation after thespike anneal. A spike anneal generally degrades SiCP resistivity, and thisdegradation can only partially be recovered with laser annealing. As[C]total and [P]total remain constant after the spike anneal, it is necessaryto compare the effect of these various anneals on the amount of carbonsubstitution to better understand the interaction between carbon andphosphorus. It has been previously reported that C substitution isenhanced after laser anneal [3,14], and that there is a negative impacton SiCP resistivity if temperatures above 950 °C are used for thesubsequent spike anneal [4,29]. Results from this work are reportedin Fig. 9 and are consistent with this previously reported result. Thecarbon and phosphorus behavior are similar: the carbon substitutionincreases after a laser treatment at 1250 °C, but is dramaticallyreduced after the spike anneal. The improvement in resistivityand change in [C]sub are compared in Fig. 10. The improvement

Fig. 10. Resistivity improvement observed after anneals (top set of figures). The variation inafter anneal−as-deposited resistivity)/as-deposited resistivity and Δ[C]sub=([C]sub after anwere measured in Si and SiC2%, respectively, using only millisecond laser annealing. The bodrop in [C]sub after spike not recoverable with a 1250 °C laser annealing.

in resistivity is not as significant after the spike anneal. This reductionin anneal efficiency for resistivity reduction is likely due to theformation of stable carbon precipitates or clusters which would impactthe P mobility. Evidence of this condition comes from the observationthat the C atomswere not able to be reactivated even after an additionallaser anneal at high temperature. However, for SiP an approximate 30%improvement in resistivity was achieved following all thermaltreatment conditions studied, with resistivity values measured aslow as 0.3 MΩ cm. For SiCP, large increases in C and P activation aremeasured after laser anneal only, with a best value of 0.46 MΩ cmmeasured for SiC2.1%P.

4. Conclusions

The capability of a low-temperature cyclical deposition-etch epitaxyprocess based on Si2H6 has been demonstrated to fabricate SiCP filmsexhibiting very-high, electrically-active P and C concentrations. Thisprocess was characterized and used to implement SiCP RSD structuresfor FDSOI devices with 20 nm design rules. It was shown that theaddition of a 1060 °C spike anneal for dopant diffusion had a negativeimpact on the substitution level of C. A high level of dopant activationwas achieved using a laser anneal, with resistivity values of0.46 MΩ cm for SiC2.1%P and 0.3 MΩ cm for SiP, which is equivalent toa carrier concentration of 3×1020 cm−3 for 5×1020 cm−3 total Pincluded in the crystal. The combination of these results demonstratesthe application of selective epitaxial layers to form RSD structureswith ultra-low resistivity and shallow dopant distribution, highlightingthe benefits of using in-situ doped epitaxy techniques for junction andstrain engineering for the most advanced field effect transistor devices.

Acknowledgments

The authors would like to thank all the many technicians, engineersand personnel involved at Albany Nanotech and the College ofNanoscale Science and Engineering for their help and everydaysupport.

References

[1] Z. Ren, G. Pei, J. Li, B. Yang, R. Takalkar, K. Chan, G. Xia, Z. Zhu, A. Madan, T. Pinto, T.Adam, J. Miller, A. Dube, L. Black, J.W. Weijtmans, B. Yang, E. Harley, A. Chakra-varti, T. Kanarsky, R. Pal, I. Lauer, D.-G. Park, D. Sadana, 2008 Symposium onVLSI Technology, 2008, p. 172.

[2] B. Yang, Z. Ren, R. Takalkar, L. Black, A. Dube, J.W. Weijtmans, J. Li, K. Chan, J. DeSouza, A. Madan, G. Xia, Z. Zhu, J. Faltermeier, A. Reznicek, T.N. Adam, A. Chakra-varti, G. Pei, R. Pal, B. Yang, E. Harley, B. Greene, A. Gehring, M. Cai, D. Sadana, D.-G. Park, D. Mocuta, D. Schepis, E. Maciejewski, S. Luning, E. Leobandung, ECSTrans. 16 (10) (2008) 317.

resistivity and substitutional carbon are defined as follows: ΔResistivity=(resistivityneal−as-deposited [C]sub)/as-deposited [C]sub. Improvements as much as 30% and 42%ttom set of figures depicts the strain improvement after laser anneal and the dramatic

3154 N. Loubet et al. / Thin Solid Films 520 (2012) 3149–3154

[3] P. Grudowski, V. Dhandapani, S. Zollner, D. Goedeke, K. Loiko, D. Tekleab, V.Adams, G. Spencer, H. Desjardins, L. Prabhu, R. Garcia, M. Foisy, D. Theodore, M.Bauer, D. Weeks, S. Thomas, A. Thean, B. White, IEEE International SOI ConferenceProceedings, 2008, p. 17.

[4] P. Verheyen, V. Machkaoutsan, M. Bauer, D. Weeks, C. Kerner, F. Clemente, H.Bender, D. Shamiryan, R. Loo, T. Hoffmann, P. Absil, S. Biesemans, S.G. Thomas,IEEE Electron Device Lett. 29 (11) (2008) 1206.

[5] K.-J. Chui, K.-W. Ang, H.-C. Chin, C. Shen, L.-Y. Wong, C.-H. Tung, N. Balasubrama-nian, M.F. Li, G.S. Samudra, Y.-C. Yeo, IEEE Electron Device Lett. 27 (9) (2006) 778.

[6] T.-Y. Liow, K.-M. Tan, D. Weeks, R. Tek Po Lee, M. Zhu, K.-M. Hoe, C.-H. Tung, M.Bauer, J. Spear, S.G. Thomas, G.S. Samudra, N. Balasubramanian, Y.-C. Yeo, IEEETrans. Electron Devices 55 (9) (2008) 2475.

[7] K. Cheng, A. Khakifirooz, P. Kulkarni, S. Ponoth, J. Kuss, D. Shahrjerdi, L.F. Edge, A.Kimball, S. Kanakasabapathy, K. Xiu, S. Schmitz, A. Reznicek, T. Adam, H. He, N.Loubet, S. Holmes, S. Mehta, D. Yang, A. Upham, S.-C. Seo, J.L. Herman, R. Johnson,Y. Zhu, P. Jamison, B.S. Haran, Z. Zhu, L.H. Vanamurth, S. Fan, D. Horak, H. Bu, P.J.Oldiges, D.K. Sadana, P. Kozlowski, D. McHerron, J. O'Neill, B. Doris, 2009 Sympo-sium on VLSI Technology, 2009, p. 212.

[8] M. Bauer, Y. Zhang, D. Weeks, V. Machkaoutsan, S.G. Thomas, ECS Trans. 6 (1)(2007) 419.

[9] Z. Ye, Y. Kim, X. Li, A. Zojaji, N.C. Dalida, X. Chen, A.V. Samoilev, US patent7682940 (2010).

[10] Q. Liu, A. Yagishita, N. Loubet, A. Khakifirooz, P. Kulkarni, T. Yamamoto, K. Cheng,M. Fujiwara, J. Cai, D. Dorman, S. Mehta, P. Khare, K. Yako, Y. Zhu, S. Mignot, S.Kanakasabapathy, S. Monfray, F. Boeuf, C. Koburger, H. Sunamura, S. Ponoth, A.Reznicek, B. Haran, A. Upham, R. Johnson, L.F. Edge, J. Kuss, T. Levin, N. Berliner,E. Leobandung, T. Skotnicki, M. Hane, H. Bu, K. Ishimaru, W. Kleemeier, M. Takaya-nagi, B. Doris, R. Sampson, 2010 Symposium on VLSI Technology, 2010, p. 61.

[11] M. Bauer, S.G. Thomas, ECS Trans. 33 (6) (2010) 629.[12] N. Loubet, P. Khare, Q. Liu, M. Takayanagi, R. Sampson, Proc. Solid State Devices

Mater. 2009 (2009) 992.

[13] M. Bauer, V. Machkauotsan, C. Arena, Semicond. Sci. Technol. 22 (2007) 183.[14] A. Dube, A. Chakravarti, R. Takalkar, J. Li, F. Yang, A. Madam, Z. Zhu, R. Loesing, R.

Murphy, T.N. Adam, L.R. Black, J.R. Holt, E.C.T. Harley, M.W. Stoker, D.J. Schepis, X.Chen, ECS Trans. 28 (2010) 63.

[15] J.M. Hartmann, M. Py, P.H. Morel, T. Ernst, B. Previtali, J.P. Barnes, N. Vulliet, N.Cherkashin, S. Reboh, M. Hytch, V. Paillard, ECS Trans. 33 (6) (2010) 391.

[16] M. Bauer, S.G. Thomas, ECS Trans. 25 (8) (2009) 667.[17] J.M. Hartmann, L. Clavelier, C. Jahan, P. Holliger, G. Rolland, T. Billon, C. Defranoux,

J. Cryst. Growth 264 (2004) 36.[18] T. Ikuta, S. Fujita, H. Iwamoto, S. Kadomura, T. Shimura, H. Watanabe, K. Yasutake,

J. Cryst. Growth 310 (2008) 4507.[19] E. Suvar, H.H. Radamson, J.V. Grahn, Mater. Sci. Eng. B 89 (2002) 314.[20] M. Bauer, D. Weeks, Y. Zhang, V. Machkaoutsan, ECS Trans. 3 (7) (2006) 187.[21] H.-S. Wong, K.-W. Ang, L. Chan, K.-M. Hoe, C.-H. Tung, N. Balasubramanian, D.

Weeks, M. Bauer, J. Spear, S.G. Thomas, G. Samudra, Y.-C. Yeo, IEEE Electron De-vice Lett. 29 (5) (2008) 460.

[22] S. Chopra, Z. Ye, A. Zojaji, Y. Kim, S. Kuppurao, ECS Trans. 13 (1) (2008) 307.[23] A. Gouye, O. Kermarrec, A. Halimaoui, Y. Campidelli, D. Rouchon, M. Burdin, P.

Holliger, D. Bensahel, J. Cryst. Growth 311 (2009) 3522.[24] B. Cho, J. Bareno, Y.L. Foo, S. Hong, T. Spila, I. Petrov, J.E. Greene, J. Appl. Phys. 103

(2008) 123530.[25] A. Gouye, F. Hue, A. Halimaoui, O. Kermarrec, Y. Campidelli, M.J. Hytch, F. Houdel-

lier, A. Claverie, D. Bensahel, Mater. Sci. Semicond. Process. 12 (2009) 34.[26] P.C. Kelires, Phys. Rev. B 55 (1997) 8784.[27] N. Loubet, P. Khare, S. Mehta, S. Ponoth, B. Haran, Q. Liu, K. Cheng, J. Kuss, T. Adam,

B. Doris, V. Paruchuri, W. Kleemeier, R. Sampson, Proceedings of Solid State De-vices and Materials 2010, 2010, p. 984.

[28] A. Khakifirooz, D.A. Antoniadis, IEEE Trans. Electron Devices 55 (2008) 1401.[29] M. Bauer, V. Machkaoutsan, Y. Zhang, D. Weeks, J. Spear, S.G. Thomas, P. Ver-

heyen, C. Kerner, F. Clemente, H. Bender, D. Shamiryan, R. Loo, A. Hikavyy, T. Hoff-mann, P. Absil, S. Biesemans, ECS Trans. 16 (10) (2008) 1001.