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RTL and TechnologySchematic ViewersTutorial

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RTL and Technology Schematic Viewers Tutorial www.xilinx.com UG685 (v13.1) March 1, 2011

The information disclosed to you hereunder (the Information) is provided AS-IS with no warranty of any kind, express or implied. Xilinxdoes not assume any liability arising from your use of the Information. You are responsible for obtaining any rights you may require for youruse of this Information. Xilinx reserves the right to make changes, at any time, to the Information without notice and at its sole discretion.Xilinx assumes no obligation to correct any errors contained in the Information or to advise you of any corrections or updates. Xilinxexpressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with theInformation. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THEINFORMATION, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, ORNONINFRINGEMENT OF THIRD-PARTY RIGHTS.

Copyright 2011 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks ofXilinx in the United States and other countries. All other trademarks are the property of their respective owners.

Revision History

The following table shows the revision history for this document.

Date Version Revision03/01/11 13.1 Updated to show that design is available from ISE Examples.

Updated graphics.
http://www.xilinx.com/http://www.xilinx.com/

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RTL and Technology Schematic Viewers Tutorial www.xilinx.com 3UG685 (v13.1) March 1, 2011

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Chapter 1: Schematic Viewer: Brief Overview

Design Flow Benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Flexibility for Both Project Navigator and Command Line Users . . . . . . . . . . . . . . 7

Chapter 2: Tutorial Description

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Prerequisites . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Chapter 3: Lab Preparation: Getting StartedInstalling a Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Setting Up Project Navigator Preferences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Chapter 4: Lab 1: Basic Features

Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Lab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Conclusion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Chapter 5: Lab 2: Working with Hierarchical Netlists

Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Lab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Conclusion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Chapter 6: Lab 3: Using Schematic Viewer for Timing Analysis

Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Lab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Conclusion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Chapter 7: Lab 4: Simplifying Design Analysis

Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Lab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Conclusion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Chapter 8: Lab 5: Comparing Two Design Implementations

Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Lab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table of Contents

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4 www.xilinx.com RTL and Technology Schematic Viewers TutorialUG685 (v13.1) March 1, 2011

Conclusion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Chapter 9: Lab 6: Dealing with Large Designs

Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Tip 1: Using Hierarchical Netlists. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Tip 2: Using Multiple Schematic Sheets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50Conclusion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Chapter 10: Lab 7: Using the Schematic Viewer as a Standalone Tool

Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Lab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Conclusion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Appendix A: Additional Resources

Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

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Chapter 1

Schematic Viewer: Brief Overview

Design Flow Benefits

The goal of this tutorial is to provide a quick introduction to the main capabilities of theSchematic Viewer available from the ISE Design Suite and how you can use thesecapabilities for design analysis and debugging. With the rapid growth in the size andcomplexity of FPGA designs, it is critical to have tools that ease the way you analyze anddebug your designs.

Some common questions can be answered by using the Schematic Viewer:

How is my HDL code interpreted by the synthesis tool?

How is my HDL code mapped to the target technology?

Where is my critical timing path situated?

In addition, todays advanced designs are often completed by several designers located indifferent parts of the world, where each designer is responsible for a part of the design.This complicates design analysis even further, and good debugging tools become critical.

Graphical tools such as the Schematic Viewer, PlanAhead software, and FPGA Editorsignificantly simplify design analysis.

In this tutorial, we introduce the latest version of the Schematic Viewer, a tool which

provides powerful ways to view and analyze your designs from different perspectives.

Key Features

The Schematic Viewer provides a flexible interface that allows you to focus on the part ofthe design that interests you. This ability to incrementally expand or localize the view ondemand provides a significantly faster means to navigate through your design.

The Schematic Viewer provides you with powerful analysis features, such as:

Drawing the schematic by selecting the only elements of interest

Extracting Input/Output logic cones

Removing objects that are not of interest Navigating Forward/Back history of previous analysis steps

Working with multiple schematics of the same netlist

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The Schematic Viewer as shown in Figure 1-1 has significantly improved performance,which improves your ability to deal with higher complexity designs.

Ultimately, the Schematic Viewer provides you with the fundamental capabilities tovisualize:

RTL views of the design

Post-synthesis netlists

Critical timing path delays reported in the post-place and route timing report (fromTiming Analyzer)

RTL ViewRTL View is a Register Transfer Level graphical representation of your design. Thisrepresentation (.ngr file produced by Xilinx Synthesis Technology (XST)) is generated bythe synthesis tool at earlier stages of a synthesis process when technology mapping is notyet completed. The goal of this view is to be as close as possible to the original HDL code.In the RTL view, the design is represented in terms of macro blocks, such as adders,multipliers, and registers. Standard combinatorial logic is mapped onto logic gates, such asAND, NAND, and OR.

Post-Synthesis Netlist

Graphical representation of the post-synthesis (optimized and mapped) netlist (.ngc

file produced by XST) contains Xilinx primitives as defined in the UNISIM library, such asLUTs, DCM, I/O buffers, and flip-flops. The Schematic Viewer allows you to visualize theprimitive properties and the constraints attached to them.

Critical Path View

When used as a cross probe target from the Timing Analyzer report, the critical timing pathof your design is represented using the post-place and route netlist. This netlist is differentfrom the post-synthesis netlist and represents your design in terms of slices.

X-RefTarget - Figure 1-1

Figure 1-1: Schematic Viewer

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Flexibility for Both Project Navigator and Command Line Users

Flexibility for Both Project Navigator and Command Line Users

Your particular design methodology (command line vs. Project Navigator) determineswhich set of features you can use in the Schematic Viewer. Use the following table tofamiliarize yourself with the features available to you.

Case 1: ISE Project Navigator

Case 2: Command Line

Although you cannot launch Schematic Viewer in a standalone mode, there is aworkaround to emulate this use model and enable you to use the Schematic Viewer toexplore the XST RTL View or XST post-synthesis netlists. Post-map and post-place androute netlists are not handled in this mode.

Please refer to Chapter 10, Lab 7: Using the Schematic Viewer as a Standalone Tool formore information.

Table 1-1: Design Features

Synthesis Tool RTL ViewPost-Synthesis

NetlistCritical Path Notes

XST Yes Yes YesUse ISE environment to fully implement your

design, and XST is your synthesis tool

Third party - - YesUse ISE environment to fully implement yourdesign, and use a third-party synthesis tool.

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Chapter 2

Tutorial Description

Overview

Throughout this tutorial, we will use the small stopwatch design which is delivered withthe Xilinx ISE software installation as an example design. We intentionally selected asmall design to allow you to complete the labs as quickly as possible.

Less than one hour is required to complete the entire tutorial which covers all majorfeatures.

We suggest:

Running the labs in order. That said, the labs are independent and can be run in anyorder if you want to immediately focus on one particular functional area.

Creating a separate design directory for each lab and copying the original design filesto that directory. Please refer to Chapter 3, Lab Preparation: Getting Started, for moreinformation.

Because the majority of Schematic Viewer features can be accessed using either the RTL,Post-Synthesis netlist, or Critical Path views, we will use the Post-Synthesis netlist view inthe majority of labs to demonstrate the main features.

The following table gives you a brief overview of all the labs.

Table 2-1: Lab Overview

Title Duration Covered Features

Chapter 4, Lab 1: BasicFeatures

9 minutes Selecting Schematic Viewer startup mode

Working with the Schematic Wizard

Understanding the Schematic Viewer interface

Zooming views

Expanding schematics

Removing elements from a schematic

Coloring new elements

Navigating history

Using Start/End signal markers

Chapter 5, Lab 2: Workingwith Hierarchical Netlists

9 minutes Selecting hierarchical blocks in the Schematic Wizard

Expanding hierarchical blocks

Starting schematic exploration with the top-level block

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Chapter 2: Tutorial Description

Prerequisites

The labs you will run through require some basic knowledge about the ISE ProjectNavigator environment. Before starting these labs, you should know:

How to open and close an existing project

How to add a new UCF (implementation constraint file) to the project and specifybasic timing constraints using Constraint Editor

How to run the basic implementation flow

How to launch and use Timing Analyzer

Chapter 6, Lab 3: UsingSchematic Viewer for TimingAnalysis

6 minutes Visualizing critical paths in the Schematic Viewer

Annotating the critical path with path delays

Chapter 7, Lab 4: SimplifyingDesign Analysis

7 minutes Using Start/End signal markers

Deleting schematic elements

Using multiple schematics of the same netlist

Starting a new schematic with selected elements

Using colors to mark various elements

Chapter 8, Lab 5: ComparingTwo Design Implementations

5 minutes Loading and comparing two netlists of the same design

Chapter 9, Lab 6: Dealing withLarge Designs

3 minutes Handling large designs

Chapter 10, Lab 7: Using theSchematic Viewer as a

Standalone Tool

3 minutes Learning how command line users can take advantage of theSchematic Viewer

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Chapter 3

Lab Preparation: Getting Started

Installing a Design

Throughout the labs, you will use the small stopwatch design and target a Spartan-3Exc3s100e-4-vq100 device. This design is delivered with the Xilinx ISE softwareinstallation.

1. In Project Navigator, select File > Open Example.

2. In the Open Example dialog box, select the watchvhd design and specifyc:\viewer_labs\labs1 as the Destination Directory.

The watchvhd project is unarchived in the specified destination directory and isopened for use in Project Navigator.

Setting Up Project Navigator Preferences

To ensure that the lab graphics provided in this tutorial match the schematic you see onyour screen, you have to setup the Light Background Color Scheme for Schematic Viewer

before starting the lab.

1. To open the Preferences dialog box, select Edit > Preferences.

2. In the left pane, expand RTL/Technology Viewers and select the Color Schemesub-category.

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Chapter 3: Lab Preparation: Getting Started

3. Select Light Background Color Scheme in zone 1 (see Figure 3-1) of the dialog box,click Apply, and click OK to finish.

Now you are ready to start the labs.


Figure 3-1: Color Scheme Selection

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Chapter 4

Lab 1: Basic Features

Objectives

The goal of this lab is to familiarize you with the basic Schematic Viewer operations whichwill be used extensively in later exercises. These include:

Selecting Schematic Viewer startup mode

Working with the Schematic Wizard

Understanding the Schematic Viewer interface Zooming views

Expanding schematics

Removing elements from a schematic


Navigating history


Note: For the sake of clarity and simplicity, all the above features will be demonstrated using a

flattened post-synthesis netlist. Hierarchical netlist navigation will be introduced in the next lab.

Lab

Step 1: Creating the Lab Project

Create and open the stopwatch project and set the Light Background Color Scheme forSchematic Viewer, as described in the Chapter 3, Lab Preparation: Getting Started.

Step 2: Setting XST Options and Synthesizing the Design

1. In the Processes pane, right-click Synthesize - XST, and select Process Properties toopen the Synthesis Options dialog box.

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2. Set the Keep Hierarchy option to Noas shown in Figure 4-1.

3. Synthesize the design by double-clicking the Synthesize - XST process in theProcesses pane.

Step 3: Launching the Schematic Wizard

Before you can view a schematic of your design, you need to select the elements you wantto use as a starting point for your design exploration.

You can start design exploration in the two different startup modes:

Start with the Explorer Wizard. In this mode, the Explorer Wizard is the initial screen,which allows you to select the elements that you want to see on the initial schematic.This mode will be used in the current lab.

Start with a schematic of the top-level block. In this mode, the Explorer Wizard isbypassed and an initial schematic is created with only the top-level block displayed.You can then use the logic expansion capabilities of the Schematic Viewer to startexpanding from the top-level block. You need to familiarize yourself with the basicSchematic Viewer operations and learn how you can manipulate hierarchical blocks

before using this mode. Please refer to Chapter 5, Lab 2: Working with HierarchicalNetlists for more information on this startup mode.

1. After synthesis is complete, start the Schematic Viewer by double-clicking the ViewTechnology Schematic process found in the Processes pane, or, alternatively, by

selecting Tools > Schematic Viewer > Technology View from the menu.2. Select the Start with the Explorer Wizard startup mode as shown in Figure 4-2.


Figure 4-1: Setting Keep Hierarchy Option


Figure 4-2: Set Viewer Startup Mode

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Lab

The Schematic Wizard enables you to select elements for exploration start up. SeeFigure 4-3.

The Available Elements window shows all the objects available in the design. They areclassified in the following categories: primitives, signals, top-level ports, and

hierarchical blocks.Note: Hierarchical blocks are visible in hierarchical netlists only. Please refer to Chapter 5, Lab

2: Working with Hierarchical Netlists for more information on working with hierarchical designs.

3. Select MACHINE/sreg_FSM_FFd1 and MACHINE/sreg_FSM_FFd1-In from theprimitives category of Available Elements and add them to the Selected Elements listusing the Add button. See Figure 4-4.

If the list of elements is too long, you can use the Filter to reduce the search scope. Asan example in our case, you can specify MACHINE/sreg_FSM_FFd1* as a searchcriteria as shown in Figure 4-5.

4. Press the Create Schematic button to create the schematic.

FigureX-Ref Target- Figure4-3

Figure 4-3: Schematic Wizard


Figure 4-4: Available Elements


Figure 4-5: Filtering

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Step 4: Using the Schematic Viewer Interface

The Schematic Viewer graphical user interface (GUI) has the following components asshown in Figure 4-6.

1. The schematic window is the main window where you explore your design by addingor removing elements.

2. This toolbar contains the functions specific to the Schematic Viewer.3. This panel contains two types of information: objects visible on the schematic

(instances, pins and signals) and object properties. For example, you can select aBRAM primitive in your schematic and see all its properties, including BRAMinitialization values.

Note: You must select the View by Category tab to see this panel.

4. This toolbar contains functions shared by different graphical tools such as Zoom(shown inFigure 4-7)

Note: Menu control functions are accessible from specific or general toolbars and can be invoked

from the menus. For example, all zoom functions can be called from the View > Zoom menu.

We will mainly deal with the schematic window and toolbars in the labs.




Figure 4-7: Zoom Toolbar

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Lab

Step 5: Zooming

Zooming is a basic function which is constantly used during design analysis. SchematicViewer has five zooming operations which can be accessed from the general toolbar showninFigure 4-7,or via the View > Zoom menu. However, the Schematic Viewer supportsspecific mouse stroke operations, allowing you to perform zoom operations much morequickly.

We suggest that you play with different zoom operations to familiarize yourself with them.They will be very helpful during the rest of the tutorial. Table 4-1 gives an overview ofZoom operations and their access methods:

Table 4-1: Zoom Functions

Step 6: Expanding the Schematic View

Although the initial schematic view is your starting point, you will typically want toexpand the view to include more objects of interest. There are several ways to expand theschematic.

First, you need to select an element to which you would like to add a new (not yet visible)element. You can select the following types of elements to be expanded: net, block, pin of a

block, and port.

To expand the view from the selected object, use the mouse right-click context menu andselect the elements you want to add, such as drivers, loads, driver and loads, or to extract,such as an input or output logic cone.

Zoom Operation Toolbar Menu Command Shortcut

Zoom In View > Zoom > In Do either of the following:

Press F8.

Click and drag down andto the left.

Zoom Out View > Zoom > Out Do either of the following:

Press F7.

Click and drag up and tothe right.

Zoom to Full View > Zoom > To Full View Do either of the following:

Press F6.

Click and drag up and tothe left.

Zoom to Box View > Zoom > To Box Starting from the upper leftcorner, click and drag to

draw a bounding boxaround the area.

Zoom to Selected View > Zoom > To Selected Select the objects you wantto center in the window, andpress F11.

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On the current schematic, select different objects and observe the context menu. Althoughsimilar, the exact content depends on the object type chosen and where it is located in thedesign.

Example

1. Select the I2 pin of the lut3 primitive, and select Show Next Drive (Output) Pin fromthe context menu to see its driver. The following schematic appears, as shown inFigure 4-9.

2. The newly added lut4 element has a different color. The Schematic Viewerautomatically colors newly added objects so they can be easily localized on theschematic. You can enable or disable this feature using the Schematic Viewer toolbar(see Figure 4-10). In addition, you can modify new object colors using the Preferencemenu.

3. If you want to incrementally expand nets, block pins, or ports, you can just point themouse on the desired object and perform a left mouse double-click. This is a veryhandy shortcut over using the context menu.


Figure 4-8: Context Menu


Figure 4-9: Example Schematic


Figure 4-10: Coloring Icon

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Lab

Double-click the I0 pin oflut3 primitive, and the result appears as shown inFigure 4-11.

A newfdc

flip-flop was added to the schematic, but it is connected toI0

pin by a netin the form of a dashed line. The presence of a dashed line means that there are otherobjects connected to this net in your design, but they are not yet visible.

4. Continue to double-click the (dashed-line) net until it becomes a solid line, meaningthat all elements connected to the net are now visible as shown in Figure 4-12.


Figure 4-11: Incremental Expansion


Figure 4-12: Connecting the Net

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Step 7: Using Start/End Signal Markers

Start/End signal markers allow you to easily identify source and destinations of a selectedsignal.

1. To use this feature you have to first enable it using a button in the Schematic Viewertoolbar. This button has two states. The green state indicates the feature is enabled, and

the red state indicates the feature is disabled. Push the button shown in Figure 4-13 toput it into the enabled state.

2. Select any signal on the schematic to see its source and destinations. See Figure 4-15.

Step 8: Navigating the History

The back button (or Ctrl+Z) provides the ability to return to previous schematic steps,and the forward button (or Ctrl+Y) provides the ability to move forward. For example,you can use the back to return to a previous schematic step so you can continue designexploration in a different direction. See Figure 4-16 and Figure 4-17.


Figure 4-13: Start Signal Marker


Figure 4-14: End Signal Marker


Figure 4-15: Sources and Destinations

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Lab

1. Push the back button several times to get the following view, shown in Figure 4-18.

2. Select the lut2 primitive, and select Show All Block Inputs/Outputs from theright-click context menu. See Figure 4-19.


Figure 4-16: Back Button


Figure 4-17: Forward Button


Figure 4-18: Previous View


Figure 4-19: Show All Block Inputs/Outputs

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Step 9: Removing Elements from the Schematic

During schematic expansion you may find that some previously added elements are not ofinterest for your particular design analysis. These elements can be selected and removedfrom the schematic. You can use Delete keyboard key, the delete button from the toolbar asshown in Figure 4-20, or the Edit > Delete menu command.

To select a single element, just use a single click. To select multiple elements, you can selectthe first one and then incrementally add other ones by holding the Ctrl key and clickingthem. Or, you can use in-box selection by holding down the Ctrl key and dragging over theobjects you want to select.

1. Select the lut4 and lut3 primitives on the schematic.

2. Press the Delete keyboard key to remove them.


Figure 4-20: Delete


Figure 4-21: Deleting Items

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Conclusion

Conclusion

In this lab you learned the basic operations available in the Schematic Viewer:

Selecting Schematic Viewer startup mode

Using the Schematic Wizard to select elements to start a schematic investigation

Performing zoom operations based on mouse strokes Expanding schematics in different ways


Navigating history


Removing elements from schematics

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Chapter 5

Lab 2: Working with HierarchicalNetlists

Objectives

The goal of this lab is to familiarize yourself with hierarchical netlists and to learn how youcan manipulate hierarchical blocks during design analysis. This includes:

Expanding external/internal hierarchical blocks Showing and hiding the entire contents of a hierarchical block

In addition, you will learn some special considerations you need to take into account whenworking with hierarchical blocks.

Finally, you will see how to start schematic exploration using the Starting schematicexploration with the top-level block startup mode introduced in Chapter 4, Lab 1: BasicFeatures.

Lab

Step 1: Creating the Lab ProjectCreate the stopwatchproject and set the Light Background Color Scheme for SchematicViewer as described in Chapter 3, Lab Preparation: Getting Started.



2. Set the Keep Hierarchy option to Yesas shown in Figure 5-1.

3. Synthesize the design usingSynthesize - XSTfrom the Processes pane.


Figure 5-1: Keep Hierarchy

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Step 3: Launching the Schematic Wizard

1. After synthesis is complete, start the Schematic Viewer by double-clicking the ViewTechnology Schematic process, and select the Start with the Explorer Wizard startupmode.

2. In the Schematic Wizard, all hierarchical blocks (including the top-level block) are

represented by the hierarchy symbol as shown in Figure 5-2. You can click the plussymbol in front of a hierarchical block to further expand its contents.

3. Select the hierarchical block named MACHINE, and move it to Selected Elementsusing the Add button, and then click Create Schematic. See Figure 5-3.

Step 4: Understanding Hierarchical Block Symbols

The created schematic appears as shown in Figure 5-4.


Figure 5-2: Hierarchy Symbol


Figure 5-3: Selecting Hierarchical Elements


Figure 5-4: Schematic Representation

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Lab

Two items distinguish a hierarchical block from a primitive:

All hierarchical blocks have triangles in four symbol corners as shown in Figure 5-4and Figure 5-5.

In addition to external pins, hierarchical blocks also have internal pins. Internal pinsallow you to explore the content of a hierarchical block while showing it on the samepage.

Expansion operations from the mouse right-click context menu (available for primitivepins and blocks) are available for internal and external pins and for the hierarchical blockitself. In addition, you can use the incremental expansion approach (mouse double-click)on internal and external pins.

Step 5: Expanding Hierarchical Blocks

1. Double-click the internal and external strstop pin of the MACHINE block to get the

following schematic (Figure 5-6).

2. Right-click the clken external pin of the MACHINEblock, and select the Show NextLoad (Input) Pin option.

The CNT60enable1 block appears as shown in Figure 5-7.


Figure 5-5: Triangle Symbol


Figure 5-6: Machine Block


Figure 5-7: Expanding Blocks

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Step 6: Showing and Hiding Block Contents

You can view the entire contents of the hierarchical block by using the View HierarchicalBlock icon (Figure 5-8) from the schematic toolbar or by using the right-click context menu.To hide its contents, use the Hide Hierarchical Block icon (Figure 5-9).

1. Select the MACHINE block, and press the View Hierarchical Block icon to see its entirecontents as shown in Figure 5-10.

2. Select the MACHINE block, and press the Hide Hierarchical Block icon to hide its

entire contents as shown in Figure 5-11.


Figure 5-8: View Hierarchical Block Icon


Figure 5-9: Hide Hierarchical Block Icon


Figure 5-10: View Block Contents


Figure 5-11: Hide Block Contents

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Lab

Step 7: Using Bottom-Up Design Expansion

In the previous steps, you were mainly dealing with top-down schematic expansion. Nowwe will use the Schematic Viewer in a bottom-up mode.

1. Select the following two tabs (Figure 5-12), and close them using the close windowbutton (Figure 5-13).

2. Restart the Schematic Viewer by selecting the View Technology Schematic processand selecting the Start with the Explorer Wizard startup mode.

3. Select the sreg_FSM_FFd3-In_F from within the MACHINE hierarchical block, add it

to the Selected Elements, and then click Create Schematic. See Figure 5-14.

4. Select the sreg_FSM_FFd3-In_F, and select Show All Block Inputs from the right-click

context menu.5. Comparing the start-up schematic (Figure 5-15) with the one we obtained at Step 6:

Showing and Hiding Block Contents (Figure 5-16), you see that thesreg_FSM_FFd3-In_F primitive is not placed inside the MACHINE hierarchy block.In addition, MACHINE I/Os are represented as primary design pins.


Figure 5-12: Tabs to Close


Figure 5-13: Close Window Button


Figure 5-14: Restarting Schematic Viewer


Figure 5-15: Start-Up Schematic

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6. Further incremental design exploration shows that schematic expansion stops atMACHINE hierarchy boundaries as shown in Figure 5-17.

To cross hierarchy in a bottom-up direction, use the Pop to the Calling Schematic icon(Figure 5-18):

7. Press the Pop to the Calling Schematic icon to cross hierarchy in a bottom-up directionas shown in Figure 5-19.

You can now continue further schematic exploration inside as well as outside theMACHINE block. Use the Pop to the Calling Schematic icon each time you need to go tothe upper hierarchy level.


Figure 5-16: Step Schematic


Figure 5-17: Hierarchical Boundaries


Figure 5-18: Pop to the Calling Schematic


Figure 5-19: Upper Hierarchical Level

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Lab

Step 8: Starting Schematic Exploration with the Top-Level Block

In Chapter 4, Lab 1: Basic Features, we introduced two modes to start schematicexploration:

Start with the Explorer Wizard

Start with a schematic of the top-level block

Until now, we exclusively used the first mode. Now we will learn how to use the secondmode.

1. Close all currently opened schematic tabs using the close window button.

2. Restart the Schematic Viewer by selecting the View Technology Schematic process.

3. Select the Start with a schematic of the top-level block startup mode, and press theOK button as shown in Figure 5-20:

The following startup schematic appears, as shown in Figure 5-21.

4. You can start design exploration by using all previously described schematicexpansion methods.


Figure 5-20: Startup Modes


Figure 5-21: Top-Level Block

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Conclusion

In this lab, you learned how to use the Schematic Viewer on a design with hierarchicalblocks. This included learning how the blocks are represented in the Schematic Wizard andhow they can be expanded for design analysis.

In addition, you learned how to start schematic exploration using the Starting schematic

exploration with the top-level block startup mode introduced in Chapter 4, Lab 1: BasicFeatures.

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Chapter 6

Lab 3: Using Schematic Viewer forTiming Analysis

Objectives

Critical timing paths from the post-place and route timing report can be easily visualizedin the Schematic Viewer by cross probing from the Timing Report to the Schematic Viewer.The visualized critical path can be used as a starting point for further design exploration.

Moreover, it is easy to annotate the critical path with timing delays.

The goal of this lab is to demonstrate how to cross probe from the timing report to theSchematic Viewer and how to annotate the visualized timing path with reported delays.

Lab


Create the stopwatch project and set the Light Background Color Scheme for SchematicViewer as described in the Chapter 3, Lab Preparation: Getting Started.

Step 2: Specifying Timing Constraints

To use the cross probing mechanism, add a new UCF file called stopwatch.ucf to theproject. Then, using Constraints Editor, specify a period constraint of 3.5 ns for the CLKsignal as shown in Figure 6-1.

Step 3: Specifying XST Options and Implementing the Design1. In the Processes pane, right-click Synthesize - XST, and select Process Properties to

open the Synthesis Options dialog box.


Figure 6-1: Clock Signal Definition

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3. Implement the design by double-clicking the Place & Route process in the Processespane, as shown in Figure 6-3.

4. Open Timing Analyzer for the post-place and route design.

Step 4: Viewing the Critical Path in the Schematic ViewerIn the timing Report Navigation section, select the critical path to access the detailed datapath information. The detailed path view allows you to cross probe (from the mouseright-click context menu) to different views, for example, FPGA Editor or a Datasheetview.

In this lab, we will focus on the links dedicated to Schematic Viewer only (Figure 6-4):

Selecting (1) Maximum Data Path allows you to visualize the entire data path.

Selecting (2) a net from thePhysical Resource column visualizes just a portion of adata path connected by a selected net.




Figure 6-3: Analyze Post-Place & Route Static Timing


Figure 6-4: Report Navigation

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Lab

1. Right-click Maximum Data Path, and select Show in Technology Viewer. This drawsthe selected data path in the Schematic Viewer as shown in Figure 6-5.

2. Observe the following: The start point of the critical path is marked with a start icon (Figure 6-6).

Slices are represented as hierarchical blocks. This means that you can explore theirinternal contents using internal pins as well as their external connections.

You can use all available features (described in earlier labs) to further explore theschematic.

Step 5: Annotating the Schematic with Timing DelaysDelays from detailed path report (Figure 6-7) can be directly visualized on a schematic.

1. Select the schematic sheet with the visualized data path.

2. Press the Annotation icon (Figure 6-8) from the Schematic Viewer toolbar.




Figure 6-6: Start Icon


Figure 6-7: Path Report


Figure 6-8: Annotation Icon

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3. In the following dialog box, check the Delay Values option. Check thePin Namesoptionas shown in Figure 6-9.

A schematic view of the data path annotated with timing delays appears, as shown inFigure 6-10.

Conclusion

In this lab, you learned how the Schematic Viewer can be used to help visualize keyinformation during timing analysis. You were able to select critical timing paths from thetiming report, and graphically visualize them in the Schematic Viewer. Finally, youannotated the critical path in the Schematic Viewer with timing delays from the timingreport.


Figure 6-9: Select Block Pin Annotation


Figure 6-10: Data Path Annotated with Timing Delays

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Chapter 7

Lab 4: Simplifying Design Analysis

Objectives

Very often, during design exploration, you must deal with a significant number ofelements incrementally added to the schematic sheet. The sheer number of elements on theschematic can complicate the design analysis process.

The goal of this lab is to show you several methods to reduce design complexity and makethe analysis process more efficient. These methods include capabilities to:

Use Start/End Signal markers to quickly identify source and destinations of selectedsignals

Remove elements that are not of interest from the schematic sheet

Work with multiple schematics of the same netlist

Start a new schematic by selecting a subset of elements from the current design view

Use colors to highlight a specific design instance or a group of similar elements

The first two methods were already described in Chapter 4, Lab 1: Basic Features;therefore, the main focus is the last three features.

Lab


Create the stopwatch project and set the Light Background Color Scheme for SchematicViewer as described in Chapter 3, Lab Preparation: Getting Started.



2. Set the Keep Hierarchy option to Noas shown in Figure 7-1.X-RefTarget - Figure 7-1

Figure 7-1: Keep Hierarchy Option

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3. Synthesize the design using the Synthesize - XST process.

Step 3: Working with Multiple Schematics of the Same Netlist

To demonstrate this feature, we will select a flip-flop and analyze its input and output logiccones. To simplify schematic complexity, you will place the input logic cone on one sheet

and the output logic cone on another sheet.1. After synthesis is complete, start the Schematic Viewer by launching the View

Technology Schematic process, and select the Start with the Explorer Wizard startupmode.

2. Select the MACHINE/sreg_FSM-FFd1 flip-flop for schematic startup, and then clickCreate Schematic.

3. Select the visualized flip-flop, and select Add Input Cone from the right-click menu.

The input appears as shown in Figure 7-2.

4. Click the Stopwatch.ngc tab to return to the Schematic Wizard. Select CreateSchematic to open a new schematic tab. Select the visualized flip-flop, and select Add

Output Cone from the right-click context menu.


Figure 7-2: Adding Input

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Lab

The output appears as shown in Figure 7-3.

Observe that you were able to reduce complexity of the design view by dividing it into twopieces. The capability to visualize multiple schematics can be used for many differentpurposes. One of them is discussed in Chapter 8, Lab 5: Comparing Two DesignImplementations, where you will see how to use this feature and to compare two differentnetlists of the same design.

Step 4: Starting a New Schematic by Selecting Elements from the Current

ViewSuppose during design debugging you are able to localize the source of a problem andwould like to focus just on that limited portion of the design. However, the drawnschematic might have many other elements that are not of direct interest and clutter theview.

Of course, as described earlier, you can try to select those objects you are not interested inand remove them. Another way to accomplish this is to return to the Schematic Wizard andstart a new schematic by selecting required elements. Depending on your particulardesign, these methods can be tedious and time-consuming.

Often, the best way to handle this is to directly select the required elements from thecurrent view and start a new schematic by pushing the Start Schematic icon (Figure 7-4)from the schematic toolbar.

Note: In this case, the Schematic Viewer does not create a new schematic sheet. It places the new

schematic on the same sheet.


Figure 7-3: Adding Output


Figure 7-4: Start Schematic Icon

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1. Select the Stopwatch (Tech1) tab on the schematic.

2. On this sheet, select elements surrounded by the rectangle as shown in Figure 7-5.

3. Press the Start Schematic icon to start new schematic. The new schematic appears asshown in Figure 7-6. You can continue to further expand as described in earlier labsegments.


Figure 7-5: Stopwatch (Tech1) Schematic


Figure 7-6: New Schematic

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Lab

Step 5: Using Colors to Highlight a Group of Specific Elements

Select the Stopwatch (Tech2) tab on the schematic. The schematic appears as shown inFigure 7-7.

You can see many elements in this view. We will highlight all fd* type flip-flops using adifferent color as a means to simplify analysis.

1. Open the Preference dialog box by selecting Edit > Preferences.

2. Under the RTL/Technology Viewers category, select the User Color Rulessub-category as shown in Figure 7-8. This is where we can define specific color rules

for our needs.

3. Click the New button to open the Color Rules dialog box.


Figure 7-7: Stopwatch (Tech2)


Figure 7-8: Preferences Dialog Box

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4. Specify fd_ff_colors as a name for the color rule. Then click theNew button to add a newrule.

5. Select Block Type for Property Name, then select Matches (Wildcard) as Operator,and finally type fd* as a value as shown in Figure 7-9, and press OK.

6. In the Light Background column, select Gray as the color (see Figure 7-10) for createdfd_ff_colors,and then pressOK.


Figure 7-9: Color Rules Dialog Box


Figure 7-10: Selecting Light Background Gray

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Conclusion

Now all flip-flops are colored differently (gray), which allows to you to easilyrecognize them on the schematic sheet as shown in Figure 7-11.

When you expand the schematic by adding new elements with particular colors defined inthe Color Rules (as we did for fd* flip-flops), specific colors may be not be visible, becausethey are overwritten by New Object Colors. To see specific colors, disable New ObjectsColoring using the Color icon.

Conclusion

In this lab you worked with several methods that allowed you to simplify the designanalysis process:

Creating multiple schematics of the same netlist

Starting a new schematic by selecting some elements from the current design view

Using Color Rules to color all fdtype flip-flops in a particular color to easily recognizethem on the schematic sheet


Figure 7-11: Colored Items


Figure 7-12: Color Icon

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Chapter 8

Lab 5: Comparing Two DesignImplementations

Objectives

To meet design requirements (such as speed, area, and power requirements), you mayneed to modify the original HDL sources or change synthesis and implementation options.Performing such changes sometimes requires you to understand the impact of these

changes in the final implementation.

The Schematic Viewer can help you in these situations, because it allows you to visualizeand compare different design netlists. Please note that this can be done for the XST RTLview and post-synthesis netlists. Post-map and post-place and route netlists are nothandled in this mode.

The goal of this lab is to show you how to create two design implementations with XST andvisualize them in the Schematic Viewer.

Lab

Step 1: Creating a Lab ProjectCreate the stopwatch project and set the Light Background Color Scheme for SchematicViewer as described in Chapter 3, Lab Preparation: Getting Started.





4. Open a shell prompt, go to the project directory, and copy stopwatch.ngc file todefault_run.ngc.


Figure 8-1: Selecting Keep Hierarchy

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5. Open the Xilinx Specific Options dialog box, set the Register Balancing option to Yes(see Figure 8-2), and then re-run XST.

6. During the Synthesis process, with Register Balancing enabled, XST reports thatseveral FFs were moved forward:

Register(s) sreg_FSM_FFd3 sreg_FSM_FFd1 sreg_FSM_FFd2 has(ve) been

forward balanced into : sreg_FSM_Out11_FRB.

Take a look at how this is reflected in the Schematic View.

Step 3: Loading and Comparing Two Netlists

1. Open the Technology Viewer by using the View Technology Schematic process for thelatest generated netlist in the Start with the Explorer Wizard mode. Select thehierarchical block icon (see Figure 8-3) and create the schematic.

2. Open the previously storeddefault_run.ngc netlist by selecting File > Open File.Select the Start with the Explorer Wizard mode. Project Navigator loads the netlistand starts the Schematic Viewer Wizard. Using the wizard, select the MACHINEhierarchical block icon (Figure 8-3) and create the schematic.

3. Simultaneously view the two schematics sheets horizontally using the Dual View icon

(Figure 8-4) from the general toolbar. To expand the view, double-click the inside pinsof the RST and CLKEN pins. The display appears as shown in Figure 8-5.


Figure 8-2: Select Register Balancing


Figure 8-3: Hierarchical Block Icon


Figure 8-4: Dual View Icon

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Conclusion

4.

4. The bottom netlist was generated using the Register Balancing mechanism. Note howXST moved forward several FFs (creatingsreg_FSM_Out11_FRB) towards the outputofclkenpin to improve design performance.

Conclusion

In this lab you visualized and compared two netlists for the same design, where each wasgenerated using different XST options.


Figure 8-5: Dual View of Schematic

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Chapter 9

Lab 6: Dealing with Large Designs

Objectives

The latest FPGA families from Xilinx allow you to implement ever larger and morecomplex designs, which can significantly complicate the analysis process. For the largest ofdesigns, having hundreds of thousands of design elements is entirely possible. Visualizingthe entire design on a single page is not practical.

This lab provides several tips on how you can deal with complex designs while keepinggood visibility and preserving good responsiveness using the Schematic Viewer.

Tip 1: Using Hierarchical Netlists

The presence of hierarchy in the post-synthesis netlist significantly reduces its complexityfor design analysis process as well as for the Schematic Viewer. Please note that the XSTRTL netlist is fully hierarchical.

Preserving Hierarchy

XST enables you to either fully or partially preserve design hierarchy. However,hierarchical preservation prevents logic optimization across hierarchical boundaries of

preserved blocks. As a consequence, this may negatively impact design performance.

Therefore, when using hierarchical preservation during synthesis, you have to ensure thatyou still meet design goals.

Rebuilding Hierarchy

Another way to generate a hierarchical netlist without a design performance impact is touse the Netlist Hierarchy option. If the value of this option is set to Rebuilt (as shown inFigure 9-1), XST automatically reconstructs the hierarchy of the final netlist even if it wasfully flattened during optimization.

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Chapter 9: Lab 6: Dealing with Large Designs

This feature is not set by default, because it may increase XST synthesis runtime and couldaffect the accuracy of area estimation reports.

We suggest you run tests of this option on your current design to ensure that synthesisruntime is acceptable.

Tip 2: Using Multiple Schematic SheetsEven if the hierarchy of your design is fully reconstructed, a single hierarchy level may stillcontain thousands of elements, complicating visualization and analysis.

If you need to deal with a significant number of elements, we suggest you take advantageof the capability to visualize the same netlist on multiple schematic sheets as shown inFigure 9-2. As you have seen in earlier labs, this process can be fully controlled andadapted for your specific needs.

Please refer to Chapter 7, Lab 4: Simplifying Design Analysis for more information.

Conclusion

In this lab you have seen an overview of methods you can use to handle large designs. Thefirst method consists of ways to generate hierarchical netlists. The second method suggestsusing multiple schematic sheets to reduce the number of elements you need to visualize atany one time.


Figure 9-1: Rebuilt Option


Figure 9-2: Multiple Schematic Sheets

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Chapter 10: Lab 7: Using the Schematic Viewer as a Standalone Tool


4. After synthesis is complete, close the project by selecting File > Close Project. Notethat Project Navigator remains open.

Step 3: Opening the Post-Synthesis Netlist in Schematic Viewer

1. The post-synthesis XSTstopwatch.ngc netlist is located in the project directory (the.ngc file can be generated from command line mode). To open this netlist inSchematic Viewer, select File > Open File.

2. Select the Start with the Explorer Wizard startup mode. Project Navigator loads thenetlist and starts the Schematic Viewer Wizard as shown in Figure 10-2. Now you can

move on and explore your design.

ConclusionThis lab demonstrated how the Schematic Viewer can be used by command line users in astandalone mode. You can open any post-synthesis XST netlist in the Schematic Viewerwithout first opening a project.




Figure 10-2: Schematic Viewer Wizard

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Appendix A

Additional Resources

Xilinx Resources

ISE Design Suite: Installation and Licensing Guide (UG798):http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_1/iil.pdf

ISE Design Suite 13: Release Notes Guide (UG631):http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_1/irn.pdf

Xilinx Documentation:http://www.xilinx.com/support/documentation

XilinxGlobal Glossary:http://www.xilinx.com/support/documentation/sw_manuals/glossary.pdf

Xilinx Support: http://www.xilinx.com/support
http://www.xilinx.com/http://www.xilinx.com/cgi-bin/SW_Docs_Redirect/sw_docs_redirect?ver=13.1&locale=en&topic=installhttp://www.xilinx.com/cgi-bin/SW_Docs_Redirect/sw_docs_redirect?ver=13.1&locale=en&topic=release+noteshttp://www.xilinx.com/support/documentationhttp://www.xilinx.com/support/documentation/sw_manuals/glossary.pdfhttp://www.xilinx.com/supporthttp://www.xilinx.com/supporthttp://www.xilinx.com/support/documentation/sw_manuals/glossary.pdfhttp://www.xilinx.com/support/documentationhttp://www.xilinx.com/cgi-bin/SW_Docs_Redirect/sw_docs_redirect?ver=13.1&locale=en&topic=release+noteshttp://www.xilinx.com/http://www.xilinx.com/cgi-bin/SW_Docs_Redirect/sw_docs_redirect?ver=13.1&locale=en&topic=install

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