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FPGA/DesignCompiler

TutorialWatch Design

UG100 (v1.0) July 21, 2000

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FPGA/Design Compiler Tutorial www.xilinx.com UG100 (v1.0) July 21, 20001-800-255-7778

The Xilinx logo shown above is a registered trademark of Xilinx, Inc.

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order to improve reliability, function or design and to supply the best product possible. Xilinx, Inc. will not assume responsibility for the use of any

circuitry described herein other than circuitry entirely embodied in its products. Xilinx, Inc. devices and products are protected under one or more

of the following U.S. Patents: 4,642,487; 4,695,740; 4,706,216; 4,713,557; 4,746,822; 4,750,155; 4,758,985; 4,820,937; 4,821,233; 4,835,418;

4,855,619; 4,855,669; 4,902,910; 4,940,909; 4,967,107; 5,012,135; 5,023,606; 5,028,821; 5,047,710; 5,068,603; 5,140,193; 5,148,390;

5,155,432; 5,166,858; 5,224,056; 5,243,238; 5,245,277; 5,267,187; 5,291,079; 5,295,090; 5,302,866; 5,319,252; 5,319,254; 5,321,704;

5,329,174; 5,329,181; 5,331,220; 5,331,226; 5,332,929; 5,337,255; 5,343,406; 5,349,248; 5,349,249; 5,349,250; 5,349,691; 5,357,153;

5,360,747; 5,361,229; 5,362,999; 5,365,125; 5,367,207; 5,386,154; 5,394,104; 5,399,924; 5,399,925; 5,410,189; 5,410,194; 5,414,377;

5,422,833; 5,426,378; 5,426,379; 5,430,687; 5,432,719; 5,448,181; 5,448,493; 5,450,021; 5,450,022; 5,453,706; 5,455,525; 5,466,117;

5,469,003; 5,475,253; 5,477,414; 5,481,206; 5,483,478; 5,486,707; 5,486,776; 5,488,316; 5,489,858; 5,489,866; 5,491,353; 5,495,196;

5,498,979; 5,498,989; 5,499,192; 5,500,608; 5,500,609; 5,502,000; 5,502,440; 5,504,439; 5,506,518; 5,506,523; 5,506,878; 5,513,124;

5,517,135; 5,521,835; 5,521,837; 5,523,963; 5,523,971; 5,524,097; 5,526,322; 5,528,169; 5,528,176; 5,530,378; 5,530,384; 5,546,018;

5,550,839; 5,550,843; 5,552,722; 5,553,001; 5,559,751; 5,561,367; 5,561,629; 5,561,631; 5,563,527; 5,563,528; 5,563,529; 5,563,827;

5,565,792; 5,566,123; 5,570,051; 5,574,634; 5,574,655; 5,578,946; 5,581,198; 5,581,199; 5,581,738; 5,583,450; 5,583,452; 5,592,105;

5,594,367; 5,598,424; 5,600,263; 5,600,264; 5,600,271; 5,600,597; 5,608,342; 5,610,536; 5,610,790; 5,610,829; 5,612,633; 5,617,021;5,617,041; 5,617,327; 5,617,573; 5,623,387; 5,627,480; 5,629,637; 5,629,886; 5,631,577; 5,631,583; 5,635,851; 5,636,368; 5,640,106;

5,642,058; 5,646,545; 5,646,547; 5,646,564; 5,646,903; 5,648,732; 5,648,913; 5,650,672; 5,650,946; 5,652,904; 5,654,631; 5,656,950;

5,657,290; 5,659,484; 5,661,660; 5,661,685; 5,670,896; 5,670,897; 5,672,966; 5,673,198; 5,675,262; 5,675,270; 5,675,589; 5,677,638;

5,682,107; 5,689,133; 5,689,516; 5,691,907; 5,691,912; 5,694,047; 5,694,056; 5,724,276; 5,694,399; 5,696,454; 5,701,091; 5,701,441;

5,703,759; 5,705,932; 5,705,938; 5,708,597; 5,712,579; 5,715,197; 5,717,340; 5,719,506; 5,719,507; 5,724,276; 5,726,484; 5,726,584;

5,734,866; 5,734,868; 5,737,234; 5,737,235; 5,737,631; 5,742,178; 5,742,531; 5,744,974; 5,744,979; 5,744,995; 5,748,942; 5,748,979;

5,752,006; 5,752,035; 5,754,459; 5,758,192; 5,760,603; 5,760,604; 5,760,607; 5,761,483; 5,764,076; 5,764,534; 5,764,564; 5,768,179;

5,770,951; 5,773,993; 5,778,439; 5,781,756; 5,784,313; 5,784,577; 5,786,240; 5,787,007; 5,789,938; 5,790,479; 5,790,882; 5,795,068;

5,796,269; 5,798,656; 5,801,546; 5,801,547; 5,801,548; 5,811,985; 5,815,004; 5,815,016; 5,815,404; 5,815,405; 5,818,255; 5,818,730;

5,821,772; 5,821,774; 5,825,202; 5,825,662; 5,825,787; 5,828,230; 5,828,231; 5,828,236; 5,828,608; 5,831,448; 5,831,460; 5,831,845;

5,831,907; 5,835,402; 5,838,167; 5,838,901; 5,838,954; 5,841,296; 5,841,867; 5,844,422; 5,844,424; 5,844,829; 5,844,844; 5,847,577;

5,847,579; 5,847,580; 5,847,993; 5,852,323; 5,861,761; 5,862,082; 5,867,396; 5,870,309; 5,870,327; 5,870,586; 5,874,834; 5,875,111;

5,877,632; 5,877,979; 5,880,492; 5,880,598; 5,880,620; 5,883,525; 5,886,538; 5,889,411; 5,889,413; 5,889,701; 5,892,681; 5,892,961;

5,894,420; 5,896,047; 5,896,329; 5,898,319; 5,898,320; 5,898,602; 5,898,618; 5,898,893; 5,907,245; 5,907,248; 5,909,125; 5,909,453;

5,910,732; 5,912,937; 5,914,514; 5,914,616; 5,920,201; 5,920,202; 5,920,223; 5,923,185; 5,923,602; 5,923,614; 5,928,338; 5,931,962;5,933,023; 5,933,025; 5,933,369; 5,936,415; 5,936,424; 5,939,930; 5,942,913; 5,944,813; 5,945,837; 5,946,478; 5,949,690; 5,949,712;

5,949,983; 5,949,987; 5,952,839; 5,952,846; 5,955,888; 5,956,748; 5,958,026; 5,959,821; 5,959,881; 5,959,885; 5,961,576; 5,962,881;

5,963,048; 5,963,050; 5,969,539; 5,969,543; 5,970,142; 5,970,372; 5,971,595; 5,973,506; 5,978,260; 5,986,958; 5,990,704; 5,991,523;

5,991,788; 5,991,880; 5,991,908; 5,995,419; 5,995,744; 5,995,988; 5,999,014; 5,999,025; 6,002,282; and 6,002,991; Re. 34,363, Re. 34,444,

and Re. 34,808. Other U.S. and foreign patents pending. Xilinx, Inc. does not represent that devices shown or products described herein are free

from patent infringement or from any other third party right. Xilinx, Inc. assumes no obligation to correct any errors contained herein or to advise

any user of this text of any correction if such be made. Xilinx, Inc. will not assume any liability for the accuracy or correctness of any engineering

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Copyright 1991-2000 Xilinx, Inc. All Rights Reserved.

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UG100 (v1.0) July 21, 2000 www.xilinx.com FPGA/Design Compiler Tutorial1-800-255-7778

FPGA/Design Compiler TutorialUG100 (v1.0) July 21, 2000

The followin g table shows th e revision history for this d ocument.

Date Version Revision

07/ 21/ 00 1.0 Init ial Xilinx release.



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FPGA/Design Compiler Tutorial www.xilinx.com UG100 (v1.0) July 21, 20001-800-255-7778



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UG100 (v1.0) July 21, 2000 www.xilinx.com iFPGA/Design Compiler Tutorial 1-800-255-7778

FPGA/Design Compiler Tutorial

Getting Started .................................................................................................................... 1

Nom enclature ................................................................................................................... 1

Requ ired Softw are............................................................................................................ 1

Setting up the Environment............................................................................................ 1

Ins talling th e Tutor ial ...................................................................................................... 2

Tutorial Project D irectories and File s ....................................................................... 2

VHD L or Ver ilog? ............................................................................................................ 2

Des ign Descrip tion ........................................................................................................... 2

Verilo g Des ign Files ......................................................................................................... 3

Creating a CORE Generator Module ........................................................................ 3

Synthesizing the Desig n w ith FPGA/D esign Compiler................................... 7

Setting up FPGA/ Design Com piler ’s Enviro nm ent ................................................... 7Startin g Design An alyzer ................................................................................................ 8

FPGA/ Design Compiler Shell Scripting..................................................................... 14

Contents




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UG100 (v1.0) July 21, 2000 www.xilinx.com 1FPGA/Design Compiler Tutorial 1-800-255-7778

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FPGA/Design Compiler Tutorial

This chapter gu ides you throu gh a typical HDL-based design p rocedure using a d esign of

a runner ’s stopwa tch called Watch. The design examp le used in this tutorial demon strates

man y device features, software features and d esign flow pr actices which you can ap ply to

you r own design. This design targets an Virtex device; how ever, all of the p rinciples and

flows tau ght are a pp licable to any Xilinx device fam ily, unless otherw ise noted.

The design is comp osed of H DL elemen ts and a CORE Generator m acro. You will

synth esize the d esign u sing FPGA/ Design Comp iler v1999.05.

• This chap ter contains th e following sections:

• “Getting Started”

• “Tut orial Project Directories Files”

• “Creating a CORE Generator Mo du le”

• “Synth esizing th e Design with FPGA/ Design Com piler”

Getting StartedThe followin g subsections describe the basic requirem ents for runn ing the tut orial.

NomenclatureIn this tutorial, the followin g terms are u sed:

• “Virtex family” includes th e Virtex, Spa rtan -II and Virtex-E devices only.

• Through out th is tutorial, file nam es, pro ject names, and d irectory nam es (paths) are

specified in lower case, and the d esign is referred t o as Watch.

Required Software

The Xilinx Alliance Series vers ion 3.1i and Synop sys FPGA/ Design Com piler v 1999.05 is

required t o perform this tutorial. The d esign requires that you hav e installed th e Virtex XSI

(Xilinx Synopsys Interface) libraries foun d on the CAE CD-ROM th at came w ith the

Alliance softw are. You m ust also ha ve the Watch p rojects which may be d own loaded from

http://support.xilinx.com.

Setting up the Environment

Set the $XILINX variable to reflect the path o f the softwa re installation .

setenv XILINX <path_to_Alliance_31i_installation>

Set the $SYN OPSYS variable to reflect the pa th of the softw are insta llation.

setenv SYNO PSYS <path_to_Synopsys_v1999.05_installation>

Set the Synop sys license file variable SYN OPSYS_KEY_FILE to th e location of th e license.


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FPGA/Design Compiler TutorialR

setenv SYNOPSYS_KEY_FILE <path_to_license_file>

Note: If you are un sure of the locations of the installed softwa re, please see your system

administrator.

Installing the Tutorial

This tuto rial assumes that th e software is installed in the location associated w ith the

$XILINX variable. If you h ave installed the softwa re in a different location, substitute your

var iable w ith $XILIN X.

• Make a directory called tutorial in your $XILINX directory.

mkdir $XILINX/tutorial

• Move th e file from the cu rrent location t o $XILINX/ tu torial.

mv watch.tar.gz $XILINX/tutorial

• Extract th e d esign files.

gzip -cd watch.tar.gz | tar -xvf -

Tutorial Project Directories and FilesThe WTUT_VHD an d WTUT_VER directories are created within

$XILINX/ tutorial/ wa tch_source. These d irectories contain th e incomp lete versions of thedesign d one in VHDL and Verilog resp ectively. The WATCHVH D and WATCHVER

directories are created w ithin $XILINX/ tutor ial/ w atch_solution. These d irectories contain

the com plete versions of th e d esign d one in VHDL and Verilog resp ectively. You will create

the rem aining files wh en you perform the tu torial. The follow ing table lists the associated

project.

VHDL or Verilog?

This tuto rial has been prep ared for both VHDL and Verilog designs. This docum ent

app lies to both designs simu ltaneously, noting d ifferences wh ere app licable. You w ill need

to decide which HDL langu age you w ould like to work through the tutorial when you

open th e project.

Design Description

The design used in this tutorial is a hierarchical, HDL-based d esign, mean ing that th e top-level design file is an H DL file that references several other lower-level m acros. The lower-

level macros are either HDL mod ules or CORE Generator m odu les.

The d esign begins as an unfinished design. Throughou t the tu torial, you comp lete the

design by generating some of the mod ules from scratch an d by completing some others

from existing files.

Watch is a simp le runn er ’s stopw atch. There are three external inp uts, and three external

outp ut bu ses in the comp leted design. The system clock is an externa lly generated signal.

The following list sum marizes the input lines and outpu t buses.

Table 1: Tutorial Project Directories

Directory Description

watch_source/ wtut_vhd Incomplete Watch Tutorial - VHDL

watch_source/ wtut_ver Incomplete Watch Tutorial - Verilog

watch_solution/ watchvhd Solution for Watch - VHDL

watch_solution/ watchver Solution for Watch - Verilog



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Inputs:

• STRTSTOP Starts and stops the stop wa tch. This is an active low signal w hich acts

like the start/ stop button on a runn er ’s stopwatch.

• RESETResets the stopw atch to 00.0 after it has been stop ped .

• CLKExternally generat ed system clock

Outputs:

• TENSOUT[6:0]7-bit bus w hich represen ts the Ten’s d igit of the stopw atch value.

This bus is in 7-segment d isplay format view able on a 7-segment LED d isplay.

• ONESOUT[6:0]Similar to TENSOUT bus above, bu t represents th e One ’s digit of

the stopwatch value.

• TENTHSOUT[9:0]10-bit bus w hich represents t he Tenths ’ digit of the stopw atch

value. This bus is one-hot encod ed.

The completed d esign consists of the following fun ctional blocks.

• STATMACH

State Machine mod ule.

• CNT60

HDL-based m odu le which coun ts from 0 to 59, decimal. This macro ha s two 4-bit

outp uts, wh ich represent the ones an d ten s digits of the d ecima l values, respectively.

• TENTHS

A CORE Generator 4-bit, binary encoded counter. This macro ou tpu ts a 4-bit code

wh ich is decoded to represent th e tenths d igit of the w atch value as a 10-bit one-hot

encoded value.

• HEX2LED

HDL-based ma cro. This macro decodes the ones an d ten s digit values from

hexad ecima l to 7-segmen t display format.

• SMALLCNTR

A simple Coun ter.

• DECODE

Decod es the CORE Generator ou tpu t from a 4-bit binary to a 10-bit one hot ou tpu t.

VHDL/Verilog Design Files

Below is a list of the VHDL/ Verilog d esign files with “stopwatch” being the top level file.

• stopwatch

• cnt60

• decode

• hex2led

• smallcntr

• statmach

Creating a CORE Generator ModuleCORE Generator is a grap hical interactive d esign tool you u se to create high-level mod ules

such as coun ters, shift registers, RAM an d m ultiplexers. You can customize an d p re-

optim ize the mod ules to take ad vanta ge of the inherent architectural features of the Xilinx

FPGA architectures, such as Fast Carry Logic for ar ithmetic functions, and on-chip RAM

for d ual-port and synchronous RAM.

In this section, you create a CORE Generator mod ule called Tenths. Tenths is a 4-bit binar y

encoded counter. The 4-bit nu mber is decoded to count the tenth s digit of the stop watch ’s

time value.



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Creating the CORE Generator Module

You select the type of modu le you wa nt in the CORE Generator d ialog box as well as the

specific features of the m odu le. You can in voke this GUI from an xterm comman d -line

prompt.

1. In an xterm window type in coregen.

2. Select the Create a New Project → OK.

3. In the resulting window select the following:

a. Browse to $XILINX/tutorial/watch_source/wtut_vhd (or wtut_ver) for

the location of the CORE Generator project.

b. Select the Virtex family as the target a rchitecture.

c. Select VHDL (or Verilog) and Synopsys for the design ent ry.

d. Select the OK button.

4. The Xilinx CORE Generator 3.1i opens and displays a list of possible COREs available.

Double Click on Basic Elements → Counters.

5. Double Click on Binary Counter to open th e Binary Coun ter dialog. This dialogallows the user to custom ize the counter to the d esign specifications.

6. Fill in the Binary Coun ter dialog with the following settings.

a. Component Name: Tenths

Defines the nam e of the mod ule.

b. Output Width: 4

Defines the width of the outpu t bus.

Figure 1: New Project Window



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c. Operation: Up

Defines how t he count er will operat e. This field is depen dan t on the typ e of

mod ule you select.

d . Count Restrictions: Restrict Coun t to A.

This dictates the maximum cou nt value.

e. Output Options: Thresh old0 set to A

Signal goes high wh en the value sp ecified h as been reached.

f. Output Options: Registered

Click on th e Register Options bu tton to op en the Register Options d ialog. Enter th e

following settings.- Clock Enable: Selected

- Asynchronous Settings: Init w ith a v alue of 1.

- Synchronous Settings: Non e

- Click OK.

7. Check that only the following pins are u sed.

a . AINIT

b. CE

c. Qd. Q_Thresh0

e. CLK



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8. Click Generate.

A nu mber of files are add ed to th e pr oject directory. These files follow :

a. TENTHS.EDNThis file is the netlist that is used du ring the Translate p hase of implemen tation.

b. TENTHS.VHO or TENTHS.VEO

This is the instantiation temp late that is used to incorp orate the CORE Generator

mod ule in you r source HDL.

c. TENTHS.XCO

This file stores the configuration informa tion for the Tenth s mod ule.

d. COREGEN.PRJ

This file stores the Coregen configur ation for th e pr oject.

9. Select Cancel and close CORE Generator.

Instantiating the CORE Generator Module in the HDL Code

VHDL Flow

1. Open STOPWATCH.VHD and TENTHS.VHO in a text editor.

2. Copy the “COMPONEN T Declaration” section from TENTHS.VHO file and paste it

into STOPWATCH.VHD file in t he section: “-- Insert Coregen Counter Comp onent

Declaration.”

Figure 2: Binary Counter Dialog Window



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3. Copy the “COMPONEN T Instant iation” section from TENTHS.VHO file and paste it

into STOPWATCH.VHD in th e section: “-- Insert Coregen Count er Instantiation.”

Change “your_instance_name ” to “XCOUNTER”.

4. Edit this instantiated code to connect the signals in the Stopwatch d esign to the ports

of the CORE Generator m odu le. The instantiated port ion looks like the following:

XCOUNTER: tenths port map (

Q => Q,

CLK => CLK,

Q_THRESHO => xterm cnt,

CE => clkenable,

AINIT => rstint);

5. Save the design and close the text editor.

Verilog Flow

1. Open STOPWATCH.V and TENTHS.VEO in a text editor.

2. Copy the MODULE Declaration section from TENTHS.VEO file and pa ste it into

STOPWATCH.V file in the section //Place the CoreGen Module Declaration

for Tenths here.

3. Copy the INSTANTIATION Template section from TENTHS.VEO file and pa ste it

into STOPWATCH.V in th e section

//Place the CoreGen Component Instantiation for Tenths here.

Change “YourInsta nceNam e” to “XCOUNTER” .

4. Edit this instantiated code to connect the signals in the Stopwatch d esign to the ports

of the CORE Generator m odu le. The instantiated port ion looks like the following:

tenths XCOUNTER (

.Q(Q),

.CLK(CLK),

.Q_THRESH0(xtermcnt),

.CE(clkenable),

.AINIT(rstint));

5. Save the design and close the text editor.

Synthesizing the Design with FPGA/Design CompilerNow that the CORE Generator modu le has been mad e and the top level file has been

mod ified, the next step is to synth esize the design. FPGA/ Design Com piler will be used in

this step to translate and optimize the H DL files for the target architecture.

Setting up FPGA/Design Compiler’s Environment

In order for the Synop sys softwar e to run p roperly you will need a .synop sys_dc.setupenvironm ent file. The .synopsys_d c.setup contains all of the env ironment v ariables

necessary for FPGA/ Design Com piler to ru n. Examp les of these files can be foun d in

$XILINX/ synop sys/ examp les directory. Copy the Virtex examp le file into th e tu torial

directory. Renam e the file to .synopsys_d c.setup .

cd $XILINX/ synopsys/ examples/

cp template.synopsys_dc.setup_virtex

../ ../ tutorial/ wa tch_source/ wtut_vh d/ .synop sys_dc.setup

If you wan t to d o the Verilog flow copy th e setup file in the ap prop riate Verilog directory.



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cp template.synopsys_dc.setup_virtex

../ ../ tu torial/ watch_source/ wtu t_ver/ .synopsys_dc.setup

While in th e $XILINX/ tu torial/ watch_source/ wt ut_vhd (or wtu t_ver) directory ru n th e

following comm and to app end Virtex library information to the .synopsys_dc.setup file.

synlibs xfpga_virtex-5 >> .synop sys_dc.setup

Now your .synop sys_dc.setup file contains all the informa tion necessary to run a synth esis

flow that w ill be comp atible with A lliance 3.1i.

Note: The .synop sys_dc.setup file contains commen ts on the various Synopsys

environm ent variables that are being set.

Starting Design Analyzer

Design Analyzer is the GUI for FPGA/ Design Com piler. More inform ation on a ny of the

command s discussed in the following steps can be foun d by typing the man

<command_name> comma nd in the "Comm and Wind ow" or in "d c_shell".

1. Start Design Analyzer in the $XILINX/ tutorial/ watch_source/ wtut_vhd (or

wtu t_ver) directory by typing in design_analyzer at an xterm promp t.

Figure 3: Design Analyzer GUI



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2. Verify that all of the settings in the .synopsys_dc.setup file are active by selecting

Setup → Defaults... The settings shou ld be similar to those seen in the figu re

below.

1. Open the "Command Window"Setup →Command Window ... so that w e can view

all the comm and s that the GUI is executing. The "Comm and Window " will be helpful

in typing in comman ds that can not be accessed th rough the GUI.

2. Below are a list of the design files (the same nam e in VHDL and Verilog) that w ill need

to be analyzed.

a . cnt60

b. decode

c. hex2led

Figure 4: Defaults Window

Figure 5: Design Analyzer Command Window



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d. smallcntr

e. statmach

f. stopwatch

3. Analyze all of the design files File→Analyze... You can read in m ultiple files by

hold ing th e "Shift" key and selecting the n ext file. Create a "WORK" d irectory by

selecting the "Create New Library if it Doesn’t Exist" butto n or chan ge to the

$XILINX/ tuto rial/ watch_source/ wtu t_vhd (or wtu t_ver) directory and make th e

"WORK" directory in the xterm pro mp t by th e mkdir command.

4. Click OK.

5. Design Compiler should h ave reported an error in the smallcntr file. Open the

smallcntr file in a text editor and correct the mistakes repor ted a nd re-ru n step 6.

Figure 6: Analyze File Dialogue



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6. Next run the elaborate comm and File→ Elaborate...on the top level design

"stop w atch" in the library "WORK".

Note: Steps 6 and 8 can be don e with the File→ Read... command except that

there is n o op tion to au tomatically create a "WORK" d irectory.

7. There shou ld be six blocks (seven blocks for the Verilog flow) inside th e main Design

Analyzer wind ow. Because th e d esigns "HEX2LED" and "sma llcntr" are instan tiated

mu ltip le times FPGA/ Design Com piler requires that a "dont_tou ch" attribute be

placed on them (see

http://sup port.xilin x.com/techdocs/5048.htm for more information).

Figure 7: Elaborate Design Dialogue



http://support.xilinx.com/techdocs/5048.htm%20for%20more%20information

http://support.xilinx.com/techdocs/5048.htm%20for%20more%20information


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a. Highlite the "HEX2LED" block.

Note: High liting a p articular block is the sam e as executing the "cur rent_design"

command on a d esign.

b. First comp ile the selected design. Select Tools → FPGA Compiler... →

Optmization... → OK

Figure 8: Design Analyzer with Elaborated Designs



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c. Next place the "d ont_touch" attribute on the d esign. Select Attributes →

Optimization Directives → Design... Hit the "Don’t Touch" then the

"App ly" button s.

d. Follow the above steps for the "smallcntr" design.

8. The top level ports in "stopwatch" will have to be declared as pad s so that the

necessary buffers can be inserted .

a. Select the "stopwatch" design.

b. Select Attributes → Optimization Directives → Design... Select the

"Port is Pad" but ton.

c. Hit the "App ly" then the "Cancel" button s.

9. Now that th e ports have been d eclared as p ads bu ffers (IBUF, OBUF, etc.) will need to

be inserted.

a. Make sure that the "stopwatch" design is still selected.b. Select Tools → FPGA Compiler... then hit the Insert Pads... button.

Note: Alternatively you ma y "Insert Pad s" by selecting Edit → Insert

Pads...

c. H it OK.

10. Now compile the "stopw atch" design by selecting Tools → FPGA Compiler... →

Optmization... → OK

11. Before writing out th e EDIF netlist, the "don t_touch" attributes w ill need to be

remo ved from "HEX2ED" an d "smallcntr ".

Figure 9: Design Attributes Window



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a. Highlite the "HEX2LED" d esign.

b. Remove the "don t_touch" attribute by selecting Attributes → Optimization

Directives → Design... Deselect the "Don’t Touch" button then h it the

"App ly" but ton.

c. Repeat the two steps above for the "smallcntr" design.

12. The last step will be to write out the d esign as an EDIF file.

a. Select Tools → FPGA Compiler... → Save As...Note: you can also do File → Save As...

b. Select the "File Form at" to be EDIF.

c. Write "stopw atch.sedif" as the file nam e.

Note: The extension .sedif will allow t he imp lementation tools to know that th e

netlist is coming from FPGA/ Design Com piler.

FPGA/Design Compiler Shell Scripting

FPGA/ Design Com piler can be run ein tirely from the FPGA/ Design Comp iler comm and

wind ow called "dc_shell". This section w ill be very brief as it is beyond the scope of this

tutorial to get d etailed a bou t scripting for FPGA/ Design Com piler.

Xilinx provid es samp le scripts to u se wh en th e CAE CD-ROM libraries are installed. These

samples can be foun d at:$XILINX/ synp osys/ exam ples. Below is a script th at is comp atible with th e GUI synthesis

flow th at was just comp leted. To run the script, typ e in at an xterm prom pt dc_shell -f

<scriptname> in the location where the sou rce files are found .

an alyze -format vhdl -lib WORK {cnt60.vhd, decode.vhd,

hex2led.vhd, smallcntr.vhd, statmach.vhd, stopwatch.vhd}

elaborate stopwatch -arch "inside" -lib WORK -update

current_design HEX2LED

Figure 10: Save File Window



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compile -map_effort medium

set_dont_touch HEX2LED

current_design smallcntr


set_dont_touch smallcntr

current_design stopwatch

set_port_is_pad "*"

insert_pads


remove_attribute find(design, "HEX2LED") dont_touch

remove_attribute find(design, "smallcntr") dont_touch

write -format edif -hierarchy -output "stopwatch.sedif"

exit

You h ave now completed the FPGA/ Design Comp iler tu torial!

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