Single-ended vs. Differential SC Circuits

Single Ended Differential

Number of Caps 1 (Cs) 2 (Cd)

Max Signal 1Vpp 2Vpp

Max Power V2/2 2V2

Thermal Noise kT/Cs 2kT/Cd

SNR V2Cs/(2kT) V2Cd/(kT)

Conclusion: For the same SNR, Cd = Cs/2, so total capacitance is same, and no extra layout area required for the capacitors

Charge Injection Cancellation (Johns & Martin “Switched Capacitor Circuit” p.45)

Charge Injection Cancellation cont.

Clock Phase/Sequence Switch state Charge Transfer

Φ2 = 1, Φ2a = 1

Φ1 = 0, Φ1a = 0

Q2 and Q3 on

Q1 and Q4 off

C2, C3 discharged

Φ2a 0 Q3 off Q3 deposits q/2 in C2||C3

Φ2 0 Q2 off No injection since top plate of C2 is open

Φ1a 1 Q4 on Q4 acquires q from CA

Φ1 1 Q1 on C2 charges to Vi; C3 charges to Vo

CA charges to C2Vi(n) + C3Vo(n) + q/2

Φ1a 0 Q4 off Q4 deposits q/2 into CA

Net charge injection in CA: -q + q/2 +q/2 = 0

±q cancel when Φ1 1

The switching sequence: Q3(Φ2a) off Q2(Φ2) off Q4(Φ1a) on Q1(Φ1) on

Integrator Using a Two-stage (Buffered) OPAMP

/ 1

OV

p

AA

s

Let Initial Values: VC1 = V1, VC2 = 0

1 21 2

1 2

( ) ( )O O

sC CI V V sC V V

C C

1

1

/ ( ) 1/O V

O p O

V A V Vs A A

2

1 2

C

C C

( 1/ )O O p uA A

1

02

1( )

1/O s

O

CV s

A C

Pole at:

Settling level:

Time Constant of OTA-SC Integrator

Open-loop Gain

0m L O S Og V sC V sC V 1 2

1 2

S

C CC

C C

( )

mO

L S

g VV

s C C

1 OV V 2

1 2

C

C C

1( )

m

L S

g VV

s C C

2

1 2 1 2( )

m mP

L S L

g C gs

C C C C C C C

At pole SP, , so:1V V

/Ps t te e 1

ps Transient term:

Unity-gain conventional integrator, assuming all C’s equal: 3

m

C

g

First-Order Gm-C Filter

1 2( )in out X in M out M out AV V sC V G V G V sC

1

2

( )( )

out X M

in X A M

V sC GH s

V s C C G

lim ( )( )

X

X A

CH s

C C

KCL at output:

1 0

0

( )k s k

H ss

1 1lim ( ) 1

sH s k k

The specified transfer function is:

1

11X A

kC C

k

10 1 for positive and A Xk C C

1 high frequency gaink

01

11M A

kG C

k

02

11M AG C

k

Equating the coefficients gives:

CA and CX can be chosen arbitrarily

Gm-C Biquads with Transmission Zeroes ≠ 0 or ∞

Vin

Gm1 Gm2 Gm3

Gm4 Gm5

2CA

2CA

2CB

2CB

2CX

2CX

Vout

Iin

Iin

2 5 2 4

2 3 1 2

( )( )( )

( )

( )

MX M M

X B X B A X Bout

in M M M

X B A X B

GC G Gs s

C C C C C C CV sH s

V s G G Gs s

C C C C C

( ) [1 ( )]in X in out X inI sC V V sC V H s

2

3 5 2 1 4

2

3 1 2

( ) ( ) /

( ) /

in B M M M M M Ain X

in X B M M M A

I s C s G G G G G CY sC

V s C C sG G G C

To calculate the input impedance, find

X Bin

X B

C CY s

C C

4

1

Mout in

M

GV V

G 1 4

1

M Min X

M

G GY sC

G

1 40 for in M MY G G

For s ∞,

At DC,

Dynamic Scaling GM-C Circuits

1. Let a cascade of N biquads realize H(s) = H1(s) H2(s) …HN(s). Before starting the circuit design, scle H1(s) so that k1|H1|(max) gives the largest allowable Vout1. Divide H2(s) by k1, and repeat scaling for H2/k1. Continue until all N Hi(s) are scaled

2. Realize all stages, scale the intermediate voltage VCA across CA in the first biquad by an appropriate k1A. Multiply incoming GMs (GM1 & GM2) by k1A, and divide outgoing GMs (GM4) by k1A. Then, the output current will be unchanged. Continue for all N biquads

V1

Gm1 Gm4

Gm2 Gm3

C VMV2 Vout1

Note: This scaling procedure avoids the complications caused by CX in the scaling of VCB in

biquads where H is not zero at infinite frequencies. This does not take care of loading by CX!

Fixed-Bias Triode Transconductor

I1 I1

I2I2

Q1 Q2

VC

Q3 Q4

Q9

Q5 Q6

Q7 Q8

I1+io1I1-io1

VDD

vi vi+ -

V VRout

Feedback loop to hold V

constant, Rout low, I1 in

Q1/2. Hence, VGS constant,

iq proportional to vi+ - vi

-,

9

9

1( )M n ox gs T

dsq

WG C v V

L r

where i i

q

dsq

v vi

r

Vgs9 is controlled by VC