tutorial on logic synthesis for lookup-table based fpgas

8/3/2019 Tutorial on Logic Synthesis for Lookup-Table Based FPGAs

1/8

A Tutorial on Logic Synthesis for Lookup-Table Based FPGAsRobert J. Francis

Department of Electrical Engineering, University of Toronto

AbstractThe ability to shorten development cycles has madeField-Programmable Gate Arrays (FPGAs) an attrac-tive alternative to Standard Cells an,d Mask Pro-grammed Gate Arrays for the realization of ASICs.One important class of FPGAs are those that uselookup tables (L UTs) to implement combinationallogic. The ability of a K-input LUT to implement anyBoolean function of Ii- variables di$eren,tiates the syn-thesis of LUT circuits from synthes is for conventionalASIC technologies. The major difference occurs dur-ing the technology mapping phase of logic synthesis.

For values of I( greater th,an 3, th.e large number offunctions that can be implemented by a K-input LUTmakes it impractical to use conventional library-basedtechnology mapping. However, the completeness ofthe set of functions th.at can be implemented by a LlJTeliminates the need for a library of separate junctions .In addition, this completeness can be leveraged to op-timize the final circuit.1 Introduction

Field-Programmable Gate Arrays (FPGAs) nownrovide an alternative to Standard Cells and Mask Pro-grammed Gate Arrays for the realization of ASICs. AnFPGA consists of an array o f logic blocks that imple-ment combinational and sequential functions, a,nd auser-programmable routing network that provides con-nections between the logic blocks. User-programabilityallows for rapid and inexpensive prototype develop-ment [l]. This tutorial discusses combinational logicsynthesis for FPGAs that use lookup tables (LUTs)to implement combinational logic, and focuses on is-sues that differentiate LUT synthesis from conven-tional logic synthesis.A K-input lookup table is a digital memory thatcan implement any Boolean function of K variables.The I< inputs are used to address a 2K by l-bit digi-tal memory that stores the truth table of t,he Booleanfunction. For example, Figure la illustrates the truthtable for the function 2 = ab + zc, and Figure lb il-lustrates the st,ructure of a 3-input LUT implementingthis function. The truth table is stored in an 8 by l-bit,memory, and an 8 to 1 multiplexer, controlled by thevariables a, b, and c, selects the output value z.The goal of combinational logic synthesis is to pro-duce an optimized circuit implementing a given combi-national function. The original function can be repre-sented by a Directed Acyclic Graph (DAG) where each

node represents a local function of the global functionsrepresented by its immediate fanin nodes. For exam-ple, in the DAG illustrated in Figure 2a the local func-tion at the node z is z = wxy, and the global functionis z = ((abc) + (def))(g + h)(i + j).The netlist describing a circuit of LUTs can be rep-resented by a similar DAG. In this case, each node rep-resents a smgle LUT and the nodes local function spec-ifies the function implemented by the LUT. Figure 2billustrates a circuit of 5-input LUTs implementing thefunction illustrated in Figure 2a. The dotted bound-aries in Figure 2b indicate the local function imple-mented by each LUT. The local function implementedby the LUT t is z = (u + (def))t. Unless stated other-wise, all examples in the remainder of this tutorial willuse 5-input LUTs.Combinational logic synthesis can be conceptuallydivided into two phases; technology-independent logicoptimization, and technology mapping [2]. Logicoptimization restructures the original network, withoutchanging the function of its primary outputs, and tech-nology mapping implements the optimized network us-ing the circuit elements available in the given ASIC

x = ab + bc0

a) Truth Tableabc

S lo 1 multiDlexeri............ ._........I . ._I............. /.. ..... . ... .._..._

xb) 3-Input LUT

Figure 1: A LUT Implementing z = ub + zc

40O-8186-3010-8/92 $03.00 0 1992 IEEE


2/8

abc def gh1

x

Yw

za) Boolean Network

abc

de f

i j

Y

g i j

b) Circuit of S-input LUTsFigure 2: Network a.nd Circuit

technology.The modifications performed by logic optimizationtypically include redundancy remova l and commonsub-expression elimination. The intention is to im-prove the final circuit by simplifying the underlyingnetwork. For example, consider the network shownin Figure 3a. The common sub-expression e + f canbe factored out of the functions x and g leading to thesimplified network covered by the circuit shown in Fig-ure 3b. Conventional techniques for logic optimizationcan be effective for LUT circuits particularly at a levelof granularity where factors ha.ve more t,han AV nputs.These techniques have been summarized in [2] and willnot be discussed here.Technology mapping selects sub-networks of the op-timized network to be implemented by the availablecircuit elements. In the case of LUT-based FPGAs,any sub-network wit.11 at most K inputs can be im-plemented by a K-input LUT. The final circuit mustinclude a LUT implementing each of the primary out-puts and all of the LUT input,s t,hat a.re not primaryinputs.The optimization goa. for the synthesis of LUT cir-cuits is typically the minimiza.tion of the t.ot.al munberof LUTs, t,he number of ferlels of LUTs, or bot,h. Min-imizing the number of LUTs in the circuit increasesthe size of designs tha t can fit into the fixed numberof LUTs availa.ble in a given FPGA. The minimiza-tion o f the number of levels of LUTs can improve theperformance of the circuit by reducing the number oflogic block delays and programmab le routing delays

ab, , f de df

x Y

a) Boolean Network

Xb) Circuit of 5-input LUTs

Figure 3: Common Sub-Expression Elimination

on the longest path. To illustrate the issues that dif-ferentiate LUT synthesis from conventional logic syn-thesis, this tutorial will focus on the minimization ofthe total number of LUTs in the final circuit. The fol-lowing section discusses the limitations of conventionallibrary-based synthesis when applied to LUT circuits,and Section 3 discusses approaches to logic synthesisthat deal specifica.lly with LUT circuits.2 Library-Based Synthesis

Standard Cells and Mask Programmed Gate Ar-rays both implement. combinational functions using alimited set of simple gates. The most successful ap-proach t,o synthesis for these ASIC technologies hasused library-based technology ma.pping [3]. This ap-proach traverses the network from the primary inputsto the primary outputs, and at each node the localstructure of the network is m.adched against a libraryof patterns representing the set of available gates. Foreach successful match, the cost of the circuit using thatgate is calculated from the cost of the gate, and the costof t,he previously constructed circuits implementing theinput,s to the gate. The m inimum cost circuit amongall the matches is then retained.The major obstacle to applying library-based tech-nology mapping to LUT circuits is the large numberof different functions that a K-input LUT can imple-ment. The function implemented by a K-input LUT isdetermined by the values stored in its 2K memory bits.Since each bit ca.n independently be either 0 or 1, there

are 2- K different Boolean functions of li variables. Forvalues of li greater than 3 the library required to rep-

41


3/8

without with withI< permutations permut,ations permutationsand inversions and inversions2 1G 12 43 25G 80 144 65536 3984 232Table 1: Number of Patt,erns for a K-Input LUT

resent a K-input LUT becomes impractically large.The size of the libra.ry can be reduced by notingthat some pa,tterns are equivalent after a. permutationof inputs [4]. The inversion of outputs or inputs, whichis trivially accomplished with a LUT, ca.n also produceequivalent patterns . Table 1 lists the number of differ-ent patterns, with and without permutations and in-versions, for IC = 2, 3, and 4. To match a. sub-networkagainst a pattern in the reduced library it may be nec-essary to permute or invert the sub-network. Ha.shingfunctions have been proposed to simplify the matchingof permuted patterns [5]! but the increased complexityof pattern matching limits the benefits of the reducedlibrary.Another alternative is to use a partial library tunedto take advantage of the network structure likely to beproduced by technology independent logic optimiza-tion [6 ]. The limitation of this approach is that it pre-cludes some opportunities for optimization of the finalcircuit. The following section discusses approaches toLUT synthesis that exploit the full functiona.lity of aK-input LUT to obtain improved result,s.3 LUT-Specific Synthesis

There has been a great, deal of recent, work on lo .icsynthesis that deals specifically with LUT circuits. G ,[ G71 PI P WI, Pll, 1121,13], P41, P51, I B181. The 161, P7 ,1ey to all of these approaches is t le abilityof a K-input LUT to implement ~11 unctions of Iivariables. This complelen.ess simplifies the ma.tching ofa sub-network t.o a LUT. To determine if a sub-networkmatches a. K-input, LUT it is not, necessary t,o matc!lthe sub-network a.gainst, a. ibrary of sepamte palterns,as described in the preceding sect,ion. It is sufficientto count the number of inputs to the sub-network, andverify that the number of inputs does not exceed theconstraint K.Technology mapping optimizes the final circuit byselecting which sub-networks are covered by LUTs. Ifthe original network includes nodes with more than Kinputs, referred to as infeasible nodes., it may not bepossible to find a circuit of LUTs covermg the network.In many mapping algorithms, t.o ensure that a circuitcovering the network exists, each infeasible node is de-composed into a set of feasible nodes, each wit,h at mostI< inputs. In addition, the decomposition of bot,h fea-sible and infeasible nodes present,s an opportunity tooptimize the final circuit.The next section discusses the decomposition of in-feasible nodes, Section 3.2 discusses how decompositionand covering can be combined to improve the final cir-cuit, and Section 3.3 describes how covering can exploit

fanout nodes in the original network .3.1 Decomposition of Infeasible Nodes

The general stra.tegy for the decomposition of infea-sible nodes is to decompose each infeasible node intosub-functions that use fewer inputs than the originalinfeasible node. Any sub-function that uses no moret,han K inputs is feasible and is decomposed no further.Any sub-function that has more tha.t Ii inputs is recur-sively decomposed. Eventually the original infeasiblenode is decomposed into a set of feasible nodes. Fourmethods tl1a.t have been proposed for the decom po-sition of infeasible nodes are; disjoint decomposition,algebraic factorization, AND-OR decomposition, andShannon cofactoring.3.1.1 Disjoid DecompositionA disjoint deconlposition is based on a pa.rtition of theinputs to the infeasible node into two disjoint sets re-ferred to as the bound sef and the free set. One or morefunctions of the bound set are extracted from the in-feasible node, and the infeasible node is replaced by afunction of the outputs of the extracted functions andthe inputs in the free set. The attraction of a disjointdecomposition is that the number of inputs in the eachof the t.wo sets must be less than the number of inputst,o the infeasible node.Disjoint decompositions can be found by searchingthrough all possible pa.rtitions of t,he inputs to the in-feasible node, alld using well known methods such asresidues [19], t.o determine if each ea.& partition leadst,o a disjoint decomposition. A residue function is ob-t.ained by repla.cing the inputs in the free set with con-sta.nt values. If the set of all possible residue functionsfor a given partition consists of the constants 0 or 1,or a single function h of the bound variables, or its in-verse SE, hen the partition is a disjoint decomposition,with one extracted function. For example, consider the4-input function f = ab + c&d + 7ib? + Tibz shown inFigure 4a, and t,he pa,rtition of its inputs into the freeset. (0, b} a.nd the bound set {c? d}. The set of residuefunctions for this partition, shown in Figure 4b, con-sists of the constants 0 and 1, a.nd the function cd andits inverse (cd). Therefore, this partition leads to thedisjoint, decomposition of the function f, shown in Fig-ure 4c.The number of partitions grows exponentially withnumber of inputs to the infeasible node, and the searchfor disjoint decompositions can become prohibitivelyexpensive if the infeasible node has a large number ofinputs.3.1.2 Algebraic DecompositionAlgebmic factoriza.tion techniques developed for tech-nology independent logic opt,imization can also be usedfor the decomposition of infeasible nodes [7]. For ex-ample, she function CC UC+ bc + bd + ce ca.n be alge-bra.ica.lly factored into the fa .ctor y = a + b + e, and theremainder ;c = cv + bd. Since the va.riable b is nsed by

42


4/8

ab abed abc abd

a) An infeasible function for A = 3cd b hc,d0 01 0

b) Residues for t,he partition {CL, )) {c, d)cd

ri

fc) The disjoint decomposition

Figure 4: Identifying Disjoint Decompositions

both the factor y a.nd the remainder z this is a. not adisjoint decomposition.3.1.3 AND-OR DecompositionDisjoint decompositions a,nd algebraic factorization arenot sufficient. to decom pose all infeasible nodes. For ex-ample, the majority function z = a6 + UC+ bc. has nodisjoint decomposition. AND-OR decomposition ca,nbe used to ensure that any infeasible node is clecom-posed into a set of feasible nodes. The ANDoperator is associative and commutat,ive, which I OR)a lowsan AND (OR) node to be divided into smaller AND(OR) nodes using any partition of its inputs. An in-feasible node is represented as a sub-graph of ANDand OR nodes, each of which is then decomposed us-ing AND-OR decomposition. For example, the above3-input majority function can be decomposed into the2-input functions v = ab, w = ac, x = bc, y = v + w,and t = y+s.AND-OR decomposition can also be used to decom-pose large infea.sible nodes into infeasible nodes thatare small enough t.o ma.ke an exhaust,ive search for dis-joint decompositions practical [9].

a) Original circuit, 4 LUTsb cdeg

i . . . . q.-..-:

b) With Shannon cofactoring, 3 LUTsFigure 5: Shannon Cofactoring

3.1.4 Shannon CofactoringAnother form of decomposition that. will always suc-cessfully decompose an infeasible node is Shannon co-factoring [ZO]. A n infeasible function of n. variables,f(z1 . . . ~j . x,,), is decom posed into the three func-tions fX, = f(rl . . l...z,), f- = f(Xl...O...X,)and f = zjfE, +qfq. The func?on f now depends onthe three inputs ~j, frj, and fq, and can therefore beimplemented by a single K-input LUT for Ir >_ 3. Thefunctions fZ,, and fq, each depend on at most n - 1variables. If n - 1 equals I< then the completeness of aK-input L17T ensures that these functions can be im-plemented by a single LUT. Otherwise, the functionsfQ3 and fq, ca,n be recursively decomposed. For ex-ample, t,he G nput function f = a.bcd+%eg+Z~eg canbe covered by the 4 LUT circuit shown in Figure 5a.This function can be cofactored ab_out the vqiable_a toproduce the cofact,ors fa = bcd+~@, fx = beg+Efi,and the 3 LUT circuit shown in Figure 5b.3.2 Decomposition and Covering

An importan t observation is that the decompositionof feasible nodes, as well as infeasible nodes, can leadto a superior circuit. For example, in the circuit shownin Figure 6a the AND and OR nodes in the underlyingnetwork are all feasible, and four 5-input LUTs areneeded to cover the network. In Figure Gb the original4-input OR node has been decomposed into a 2-inputand a S-input OR node a.nd only 2 LUTs are neededto cover the network.The AND-OR decomposition of feasible, and infea-

43


5/8

4 Original 4-input, OR node, 4 LUTs

b) OR node decomposed, 3 LUTsFigure G: Decomposition of a Feasible Node

sible nodes, can be combined with a covering algorithmsimilar to the library-based approach described in Sec-tion 2 to optimize the final circuit [lo]. The originalnetwork consists of AND and OR nodes, and is tra-versed from the primary inputs to the primary outputs.A circuit implementing each node is constructed fromthe circuits implementing its immediate fanin nodes.This circuit is optimized to minimize the total numberof LUTs, and to minimize the number of inputs used byits root LUT. This increases the number of unused in-puts available at the root, LUT, and these may reducethe number of LUTs required to implement a subse-quent node.At each node, the root LUTs of the fanin circuitsare referred to as the funin. L UTs. For example, Figure7a illustrates the fanin LUTs for the node z. In thisexample, the LUTs preceding the fanin LUTs are notshown, and the functions implemented by the faninLUTs are simple AND gates. In general, the faninLUTs can implement more complex functions.At each node, a tree of LUTs replacing the faninLUTs and implementing a decomposition of the nodebeing mapped is constructed in two st,eps. The firststep selects decompositions, as shown in Figure 7b,that allow several fanin LUTs to be packed togetherinto a single LUT. The second step comiects theseLUTs to form the circuit implemeuting the node beingmapped, as shown in Figure 7c. The following sectionsdescribe these two steps.

3.2.1 Decomposition Using Bin PackingThe objective of the first step is the minimization ofthe number of LUTs into which the fanin LUTs arepacked. To determine if a group of fanin LUTs canbe packed into a single LUT it is sufficient to countthe total number of inputs used by this group. The

a) Fanin LUTsr .. .IV

1i: . . -...........

zb) After bin packing- . ...I...

1I~.~~~~~~~.~.~.,~~1%

I .- ._! iII _.........,............_..._,...i7 Ii _..I.z

c) The final circuitFigure 7: Decomposition and Covering

completeness of K-input LUTs ensures that any groupof fanin LUTs that together have no more than K in-puts can be implement,ed by a single LUT. This allowsthe minimization of the number of packed LUTs to berest.ated and solved as a bin packing problem.The goal of the bin packing problem is to find theminimum number of fixed capacity bins into which agiven set of arbitrary sized boxes can be packed. Inthis case, the boxes are the fanin LUTs and the binsare the LUTs into which they are packed. The sizeof each box is the number of inputs used by the faninLUT and the capacity of each bin is K. In Figure 7athe boxes have sizes 3, 2, 2, 2, and 2.Bin packing is a well known combinational optimiza-t,ion problem, and there exists several effective algo-rithms for its solution [21]. In particular, the First FitDecreasing (FFD) algorithm is optimal for boxes andbins with integer sizes less than equal to 6 [22]. The

44


6/8

FFD algorithm begins with an empty list of bins. Theboxes are sorted by size and then each box, beginningwith the largest, is packed into the first bin in the listinto which it fits. If the box does not fit int.o any binthen it is packed into a new bin added to t,he end ofthe list. In Figure 7b the FFD algorit.hm has packedthe fanin LUTs from Figure 7a into LUTs having filledcapacities of 5, 4, and 2. Note that packing boxes intobins implies decomposition of the node being mapped.3.2.2 Completing the CircuitAfter the fanin LUTs have been packed into the bins,the final circuit, shown in Figure 7c, is formed by sort-ing the bins by filled capacity and then connecting theoutput of each bin to an unused input, of one of thefollowing bins. If no unused inputs are available thena new LUT is added to the root o f circuit. Connect-ing the bins alters the decomposition of the node beingmapped, however, the completeness of a K-input LUTensures that each sub-function can be implemented bya single LUT. In addition to minimizing the numberof LUTs in the circuit, this approach minimizes thenumber of inputs used a.t the root LUT of the circuit.This is an important consideration, since the root LUTbecomes a box when the following node is mapped.Smaller boxes ca.n reduce the number of bins requiredby the bin packing step and lead to a superior circuit.3.2.3 OptimalityIf the original network is a fallout-free t,ree then t,heabove approach constructs the circuit containing t,heminimum number of K-input LUTs for values of Ii 55. A similar approach can map fallout-free trees intothe the minimum depth circuit for values of I< 5 G [14].The mapping of trees can be used as part of a divideand conquer strategy to map arbitrary networks bypartitioning the network at, fa.nout nodes int,o a forestof trees that are then mapped separately.3.3 Covering of Fanout Nodes

While separate trees can be mapped effectively usingthe approach described in the previous section, generalnetworks containing fanout nodes present additionalchallenges and opportunities. The following two sec-tions describe the opportunities presented by reconver-gent paths and the replication of logic at fanout nodes,and Section 3.3.3 describes an a.pproach to LUT tech-nology mapping that takes adva.ntage of these oppor-tunities.3.3.1 Covering Reconvergent PathsIn some networks sepa.rate paths tha.t originate a.t afanout node reconverge at a subsequent node. For ex-ample, in Figure Sa, there are a pair o f reconvergentpaths origina.ting at the node a and termina.ting at thenode z. If the reconvergent paths are realized by sepa-rate LUTs, as in Figure 8a, then each path requires oneLUT input connected to the fanout node. If the recon-vergent paths are contained within a sub-network that

a) Reconvergent paths covered separately, 3 LUTs

b) Reconvergent paths covered together, 2 LUTsFigure 8: Covering Reconvergent Paths

has at most K distinct inputs, as shown in Figure 8b,then the completeness of a K-input LUT ensures thatt,he paths can be covered by a single LUT with onlyone input connected to the fanout. node. The reduc-tion in the number of inputs connected to the fanoutnode can lead to a superior circuit, as shown in Figure8b. However, it is not always advantageous to coverreconvergent. paths wit,11 a single LUT. For example, inthe circuit shown in Figure 9a the reconvergent pathsoriginating from the node a are realized within a singleLUT, and 4 LUTs cover the network. This network canbe covered with a circuit of 3 LUTs, as shown in Fig-ure 9b if the reconvergent paths are covered separately.The challenge for LUT synthesis is to determine whenreconvergent paths should be covered by a single LUT.3.3.2 Replication of Logic at Fauout NodesThe replication of logic at fanout nodes a,lso presentsan opportunity t,o improve the final circuit. For ex-ample , in t,he 3 LUT circuit shown in Figure 10a thefanout node L is explicitly implemented as the out-put of a LUT. Replicat,ing t,he function of this LUTlea.ds to the 2 LUT circuit shown in Figure lob. Thesub-circuits implementing the nodes y and z in Figure10a have sufficient unused capacity to include a copyof the 3-input AND node, and the completeness of aK-input LUT ensures that the functions incorporatingthe copies can be realized. Replication of logic is not

45


7/8

a) Reconvergent paths covered together, 4 LTJTs

b) Reconvergent paths covered separately, 3 LUTsFigure 9: Covering Reconvergent Paths

always beneficial and LUT synthesis must determineat which fanout nodes replica.tion should occur.3.3.3 Covering using Edge Visibility 4 ConclusionIn the fina. circuit produced by technology ma.ppingevery edge of the original net,work is either driven asthe output of a LUT or implemented within a LUT.The covering of reconvergent paths and the replicationof logic at fanout nodes can be described by the as-signment o f edge visibility labels [12]. A visible edgeis driven by the output of a LUT, whereas an itlvisi-ble edge is implemented within a LUT. For example,the circuit shown in Figure llb covers by the networkshown in Figure lla. In this circuit the invisible edges(2, y) and (to, y) are represent,ed by curved lines. Thisassignment of edge labels implies the replicat,ion of the3-input OR node, a.nd leads t.o a circuit cont,aining 3LUTs. In Figure llc the edges (2, z) a.nd (9, z) are in-visible, and the reconvergent pa.ths origina.ting at, t#henode w are realized within a single LUT, leading to acircuit containing 2 LUTs.

The key feature that differentiates the synthesis ofLUT circuits from synthesis for conventional ASICtechnologies is the completeness of the set of functionsthat can be realized by a K-input LUT. This complete-ness simplifies technology mapping by eliminating theneed for a library of separate functions. In addition,completeness presents opportunities to select decom-positions that improve the final circuit.

After the decomposition of infeasible nodes, the as-signment of edge labels can be optimized using a di-vide and conquer s trategy. The network is partitionedinto sub-networks, and within each sub-network, the

To date research in LUT synthesis has focused pri-marily on technology mapping. The challenge for thefuture is to exploit the completeness of LUTs to im-prove other phases of FPGA synthesis. In particu-lar, delay penalties incurred by programmable routingin FPGAs, provide motivation for the investigation ofthe combined effect of logic synthesis, placement, androuting on circuit performance. Another important is-sue is t,he tradeoff between optimization to fit a designinto the fixed logic and routing resources available ona given FPGA, and optimization to improve the per-formance of the final circuit.

Y 2

a) Without replication, 3 LUTs

Y zb) With replication, 2 LUTs

Figure :lO: Replication of Logic at a Fanout Node

optimal assignment is found by exhaustively search-ing all possible combinations of edge labels. If thesub-network containing m edges, t,here are 2 differentcombinations. For each combination a circuit is formedby combining the source and destination nodes of invis-ible edges into one LUT. If any of the resulting LUTshave more than K inputs, then the combination of edgelabels is re.jected. Otherwise, the combination resultingin the circuit containing the fewest LUTs is retained.The computational cost of the search is controlled bythe limit on the number of edges in the sub-network.In addition, the search can be pruned whenever a com-bination leading to a LUT with more than IZ inputs isrejected.

46


8/8

w

+x Y

za) Original network

zb) Edges (cz), (WY) invisible, 3 LUTs

! . . .ILit;. i._i . . . .

i.i

4+

Ii j! xI . ..?

c) Edges (zz), (yz) invisible, 2 LUTsFigure 11: Covering Using Edge Visibility

ReferencesPIPI

[31

141

[5!

[61

S. D. Brown, R. J. Francis, J. Rose, Z. G. Vranesic, Field-Programmable gate Arrays, Kluwer Acedemic Publish-ers, 1992.R. K. Brayton, G. D. Hachtel, A. Sangiovanni-Vincentelli,Multilevel Logic Symhesis, Proc. of IEEE, Vol. 78, No.2, Feb. 1990, pp. 264-300.K. Keutzer, DAGON: Technology Binding and Local Op-timization by DAG Matching, Proc. 24th DAC, June1987, pp. 341-347.S. Trimberger, A Small Complete Mapping Library forLookup-Table-Based FPGAs, 2nd Intl. Workshop onField-Programmable Logic and Applications, Aug. 1992.U. Schlichtmann, F. Brglez, M. Hermanrl, Characberiza-tion of Boolean functions for Rapid Matching in EPGATechnolgy Mapping, Proc, 29th DAC. Jurle 1992, pp. 374-379.R. J. Francis, J. Rose, K. Chung, Chortle: A Technol-ogy Mapping Program for Lookup Table-Based Field Pro-

[71

PI

[Ql

PO1illI1121

[131

[I41

1161

1171

WI

WIPO11211

WI

grammable Gate Arrays, Proc. 27th DAC, June 1990, pp.613-619.Ft. Murgai, Y, Nishizaki, N. Shenay, R .. K. Brayton,A. Sangiovanni-Vincent&, Logic Synthesis for Pro-grammable Gate Arrays, Proc. 27th DAC, Jtme 1990, pp.620-625.P. Abouzeid, L. Bouchet, K. Sakouti, G. Saucier, P. Sicard,Lexicographical Expression of Boolean Function for Mul-tilevel Synthesis of high Speed Circuits, Proc. SASHIMI90, Oct. 1990, pp. 31-39.D. File, J. C. Yang, F. Mailhot, G. De Micheli, Tech-nology Mapping for a Two-Output RAM-based field Pro-grammable Gate Array, Proc. EDAC, Feb. 1991, pp. 534-538.R. J. Francis, J. Rose, Z. Vranesic, Chortle-crf: Fast Tech-nology Mapping for Lookup Table-Based FPGAs, Proc.28th DAC, June 1991 pp. 227-233.I

tutorial on logic synthesis for lookup-table based fpgas

Documents