tutorial] 11 encounterflow[20080319]

The Chinese University of Hong Kong Department of Electronic Engineering ELE 4550 ASIC Technologies (2005-06 2nd Semester)

Level 3: Physical Design and SOC Encounter

Output Verilog Netlists 1. After adding I/O pads

2. Go to “icfb windows -> Tools -> Verilog Integration -> NC-verilog” to open “Virtuoso

Schematic Composer Analysis Environment for NC-Verilog Integration” window.


3. When the NC-Verilog is opened, select “Browse” to choose your design, then press “Initial Design” and “Generate Netlist”.

4. The netlist is generated in the XXX_run1/ihnl/cdsYY/netlist directory, where XXX is your design name and YY is a number depends on your hierarchy level.

5. Create a folder named “encounter” and create a folder named “verilog” and another named

“work_fe” under the “encounter” folder. Copy all the files named “netlist” under cdsxx into that “verilog” directory.

6. Add the Corner Pad to the top level verilog file(e.g. cds12.v), just before the statement “endmodule”.

7. To run the “Clock Tree Synthesis” in SOC Encounter, we need to integrate those cdsxx files into single verilog code by cascading them together first. For example, create a new file “top.v”, copy the content of “cds0/netlist” to “top.v”, and then “cds1” and so on.

8. When the file “top.v” is ready, in the unix console, type “uniquifyNetlist –top <top_cell_name> <output_netlist_name> <input_netlist_name>”, for the case used in this tutorial, top cell name is “topview”, so the command is “uniquifyNetlist –top topview topout.v top.v”.


9. “topout.v” is ready for use in SOC Encounter.


Physical Design with SOC Encounter 1. Introduction

The Cadence Encounter provides a variety of digital solutions for nanometer design. The Encounter main window is shown below.

The UNIX window where you start the Encounter session is called the Encounter console. This is where you enter the Encounter text commands and where the software displays messages.

2. Setup and invoke the Encounter

a. Copy the follow lines to your .cshrc file and source it. # start setup SOC encounter license set path = (/export_w16/soc33/tools/bin $path) setenv LM_LICENSE_FILE /export_w16/soc33/share/license/license.80e7779d # end setup SOC encounter license

b. Go to the project directory, “ele4550/encounter/work_fe” c. Download the LEF files and the TLF files from the course’s website. Put all these files in the

encounter directory and also prepare the netlist created in previous section.

lxin

Cross-Out

lxin

Replacement Text

Open one term and run: source \ /export_w19/cds/ic5141ams370.env


d. Type “encounter” to invoke the Encounter graphic user interface.

3. Import a design. Click Design Design Import, the Design Import form appears. Complete the Design page as below. You can use the file widget to browse and select the files. Change to the Power Tab, set Power Nets = vdd! vdd3r1! vdd3r2! vdd3o!, Ground Nets = gnd! gnd3r! gnd3o!. Click Save to save the configurations to topview.conf. You can reload these configurations later by loading this file. Click OK to import your design.

Click Design Save Design to save your design as topview.enc. To load your design later, use Design Restore Design.

4. Extract I/O pad file. a. Click Design Save I/O File…, to save the I/O file. b. Open the I/O file to change the CORNERP pads direction, i.e. change C1, C2, C3, C4 to

SW, SE, NW, NE respectively. You can also rearrange other I/O pads to meet your design requirements.


c. Goto Design Import again to include the modified I/O file in the IO Assignment File.

5. Initialize floorplan. Click Floorplan Specify Floorplan, under Size by Core Size by Aspect Ratio, set Ratio = 1, core Utilization = 0.7. And use 400 for Core to IO Boundary. Click OK. Save your design.


6. Add power/ground rings and stripes. a. Assign the global nets of power and ground: click Floorplan Global Net Connections.

Enter set 1 configurations as the table below and click Add to List. Connect the rest global nets and then click Apply.

b. Add power rings: click Floorplan Power Planning Add Rings. Type gnd! vdd! in the Net(s) line. Set ring width to 15, spacing to 2, offset to 15 and active specify. Click OK.

Entry Set 1 Set 2 Set 3 Set 4 Set 5 Set 6 Set 7

Pins vdd! vdd3o! vdd3r1! vdd3r2! gnd! gnd3r! gnd3o!

In Instance * * * * * * *

Apply All Selected Selected Selected Selected Selected Selected Selected

To Global Net vdd! vdd3o! vdd3r1! vdd3r2! gnd! gnd3r! gnd3o!


c. Add stripes: click Floorplan Power Planning Add Stripes. For this small design, we add one pair of stripes. Make the changes as the figure below and click OK. The values in the stripe offset boundary decide the stripes’ position. Try to put the stripes in the middle of your floorplan.


d. Save your design.

7. Place the cells. a. Place the endcap cells: click Place Filler Add End Cap. Use Select to select

ENDCAPL as Pre Cap Cell and ENDCAPR as Post Cap Cell. Leave others as default and click OK.


b. Place the cells: click Place Place. Use Medium Effort for Placement Effort Level. Active Timing Driven and save the netlist to cla.post_tdp.v. Click OK. After successful placement, you can see that all the cells have been placed in your floorplan by clicking .

c. Create the clock tree: select Clock Specify Clock Tree. Use topview.ctstch as the Clock

Tree File and press OK. You can download topview.ctstch on the web page. In this file, you need to modify the line AutoCTSRootPin, default is instance name I1/Y, you can find the instance name of your design from schematic CLK signal pin. For example, if your CLK pad instance name is I123, then update the line to AutoCTSRootPin I123/Y.

Click Clock Synhesize Clock Tree. Use the default configurations and click OK.


After the clock tree is created, a new netlist topview_cts.v will be generated in the topview_cts directory by the Encounter. You should use this netlist for postlayout simulation. Use Clock Display Display Clock Tree to view the clock tree.

d. Place the core filler cells: Click Place Filler Add Filler. Select FILL1, FILL2, FILL5,

FILL10, FILL25 as Cell Name(s). Leave other settings as default and press OK.


e. Save your design. 8. Routing.

a. Power routing: select Route Sroute. Use the default settings and click OK.

b. Running Trial Route: TrailRoute is an internal router to help quickly estimate the timing and

congestion of your design before going to NanoRoute/WRoute. Select Route Trial Route. Use topview_cts.guide in the topview_cts directory as the routing guide and click OK.


c. Running NanoRoute or WRoute: NanoRoute and WRoute are both global/detail routers with

signoff tapeout quality. They are very similar but NanoRoute is a newer engine which is running faster with better quality. For 0.18um or below, it is highly recommended using NanoRoute in detailed routing. For NanoRoute, click Route NanoRoute. Active Timing Driven and leave others as default. Click OK. For WRoute, select Route WRoute, use the default settings and click OK


d. Save your design.

9. Verify connectivity. Select Verify Verify connectivity, keep the default settings and click OK. View the information in the Encounter console and the report topview.conn.rpt to be sure there is no connection problems.

10. Generate the SDF file and the GDS file. a. Generate SDF file: select Timing Specify Analysis Condition Specify RC Extraction

Mode, set Mode to Detail. Then click Timing Extract RC. Unselect all and click OK. Then click timing Calculate Delay. Unselect Ideal Clock, use topview_en.sdf as the SDF file name and click OK. The SDF file will be generated.

b. Generate the GDS file: click Design Save GDS. Use topview.gds as the output srteam file name, leave others as default and click OK.

tutorial] 11 encounterflow[20080319]

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