turbo decoder core for asic&system development softdsp corporation 1999-2000
Post on 15-Jan-2016
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Turbo code
Offers near idealistic, Shannon-limit Error correction performance
This great coding capability has lead turbo codes to the standard of 3rd generation wireless mobile communications (3GPP)
softDSP Turbo decoder
Fully Implemented with VHDL and offer flexible interface for use in various applications such as..
3GPP, Power-line modem, Military comm. Magnetic-storage channel, Satellite comm. High-speed wireless comm. Etc.
Features
Use max-log-MAP decoding method as an internal component decoder
Use sliding-window technology to reduce memory size
3GPP compliant (block size 40-5114) Constraint length K=4, Rate ½, 1/3 5bit input (4-8bit) and internal 8bit processing Easy external I/O interface Easy to modify code to your system
What we offer?(Offering Materials) VHDL Source code Turbo code simulation C-source (floating/
fixed point) 3GPP standard interleaver generation C-s
ource (3G TS 25.212 V.3.2.0) Turbo decoder test vector Designer’s guide file
Entire Turbo decoder Core Structure MAP decoder FIFO memory LLR memory Turbo controller SNR scaler Additional circuitry
+
system
LLR memory 1
LLR memory 2
MU
X
SwapParity alternateFirst IterRd_addressIntaddr_requireInt_deintBlocksize_2
MAP decoder
FIFO logic
-
MU
X
parity
Interleaveraddress
MUX
Int/deint
reset startblocksize iteration
llr_out
out_clk
Num_iter
output_clock
rd_clk
data_enable
SNR scaler
Interleaver/DeinterleaverSNR
Turbo_ctrl
SNR
DFF
DFF
I/O Interface of Turbo decoder core
System Address
System Data
Parity Address
Parity DataParity Alternate flag
Block Size
Iteration
Number of MAP Iteration
Decoded LLR Output
Output EnableOutput Data Clock
13
13
13
4
8
84
8
Reset
CLK
Intaddr_requireInterleaver_address
13
13
Start
Rd_clk
3SNR
Data Enable
Swap
Notwr_clk
Int_deint
Block Size213
READ READ READ
WRITE WRITE WRITE
READ READ
WRITE WRITE
READ READ
WRITE WRITE
READ
WRITE
Decoding Operation Normal vs. Sliding-window
(a) Normal Turbo(MAP) decoding operation
(b) Sliding-window decoding operation
Procedure of system operation Easy to control : Just by reset and start
signal Turbo decoder operates as a slave device
of the master processor Turbo decoder generate address signal
and get the data and decode it You can extract decoded output just when
output clock is validated
Disable Reset signal
By asserting start signal, Let the Turbo decoder start decoding
Supply System/Parity data andInterleaver address
Get the decoded output
If decoding of current block ended?The re-assert start signal
Operation of external processor Operation of Turbo decoder
Initialize Blocksize / Iteration / SNR informationRegister
Memory read address / Interleaver addressrequire signal
Get the data & decode it
Blocksize, Iteration, SNR
Application system designSoftDSPTurbo decoder core
Host processor
Start
System data memory
Parity data memory
From equalizer/ RAKE receiver/ AGC etc
Reset
Interleaver memory Parity_dataParity_address
System_dataSystem_address
Interleaver_addressIntaddr_require
Blocksize/Iteration/SNR
Int/deint
Output data clock
Output data
Iteration Number
Parity_alternate