Lesson 1: H thng thi gian thc Real time embedded system (RTES)_Cuong_Ngoc3I. nh ngha3II. c im ca RTES3III. Kin trc thng thng ca RTES3IV. Cc phn t ca h thng nhng5V. Cc rng buc trong thit k RTES5Lesson 2: Microprocessor & Microcontroller_Cuong_Ngoc7Lesson 3: Memory _Cuong_Ngoc9Lesson 5: Memory I._LAI9I.Introdution: ( gii thiu)9II.Data Storage11III.Common Memory Types13IV.Example: HM6264 & 27C256 RAM/ROM devices18V.Example: TC55V2325FF-100 memory device18VI.Composing memory18Lesson 6: Memory II._CHAU18I.Phn cp b nh18II.Cache19III.Cache mapping19Lesson 8: General Purpose Processors I Vi x l a dng_NGOC_CUONG29I. Kin trc29Tm tt34Lesson 10: Embedded Processors I Cc b x l nhng I_NGOC_CUONG34I.Gii thiu34The Architecture of a Typical MicrocontrollerKin trc ca 1 vi iu khin in hnh35Timer49Counter49Timer in 8051 Microcontroller521.Timer0 v Timer1:522.MODE0:523.Cc bit M1, M0524.Bit C/T(Counter/Timer)535.Bit cng GATE536.MODE154The Programmable Interval Timer 825355Ch hot ng ca 8253581.Ch 0: Ngt khi m ht592.Ch 1: mono shot lp trnh c:593.Ch 2: Programmable Rate Generator614.Ch 4: Phn mm kch hot xung635.Ch d 5: Phn cng kch hot xung64Watchdog timer64Watchdog Circuit64

1. Realtime SystemLesson 1: H thng thi gian thc Real time embedded system (RTES)_Cuong_Ngoc

I. nh ngha- Thi gian thc thng c ngha l thi gian c quy nh bi ngun ngoi (xung vt l). Thi gian c to ra theo yu cu ca ngi dng.- H thng thi gian thc l tp hp chnh xc cc h thng con hon thnh 1 nhim v c th 1 cch tri chy. Ni cch khc, nhim v s c thc thi trong 1 thi gian quy nh.II. c im ca RTES- n chc nng: RTES thng c ngha dng cho cc chc nng rt c th. Thng thng 1 vi x l mc ch c bit thc thi 1 chng trnh nhiu ln cho 1 mc ch c th. Nu ngi dng mun thay i chc nng (vd nh chuyn chc nng in thoi di ng t hi thoi sang ch camera hay ch tnh ton, th chng trnh s c y ra & chng trnh mi c ti vo. Cc hot ng ny c theo di & iu khin bng 1 h iu hnh thi gian thc (Real Time Operating System (RTOS)), n gin hn nhng c nhiu hn ch cng nhc hn so vi cc h iu hnh thng thng nh Micro Soft Windows hay Unix...- Rng buc cht ch: RTES c cc rng buc trong thit k v tiu th: rng buc v min thi gian, kch thc, trng lng, in nng tiu th & gi c.- Phn hi & thi gian thc: rt nhiu h thng nhng phi lin tc phn ng vi nhng thay i trong mi trng ca h thng & phi tnh ton ra kt qu c th trong thi gian thc m khng c s chm tr.III. Kin trc thng thng ca RTES- Bt k h thng no cng c chia thnh cc h thng con. Mi h thng con li c chia thnh cc h thng nh hn. V cc h thng c th bao gm cc thnh phn ri rc. y gi l cu hnh phn cng. Mt s cc b phn c th c lp trnh & v th, phi c 1 vi ni lu tr cc chng trnh. Trong RTES, b nh on-chip hay b nh non-volatile (vn lu chng trnh d mt in) s lu cc chng trnh. Cc chng trnh ny l b phn ca h iu hnh thi gian thc RTOS. - C phn cng & phn mm u cng tn ti 1 cch cht ch. Cc task c th c thc hin bi phn mm & phn cng nh hng n qu trnh thit k ca h thng. VD b nhn da trn phn cng c ci thin tc nhng gia tng chi ph v phc tp ca ALU, trong khi , b nhn da trn phn mm tuy chm hn nhng thit k b ALU n gin hn.

- User interface: giao din ngi dng, dng tng tc vi ngi dng. Bao gm: bn phm, touch pad- ASIC: Application Specific Integrated Circuit: dng cho cc chc nng chuyn bit nh iu khin ng c, iu ch d liu- Microcontroller: vi x l- Real Time Operating System (RTOS): cha tt c cc phn mm iu khin h thng & giao tip ngi dng.- Controller Process: tin trnh iu khin : 1 phn ca RTOS , c cc thut ton iu khin tng th. nh thi & iu khin nhiu chc nng bn trong h thng nhng.- Digital Signal Processor (DSP): b x l tn hiu s: h c trng ca vi x l.- DSP assembly code : m cho DSP c lu trong b nh chng trnh- Dual Ported Memory: cho php 2 b x l truy cp b nh d liu cng 1 lc- CODEC: Compressor/Decompressor: nn & gii nn d liu- User Interface Process: tin trnh giao din ngi dng: 1 phn ca RTOS m chy phn mm cho cc hot ng giao tip vi ngi dng.=> C nhiu vi x l (2 DSP & 1 uC) thc hin nhiu nhim v khc nhau. uC thng n gin & thc thi chm. DSP l b x l c cng sut cao hn, c th x l tn hiu thi gian thc & iu khin. C 2 DSP cng vi h iu hnh & code ca chng c lp vi nhau. Tuy nhin chng cng chia s cng b nh. Dng b nh ny c gi l b nh cng kp (dual port). RTOS kim sot cc yu cu thi gian ca tt c cc thit b. N thc thi thut ton iu khin tng th ca tin trnh trong khi chuyn hng cc nhim v phc tp hn cho cc DSP. N cng c bit kim sot uC cho hot ng tng tc ngi dng cn thit.- ASIC l cc n v chuyn bit c cc chc nng nh iu khin ng c, m ha ging ni, iu ch/ gii iu ch (MODEM) hnh ng. Chng c th l mch VLSI s, tng t hay tn hiu hn hp. CODECs thng c dng giao tip ni tip ADC in nng thp. Tn hiu analog t tin trnh kim sot c th c theo di thng qua giao tip ADC thng qua CODEC ny.

IV. Cc phn t ca h thng nhng- Microprocessor: l thnh phn quan trng nht ca RTES. Cc vi x l c s dng y khc vi cc vi x l mc ch chung. Chng c thit k thc hin cc yu cu ring bit. Vd: Intel 8048 l vi x l n mc ch, c s dng qut cc hot ng nhn phm & gi ti h iu hnh.- B nh: vi x l & b nh cng nm trn 1 Power Circuit Board (PCB) hay 1 chip. Nh gn, nhanh & t tiu tn nng lng l cc yu cu ca b nh trong RTES. Bn cnh , b nh cn phi c kh nng lu tr sau khi b ngt ngun. - Thit b & giao din nhp xut: giao din I/O cn thit RTES tng tc vi th gii bn ngoi. Chng c th l khi hin th trc quan nh mn hnh TFT trong in thoi, bn phm touch pad, microphone, loa. Cc RTES cng c cc giao din m cho cc thit b khc nh mn hnh my tnh, LAN, v RTES khc. Vd: bn mun ti file mp3 t internet vo my nghe nhc, cc thit b I/O cng vi cc giao thc phn mm tiu chun trong RTOS s cung cp giao din cn thit.- H iu hnh.

V. Cc rng buc trong thit k RTES1.Vn thit k: Cc rng buc trong thit k h thng nhng c quyt nh bi cc thng s k thut (c t) bn ngoi cng nh bn trong.2.Yu cu thit k: Yu cu thit k l mt c trng ca h thng c th o c: hiu sut, chi ph, thi gian cho vic hin thc, \dots. V gia chng c s mu thun (v d ti u ha v chi ph nhng hiu sut s gim i). Cc yu cu thng bt gp trong khi thit k mt h thng nhng nh sau:a)Chi ph k thut khng lp li (NRE cost): N l chi ph ch pht sinh mt ln trong vic thit k h thng nhng gm chi ph nghin cu, pht truyn, cng ngh, . Mt khi h thng c thit k, c th sn xut vi s lng sn phm bt k m khng c pht sinh thm chi ph v thit k.b)Chi ph sn phm: l chi ph sn xut mi sn phm m khng tnh NRE cost.c)Kch thc: khng gian vt l i hi bi h thng, thng c o theo byte i vi phn mm, v cng logic hay transistor i vi phn cng.d)Hiu sut: Thi gian thc thi ca h thng. C 2 yu t chnhi)thi gian ch (thi gian p ng): l khong thi gian t lc bt u thc thi n khi kt thc ca tc v.ii)thng lng: s lng tc v c th c x l trong mt n v thi gian.e)Cng sut tiu th: n gii hn thi gian sng ca pin, hoc yu cu lm mt ca IC, v cng sut tiu th cng ln th nhit cng ln.f)Tnh linh hot: kh nng thay i chc nng ca h thng m khng lm tng ng k chi ph NRE. Phn mm thng c xem nh rt linh hot so vi phn cng.g)Time-to-prototype: Thi gian cn xy dng mt phin bn c th lm vic c, thm ch c th ln hn hay tn km hn phin bn thng mi, nhng n c th c dng kim tra tnh hu dng v tnh tnh xc ca h thng v sng lc tnh nng ca h thng.h)time-to-market: thi gian cn pht truyn mt h thng ti khi n tr thnh phin bn thng mi. N gm thi gian thit k, thi gian ch to, thi gian kim tra. Yu cu thit k ny nh hng rt ln trong thi gian gn y (vng i sn phm gim t 4 - 5 nm xung 1 nm, thm ch l 6 thng). Vic gii thiu mt h thng nhng ra th trng sm c th to ra mt s khc bit ln trong vic to ra li nhun ca h thng.i)kh nng bo tr: N l kh nng iu chnh h thng sau khi c thng mi ha.ii)tnh chnh xc: yu cu h thng phi hot ng chnh xc v mt chc nng. C th kim tra chc nng thng qua qu trnh thit k, v chng ta c th chn mch test kim tra vic ch to l chnh xc.

Lesson 2: Microprocessor & Microcontroller_Cuong_Ngoc

- Microprocessor VI X L : l khi x l trung tm a dng ca my tnh s. to thnh my vi tnh, cn thm vo b nh (RAM & ROM), b gii m a ch, b to xung & cc I/O. Chc nng chnh ca vi x l l c d liu, thc hin cc php ton trn d liu , lu kt qu trn thit b lu tr hay hin th ra bn ngoi. Cc b x l ny c kin trc phc tp vi nhiu tng pipeline & x l song song. B nh c chia thnh nhiu tng nh cache a cp & RAM. Thi gian pht trin ca b x l a dng l kh lu v thit k VLSI rt phc tp.

- Microcontroller VI IU KHIN : thng c RAM v ROM (hay EPPROM) thm vo chip gim thiu s lng chip. Vic s dng phn cng chip cho IO, RAM & ROM lm cho hiu sut CPU kh thp. Vi iu khin thng c timer to ngt. Chc nng chnh ca vi iu khin l kim sot cc hot ng ca 1 h thng s dng 1 chng trnh c nh c lu trong ROM & khng thay i. Vi iu khin gi & nhn d liu t cc chn ca mnh, kin trc & tp lnh c ti u ha x l d liu.

- im khc bit r rng nht gia vi x l & vi iu khin l: hu ht cc vi x l c nhiu opcode di chuyn d liu t b nh ngoi vo CPU, trong khi vi iu khin ch c 1 hoc 2 opcode. Vi x l c 1 hoc 2 loi lnh x l bit, cn vi iu khin c nhiu loi.

2. MemoryLesson 3: Memory _Cuong_Ngoc

- Cc h thng my tnh hin i u da trn kin trc Von-Neumann. Theo , b nh s lu cc lnh & d liu. B nh giao tip vi CPU thng qua 3 ng: d liu, a ch & ng iu khin.

- c d liu: CPU np a ch ln bus a ch. Hu ht cc trng hp c thm b m ha chn ra v tr chnh xc trong b nh. Sau , CPU s gi tn hiu iu khin c. D liu c lu trong v tr s c chuyn n b x l thng qua bus d liu.- Ghi d liu: CPU np a ch ln bus a ch. Sau CPU tip tc gi lnh lu yu cu 1 v tr trong b nh. Sau , d liu s c gi n b nh.Lesson 5: Memory I._LAII. Introdution: ( gii thiu)Phn s m t v b nh. Hu ht cc h thng my tnh hin i c thit k trn c s ca mt kin trc c gi l Kin trc - Von Neumann

B nh lu cc ch dn cng ging nh d liu. Khng th phn bit mt lnh v d liu. CPU phi c chuyn trc tip ti a ch ca m lnh. B nh c kt ni vi CPU thng qua cc dng sau:

1. Address a ch2. Data d liu3. Control iu khin

Trong mt b nh c hot ng ca CPU np a ch trn bus a ch. Hu ht cc trng hp nhng dng ny c fed vo mt b gii m m chn v tr b nh thch hp. CPU sau s gi mt tn hiu iu khin c. Cc d liu c lu tr trong v tr c chuyn giao cho cc b x l thng qua cc dng d liu.

Trong hot ng b nh ghi a ch sau khi c ti CPU gi tn hiu iu khin ghi tip theo l d liu vo b nh v tr yu cu.

B nh c th c phn loi theo nhiu cch khc nhau, tc l da trn v tr, in nng tiu th, cch lu tr d liu vvB nh mc c bn c th c phn loi nh:

1. Processor Memory (Register Array) b nh s l (mng thanh ghi)2. Internal on-chip Memory b nh on chip3. Primary Memory b nh chnh4. Cache Memory b nh cache5. Secondary Memory b nh th cp

Processor Memory (Register Array):Hu ht cc b vi x l c mt s thanh ghi lin kt vi cc n v logic s hc. H lu tr cc ton hng v kt qu ca mt hng dn. Tc truyn ti d liu nhanh hn nhiu m khng cn bt k chu k ng h. S lng thanh ghi thay i t b vi x l n x l. Nhng s phc tp ca cc kin trc t mt gii hn v s lng b nh x l.

Internal on-chip Memory - B nh on-chip:Trong mt s b vi x l c th c mt khi v tr b nh. Chng c coi nh cng mt tng t nh l b nh bn ngoi. Tuy nhin n rt nhanh.

Primary Memory- B nh chnh:y l mt phn t ngay bn ngoi CPU. N cng c th trong cng mt chip tng t nh CPU. B nh ny c th tnh hoc ng.

Cache Memory- B nh CacheNm gia b x l v b nh chnh. N phc v nh mt b m cc ch dn trc tip hoc d liu m b vi x l d on. C th c nhiu hn mt mc ca b nh cache.

Secondary Memory - B nh th cp:Chng c coi l thit b u vo / u ra Chng lu tr r hn nhiu v cc thit b chm kt ni thng qua mt s cc mch giao din u vo / u ra. Ni chung l b nh t hoc quang hc nh a cng v cc thit b a CD-ROM. B nh cng c th c chia thnh b nh khng n nh v n nh.

Volatile MemoryCc ni dung c xo hon ton khi ngun in c tt. Bn dn truy cp ngu nhin Memories thuc th loi ny.

Non-volatile MemoryCc ni dung cn nguyn vn ngay c trong nhng in c tt. Nhng k nim t ( cng), a quang (CDROM), Read Only Memories (ROM) thuc th loi ny.

II. Data StorageMt b nh t m c th lu tr MXN: t m ca n bit mi. Mt t c t ti mt a ch do gii quyt t m chng ta cn. k = Log2 (m) gii quyt cc tn hiu u vo hoc k dng a ch s c th gii quyt m = 2 ^ (k) t

V d 4096 x 8 b nh: 32.768 bit 12 a ch tn hiu u vo 8 u vo / u ra Tn hiu d liuMemory accessV tr b nh c th c truy cp bng cch t a ch trn dng a ch. Cc dng iu khin c / ghi selects c hoc vit. Mt s thit b b nh l a cng tc l truy cp n nhiu a im khc nhau cng mt lc.Memory SpecificationsCc c im k thut ca mt b nh in hnh nh sau Dung lng lu tr: S lng bit / byte hoc t n c th lu tr Thi gian truy cp b nh (c truy cp v vit truy cp): bao lu b nh cn ti cc d liu trn cc dng d liu ca n sau khi n c gii quyt hoc lm th no n c th nhanh chng lu tr d liu khi c cung cp thng qua ng dy d liu ca n. S kt ni ny ca thi gian truy cp b nh c gi l b nh.

Bandwidth Bng thng.Tiu th in v in p Levels: Tiu th in nng l yu t chnh trong cc h thng nhng. Cc t hn l tiu th in nng nhiu hn l ng gi mt . Kch thc: Kch thc c lin quan trc tip n vic tiu th in nng v dung lng lu tr d liu.

C hai thng s k thut quan trng i vi b nh xa nh thi gian thc H thng nhng c lin quan.- Kh nng Ghi- Hiu sut lu tr

Write abilityy l cch thc v tc m mt b nh c bit c th c ghi Phm vi ca kh nng ghi - Cao cp B x l ghi vo b nh n gin v nhanh chng nh RAM - Phm vi Trung B x l ghi vo b nh, nhng chm hn v d nh, FLASH, EEPROM (in Xa c v lp trnh b nh ch c) - Phm vi thp hn thit b c bit, "lp trnh", phi c s dng ghi vo b nh v d: EPROM, OTP ROM (Mt TimeProgrammable Read Only Memory) - Cui thp bit c lu tr ch trong ch to v d, Mask-ROM lp trnh B nh lp trnh trong h thng- C th c vit bi mt b vi x l trong cc h thng nhng s dng b nh - B nh cao cp v tm trung ca kh nng ghi

Storage permanence- lu gi lu:N l kh nng gi cc bit c lu tr. Phm vi lu tr - Cao cp bn cht khng bao gi mt bit v d, mt n lp trnh ROM - Phm vi Trung gi bit ngy, thng, hoc nm sau khi ngun in ca b nh tt v d, NVRAM - Phm vi thp hn gi bit min l in cung cp cho b nh v d, SRAM - Cui thp bt u mt bit gn nh ngay lp tc sau khi vit v d, DRAM b nh n nh - Gi bit sau khi in khng cn c cung cp - Cao cp v tm trung ca lu tr lu

III. Common Memory Types

Read Only Memory (ROM)y l mt b nh n nh, N ch c th c c t nhng khng c ghi vo, bi mt b x l trong mt h thng nhng, Thng ghi vo, "lp trnh", trc khi chn vo h thng nhngs dng:- Chng trnh ca hng phn mm cho b x l c mc ch chung hng dn chng trnh c th l mt hoc nhiu t ROM- Lu tr d liu lin tc theo h thng- Thc hin cc mch t hp

Implementation of Combinatorial Functions(Thc hin chc nng t hp)Bt k mch t hp ca n chc nng ca cng mt bin k c th c thc hin vi 2 ^ (k) x n ROM. u vo ca cc mch t hp l a ch ca a im ROM. u ra l t c lu tr ti a im .

Mask-programmed ROM(Mt n lp trnh ROM )Cc kt ni "lp trnh" ti ch to. H l mt tp hp cc mt n. N c th c vit ch mt ln (trong nh my). Nhng n lu d liu cho bao gi ht. Do n c tnh lu di lu tr cao nht. Cc bit khng bao gi thay i tr khi b h hng. Chng thng c s dng cho cc thit k cui cng ca h thng m lng cao.

OTP ROM: One-time programmable ROMCc kt ni "lp trnh" sau khi sn xut bi ngi s dng. Ngi s dng cung cp cc ni dung tp tin mong mun ca ROM. Cc tp tin u vo cho my c gi l ROM lp trnh vin. Mi kt ni c th lp trnh l mt cu ch. Cc lp trnh vin ROM thi cu ch, ni kt ni khng nn tn ti. Kh nng ghi rt thp: thng vit ch mt ln v yu cu ROM thit b lp trnh vnh cu lu tr rt cao: bit khng thay i tr khi kt ni li lp trnh v nhiu hn na cu ch thi Thng c s dng trong sn phm cui cng: r hn, kh khn hn v tnh sa i

EPROM: Erasable programmable ROMNy c gi l lp trnh xa c b nh ch c. Cc thnh phn lp trnh l mt bng bn dn MOS. Bng bn dn ny c mt "ni" ca bao quanh bi mt cht cch in. Nhng chi ph tiu cc to thnh mt knh gia cc ngun v mng lu tr mt logic 1. in p tch cc ln ti ca gy ra in tch m di chuyn ra khi knh v b mc kt trong ca ni lu tr mt logic 0.The (Erase) Shining tia UV trn b mt ni ca khu gy ra in tch m quay tr li knh t cng ni khi phc li logic 1. Mt gi EPROM hin th ca s thch anh qua nh sng tia cc tm c th vt qua. EPROM c Kh nng ghi tt hn - C th c xo hon ton v lp trnh li hng ngn ln vnh cu lu tr Gim - Chng trnh ko di khong 10 nm nhng d b bc x v ting n in Thng thng c s dng trong pht trin thit k

EEPROMEEPROM cn c bit n nh Electrically Erasable v chng trnh b nh ch c. N c xa bng cch s dng in p cao hn bnh thng. N c th lp trnh v xa cc t ring bit khng ging nh EPROMs ni tip xc vi nh sng tia cc tm xa tt c mi th.N c:Kh nng ghi tt hn- C th l trong h thng lp trnh c xy dng vi mch cung cp cao hn in p bnh thng tch hp b iu khin b nh thng c s dng n thng tin chi tit t ngi s dng b nh- ghi rt chm do ty xo v lp trnh "bn rn" pin ch x l EEPROM vn ghi- C th c xo hon ton v lp trnh hng chc ngn ln lu tr vnh cu Tng t nh EPROM (khong 10 nm) Vin thun tin hn EPROMs, nhng t hn.

Flash MemoryN l mt phn m rng ca EEPROM n l mt phn m rng ca EEPROM. N c nguyn tc cng ni v cng kh nng ghi v lu tr vnh cu. N c th c xo hon ton vi tc nhanh khi tc l ln b nh b xa cng mt lc, ch khng phi l mt t ti mt thi im. Cc khi thng vi ngn byte ln Vit cho nhng t n l c th chm hn- Ton b khi phi c c, t cp nht, sau ton b khi ghi tr li c s dng vi cc h thng nhng cc mc lu tr d liu ln trong b nh khng bay hi- V d, my nh k thut s, truyn hnh hp set-top, in thoi di ng

RAM: Random-access memoryL b nh khng n nh- Bit khng c gi nu khng cung cp nng lng. c v ghi vo d dng bng h thng nhng trong qu trnh thc hin. Cu trc bn trong phc tp hn ROM- Mt t bao gm mt s nh, mi nh 1 bit- Mi u vo v u ra dng d liu kt ni vi mi trong ct ca n- Rd / WR kt ni vi mi - Khi hng c kch hot bi b gii m, mi c logic m cc ca hng u vo bit d liu khird / WR ch ghi hoc kt qu u ra c lu tr cht khi rd / WR ch c

Basic types of RAMa. SRAM: Static RAM- nh s dng flip-flop lu tr bit- Yu cu 6 transistor- Gi d liu min l ngun in cung cp

b. DRAM: Dynamic RAM - nh s dng bng bn dn MOS v t in lu tr cc bit - Nh gn hn SRAM - "Lm mi" cn thit do t in r r

c. t c lm mi khi c - Tc lm mi in hnh 15,625 microsec. - Chm hn truy cp hn SRAM

Ram variationsa. PSRAM: Pseudo- static RAM DRAM c xy dng vi b iu khin lm mi b nh. Tnh ph bin chi ph thp mt cao thay th cho SRAM.b. NVRAM: Nonvolatile RAM Gi d liu sau khi ngun in bn ngoi b loi b Pin-h tr b nh RAM Ghi nhanh nh ln c Khng c gii hn v s lng ghi khng ging nh nn n nh b nh ROM

c. SRAM vi EEPROM hoc flash Lu ni dung b nh RAM y v EEPROM hoc flash trc in.

IV. Example: HM6264 & 27C256 RAM/ROM devicesThit b b nh dung lng thp chi ph thp Thng c s dng trong cc h thng nhng vi iu khin da trn 8-bit hai ch s u tin ch ra s loi thit b - RAM: 62 - ROM: 27 ch s tip theo cho thy nng lc kilobits

V. Example: TC55V2325FF-100 memory deviceThit b 2-megabit b nh SRAM ng b pipelined c thit k c giao tip vi b vi x l 32-bit C kh nng nhanh chng tun t c v vit cng nh byte I / O

VI. Composing memoryKch thc b nh cn thit thng khc vi kch thc ca b nh c sn Khi b nh c sn l ln hn, ch n gin l b qua bit a ch bc cao khng cn thit v cc dng d liu cao hn Khi b nh c sn l nh hn, nhiu b nh nh hn vo mt b nh ln hn- Kt ni side-by-side tng chiu rng ca t - Kt ni trn xung di tng s lng t thm dng a ch cao la chn b nh nh hn c cha t mun tms dng mt b gii m- Kt hp k thut tng s lng v chiu rng ca tLesson 6: Memory II._CHAUI. Phn cp b nh Mc tiu l s dng b nh nhanh v t tn km B nh chnh: b nh ln, chm, t tn km cha d liu v chng trnh trn vn. Cache (b nh m): B nh nhanh, nh, tn km cha bn sao ca cc phn c kh nng truy cp ca cc b nh ln hn. Cache c th c nhiu cp

II. Cache Thng c thit k vi SRAM: nhanh hn nhng t hn DRAM (qu nhanh qu tn tin :3)Thng trn cng chip vi b x l Khng gian b gii hn, nh hn rt nhiu so vi b nh chnh off chip (off chip main memory) Truy cp nhanh hn (1 cycle vs nhiu cycles ca b nh chnh) S hot ng ca b nh cache Yu cu truy nhp vo b nh chnh Kim tra b nh cache cho bn sao Cache hit: bn sao ang trong b nh cache, truy cp nhanh Cache miss: bn sao khng c trong b nh cache. c a ch v cc thnh phn c lin quan vo b nh cache Nhng la chn thit k b nh cache: cache mapping, replacement policies, and write techniquesIII. Cache mapping Cn thit v a ch b nh cache cn trng t hn b nh. Ni dung cha trong a ch c trong b nh cache? Cache mapping dng gn a ch b nh chnh vo b nh cache v xc nh bn sao c trong b nh khng (hit or miss). C 3 phng php c bn: Direct mapping (lp bn trc tip) Fully associative mapping (lp bn lin kt y ) Set-associative mapping (thit lp bn lin kt) B nh cache phn vng vo cc khi khng th chia c hoc line ca a ch b nh lin k: thng c 4 n 8 a ch mi tuyna. Direct mapping a ch b nh chnh uc chia thnh 2 vng: Index (ch s): gm c: a ch b nh cache S bit c xc nh bi kch thc b nh cache Tag (th): c so snh vi th lu tr trong b nh cache ti a ch c ch nh bi ch s Nu th ging nhau, nh du hp l Valid bit (bit hp l): ch ra nu d liu trong slot c ti t b nh Offset: dng tm word no n trong dng b nh cache

b. Fully associative mapping Lu tr hon ton a ch ca b nh chnh trong mi a ch ca b nh cache Tt c cc a ch c lu tr trong b nh cache c so snh ng thi vi a ch c yu cu. Bit hp l v offset nh l nh x trc tip

c. Set-associative mapping Kt hp gia direct mapping v fully associative mapping Ch s index ging nh ca direct mapping Nhng mi a ch b nh cache cha ni dung v cc th ca 2 v tr a ch b nh tr ln Th (tag) c thit lp so snh ng thi ging nh trong Fully associative mapping B nh cache vi kch thc N c gi l N way set associative: 2, 4, 8 way ph bin

IV. Cc nguyn tc thay th b nh cache Phng php chn block no s b thay th Khi b nh cache c lin kt hon ton th y Khi cc tuyn ca b nh cache c thit t kt hp (set associative) Direct mapped cache has no choice (b nh cache b nh x trc tip) Ngu nhin: block b chn thay th ngu nhin LRU: least recently used: block c s dng t nht b thay th FIFO: Cho block vo hng i khi c s dng Chn block b thay th bng cch y hng iV. Phng php ghi ln b nh cache D liu b nh m phi cp nht t b nh chnh khi c ghi (write - through) Ghi hon ton Ghi ln b nh chnh bt c khi no b nh m c ghi Thc hin d dng nht B x l phi ch b nh chnh ghi potential for unnecessary writes hi li (write - back) b nh chnh ch c ghi khi cc khi c thay th Thit lp thm dirty bit m rng cho mi block khi cc khi b nh m c ghi Gim s lng b nh chnh chm phi ghiVI. nh hng ca b nh m m hiu sut h thng nhng gi tr quan trng nht lin quan n hiu nng: kch thc b nh cache tng s byte d liu m b nh m c th cha khng bao gm th, bit hp l v cc bit gi nh (house keeping bits) trong tng trn mc kt hp kch thc khi d liu b nh m ln, th t l ht thp (tc l t l n tm thy ci cn tm trong b nh cache cao), nhng chi ph truy nhp li cao hn

VII. Cache Performance Trade-Offs (tha hip nng sut b nh m) Tng t l hit m khng tng kch thc Tng kch thc line Thay i thit t kt hpVIII. RAM ci tin (advanced RAM) DRAM thng c s dng nh l b nh chnh trong b vi x l da trn h thng nhng Dung lng ln, chi ph thp Nhiu bin th ca DRAM c xut: Cn phi gi n nh nhp vi tc ca b x l FPM DRAM: fast page mode DRAM EDO DRAM: extended data out DRAM (d liu m rn gra DRAM) SDRAM/ESDRAM: b nh DRAM ng b v DRAM ng b nng cao RDRAM: rambus DRAMIX. B nh DRAM c bn Bus a ch dn knh gia thnh phn hng v ct a ch hng v ct b cht lin tc bi cc tn hiu strobing ras (row address strobe) (xung a ch dng) v cas (xung a ch ct)(AbbreviatedRAS, a signal, orstrobe, sent by theprocessorto a DRAMcircuit to activate a row address. DRAM stores data in a series of rows and columns, similar in theory to a spreadsheet, and each cell where a data bit is stored exists in both a row and a column. A processor uses RAS andCAS(column address strobe) signals to retrieve data from DRAM. When data is needed, the processor activates the RAS line to specify the row where the data is needed, and then activates the CAS line to specify the column. Combined, the two signals locate the data stored in DRAM.) Lm ti mng in ca DRAM (DRAM device) c th thc hin t bn trong hoc ngoi Xung a ch b nh nhy thng xuyn theo chu k c th lm cho ni dung nh b refresh Lm ti mng in b tt trong qu trnh ghi v c

a. Fast Page Mode DRAM (FPM DRAM) Mi hng ca mng bit b nh uc xem nh l mt trang Trang cha nhiu word Nhng word ring l c gi bi a ch ct Gin nh thi a ch row (hoc page) c gi i 3 word c lin tc bng vic gi a ch ct cho mi word

b. Extended data out DRAM (EDO DRAM) L ci tin ca FPM DRAM C thm cht trc b m output Cho php xung ca cas trc khi vic c d liu hon tt Gim tr ca vic c/ghi bi chu k b sung

c. (S)ynchronous and Enhanced Synchronous (ES) DRAM SDRAm cht d liu trn cnh tch cc ca xung clock Khng mt thi gian d tn hiu ras/cas v rd/wr (read/write) Mt b m c khi to n a ch ct sau c tng ln khi xung clock tch cc truy cp v tr cc vng nh lin tip ESDRAM ci thin hn SDRAM Thm b m cho php chng lp vo a ch ct Faster clocking v gim tr c th xy ra ca vic c hoc ghi

d. Rambus DRAM (RDRAM) Cu trc giao din Bus nhiu hn DRAM D liu b cht c cnh ln v xung ca xung clock Chia thnh 4 bank c b gii m hng ring C th m 4 page cng lc Thng lng caoX. Vn tch hp DRAM SRAM d dng tch hp ln chip nh b x l DRAM th kh hn Qu trnh to chip khc nhau gia DRAM v mch logic thng thng Mc ch ca ngi thit k mch logic thng thng: Gim thiu nhiu gim s tr khi truyn tn hiu v hao tn in nng Mc ch ca ngi thit k DRAM To t in lu tr thng tin S tch hp bt u xut hinXI. Memory Management Unit (MMU) (n v qun l b nh) Nhim v ca MMU Refresh DRAM, giao din v phn x bus Qun l vic chia s b nh gia nhiu b x l Dch a ch b nh lun l ca b x l sang a ch b nh vt l ca DRAM CPU hin i thng c MMU sn B x l n mc ch c th c s dngLesson 12 Memory Interfacing_CHAUI. Intro

Hnh bn ch ra cu trc bn trong ca mt b vi iu khin c c RAM v ROM. Thng th nhng b vi iu khin khng yu cu b nh ngoi cho cc tc v n gin. di chng trnh tr nn ngn i (The program lengths being small) c th d dng va vn bn trong b nh trong. V vy, n thng ch cung cp cc gii php n chip. Tuy nhin, s lng b nh trong khng th tng ln khng kim sot, bi v: nhu cu tiu th in nng v kch thc.

Tng b nh lm cho in nng tiu th nhiu hn v v vy nhit s tng ln. Ngoi ra, kch thc cng phi tng ln c th cha c b nh b sung (additional memory). S cn thit tng dung lng b nh pht sinh trong mt s ng dng c th. Hnh bn di cho thy s khi c bn ca b nh ghp ni vi mt b x l.

II. B nh m rng ghp ni vi h PIC18F8XXX ca b vi iu khin

H vi iu khin trn c th c c b nh on chip v off chip. i khi b nh on chip l mt loi flash lp trnh c. Mt thanh ghi c bit bn trong b vi iu khin c th c lp trnh (bng cch ghi 1 s 8 hoc 16 - bit) s dng b nh ngoiaf trong cc ch khc nhau. Trong h PIC cc ch sau l kh dng:a. Ch vi iu khin B vi x l ch truy cp vo b nh flash on chip. Chc nng giao din b nh ngoi b tt i. C gng c maf vt qua gii hn vt l ca flash on chip s khin c ra ton b bit 0.b. Ch vi x l B x l cho php thi hnh v truy cp ch qua b nh chng trnh ngoi. Ni dung ca b nh flash on chip b cm.c. Ch vi x l vi khi khi ng (boot block) (MBB) B x l truy nhp b nh flash on chip nhng ch bn trong khi khi ng. Kch thc ca khi khi dng ph thuc vo thit b v c t v tr u ca b nh chng trnh. Ngoi khi khi ng. B nh chng trnh ngoi c truy cp n gii hn 2 Mbyte. Khi chng trnh thc thi s t ng chuyn i gia 2 b nh nh yu cu.d. Ch vi iu khin m rng B x l truy nhp c b nh chng trnh trong ln ngoi nh l mt khi n. Thit b c th truy nhp ton b b nh flash on chip ca n, v cp nh trn, thit b truy nhp b nh chng trnh ngoi ln n gii hn 2 MByte khng gian chng trnh, v cng ging nh ch MBB, khi thc thi s t chuyn i gia 2 b nh nh yu cu.

3. Processor

Lesson 8: General Purpose Processors I Vi x l a dng_NGOC_CUONG

I. Kin trc- Vi x l c 12 tng kin trc pipeline: I,B,V,FS, W.- Pipeline: l 1 c im rt quan trng ca vi x l a dng hin i. 1 chng trnh l 1 tp cc lnh c lu trong b nh. Trong qu trnh thc thi, vi x l s np cc lnh t b nh, gii m & thc thi chng. Tin trnh ny mt 1 vi chu k my. tng tc x l, vi x l c chia thnh nhiu khi khc nhau. Trong khi 1 khi np lnh t b nh, 1 khi khc gii m & 1 khi khc thc thi chng. gi l pipeline. iu ny c th c gi l phn chia 1 khi chc nng, do n c th tip nhn cc ton hng mi trong mi chu k, trong khi tng thi gian thc hin lnh c th mt nhiu chu k. - 12 tng pipeline ny c chia thnh 4 nhm: I-fetch, gii m & dch, thc thi & data cache.+ I-fetch: ly cc byte lnh t I-catch ln hay t bus ngoi.+ Gii m & dch: chuyn i cc byte lnh thnh cc form thc thi ni b.+ Thc thi: kim sot vic thc hin & ngng thc hin cc lnh ni b.+ Data cache: qun l hiu qu ca vic ti & lu d liu thc thi n & i t cc cache, bus & cc phn t ni.

- Chi tit cc nhm nh sau:

1. I-fetch (Instruction Fetch Unit): - 3 tng pipeline u tin (I,B,V) cung cp cc d liu lnh ph hp t I-cache (Instruction Cache) hoc bus ngoi ti cc b m gii m lnh (instruction decode buffers). I-cache chnh bao gm 64 KB c t chc nh 4 chiu thit lp lin kt vi cc dng 32-byte. Cc lin kt ln I-TLB (translation look-aside buffer ) cha 128 mc c t chc nh 8 chiu thit lp lin kt.- TLB (translation look-aside buffer): l 1 bng trong b nh ca vi x l cha cc thng tin v cc trang ca b nh c truy cp gn y nht. Bng ny tham chiu cho a ch o ca chng trnh vi cc a ch tuyt i tng ng trong b nh vt l m chng trnh s dng gn y nht. TLB gip tnh ton nhanh hn v n cho php vic x l a ch din ra c lp vi pipeline dch a ch bnh thng (normal address-translation pipeline)- D liu lnh s c tin-gii m khi chng ra khi cache. Qa trnh tin-gii m ny chng cho vi cc php ton khc, nn khng tn thi gian. Cc d liu lnh np c t tun t vo nhiu b m. 2. Instruction Decode Unit khi gii m lnh- Cc byte lnh s c gii m & dch thnh nh dng ni b bi 2 tng pipeline F &X.- Tng F gii m & formats lnh thnh 1 nh dng trung gian. Cc lnh nh dng ni (the internal-format instructions) c t trong 1 hng i five-deep FIFO (FIQ).

- Tng X dch lnh dng trung gian t FIQ thnh nh dng vi lnh ni (the internal microinstruction format). Np, gii m & dch lnh c thc hin bt ng b thng qua hng i five-entry FIFO (XIQ) gia b dch v khi thc thi.3. Branch Prediction d on r nhnh- BHT (Branch History Table) Bng lch s r nhnh & BTB (Branch Target Buffer) B m mc tiu r nhnh.- Chng trnh thng gi cc chng trnh con c lu tr ti cc v tr khc nhau trong b nh. Thng thng, c ch np lnh s np trc lnh & gi chng trong cc b nh cache ti nhng tng khc nhau & gi chng i gii m. Trong trng hp ca 1 r nhnh, tt c cc lnh nh vy cn phi b loi b & tp cc m lnh mi t cc chng trnh con tng ng s c np. D on ca r nhnh trc trong pipeline c th tit kim thi gian thc hin lnh hin ti & ly lnh k tip. D on r nhnh l 1 k thut c gng suy ra cc a ch lnh k tip thch hp m ch bit lnh hin ti. Thng thng n s dng 1 BTB - 1 b nh lin hp nh, theo di ch s cache lnh & c gng d on ch s no s c thc thi k tip, da trn lch s r nhnh c lu ti 1 tp b m gi l BHT. Vic ny c thc hin ti tng F.4. Integer Unit khi kiu s nguyn- Tng gii m (R): cc vi lnh c gii m, cc tp thanh ghi kiu s nguyn c truy cp & cc ti nguyn ph thuc c nh gi.- Tng nh a ch (A): cc a ch b nh c tnh ton & gi n D-cache (Data cache)- Tng truy cp cache (D,G): D-cache & D-TLB (Data Translation Look aside Buffer) c truy cp & sp d liu ti quay li cui tng G.- Tng thc thi (E): cc php ton kiu s nguyn ALU c thc hin. Tt c cc hm ALU c bn c thc hin trong 1 chu k ngoi tr php nhn & chia.- Tng lu tr (S): d liu lu tr kiu s nguyn c ly ti tng ny & c t ti 1 b m lu tr.- Tng hi m / ghi li (W): kt qu ca cc php ton c chuyn vo tp thanh ghi.5. Data-cache & Data path - D-cache chnh bao gm 64 KB c t chc nh 4 chiu thit lp lin kt vi cc dng 32-byte. Cc lin kt ln D-TLB (translation look-aside buffer ) cha 128 mc c t chc nh 8 chiu thit lp lin kt.- Cache, TLB, & cache th mc trang u s dng 1 LRU-gi (Least Recently Used) thay th thut ton.

6. L2-Cache Memory - Cache L2 ti bt k thi im no cng khng nm trong cache L1. Cc line c di di t cc cache L1 (do cc dng mi c a vo t b nh) s c t ti cache L2. Do , cc dng di di b l L1-cache trong tng lai c th c p ng bng cch tr li dng t cache L2 thay v phi truy cp t b nh ngoi.

7. FP, MMX and 3D- FP: Floating Point Processing Unit khi x l du chm ng.- MMX: Multimedia Extension or Matrix Math Extension Unit khi a phng tin m rng hay ma trn ton m rng.- 3D: Special set of instructions for 3D graphics capabilities tp lnh c bit cho ha 3D

- Ngoi cc khi thc thi s nguyn, cn c 1 khi thc thi s du chm ng 80-bit ring r, c thc hin cc lnh trn s du chm ng song song vi cc lnh trn s nguyn. Cc lnh du chm ng c x l qua cc tng s nguyn R,A,D & G. Cc lnh du chm ng c truyn t pipeline s nguyn ti khi FP thng qua hng i FIFO. Hng i ny chy vi tc ca b x l, tch ring cc khi hot ng chm hn FP t pipeline s nguyn, do , pipeline s nguyn c th x l cc lnh chng cho vi cc lnh FP. Cc lnh s hc du chm ng n gin (+,-,*,/, cn bc 2, so snh) c biu din bi 1 lnh du chm ng ni b n. Mt s cc lnh du chm ng t dng & phc tp (sin, tan..) c thc hin trong cc microcode & c biu din bi 1 stream di cc lnh n t ROM. Cc lnh ny s lm tc nghn pipeline lnh s nguyn, vic tnh ton trn s nguyn khng th c x l cho n khi cc lnh ny hon tt.- B x l cha 1 khi thc thi ring r cho cc lnh tng thch MMX. Cc lnh MMX c thc thi qua cc tng R,A,D & G. 1 lnh MMX c a vo khi MMX mi chu k. B nhn MMX l 1 pipeline y & c th bt u 1 lnh nhn MMX c lp (bao gm ti 4 php nhn ring l) mi chu k. Cc lnh MMX khc thc thi trong 1 chu k. Php nhn c theo sau bi lnh MMX ph thuc cn 2 chu k. V kin trc, cc thanh ghi MMX ging vi cc thanh ghi du chm ng. Tuy nhin, thc ra chng l 2 tp thanh ghi khc nhau (1 trong khi FP & 1 trong khi MMX), chng c gi ng b bi phn cng.- C 1 khi thc thi ring cho 1 s lnh 3D. Cc lnh ny h tr chuyn i ha thng qua SIMD (Single Instruction Multiple Data lnh n a d liu ) mi , du chm ng chnh xc n. Cc m lnh ny c x l qua cc tng R,A,D &G. 1 lnh 3D c chuyn vo khi 3D mi chu k. Khi 3D c 2 b nhn du chm ng chnh xc n & 2 b cng du chm ng chnh xc n. Cc lnh khc nh chuyn i, nghch o c cung cp. B nhn & b cng l pipeline y v c th bt u cc lnh 3D c lp mi chu k.

Tm tt

Kin trc ca b x l a dng c cc c im sau:- Pipeline nhiu tng- B nh cache c nhiu cp- C ch d on r nhnh ti nhng tng u ca pipeline - Cc khi x l ring r & c lp (s nguyn, du chm ng, MMX, 3D)- Bi v s lin kt khng chc chn vi r nhnh nn thi gian thc thi tt c cc cu lnh l khng c nh. V th n khng thch hp cho 1 s ng dng thi gian thc.- X l cc tp lnh rt phc tp- Tiu tn nhiu nng lng v b x l c phc tp cao.

Lesson 10: Embedded Processors I Cc b x l nhng I_NGOC_CUONG

I. Gii thiuKhc nhau gia vi iu khin & vi x l a dng:- Vi iu khin thng lin quan vi cc h thng nhng.- Vi x l thng lin quan ti my tnh- Vi iu khin c cu trc b nh n gin hn, vd RAM & ROM tn ti trn cng 1 chip & thng th khng c b nh cache.- Tiu t nng lng & tng nhit ca vi iu khin c gim thiu v s rng buc v kch thc vt l.- Vi iu khin 8bit & 16 bit rt ph bin vi cc thit k n gin hn so vi cc vi iu khin a dng phc tp 32 hay 64bit.Tuy nhin, th phn ca cc b x l nhng 32-bit ang tng ln.

The Architecture of a Typical MicrocontrollerKin trc ca 1 vi iu khin in hnh- PTS: Peripheral Transaction Server - my ch giao tip ngoi vi- I/O: Input/Output Interface- EPA: Event Processor Array mng b x l s kin- PWM: Pulse Width Modulated Outputs- ch iu rng xung u ra - WG: Waveform Generator b to dng sng- A/D- Analog to Digital Converte

- FG: Frequency Generator b to tn s- SIO: Serial Input/Output Port port vo/ra ni tipNhn ca vi iu khin bao gm khi x l trung tm (CPU) & b iu khin b nh. CPU cha tp thanh ghi & khi thanh ghi ton hc- logic (RALU). 1 bus ni 16-bit kt ni CPU vi b iu khin b nh & b iu khin ngt. Phn m rng ca bus ny kt ni CPU vi cc module thit b ngoi vi. 1 bus ni 8-bit chuyn cc byte lnh t b iu khin bnn n thanh ghi lnh trong RALU.

- Master PC: Master Program Counter: b m chng trnh cp cao- PSW: Processor Status Word: trnh trng b x l - SFR: Special Function Registers: cc thanh ghi chc nng c bit.

1. CPU control- CPU c kim sot bi cc cng c microcode, m ch th RALU thc hin cc php ton s dng bytes, words hay double-words t tp thanh ghi thp 256-byte hay thng qua 1 ca s trc tip truy cp cc tp thanh ghi cao. Ca s l 1 k thut m cc khi bn ca cc tp thanh ghi cao hn vo trong 1 ca s trong cc tp thanh ghi thp hn. Cc lnh CPU di chuyn t hng i np trc 4-byte trong b iu khin b nh vo thanh ghi lnh ca RALU. Cng c microcode gii m cc lnh & sau to ra 1 chui cc s kin gy ra cc chc nng mong mun. 2. Register file - Tp thanh ghi - Tp thanh ghi c chia thnh file cao & file thp. Trong tp thanh ghi thp, 24 byte thp c phn b cho cc thanh ghi chc nng c bit ca CPU - CPUs special-function registers (SFRs) & con tr stack, trong khi phn cn li cho thanh ghi RAM a dng. Tp thanh ghi cao ch cha thanh ghi RAM a dng. Thanh ghi RAM c th c truy cp bi bytes, words hay double words. B RALU truy cp cc tp thanh ghi cao & thp theo cc cch khc nhau. Tp thanh ghi thp lun c th truy cp trc tip vi ch nh a ch trc tip. Tp thanh ghi cao c truy cp trc tip vi ch nh a ch trc tip ch khi c ch ca s (windowing) c bt.3. Register Arithmetic-logic Unit (RALU) - Khi thanh ghi ton hc-logic- RALU cha cng c microcode, b ton hc logic 16-bit (ALU), b m chng trnh cp cao (PC), t trng thi b x l (PSW), & 1 vi thanh ghi. Cc thanh ghi trong RALU l cc thanh ghi s nguyn, 1 hng s nguyn, 1 thanh ghi chn bit, 1 b m vng lp & 3 thanh ghi tm (the upper-word, lower-word, and second-operand registers). PSW cha 1 bit PSW.1 cho php hoc cm tt c cc ngt, 1 bit PSW.2 cho php hoc cm PTS (Peripheral Transaction Server) & 6 c Boolean phn nh trng thi ca chng trnh. Tt c thanh ghi, ngoi tr thanh ghi chn bit 3-bit & b m vng lp 6-bit, u l 16 hoc 17 bit (16 bit cng vi 1 phn m rng du). 1 s thanh ghi c th gim ti khi lng cng vic ca ALU bng cch thc thi nhng php ton n gin. - RALU dng cc thanh ghi cao & thp cng nhau cho cc lnh 32-bit & dng c thanh ghi tm cho nhiu lnh. Cc thanh ghi ny c shift logic ca ring chng & c s dng cho cc php ton cn dch logic nh chun ha, nhn & chia. B m vng lp 6-bit m cc qu trnh dch lp i lp li. Thanh ghi ton hng th 2 lu ton hng th 2 cho cc lnh 2 ton hng. Xuyn sut php ton tr, output ca thanh ghi ny l phn b trc khi n c chuyn vo b ALU. RALU tng tc tnh ton bng cch lu cc hng s trong cc thanh ghi hng, do , chng lun sn sng khi tnh phn b, tng hay gim cc byte hay word. Hn na, thanh ghi hng cn xc nh mt n (mask) n bit, da trn thanh ghi chn bit, cho cc lnh kim tra bit.4. Code Execution Thc thi m - RALU thc hin hu ht cc tnh ton cho vi iu khin, nhng n khng dng b tch ly. Thay vo n thc thi trc tip trn tp thanh ghi thp, v c bn cung cp 256 b tch ly. V d liu khng i qua b tch ly n, code ca vi iu khin s thc thi nhanh hn & hiu qu hn.5. Instruction Format nh dng lnh- Cc vi iu khin ny kt hp cc thanh ghi a dng vi nh dng lnh 3 ton hng. nh dng ny cho php lnh n nh r 2 thanh ghi ngun & tch ring thanh ghi ch. 6. Memory Interface Unit Khi giao tip b nh - RALU giap tip vi tt c b nh, ngoi tr tp thanh ghi & ngoi vi SRFs, thng qua b iu khin b nh. B iu khin b nh cha hng i np trc, b m chng trnh slave (slave PC), thanh ghi d liu & a ch & b iu khin bus. B iu khin bus kim sot bus b nh, bao gm 1 bus b nh ni & cc bus a ch/d liu ngoi.B iu khin bus nhn yu cu truy cp b nh t RALU hoc hng i np trc; hng i lun c s u tin.- Khi b iu khin bus nhn yu cu t hng i, n np code t a ch cha trong slave PC. Slave PC lm tng tc thc thi v byte lnh k tip sn sng ngay lp tc & b x l khng cn i t master PC gi a ch ti b iu khin b nh. Nu 1 lnh ngt, gi hay tr v lm thay i chui a ch, master PC ti a ch mi vo slave PC, sau CPU tip tc x l.7. Interrupt Service Phc v ngt- H thng x l ngt c 2 phn t chnh: b iu khin ngt kh trnh (the programmable interrupt controller) & my ch giao tip ngoi vi (PTS). B iu khin ngt kh trnh c 1 chng trnh u tin phn cng c th thay i bng phn mm. Cc ngt i qua b iu khin ngt u c phc v bi c ch x l ngt . PTS l b x l ngt phn cng microcode, cung cp qu trnh x l ngt hiu qu.8. Internal Timing Thi gian ni- Mch clock nhn tn hiu clock u vo trn XTAL1 c cung cp bi thch anh ni hoc b dao ng & chia tn s. B to clock nhn tn s u vo c chia t mch divide-by-two & to ra 2 tn hiu thi gian ni khc nhau: Phase 1 (PH1) & PH2. Cc tn hiu ny tch cc mc cao.- Cnh ln ca PH1 & PH2 to ra tn hiu CLKOUT ni. Mch clock dn cc tn hiu clock ni ring bit ti CPU & cc ngoi vi cung cp tnh linh ng trong qun l nng lng. V s phc tp ca mch clock nn tn hiu trn chn CLKOUT l s delay ca tn hiu CLKOUT ni. Delay thay i theo nhit & in p.

9. I/O port- Cc chn I/O ring l c ghp li phc v nh l I/O chun hoc truyn dn cc tn hiu c chc nng c bit lin kt vi ngoi vi on-chip hay phn t off-chip. Nu tn hiu c chc nng c bit khng c s dng trong ng dng, chn lin quan c th c cu hnh ring l phc v nh 1 chn I/O. Port 3 &4 l ngoi l. Chng c iu khin cp port (port level). Khi b iu khin bus cn s dng bus a ch/data, n cn kim sot cc port. Khi bus a ch/data rnh ri, c th dng cc port cho I/O. Port 0 l port ch nhp, n cng l u vo analog cho b ADC.10. Serial I/O (SIO) Port Port I/O ni tip- Vi iu khin c 1 port I/O ni tip 2 knh, chng chia s cc chn vi port 1 & 2. Mt s phin bn ca vi iu khin c th khng c. Port I/O ni tip l port ng b/ bt ng b, bao gm 1 b truyn nhn ni tip bt ng b (UART). UART c 2 mode ng b (mode 0 & 4) & 3 mode bt ng b ( mode 1, 2, 3) cho c truyn & nhn.Cc mode bt ng b l song cng, ngha l chng c th truyn & nhn d liu cng 1 lc. B nhn l b m, nn vic tip nhn byte th 2 c th bt u trc khi byte u tin c c. B truyn cng l b m, cho php truyn lin tc. SIO port c 2 knh (channel 0 & 1) c cc tn hiu & thanh ghi ging nhau.11. Event Processor Array (EPA) and Timer/Counters - Mng x l s kin & timer/counter- The event processor array (EPA) thc thi cc chc nng u vo & u ra tc cao kt hp vi timer/counter. Trong ch input, EPA gim st input cho qu trnh chuyn i tn hiu. Khi 1 s kin xy ra, EPA ghi li gi tr thi gian lin kt vi n. y gi l nm bt s kin (capture event). Trong ch output, EPA gim st timer cho n khi gi tr ca n khp vi gi tr thi gian lu. Khi iu xy ra, EPA kch s kin u ra, n c th l set, clear hay cht chn output. y gi l so snh s kin. C capture and compare events u c th to ra ngt, c phc v bi b iu khin ngt hay PTS. Timer 1 & 2 l b timer/counter m ln/xung bit, c th dng xung ni hoc ngoi. Mi timer/counter c gi l timer nu l xung ni & gi l counter nu l xung ngoi.

12. Pulse-width Modulator (PWM) - B iu rng xung- Dng sng ng ra t mi knh PWM l xung duty-cycle. Mt s loi ng dng iu khin ng c in i hi mt dng sng PWM cho hu ht cc hot ng hiu qu. Khi c lc, dng sng PWM to ra 1 mc DC c th thay i trong 256 bc bng cch thay i duty cycle. S bc ca mi chu k PWM c th c lp trnh (8bit).13. Frequency Generator b to tn s- 1 s vi iu khin c b to tn s. Ngoi vi ny to ra sng vi duty cycle c nh l 50% & tn s c th lp trnh c (thay i t 4kHz n 1MHz vi 16 MHz input).14. Waveform Generator b to dng sng- 1 b to dng sng n gin ha cc nhim v to ng b, ng ra PWM. Dng sng ny c t u ha cho cc ng dng iu khin chuyn ng. 1 b to dng sng c th to ra 3 cp ng ra PWM b sung c lp, chng chia s 1 chu k, thi gian cht & ch hot ng thng thng. 1 khi n c khi to, b to dng sng hot ng , khng cn CPU can thip, tr khi thay i duty cycle.15. Analog-to-digital Converter b chuyn i A/D- B ADC chuyn i 1 in p u vo tng t thnh 1 gi tr s tng ng. phn gii l 8 hoc 10 bit. Thi gian ly mu & chuyn i c th lp trnh c.

Lesson 11 Vi x l nhng_NGOC_CUONGTn hiu ca 1 vkd thng thng: Tng quan v tn hiu ca dn vdk Intel MCS 96 Gii thiu Tn hiu in hnh ca mt vi iu khinI. Gii thiu: Vdk c kt ni cc thit b ngoi m khng cn qu nhiu giao din kt ni. Cc tn hiu vo ra bao gm c digital v analog. Data c th c truyn dc c hai song song v ni tip . Cc cp in p cng c th l khc nhau. Kin trc ca mt vi iu khin c bn c th hin trong hnh . 11.1. N minh ha cc module bn trong mt vi iu khin. B vi x l thng thng s c tn hiu Digital vo / ra , timer, ng ni vo/ra. Mt s loi vi iu khin cng h tr a knh ADC v DAC. Do tn hiu tng chn tn hiu ra/vo cng c mt trong cc n v vi iu khin. VDK h tr b nh, a ch ngoi cng nh cc ng d liu.

II. Cc ng tn hiu ca intel Msc96 ( ng mch! hc ci con qui ny lm g nh?)Cc n v khc nhau ca mt b x l MCS96 c hin th trong hnh . 11.2. Cc tn hiu ca mt b x l nh vyc th c chia thnh cc nhm sau

4. DMALesson 16: DMA - Direct Memory Access_DUONG

Mc tiu Sau khi hon thnh bi hc ny, sinh vin c th nm c: Khi nim ca DMA DMA c s dng khi no v u? Khi to mt chu k DMA nh th no? Mt b iu khin DMA (DMA controller) in hnh l g?

Tin quyt: in t S, Vi x l

I. Introduction Gii thiuDirect Memory Access (DMA) cho php cc thit b truyn d liu m khng c s chi phi ca b x l. Khi DMA din ra, b x l khng th thc hin cc tc v m c i hi truy cp bus, nhng n c th lm bt k cc tc v khc m khng yu cu truy cp bus. DMA l phn thit yu cho cc h thng nhng hiu sut cao - ni m cc khi d liu ln cn c truyn t cc thit b I/O ti/t b nh chnh. (Thm ch DMA l iu kin tin quyt cho cc my tnh h tr h iu hnh a nhim.)II. DMA Controller B iu khin DMAMt DMA Controller l mt thit b ngoi vi kt ni ti CPU c lp trnh thc hin mt chui truyn d liu (truyn theo th t) thay cho CPU. Mt DMA Controller c th trc tip truy cp b nh v c s dng truyn d liu t mt v tr ti mt v tr khc trong b nh, hoc t mt thit b I/O ti b nh v ngc li. Mt DMA Controller qun l mt vi knh DMA (DMA Channel), mi knh c th c lp trnh thc hin mt chui truyn d liu. Cc thit b, thng l cc ngoi vi I/O, khi mun truyn d liu (hoc mun nhn d liu), n phi gi yu cu (DMA request) ti DMA Controller thc hin DMA transfer. Mt tn hiu DMA request (yu cu DMA) cho mi knh DMA c nh tuyn ti DMA controller. Tn hiu ny c gim st v c p ng theo nhiu cch ging nh b x l x l ngt. Khi DMA nhn c DMA request, n p ng li bng cch thc hin mt hay nhiu DMA transfer t thit b I/O ti h thng b nh hoc ngc li. Cc knh DMA phi c cho php bi b x l cho DMA controller p ng li cc DMA request. S lng truyn, ch truyn, v v tr b nh c s dng ph thuc vo cch cc knh DMA c lp trnh. Mt DMA controller in hnh chia s bus b nh v I/O vi CPU v c c kh nng bus master v bus slaver. Hnh 16.1 cho thy kin trc DMA controller v cch DMA controller tng tc vi CPU.

Hnh 16.1 Kin trc DMA controllerTrong ch bus master, DMA controller nhn bus h thng (cc ng a ch, cc ng d liu, v cc ng iu khin) t CPU thc hin DMA transfer. Bi v CPU nh bus h thng trong khi DMA transfer din ra nn mt s tin trnh (process) thnh thong b b i do n yu cu truy cp bus h thng.Trong ch bus slaver, DMA controller c truy cp bi CPU, cc thanh ghi bn trong (cc thanh ghi ni) ca DMA controller c lp trnh thit lp DMA transfer. Cc thanh ghi ni gm thanh ghi a ch ngun, thanh ghi a ch ch v thanh ghi m s lng truyn cho mi knh DMA, cng nh thanh ghi iu khin v thanh ghi trng thi cho vic khi to, gim st, v duy tr thao tc ca DMA controller.II.1Cc kiu v ch DMA transferCc DMA controller c nhiu kin DMA transfer cng nh s knh DMA m chng h tr. 2 kiu DMA transfer l flyby DMA controller v fetch-and-deposit DMA transfer. 3 ch DMA transfer ph bin l truyn n l, truyn theo khi, v truyn theo yu cu.Kiu DMA transfer nhanh nht l single-cycle (1 chu k), single-address (1 a ch), hay flyby DMA transfer. Trong flyby DMA transfer, mt thao tc bus duy nht c s dng hon tt DMA transfer, vi d liu c t ngun v c ghi ti ch mt cch ng thi. Trong thao tc flyby, thit b yu cu dch v gi mt DMA request trn ng yu cu knh (channel request line) ph hp ca DMA controller. DMA controller p ng bng cch cp php iu khin h thng bus t CPU v sau a ra a ch b nh c lp trnh trc (pre-programmed). Mt cch ng thi, DMA controller gi mt tn hiu DMA acknowledge (xc nhn DMA) ti thit b yu cu DMA. Tn hiu ny bo cho thit b yu cu DMA li d liu ti h thng bus hoc cht d liu t h thng bus, ph thuc vo hng ca DMA transfer. Theo mt cch khc, mt flyby DMA transfer ging nh mt chu k c/ghi b nh vi DMA controller cung cp a ch v thit b I/O c/ghi d liu. Bi v flyby DMA transfer dng mt chu k b nh duy nht cho mi data transfer, nhng data transfer ny rt hiu qu. Hnh 16.2 cho thy giao thc tn hiu flyby DMA transfer.

Hnh 16.2 Flyby DMA transferKiu DMA transfer th 3 l dual-cycle, dual-address, flow-through, hay fetch-and-deposit DMA controller. Nh tn gi ca n, Kiu DMA transfer ny cn 2 chu k b nh hoc I/O. D liu bt u c truyn l ln c u tin t thit b I/O hoc b nh ti mt thanh ghi d liu tm bn trong ti DMA controller. D liu sau c ghi ti b nh hoc thit b I/O trong chu k tip theo. Hnh 16.3 cho thy giao thc tn hiu fetch-and-deposit DMA transfer.

Hnh 16.3 Fetch-and-deposit DMA transferBa ch DMA transfer ph bin nht l truyn theo single, truyn theo khi, v truyn theo yu cu. Ch truyn theo single truyn 1 gi tr d liu cho mi xc nhn DMA request. Ch ny l phng thc truyn chm nht v n yu cu DMA controller phn x bus h thng cho mi ln truyn. Vic phn x ny khng phi l vn trng tm trong mt h thng bus chu ti thp, nhng n c th dn n cc vn tr (latency) khi nhiu thit b ang s dng bus. Cc ch truyn theo khi v truyn theo yu cu lm gia tng thng lng h thng bng vic cho php DMA controller thc hin nhiu DMA transfer khi DMA controller c cp php s dng bus. i vi ch truyn theo khi, DMA controller thc hin ton b chui DMA c xc nh trc trong thanh ghi m s lng truyn tc nhanh nht c th p ng li mt DMA request duy nht t thit b I/O. i vi ch truyn theo yu cu, DMA contrller thc hin DMA transfer tc nhanh nht c th min l thit b I/O gi DMA request ca n. Khi thit b I/O nh DMA request ny, DMA transfer c dng li.II.2Hot ng ca DMA controlleri vi mi knh, DMA controller lu a ch c lp trnh v s lng truyn trong cc thanh ghi nn v duy tr cc bn sao thng tin trong thanh ghi m hin thi v trong thanh ghi a ch hin thi, nh trong hnh 16.1. Mi knh DMA c cho php v c v hiu ha thng qua mt thanh ghi mt n DMA. Khi DMA c bt u bng vic ghi ti cc thanh ghi nn v cho php (enable) knh DMA, cc thanh ghi hin thi c np t cc thanh ghi nn. Vi mi DMA transfer, gi tr trong thanh ghi a ch hin thi c li ti bus a ch, v thanh ghi a ch hin thi c t ng tng hoc t ng gim. Thanh ghi m hin thi xc nh s lng truyn cn li v c t ng gim sau mi ln truyn. Khi gi tr trong thanh ghi m hin thi chuyn t 0 sang -1, mt tn hiu chm dt m c to ra, n c ngha hon thnh chui DMA transfer. DMA controller thng to mt xung chm dt m trong chu k cui cng ca chui DMA transfer. Tn hiu ny c th c gim st bi thit b I/O tham gia vo DMA transfer. DMA controller yu cu lp trnh li khi mt knh DMA nhn c tn hiu chm dt m. V th, DMA controller yu cu mt s thi gian CPU (CPU time), nhng t hn so vi thi gian CPU cn phc v cc ngt t cc thit b I/O. Khi mt knh DMA nhn c tn hiu chm dt m, b x l c th cn lp trnh li b iu khin cho vic thm DMA transfer. Mt s DMA controller ngt b x l bt c khi no mt knh DMA chm dt truyn. DMA controller cng c cc c ch cho vic t ng lp trnh li mt knh DMA khi chui DMA transfer hon tt. Nhng c ch ny bao gm vic t ng khi to v mc ni b m. Tnh nng t ng khi to lp li chui DMA transfer bng cch np li cc thanh ghi hin thi ca knh DMA t cc thanh ghi nn im kt thc ca chui DMA transfer v cho php (enable) li knh ny. Mc ni b m hu ch cho vic vic truyn cc khi d liu vo cc vng b m khng lin tc hoc cho vic x l vic thu thp d liu c m gp i (doublebuffered data acquisition). Vi vic mc ni b m, mt knh ngt CPU v c lp trnh vi a ch tip theo v m cc thng s trong khi cc DMA transfer bt u c thc hin trn b m hin thi. Mt s DMA controller ti gin vic can thip ca CPU hn na bng cch c mt thanh ghi a ch chui (chain address register) tr ti mt bng iu khin chui (chain) trong b nh. DMA controller sau np cc thng s knh ca ring n t b nh. V tng qut, the more sophisticated the DMA controller, the less servicing the CPU has to perform.Mt DMA controller c mt hay nhiu thanh ghi trng thi c c bi CPU quyt nh trng thi ca mi knh DMA. Thanh ghi trng thi thng thng ch ra nu mt DMA request c xc nhn trn mt knh v nu mt knh nhn c tn hiu chm dt m. Vic c thanh ghi trng thi thng xa thng tin chm dt ngt trong thanh ghi, iu ny dn n cc vn khi nhiu chng trnh ang c gng s dng cc knh DMA khc nhau.Cc bc trong mt chu k DMA in hnh.1. B x l hon tt chu k bus hin thi v sau xc nhn tn hiu cp php bus cho thit b.2. Thit b xc nhn tn hiu ack cp php bus.3. B x l cm nhn s thay i theo trng thi ca tn hiu ack cp php bus v bt u lng nghe bus a ch v bus d liu i vi hot ng DMA.4. Thit b DMA thc hin truyn t a ch ngun ti a ch ch.5. Trong lc truyn, b x l theo di a ch trn bus v kim tra nu c bt k v tr no b thay i trong khi din ra cc hot ng DMA c cache trong b x l. Nu b x l pht hin mt a ch c cache trn bus, n c th thc hin 1 trong 2 thao tc:a. B x l hy b mc cache bn trong cho a ch m thc hin thao tc ghi DMA.b. B x l cp nht cache bn trong khi pht hin mt thao tc ghi DMA.6. Mt khi cc thao tc DMA c hon tt, thit b nh bus bng cch xc nhn tn hiu nh bus.7. B x l xc nhn (ack) tn hiu nh bus v thc hin li chu k bus t im m n lu.

5. TimerLesson 14 Timer_LAMTimer Timer l mt thit b ngoi vi rt ph bin v hu ch. N c s dng to ra cc s kin ti thi im c th hoc o thi gian ca cc s kin c th bn ngoi x l. N l mt thit b c th lp trnh, tc l khong thi gian c th c iu chnh bng cch vit mu bit c th cho mt s ca thanh ghi c gi l thanh ghi timer iu khin.CounterCounter l mt phin bn tng qut hn ca Timer. N c s dng m cc s kin dng xung nhpc cung cp cho n.Hnh .14.2 (a) cho thy s khi ca mt Timer n gin.

N l b m ln 16 bit m ln vi mi xung clock u vo.. Do , gi tr u ra Cnt th hin s xung t ln cui cng c reset v 0. Mt u ra b xung Top cnh bo khi no t n gi tr cui ca b m. N c th ln mc cao trong mt khon thi gian xc nh trc c thit lp bi b iu khin t nh c th lp trnh c bn trong n v Timer. Vic m c th c np ln bi mt chng trnh bn ngoi.

Hnh.14.2 (b) cung cp cc cu trc ca mt Timer khc ni mt b dn knh c s dng la chn gia internal clock hoc external clock, bit Mode thit lp hoc reset thit b c chn. Internal clock(Clk) hot ng nh mt Timer trong hnh 14.2a. External count in(Cnt_in) ch m s ln xy ra.

Hnh.14.2 (c) cho thy mt timer vi m thit b u cui. N c th to ra mt s kin nu mt khong thi gian c th c tri qua. B m khi ng li sau mi Terminal count

Hnh. 14,3 Timer Count and Output. Timer ch m xung. mi xung clock m gim i 1. Khi gi tr m v 0 u ra ca counter l TOP ln mc cao trong mt khong thi gian c nh trc. B m phi c np vi mt gi tr mi hoc trc bi chng trnh bn ngoi hoc n c th c np t ng mi ln m v 0.Timer in 8051 Microcontroller

Fig.14.1 cho thy kin trc ca 8051 c hai n v timer. 8051 c trang b hai timer, c hai u c th c kim sot, thit lp, c, v cu hnh ring. Timer ca 8051 c ba chc nng chung: 1) Duy tr thi gian v/hoc tnh ton s lng thi gian gia cc s kin, 2) m nhng s kin, 3) To tc truyn cho cng ni tip. Nh cp trc , 8051 c hai timer mi timer c nhng chc nng c bn theo cng mt cch. Mt TIMER0 v mt TIMER1. Hai Timer chia s hai chc nng c bit, Thanh ghi (SFR) (TMOD v TCON) kim sot Timer, v mi Timer cng c hai SFR dnh ring (TH0/TL0 v TH1/TL1).1. Timer0 v Timer1:B timer v Counter c la chn trong cc thanh ghi chc nng c bit TMOD. Hai Timer / Counter c bn ch hot ng c la chn bi cp bit (M1. M0) trong TMOD. Ch 0, 1, v 2 ging nhau c hai Timer/Counters. Ch 3 th khc nhau.2. MODE0:C hai timer trong ch 0 l mt b m 8-bit vi mt chia-32-pre-scaler. Trong ch ny, thanh ghi Timer c cu hnh nh mt thanh ghi 13-Bit. Ngay khi b m xoay vng t 1s v 0s, n t c ngt TF1. u vo m c kch hot Timer khi TR1 = 1 v GATE = 0 hoc TR1=1 v INT1 = 1. (Thit t GATE = 1 cho php Timer c kim sot bi u vo bn ngoi INT1, to iu kin cho php o rng xung).

3. Cc bit M1, M0

L ccbit ch ca cc b Timer 0 v Timer 1. Chng chnch ca cc b nh thi:0,1,2v3nhbng di. Chng ta ch tp chung vo cc ch thng c s dng rng ri nht lch 1vch 2. Chng ta s sm khm ph ra cc c tnh ca cc ch ny sau khi khm phn cn li ca thanh ghiTMOD. Cc ch c thit lp theo trng thi caM1vM0nh sau:

4. Bit C/T(Counter/Timer)

Bit ny trong thanh ghiTMODc dng quyt nh xem b nh thi c dng nh mt myto trhayb ms kin. Nu bitC/T = 0th n c dng nh mtb nh thi to trthi gian.

5. Bit cng GATE

Mt bit khc ca thanh ghiTMODl bit cngGATE. C hai b nh thi Timer0 v Timer1 u c bitGATE. Mi b nh thi thc hin im khi ng v dng. Mt s b nh thi thc hin iu ny bng phn mm, mt s khc bng phn cng v mt s khc va bng phn cng va bng phn mm. Cc b nh thi trn 8051 c c hai:

Vickhi ngvdngb nh thi c khi ng bng phn mm bi ccbit khi ng b nh thi TRlTR0 v TR1. iu ny c c nh cc lnh Set bitTR0ln1(khi ng b nh thi) hoc Clear bitTR0(dng b nh thi) i viTimer 0, v tng tTR1i viTimer 1.Cc lnh ny c tc dng khi bit GATE = 0trong thanh ghiTMOD.Vic khi ng v ngng b nh thi bngphn cng t ngun ngoibng cch t bitGATE = 1trong thanh ghiTMOD.

Tuy nhin, trnh s ln ln ngay t by gi ta tGATE = 0c ngha l khng cn khi ng v dng cc b nh thi bng phn cng t bn ngoi.

SymbolPositionName and SignificanceSymbolPositionName and Significance

TF1TCON.7Timer 1 trn Flag. thit lp biphn cng trn Timer / Countertrn. Xa bi phn cng vector ngt chng trnh conIE1TCON.3Ngt cnh xung, Thit lp b phn cng khi ngt ngoi cnh xung c pht hin

TR1TCON.6Timer 1 chy bit iu khin, Tht lp/xa bi phn mm bt hoc tt Timer/CounterIT1TCON.2Ngt loi 1 iu khin bit.Tht lp/xa bi phn mm tch cc cnh xung / mc thp kch hot ngt ngoi

TF0TCON.5Timer 0 trn Flag. thit lp biphn cng trn Timer / Countertrn. Xa bi phn cng vector ngt chng trnh conIE0TCON.1..

TR0TCON.4Timer 1 chy bit iu khin, Tht lp/xa bi phn mm bt hoc tt Timer/CounterIT0TCON.0.

6. MODE1Ging MODE0 ngoi tr vic thanh ghi ca Timer c chy vi 16 bit.

The Programmable Interval Timer 8253Vi vi x l n v timer khng c sn th Timer on c th lp trnh c c th c s dng.Fig.14.7 cho thy tn hiu ca Timer on c th lp trnh c ca 8253 .

Fig.14.8 cho thy s khi bn trong. C ba n v truy cp ring bit c iu khin bi h thanh ghi (Fig.14.9).Mi counter c hai u vo, ng h(clock), cng(GATE) v mt u ra. ng h l tn hiu hu ch trong vic m gim mt gi tr ci t sn trong thanh ghi counter tng ng. Cng phc v nh l mt u vo cho php. Nu cng c duy tr mc thp vic m c v hiu ha. S thi gian gii thch chi tit v cc ch khc nhau ca hot ng ca timer.

Ch hot ng ca 8253

Ch 0: Ngt khi m ht Ch 1: a hi lp trnh c Ch 2: Programmable Rate GeneratorCh 3: To xung vung Ch 4: Phn mm kch hot xungCh d 5: Phn cng kch hot xung1. Ch 0: Ngt khi m htOutput ln mc cao khi m ht, dng Counter nu cng(GATE) mc thp (Fig.14.10(a) & (b)). Timer thanh ghi m c np m(say 6) khi WR line c xung mc thp bi vi x l. n v Counter bt u m xung vi mi xung lock. u ra ln mc cao khi thanh ghi t gi tr 0, trong khi nu GATE mc thp (Fig.14.10(b)) vic m b dng ti gi tr (3) cho n khi GATE bt tr li.

8. Ch 1: mono shot lp trnh c:u xung mc thp vi xung Gate trong mt thi gian nht nh ty thuc vo counter. Counter c v hiu ha ngay khi xung GATE xung thp. Thanh ghi counter c np gi tr m nh trong trng hp trc (say 5) (Fig.14.11 (a)). u ra p ng u vo GATE v xung mc thp khong trong khong thi gian bng vi khong thi gian thanh ghi m xung. (5 xung lock). Bng vic thay i gi tr m, thi gian xung u ra c th c thay i. Nu GATE xung mc thp trc khi vic m xung hon thnh, b m s dng li ti trng thi vi iu kin l GATE mc thp (Fig.14.11(b)). Do n lm vic nh l mt mono-shot

9. Ch 2: Programmable Rate GeneratorFig.14.12 (a) v (b) cho thy dng sng tng ng vi cc hot ng timer trong ch ny. Trong ch ny n hot ng nh mt Rate Generator. u ra ln mc cao trong mt khong thi gian bng vi thi gian m xung ca thanh ghi m (trong trng hp ny l 3). u ra xung mc thp chnh xc trong khong thi gian 1 xung lock trc khi n ln mc cao tr li. y l mt hot ng tun hon.

4. Ch 3 To xung vung.N tng t nh ch 2 nhng u ra mc cao v thp l i xng. u ra mc cao sau khi b m c np v n vn mc cao trong khong thi gian bng thi gian m xung ca thanh ghi counter. u ra sau xung mc thp trong mt thi gian bng nhau v do to ra mt sng vung i xng khng ging nh ch 2. Cc GATE khng c vai tr y. (Fig.14.13).

10. Ch 4: Phn mm kch hot xungTrong ch ny sau khi vic m c np bi b x l, m xung bt u. u ra xung mc thp vi mt chu k ng h sau khi m xung hon tt. Vic m xung c th dng bng cch lm cho GATE xung mc thp (Fig.14.14 (a) (b)). N c gi l l mt phn mm kch hot xung v vic m xung c khi xng bi mt chng trnh.

11. Ch d 5: Phn cng kch hot xungVic m c np bi b vi x l nhng m xung c khi xng bi cc xung GATE. Cc qu trnh chuyn i t thp n cao ca xung GATE cho php m xung. u ra xung mc thp trong mt chu k ng h sau khi m xung hon tt (Fig.14.15).

Watchdog timer Mt Watchdog Timer l mt mch t ng kch hot mt thit lp li nu h thng ang c theo di thng xuyn gi cc tn hiu keep-off n Watchdog.Watchdog Circuit m bo rng mt chng trnh c th c thc thi ng cc mch Watchdog c s dng.V d chng trnh c th thit lp li mt flip-flop c bit theo nh k. V cc flip-flop c thit lp bi mt mch in bn ngoi . Gi s flip-flop khng thit lp li trong thi gian di n c th c gi bng cch s dng phn cng bn ngoi . iu ny s ch ra rng chng trnh khng c thc hin ng cch v do mt ngoi l hoc gin on c th c to ra.Watch Dog Timer (WDT) cung cp mt clock c bit, n c lp vi bt k clock bn ngoi khc. Khi WDT c kch hot, mt b m bt u t 00 v tng dn ln 1 cho n khi n t n FF. Khi n i t FF n 00 (tc l FF + 1) b vi x l s c thit lp li hoc mt ngoi l s c to ra. Cch duy nht ngn chn WDT thit lp li b x l hoc to ra mt ngoi l hoc ngt l nh k thit lp li WDT tr li 00 trong sut chng trnh. nu chng trnh b tc v l do no , WDT s khng c thit lp. WDT sau s thit lp li hoc gin on x l. Mt chng trnh phc v ngt s c gi a vo ti khon hot ng sai lch ca chng trnh. (b mc kt hoc i vo vng lp v hn).

6. Homework_Phn Bit & So Snh CACHE MAPPING_NAM1. T chc b nh Cache.a. C 3 k thut t chc: Kiu tng ng trc tip (Direct Mapping) Kiu hon ton phi hp (Fully Associative Mapping) Kiu phi hp theo tp hp (Set Associative Mapping)b. Da trn 2 kha cnh: Cch t vo cache mt khi d liu t b nh trong. Cch thay th mt khi khi Cache y. Kiu tng ng trc tip. Mi khi ch c mt v tr t khi duy nht trong cache, c xc nhtheo cng thc:K = i mod nTrong : K: v tr khi t trong cache i: s th t ca khi trong b nh trongn: s khi ca cache V d: B nh trong c 32 khi, Cache c 8 khi. c im: u: n gin (V khng tn thi gian tm kim v c ch thay th khi cng n gin). Khng hiu qu khi s dng Cache. (trng hp mt s v tr khi trong cache lun c dng n trong khi nhng v tr khc th khng). Kiu hon ton phi hp. Mt khi trong b nh trong c th c t vo v tr bt k trong cache. Trong trng hp khng cn khi no trng, th nguyn l thay th khi s c p dng (chng ta khng cn quan tm n k thut thay th khi y) c im: u: S dng Cache hiu qu do khi nh c th t ti bt k v tr no, tn dng c khng gian Cache. Nhc: Kh khn trong vn tm kim khi (i hi thit k phn cng phc tp nhm p ng vic tm kim khi c nhanh hn). Phi hp theo tp hp. Nhm dung ha u khuyt im ca c hai kiu tng ng trc tip v hon ton phi hp. Cache c chia thnh cc tp hp ca cc khi. Mi tp hp cha mt s lng khi nh nhau. Mt khi ca b nh trong s c t vo tp hp no ca cache c xc nh theo cng thc nh kiu tng ng trc tip; cn trong mi tp hp, khi c th t v tr bt k nh kiu hon ton phi hp.V d: Ta c: B nh trong: 32 khi. Cache: 8 khi. Khi th 12 ca B nh t ti v tr no trong cache???

_12 Stage Pipeline_NAM

hnh trn m t cu trc pipeline 12 giai on ca h VIA C3. Xt mc cao, c 4 nhm chc nng chnh: Np lnh, gii m v translate, thc thi & data cache. I-fetch cung cp lnh x86 t b nh I-cache hoc l bus bn ngoi. Decode & Translate chuyn i lnh x86 thnh Internal Execution Forms Execution thc thi v hy b lnh. Data Cache qun l loading & store d liu ca qu trnh Thc Thi v ca Caches, Bus, v cc thnh phn bn trong.1. I, B & V instruction fetch Qu trnh ny tm v np lnh t I-cache hoc t bus bn ngoi vo b gii m lnh I-cache cha 64KB I-TLB cha 128 entries. Cache v TLB dng lm gi LRU, thut ton thay th.2. F & X decode & translate. Decode & Translate lnh c a vo thnh nh dng bn trong ca ring n, dng thc thi. Giai on ny u thc thi trn mi xung clock. F stage decode & format li nh dng ca lnh thnh cu trc lnh x86. X stage translate lnh x86 thnh lnh Internal dng cho vic thc thi.3. R Decode stage. (Trong datasheet n ghi vy, khng trng vi bc trn u) Nhng lnh con c gii m, integer register file c truy cp v c lng ti nguyn s c s dng cho qu trnh thc thi.4. A - Addressing Stage: a ch b nh c tnh ton v gi cho D-cache. Con chip ny c th tnh ton hu ht cc form ca cc lnh a ch trong mt chu k xung clock, mt vi lnh yu cu thanh ghi dch hoc 2 thanh ghi cng mt lc th phi dng 2 chu k xung clock.5. D & G Cache Acess Stages. D-cache v D-TLB c truy cp v load d liu tr v ti giai on cui ca G-stage.6. E Execution Stage. Khi ALU thc hin nhim v trong giai on ny, tt c cc chc nng ca ALU cho php thc hin trong 1 chu k xung clock (Ngoi tr b nhn v chia). Lnh Load-ALU v Load-ALU-Store ch yu cu 1 chu k xung clock. 7. S store stage. Lu d liu s c thc thi trong giai on ny v d liu s c t trong nhng b m. V tr lu tr trong giai on ny cho php lnh load-ALU-store thc hin trong 1chu k. 8. W Write Back stage. Kt qu c ghi ngc li Register File phc v cho nhng lnh k tip.nh km1. H thng nhng (Embedded system) l mt thut ng ch mt h thng c kh nng t tr c nhng vo trong mt mi trng hay mt h thng m. l cc h thng tch hp c phn cng v phn mm phc v cc bi ton chuyn dng trong nhiu lnh vc cng nghip, t ng ho iu khin, quan trc v truyn tin. c im ca cc h thng nhng l hot ng n nh v c tnh nng t ng ho cao. H thng nhng thng c thit k thc hin mt chc nng chuyn bit no . Khc vi cc my tnh a chc nng, chng hn nh my tnh c nhn, mt h thng nhng ch thc hin mt hoc mt vi chc nng nht nh, thng i km vi nhng yu cu c th v bao gm mt s thit b my mc v phn cng chuyn dng m ta khng tm thy trong mt my tnh a nng ni chung. V h thng ch c xy dng cho mt s nhim v nht nh nn cc nh thit k c th ti u ha n nhm gim thiu kch thc v chi ph sn xut. Cc h thng nhng thng c sn xut hng lot vi s lng ln. H thng nhng rt a dng, phong ph v chng loi. c th l nhng thit b cm tay nh gn nh ng h k thut s v my chi nhc MP3, hoc nhng sn phm ln nh n giao thng, b kim sot trong nh my hoc h thng kim sot cc my nng lng ht nhn. Xt v phc tp, h thng nhng c th rt n gin vi mt vi iu khin hoc rt phc tp vi nhiu n v, cc thit b ngoi vi v mng li c nm gn trong mt lp v my ln. Cc thit b PDA hoc my tnh cm tay cng c mt s c im tng t vi h thng nhng nh cc h iu hnh hoc vi x l iu khin chng nhng cc thit b ny khng phi l h thng nhng tht s bi chng l cc thit b a nng, cho php s dng nhiu ng dng v kt ni n nhiu thit b ngoi vi. H thng nhng thng c mt s c im chung nh sau: Cc h thng nhng c thit k thc hin mt s nhim v chuyn dng ch khng phi ng vai tr l cc h thng my tnh a chc nng. Mt s h thng i hi rng buc v tnh hot ng thi gian thc m bo an ton v tnh ng dng; mt s h thng khng i hi hoc rng buc cht ch, cho php n gin ha h thng phn cng gim thiu chi ph sn xut. Mt h thng nhng thng khng phi l mt khi ring bit m l mt h thng phc tp nm trong thit b m n iu khin. Phn mm c vit cho cc h thng nhng c gi l firmware v c lu tr trong cc chip b nh ROM hoc b nh flash ch khng phi l trong mt a. Phn mm thng chy vi s ti nguyn phn cng hn ch: khng c bn phm, mn hnh hoc c nhng vi kch thc nh, dung lng b nh thp Sau y, ta s i su, xem xt c th c im ca cc thnh phn ca h thng nhng.2. Cu trc in hnh ca 1 h thng nhng

Coi thm ci n: m hnh ca 1 my tnh bn

3. Kin trc in hnh ca mt h thng nhng

4. Th bc ca cc thnh phn

5. B vi x l v DSP cn bn DSP: B x l chuyn bit cho cc ng dng x l tn hiu Cu trc Harvard

2 n 4 b nh truy cp mi chu k Phn cng tn hin thc hin SIMD b gii hn (1 cu lnh c th thap tc vs nhiu d liu) (Single Instruction Multiple Data) v tnh nng v tnh chuyn mn ha, cu lnh phc tp. Nhiu php tnh mi cu lnh n v tao a ch chuyn bit nh a ch c chuyn bit ha Lp phn cng Ngt b v hiu ha trong cc hat ng nht nh Thanh ghi Shadowing khng c hoc b gii hn (shadow registers are used when we need to modify the read only registers. they help the programmer to keep track of what is written to write only registers) Relatively narrow range of DSP oriented on-chip peripherals and I/O interfaces Rarely have dynamic features synchronous serial port b x l a dng CPU dung cho my tnh v my trm Kin trc Von Neumann Thng c thanh ghi Shadowing Thng c b nh cache ng H tr nhiu ngoi vi Cng giao tip bt ng b.

Thng th ch c 1 lt truy cp mi chu k Hu ht cc thao tc thc thi mt hn 1 cycle Cu lnh a dng nhng ch c 1 thao tc trong 1 cu lnh Thng khng c n v to a ch Ch nh a ch a dng Ch c lp phn mm Ngt thng b v hiu ha Thng c thanh ghi shadowing Thng c cache ng H tr nhiu ngoi vi cng nh giao tip on-chip v off-chip Cng ni tip bt ng b,

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