tunneling-based memory and advances in inp-based...
TRANSCRIPT
Tunneling-based Memory and Advances in InP-based Processing
A Dissertation
Submitted to the Graduate School
of the University of Notre Dame
in Partial Fulfillment of the Requirements
for the Degree of
Ph.D. in Electrical Engineering
by
Surajit Sutar, M.S.E.E
Alan C. Seabaugh, Director
Graduate Program in Electrical Engineering
Notre Dame, Indiana
March 2009
Tunneling-based Memory and Advances in InP-based Processing
Abstract
by
Surajit Sutar
This research explores InP-based tunnel diodes to supplement existing mem-
ory and high speed IC technology. Tunneling-based static random access memory
(TSRAM) uses the bistability of tunnel diodes to construct memory elements and
requires tunnel diodes with peak currents exceeding transistor leakage currents, high
peak-to-valley ratio (PVR) and low valley currents and voltages. InAlAs-InGaAs
resonant interband tunnel diodes (RITD) were investigated for TSRAM through
design, fabrication and electrical characterizations. In particular, the effects of dop-
ing density, barrier thicknesses and alloy composition on the RITD properties were
studied. Tunnel diodes with peak and valley currents spanning 5 orders of mag-
nitude, with PVRs as high as 70 were demonstrated through 3x variation in the
effective doping density. Valley currents as low as 0.07 nA/µm2, which is the lowest
reported for TSRAM tunnel diodes, and valley voltages as low as 250 mV were
demonstrated. Submicron device scaling was explored through the development of
a fabrication process.
To reduce the parasitics in tunnel diode/transistor integrated circuits, a novel
self-aligned contact process using dielectric spacers and benzocyclobutene etchback
was developed. Silicon nitride and oxide spacer sidewalls were demonstrated through
the development of anisotropic plasma etches. InP-based monolithically integrated
Surajit Sutar
resonant tunnel diodes and heterojunction bipolar transistors were fabricated using
this process and electrically characterized.
CONTENTS
TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv
FIGURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v
ACKNOWLEDGMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix
CHAPTER 1: INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . 11.1 Research Accomplishments . . . . . . . . . . . . . . . . . . . . . . . . 41.2 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
CHAPTER 2: TUNNELING-BASED DEVICES AND CIRCUITS . . . . . . . 62.1 Resonant Tunnel Diode . . . . . . . . . . . . . . . . . . . . . . . . . . 62.2 Resonant Interband Tunnel Diode . . . . . . . . . . . . . . . . . . . . 72.3 Tunneling-based SRAM . . . . . . . . . . . . . . . . . . . . . . . . . 8
CHAPTER 3: TUNNEL DIODES FOR TSRAM . . . . . . . . . . . . . . . . 153.1 Prior Art . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153.2 Intraband Resonant Tunnel Diode . . . . . . . . . . . . . . . . . . . . 17
3.2.1 Experiment Description . . . . . . . . . . . . . . . . . . . . . 183.2.2 Current-voltage Characteristics . . . . . . . . . . . . . . . . . 18
3.3 Resonant Interband Tunnel Diode . . . . . . . . . . . . . . . . . . . . 233.3.1 Experiment Description . . . . . . . . . . . . . . . . . . . . . 263.3.2 Current-voltage Characteristics . . . . . . . . . . . . . . . . . 273.3.3 Matching RITDs to TSRAM MOSFETs . . . . . . . . . . . . 363.3.4 Capacitance-Voltage Characterization . . . . . . . . . . . . . . 373.3.5 Temperature Dependence of the I-V . . . . . . . . . . . . . . . 403.3.6 Alloy Composition Experiment . . . . . . . . . . . . . . . . . 433.3.7 0.25 V Tunnel Diode Memory . . . . . . . . . . . . . . . . . . 47
CHAPTER 4: TUNNEL DIODE AND TRANSISTOR FABRICATION PRO-CESSES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494.1 InP-Based Tunnel Diode and Transistors . . . . . . . . . . . . . . . . 49
ii
4.2 Self-Aligned HBT/RTD Contact Process . . . . . . . . . . . . . . . . 514.2.1 Dielectric Spacer Process . . . . . . . . . . . . . . . . . . . . . 544.2.2 BCB Etch-back Process . . . . . . . . . . . . . . . . . . . . . 65
4.3 Semiconductor Etches . . . . . . . . . . . . . . . . . . . . . . . . . . 684.4 Device Measurements and Characteristics . . . . . . . . . . . . . . . . 764.5 RITD Submicron Device Process for TSRAM . . . . . . . . . . . . . 80
CHAPTER 5: CONCLUSIONS AND RECOMMENDATIONS FOR FUR-THER STUDY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 885.1 TSRAM Diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 885.2 Self-aligned HBT/RTD Contact Process . . . . . . . . . . . . . . . . 905.3 Further Study . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
REFERENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
APPENDIX A: RTD/HBT FREQUENCY PERFORMANCE ESTIMATION 100A.1 HBT Cut-off Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . 100A.2 RTD Maximum Frequency of Oscillation . . . . . . . . . . . . . . . . 106
APPENDIX B: HBT/RTD PROCESS FLOW . . . . . . . . . . . . . . . . . . 114
APPENDIX C: PUBLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . 125
APPENDIX D: HBT/RTD PROCESS TRAVELER . . . . . . . . . . . . . . . 135
APPENDIX E: SUBMICRON TSRAM PROCESS TRAVELER . . . . . . . . 157
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TABLES
3.1 EPITAXIAL LAYER STRUCTURE FOR THE RTD. THESE STRUC-TURES WERE GROWN BY MOLECULAR BEAM EPITAXY BYINTELLIGENT EPITAXY OF RICHARDSON, TEXAS. . . . . . . . 19
3.2 DOPING DENSITY AND BARRIER THICKNESSES FOR A SETOF FIVE RITD WAFER GROWTHS, THE FILLED BOXES INTHE TABLE HIGHLIGHT THE VARIATION . . . . . . . . . . . . 26
3.3 COMPARISON OF THE PEAK CURRENTS AND PVR FOR GROWTHS1 AND 2 WITH DAY [1], and TSAI [2] . . . . . . . . . . . . . . . . . 28
3.4 ALLOY COMPOSITION VARIATION IN THE SECOND RITDWAFER GROWTH SET, THE SHADED BOX SHOWS THE VARI-ATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.1 HBT/RTD LAYER STRUCTURE GROWN BY MOLECULAR BEAMEPITAXY BY INTELLIGENT EPITAXY OF RICHARDSON, TEXAS 50
4.2 PLASMA-ENHANCED-CHEMICAL-VAPOR-DEPOSITION AND RE-ACTIVE ION ETCH CONDITIONS FOR SILICON NITRIDE . . . 56
A.1 MATERIAL PARAMETERS AND OPERATING CONDITIONS USEDTO COMPUTE CUT-OFF FREQUENCIES FOR INP/GAASSB/INPHBTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
A.2 INGAAS/ALAS DEVICE AND MATERIAL PARAMETERS USEDFOR COMPUTING THE MAXIMUM OSCILLATION FREQUENCY111
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FIGURES
2.1 Energy band diagram of an InP-based resonant tunneling diode, com-puted using W. R. Frensley’s BandProf, a Schrodinger-Poisson solver. 7
2.2 Measured I-V characteristics of a 20 x 20 square micron low-currentInP-based RTD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Energy band diagram of an InGaAs-InAlAs resonant interband tun-neling diode, computed using W. R. Frensley’s BandProf, a Schrodinger-Poisson solver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4 Tunnel diode based memory cell, (a) two TDs in series with a bias VTDroughly equal to the TD valley voltage, (b) the load line diagram ofthe two diodes for external current ∆I = 0, with the operating pointbeing in the low state of the two stable states, (c) an external current∆I shifts the bias point to the high state, (d) when ∆I is removed,the operating point stays in the high state. . . . . . . . . . . . . . . . 10
2.5 A 1T-TSRAM cell. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112.6 A 3T-2TD TSRAM gain cell eliminating the need for an external
capacitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122.7 Predicted nCMOS transistor gate leakage current IG and drain-to-
source leakage IOFF vs. minimum feature size as given by the 2008ITRS roadmap. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1 Computed energy band diagram for the triple barrier RTD , usingW. R. Frenseley’s BandProf. . . . . . . . . . . . . . . . . . . . . . . . 17
3.2 Current density vs. voltage characteristics of the RTD growths 381-638, the growth variables being TCB and TALT . The bottom barrierthickness TALB being fixed at 19 A. . . . . . . . . . . . . . . . . . . . 20
3.3 Dependence of the reverse bias peak and valley current densities andthe PVR on design parameters : (a) central InAlAs barrier thickness,and (b) top AlAs barrier thickness. . . . . . . . . . . . . . . . . . . . 22
3.4 InAlAs-InGaAs resonant interband tunnel diode, (a) layer structureand (b) energy band diagram. . . . . . . . . . . . . . . . . . . . . . . 24
3.5 Comparison of (a) growth 1 and (b) growth 2 I-V characteristicswith identical epitaxial structures by Tsai [2], and Day [1], respec-tively. The I-V characteristics for growths 1 and 2 have been scaledto compare with the device sizes in [2], Day [1], which were 150 and100 µm diameter circles, respectively. . . . . . . . . . . . . . . . . . . 27
v
3.6 The effect of the structural variation on the device characteristicsfor growths 1-5, (a) Computed energy band diagrams using W. R.Frensley’s BandProf, (b) Current-voltage measurements after beingcorrected for the voltage drop across the series resistance. For growths1, 2 and 3, the data in the NDR region has been masked to removedata resulting from circuit oscillations. . . . . . . . . . . . . . . . . . 30
3.7 Reverse bias tunneling currents for growths 1-5 plotted against themaximum electric field at the junction. The solid line is a curve fitusing the method of least squares to the data, using Eq. (3.2) tocalculate the tunneling current. . . . . . . . . . . . . . . . . . . . . . 32
3.8 Computed effective overlap density integral D as a function of biasfor different doping densities. . . . . . . . . . . . . . . . . . . . . . . 34
3.9 (a) Peak, valley current densities and PVR, and (b) peak and valleyfor growths 1-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.10 The difference in the peak and valley currents for a diode area F2 afunction of the minimum feature size F, compared against the highperformance (HP) and low operating power (LOP) CMOS transistorleakage currents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.11 Current-voltage characteristics and small-signal parallel conductanceand capacitance as a function of bias for growths 1-5. The markersand lines in (b) represent the measured conductance (markers) andthe I-V extracted conductance (lines); the solid markers denote theNDR region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.12 Effect of temperature on the growth 5 tunnel diode I-V characteristic 423.13 Arrhenius plot of the valley current of growth 5 at different valley
voltages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433.14 Current density vs. voltage characteristics for identical device struc-
ture growths 5 and 6, grown about 6 months apart. The differencein the I-V characteristics for the same growth is significantly largerthan the linear variation. . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.15 The effect of the p-InxAl1-xAs alloy composition variation on the de-vice characteristics (a) Computed energy band diagrams using W. R.Frensley’s BandProf, (b) Current density vs. voltage measurements. . 46
3.16 Load line diagram for a growth 5 tunnel diode pair connected inseries, needing a supply voltage of only 0.25V for bistable bias points. 48
4.1 Energy band diagram of an InP-based RTD/HBT structure, com-puted using W. R. Frensley’s BandProf. The resonant tunnel diodeis grown above the heterojunction bipolar transistor, in the sameepitaxial growth sequence. . . . . . . . . . . . . . . . . . . . . . . . . 51
4.2 Self-aligned HBT emitter-base contact process using BCB etch-back,drawn to scale with 2 µm emitter width . . . . . . . . . . . . . . . . . 53
4.3 Schematic cross-section of adjacent HBT and RTDs on InP. . . . . . 554.4 Silicon nitride etch depth as a function of time in an SF6/Ar plasma. 574.5 Scanning electron micrograph of a Si3N4 sidewall on a GaAs substrate . 58
vi
4.6 In-process scanning electron micrographs of Si3N4 spacers aroundHBT emitters showing run-to-run in the spacer thickness and thenonuniformity of the sidewall profile, (a), (b), (c), and (d) top view;(e) and, (f) are viewed at a 45 angle. In (d) the Si3N4 spacer isalmost etched off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.7 Variation in the Si3N4 RIE etch rate in SF6/Ar plasma (2/18 sccm,15 mTorr) from run-to-run, the RF power is adjusted to keep the DCbias in the range 400±5 V . For each run, the etch rate was foundfrom the best least-squares linear fit to the etch depth vs. time curve,taken for three data points. . . . . . . . . . . . . . . . . . . . . . . . 60
4.8 Silicon dioxide etch depth as a function of time in a CF4/O2 plasma. 634.9 Scanning electron micrograph of a silicon dioxide sidewall, (a) cross-
section view of a Ti/Au pattern a GaAs substrate, (b), and (c) HBTsamples with the spacer around the HBT emitters, top and angled(45 to the vertical) views, respectively. . . . . . . . . . . . . . . . . . 64
4.10 In-process optical micrographs and step-profile measurements of theHBT samples at various stages of the etch-back process: (a) before theBCB etch-back, (b) after the BCB etch-back, (c) after the tungstenetch, and (d) after the BCB removal etch. . . . . . . . . . . . . . . . 66
4.11 Scaled schematic of a modified BCB etch-back process, (a) over etchof the dielectric spacer causes the emitter and the base contact metalto be connected, (b) Etching back the tungsten in RIE to a sufficientdepth isolates the two contacts. . . . . . . . . . . . . . . . . . . . . . 68
4.12 Current-voltage characteristics of HBT base-emitter junctions afterthe BCB etch-back process, (a) the contacts are electrically separatedwithout having to do a tungsten etch-back, (b) inadequate isolationbetween the contacts requires a tungsten etch-back process whichreduces the leakage current. . . . . . . . . . . . . . . . . . . . . . . . 69
4.13 Etch characteristics of InGaAs in CH4/H2/Ar plasma, (a) Etch depthvs. time characteristic, (b) SEM micrograph of the cross-section witha post-RIE wet etch of InGaAs. . . . . . . . . . . . . . . . . . . . . . 70
4.14 Optical micrographs of InGaAs/InP surfaces after RIE in CH4/H2/Arplasma, (a) InGaAs collector surface after RIE and wet etch of theInP subcollector, (b) InP surface after RIE, a visible mark is left bythe step-profile stylus on the sample surface. . . . . . . . . . . . . . . 72
4.15 Effect of ACTrNE-14 descum on reactive ion etched InP surface (a)Optical micrographs of InP surfaces with and without the soak, (b),(c) SEM micrographs of samples without and with the descum process. 73
4.16 Effect of mesa undercut on the HBT, (a) SEM micrograph of an HBTemitter array showing HBT emitters lifted off by excessive undercutsduring HBT mesa etch, (b) Optical micrograph of an HBT showsthe tearing off of the W base contact upon electrical probing, nosubcollector mesa is observed underneath, showing the effect of theundercut during the subcollector mesa etch, the emitter contact metalis also absent, showing the HBT mesa. . . . . . . . . . . . . . . . . . 75
4.17 Current-voltage characteristics of fabricated HBTs (a) Forward Gum-mel characteristics, (b) Output characteristics. . . . . . . . . . . . . . 76
4.18 Transfer line method measurements for the contact resistances, (a)HBT emitter, (b) HBT base, (c) HBT collector, and (d) RTD emitter. 78
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4.19 Current-voltage characteristics of RTDs in double bias sweep (a) one3×4 µm2 RTD shows no hysteresis in the double sweep showing thelack of a significant series resistance, (b) two 3×4 µm2 RTDs in se-ries, showing slightly different peaks, and hysteresis, pointing to asignificant series. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
4.20 Submicron process flow (a) emitter contact definition, (b) formationof SiO2 spacer sidewall, (c) emitter mesa wet chemical etch, (d) pla-narization by BCB, (e) BCB etch-back, exposing the emitter con-tacts, and (f) Contact metallization for the bondpad, connecting tothe emitter contacts, and the Ti/Au back contact. . . . . . . . . . . . 80
4.21 In-process SEM micrographs for the submicron fabrication process :(a) top view of the emitter contacts after lift-off, (b) emitter mesasafter wet etch, with the SiO2 spacer sidewall, (c) emitter contact postssticking out after the BCB etch-back, (d) Ti/Au bondpad contactsconnecting to the emitter contacts. Figures b, c, and d are imagesviewed at an angle of 45 to the vertical. . . . . . . . . . . . . . . . . 82
4.22 Current-voltage measurements for arrays of diodes connected in par-allel, the diode current is observed to scale with the number of devicesin parallel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
4.23 Dependence of the current and PVR on area for growths 1-5: (a) peakcurrents scale linearly with area, (b) valley currents deviate from alinear relationship with area, and (c) PVR degrades with area. . . . . 85
4.24 Effect of post growth anneals on a submicron diode for growth 1.Repeated post growth anneals in nitrogen does not recover the PVRand results in significant degradation in the device conductance andthe PVR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
A.1 Heterojunction bipolar transistor schematic cross-section showing thephysical origin of the parasitic resistances. . . . . . . . . . . . . . . . 102
A.2 Layout of a 2×2 µm2 emitter heterojunction bipolar transistor forthe 0.5 µm misalignment rule. . . . . . . . . . . . . . . . . . . . . . . 104
A.3 High frequency performance of a 4 µm2 emitter HBT as a functionof the emitter-base separation and emitter width. . . . . . . . . . . . 106
A.4 Schematic cross section of an RTD showing the physical origin of theseries resistances. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
A.5 Layout of a 3×3 µm2 emitter resonant tunneling diode. . . . . . . . . 110A.6 High frequency performance of a 9 µm2 RTD as a function of the
emitter-collector separation for different emitter geometries. . . . . . 111A.7 Maximum RTD oscillation frequencies as a function of the emitter
area, the emitter-collector separation being 35 nm. Square emittergeometries are assumed. . . . . . . . . . . . . . . . . . . . . . . . . . 112
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ACKNOWLEDGMENTS
I would like express my deepest gratitude to my advisor Dr. Alan Seabaugh,
for his continued guidance, patience, and support in the course of my research at
Notre Dame. I would like to thank Dr. Snider, Dr. Fay and Dr. Jena for valuable
discussion and advice, and for their consent to be on the dissertation committee. I
would like to thank my colleagues Wu Bin, Qingmin Liu, Qin Zhang and Tim Vasen
for their help in the projects we worked on. I am grateful to the ND nanofabrication
facilities management, especially Mike Thomas, Keith Darr and Mark Richmond,
whose help and cooperation made this work possible. Finally I would like to thank all
my friends at Notre Dame who made my stay at Notre Dame a pleasant, rewarding,
and cherishable experience.
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CHAPTER 1
INTRODUCTION
With the phenomenal advances in vertical and lateral scaling in complimentary
metal oxide semiconductor (CMOS) field-effect transistor (FET) technology, en-
abling 2 billion transistors on a chip [3], power density has emerged as the primary
limiter to further size reduction [4]. The need to lower supply voltages without
sacrificing performance requires the introduction of high-velocity channel materials,
which has renewed interest in III-V compound semiconductors [5, 6] because of their
relatively high carrier mobilities [5]. Furthermore, advances in the heterogeneous
epitaxial growth of III-V materials on Si [7] has made the prospects of harnessing
the high speed low power advantages of the III-Vs on the scalable Si platform real.
Among III-Vs, InP-based materials have been widely investigated in transistors,
e.g. InP-based MOSFETs [8, 9], high electron mobility transistors (HEMTs) [10,
11, 12], and heterojunction bipolar transistors (HBTs) [13]. Current and power gain
cut-off frequencies as high as 755 GHz [14], and 560 GHz [13], respectively, and high
breakdown voltages of 6 V [15] have been demonstrated in InP HBTs. InP-based
HEMTs with gate lengths of 60 nm have been bench-marked against 65-nm CMOS
technology and their performance, on-current, drain-induced-barrier lowering and
subthreshold slopes has been shown to be comparable if not better than CMOS [12].
From a comparison of cut-off frequency and power dissipation for 50 and 100 nm
InP HEMTs with state-of-the-art 80 nm Si-MOSFETs, it has been shown that for
1
equivalent frequency performance, InP-HEMTs can lower power dissipation by more
than an order of magnitude with respect to Si-MOSFETs [16]. Impressive advances
in scaling of InP-based transistors technologies [12, 16, 17] have demonstrated their
relevance in ongoing efforts to extend the performance of integrated circuits (ICs).
Future III-V on Si logic technology would be aided by an embedded high-density
low-power III-V SRAM (static random access memory). A candidate III-V based
memory is the tunneling SRAM (TSRAM) [18]. First proposed by Goto et al. in
1960 [19], TSRAM uses the negative differential resistance of tunnel diodes (TD)
to build circuits that are bistable, giving it a memory functionality. The Goto cell
can store data without transistor action or periodic refreshing. To perform read and
write, the TDs need to be integrated with transistors, e.g. the Si-MOSFET [20] and
III-V heterostructure field effect transistors (HFETs) [21]. Tunneling-based SRAM
cells with InP-based intraband RTDs [21, 22], GaAs-based RITDs [23], and Si-Ge
based RITDs [20, 24, 25] have been demonstrated. The motivation for investigation
of these cells is smaller cell size and lower standby power made possible by lower-
ing device count. InP-based TSRAM with standby power of 50 nW/bit has been
demonstrated [22], lowering standby power dissipation by 400 times over the best
III-V HEMT-based memory [26].
The TDs used in a III-V TSRAM must have a peak and valley currents which
are commensurate with the transistor technology. Generally, the peak current must
exceed the maximum leakage current in the statistical distribution of on-currents in
the technology. Maximizing peak-to-valley current ratio (PVR) reduces the standby
power [18] in the cell. It is also important that the TD properties do not degrade as
the device is scaled. Previous demonstrations of TSRAM have been few, Jin [27] in
Si-Ge, and van der Wagt [28] in InP-based heterostructures. This research signifi-
cantly extends the exploration and understanding of TD structures for application
2
as TSRAM. Two TD approaches, the resonant tunnel diode (RTD) and the reso-
nant interband tunnel diode (RITD) are investigated through design, fabrication,
and electrical measurements. The effects of device scaling are also studied.
Besides memory, TDs, especially the RTD, has received considerable interest in
high speed digital and mixed signal circuit applications. The bistable properties
of the TD can be used in building monostable-bistable transition logic elements
(MOBILE) [29]. MOBILE-based circuits have been investigated for reduced circuit
complexity and low power [30, 31, 32, 33]. Analog applications of RTDs include os-
cillators and pulse generators, with InAs/GaSb RTDs demonstrating a fundamental
oscillation frequency of as high as 712 GHz using the device’s negative differential
resistance (NDR) to stimulate the oscillation [34]. The performance of high speed
ICs can be improved by integrating TD with transistors. The TD, being a two
terminal device, has intrinsically no input-output isolation [35, 36], which results
in a lack of signal directionality. This deficiency can be overcome by incorporat-
ing transistors into TD circuits. Tunnel diode/transistor ICs with RTDs integrated
with HEMTs or heterojunction bipolar transistors (HBTs) have been investigated
for their reduced circuit complexity, high speed, and low power [30, 31, 32, 37].
Devices in high speed circuit applications need low access resistances and termi-
nal capacitances, as these parasitics limit the frequency performance. For example,
in RTDs, the maximum frequency of oscillation is dependent upon the emitter-
collector series resistance. In HBTs, the extrinsic base resistance restricts the maxi-
mum power gain cut-off frequency. Reductions in these parasitics can be achieved by
minimizing junction areas and utilizing self-aligned contact processes. Self-aligned
processes are also desirable for device scaling as they are independent of the litho-
graphic limits. Scalable self-aligned contact processes using dielectric spacers have
been developed for manufacturable HBT technology [38, 39]. In this research, the
3
exploration of RTD/transistor circuits is continued through the development of
an InP-based integrated RTD/HBT fabrication process, featuring dielectric spacer-
based self-aligned RTD emitter-collector and HBT emitter-base contact. A novelty
of the self-aligned process is the use of a benzocyclobutene (BCB) planarization and
etch-back process.
1.1 Research Accomplishments
• Demonstrated InP-based InGaAs-InAlAs RITDs spanning 5 orders of magni-
tudes in peak and valley currents for integration with wide range of transistor
technologies for TSRAM.
• Achieved valley currents as low as 0.07 nA/µm2, which is the best reported
for low current TSRAM diode designs.
• Achieved PVR of 4-14 in low-current RITDs, an improvement over previous
efforts at comparable current densities [24, 40].
• Lowered valley voltage to as low as 250 mV to enable construction of TSRAM
with a 250 mV TD supply voltage.
• Explored the effects of alloy composition on the RITD electrical properties to
show that lattice strain and dislocations may increase the valley current.
• First capacitance-voltage study of low-current RITDs, observed a capacitance
higher than the depletion capacitance, due to the charging of the quantum
wells.
• Demonstrated InP-based dielectric spacer and BCB etchback processes for
self-aligning HBT and RTD metallizations.
4
• Demonstrated first submicron TSRAM processes and showed that surface pas-
sivation will be needed to prevent edge leakage.
1.2 Thesis Organization
This dissertation is organized as follows. Chapter 2 outlines the physics of RTD
and RITDs and the basic operation of one (1-T) and three-transistor (3-T) TSRAM
cells. Chapter 3 describes the design, fabrication, and electrical characterization of
RTD and RITD structures for TSRAM. Chapter 4 details the development of the
self-aligned HBT/RTD contact process. The electrical characteristics of HBTs and
RTDs fabricated using this process are presented. A submicron device process for
TSRAM is described, and the effects of submicron scaling are also discussed. Chap-
ter 5 provides conclusions and recommendations for future work. Also included are
five appendices. Appendix A provides the frequency estimates for HBTs and RTDs
showing the importance of metal self-alignment. Appendix B shows the detailed
process flow for the HBT/RTD self-aligned process. Appendix C includes the pa-
pers authored/coauthored in the course of this research. Appendix D and E are the
HBT/RTD and submicron TSRAM process travelers, respectively.
5
CHAPTER 2
TUNNELING-BASED DEVICES AND CIRCUITS
This chapter introduces TD structures and the TSRAM. Two TD structures :
the intraband RTD, and the interband RITD are described, and the TD figures-of-
merits are defined. The TSRAM operating principle and circuit configurations are
described. Finally, the issues associated with leakage currents and power dissipation
in TSRAM are presented and the ways in which these factors guide TSRAM TD
design are discussed.
2.1 Resonant Tunnel Diode
The simplest embodiment of an RTD [41] is a heterostructure consisting of two
potential barriers sandwiching a quantum well. Shown in Figure 2.1 is a schematic
of an RTD energy band diagram at an applied bias Va. Labeled are the Fermi
energies, EF, in the emitter (left), and collector (right), and the quantized ground
state E0, and the first excited state E1 above the ground state. Applying a positive
bias to the collector to align the quantum well energy state E0 with filled states in
the emitter enables tunneling of electrons from the emitter through the quantum
well and into the collector.
The current-voltage I-V characteristics of an RTD is shown in Figure 2.2. From
zero volts, the current increases as more and more occupied electron energy states
are brought into alignment with the quantum well ground state, reaching a peak
6
-1.5
-1
-0.5
0
0.5
1
1.5
2
0 5 10 15 20
Ene
rgy
(eV
)
Position (nm)
InG
aAs
AlA
s
InG
aAs
InG
aAs
InG
aAs
AlA
s
InA
s
EF
EF-qV
a
E0
E1
Figure 2.1: Energy band diagram of an InP-based resonant tunneling diode, com-puted using W. R. Frensley’s BandProf, a Schrodinger-Poisson solver.
current Ip at a voltage Vp, defined as the peak voltage. Further increase in the bias
decreases the number of emitter electron states aligned to E0, decreasing the current,
giving rise to the NDR region. When the quantum well state is lowered below the
emitter conduction band edge, the current reaches a minimum, corresponding to the
valley I-V; the current and voltage at this minimum are called the valley current
Iv and valley voltage Vv. The ratio Ip/Iv is called the peak-to-valley current ratio.
As the bias is increased beyond the current minimum, the current increases due to
thermionic emission current over the barriers and by tunneling through the second
energy state E1, giving rise to an N-shaped I-V characteristic.
2.2 Resonant Interband Tunnel Diode
The RITD [42, 43] is a heterostructure in which carriers tunnel between quantum
wells in the valence and conduction bands. The computed energy band diagram for
7
0
20
40
60
80
0 0.5 1 1.5
Cur
rent
(µA
)
Bias (V)
IPVp
VvIv
NDR region
Figure 2.2: Measured I-V characteristics of a 20 x 20 square micron low-currentInP-based RTD.
an p-n InGaAs-InAlAs RITD is shown in Figure 2.3. The heterostructure consists
of valence and conduction band quantum wells formed by an intrinsic region of
two InGaAs layers sandwiching an InAlAs barrier. The p and n InAlAs emitter
and collector regions are degenerately doped. An applied forward bias brings the p-
emitter hole energy states into alignment with the n-collector electron energy states,
corresponding to a current peak. Beyond the valley, at which the band alignment is
broken, the current is due to the forward-biased p-n diode thermionic current and
defect-assisted excess tunnel current [44].
2.3 Tunneling-based SRAM
The use of a pair of series-connected NDR devices to make a memory bit was first
proposed by Goto in 1960 [45]. A Goto memory cell is shown in Figure 2.4 where a
pair of TDs, D1, D2 are connected in series, their common terminal serving as the
8
-2
-1
0
1
2
0 10 20 30 40 50 60 70
Ene
rgy
(eV
)
Position (nm)
p+ InGaAs
n+ InGaAs
EF
InGaAs quantum well
p+ InAlAsemitter
n+ InAlAscollector
InAlAsInGaAs
Figure 2.3: Energy band diagram of an InGaAs-InAlAs resonant interband tunnelingdiode, computed using W. R. Frensley’s BandProf, a Schrodinger-Poisson solver.
storage node (SN). The load line diagram for the pair is shown in Figure 2.4(b) for
an applied bias of VTD and assuming that no external current flows into the SN,
∆I = 0, ID1 = ID2. The load line diagram shows two stable bias points in the valley
regions of D1 and D2, representing binary states of 1 and 0, respectively. Since the
state in this cell is maintained by a continuous current flow in the tunnel diode pair,
no refresh is needed and the memory provides the functionality of an SRAM.
Any memory bit requires three basic operations: write, store and read. For the
Goto cell, the write operation is performed by supplying a current ∆I into the SN.
This can be understood from the load line diagrams in Figure 2.4(b), (c) and (d).
In Figure 2.4(b), consider the SN potential VSN to be at the low or 0 state. If a
current ∆I flows from the node, ID1 = ID2 + ∆I, the I-V characteristics of the TDs
in the load line diagram are shifted by ∆I with respect to each other, as shown in
Figure 2.4(c). This results in the VSN to shift from the valley voltage of one diode
to the valley of the other. If the external current ∆I is now set to zero, VSN moves
9
VTDΔIVTD
I
State ‘0’ State ‘1’
VTD
I ∆I I
VTD
ID1D2∆I = 0
∆I = 0
D1 ID2 ID1ID1ID1
ID2ID2ID2 VSN
(a) (b)
(c) (d)
Figure 2.4: Tunnel diode based memory cell, (a) two TDs in series with a bias VTDroughly equal to the TD valley voltage, (b) the load line diagram of the two diodesfor external current ∆I = 0, with the operating point being in the low state of thetwo stable states, (c) an external current ∆I shifts the bias point to the high state,(d) when ∆I is removed, the operating point stays in the high state.
to the state 1, shown in Figure 2.4(d). The value of the supplying current ∆I to
cause a switch between 1 and 0 states depends on VTD and the shape of the I-V
characteristics, its maximum value is the difference between the TD peak and valley
currents. In TSRAM this current is delivered through a pass transistor (FET) to
the SN. The 1 transistor-2 TD (1T-2TD) circuit shown in Figure 2.5 has been the
most common configuration explored for a TSRAM cell [21, 22, 20, 24], with the
FET providing isolation between the SN and the bit line (BL), which is connected
10
VTDWLBL CEXID1Ileak VSNT1 ID2
Figure 2.5: A 1T-TSRAM cell.
to the FET source. The write is performed by selecting a high state for the word line
(WL), which turns on the transistor and allows the state at the SN to be changed.
The read on the TSRAM cell in Figure 2.5 is performed by turning on the pass
transistor, and sensing the current into the BL, as in the case of a 1T-dynamic
random access memory (DRAM). The capacitance required to supply the current
into the BL for current sensing can be realized in the two TD intrinsic capacitances,
as in [28] where diodes of 100 µm2 area were used. The SN capacitances in Si 1T-
DRAM are of the order of 30 fF/cell [46], and it’s easy to see that the TD intrinsic
capacitance, which is only of the order of a few fF/µm2 [47], cannot provide this
capacitance with submicron area diodes. In this case, the TSRAM cell requires an
external capacitance CEX if it is to be sensed like a DRAM, as shown in Figure 2.5.
The resulting cell topology looks like a 1T-DRAM with an added TD pair. Com-
pared to the DRAM cell which needs periodical refreshing of the storage capacitor,
in the TSRAM cell the SN voltage is held to the TD stable bias points, avoiding the
11
WL
BL
RL
M1 M2M3VTD
Figure 2.6: A 3T-2TD TSRAM gain cell eliminating the need for an external ca-pacitor.
energy spent for the refresh. Because of the continuous flow of current in the TD
pair, the TSRAM cell has a minimum static power dissipation per bit of VTDIv.
The external capacitor in the 1T-2TD TSRAM cell requires a capacitor process,
which, in the case of DRAMs is realized using a trench [46] or stacked [48] capacitor
processes. The added process complexity of a capacitor process is avoided in a gain
cell configuration [22]. The cell, shown in Figure 2.6 uses two additional FETs, the
SN is connected to the gate of M2. A read select line RL is added and the BL is
shared for the read and write operations. The SN FET M2 provides the required
gain to drive the BL without changing the SN state. A read select pass FET M3 is
used to connect the drain of the SN FET to the BL. The write operation is exactly
the same as in a 1T-TSRAM cell. To perform a read, M3 is turned on to read the
current through M2. Because of the additional transistors, this cell requires more
area than a 1T-TSRAM.
12
Tunnel diodes for TSRAM cells must maintain the SN state in the presence of
transistor leakages as well as contribute to an overall reduction in standby power. In
order to maintain the state, the TD peak current needs to be higher than the sum
of the worst case TD valley current plus the pass transistor leakage current plus the
capacitor leakage current. Since the transistor leakage depends on the technology
and scaling, the tunnel diode must be designed to match the transistor. Figure 2.7
quantifies the absolute leakage projected for Si from the international technology
roadmap for semiconductors (ITRS), 2008 for both high performance (HP), and low
operating power (LOP) technologies plotted as a function of the microprocessor unit
Metal1 half-pitch, F. The absolute transistor gate leakage IG, and off-state drain-
source leakage IOFF have been calculated for minimum size transistors, gate width,
W equal to gate length, L, equal to F. Both the HP and LOP transistor off-state
drain-source leakages show a sharp drop at F = 32 nm, which is the predicted node
for a switch in the MOSFET structure from a planar bulk to an ultrathin body
fully depleted MOSFET structure , which results in a decrease in IOFF . The gate
leakages for both HP and LOP transistors show a decrease with scaling. Though it’s
the worst case transistor leakage plus the valley current that the TD peak current
needs to exceed in order to maintain the SN state, the sum of IG and IOFF shown
in Figure 2.7 provides an estimate of how large the TD peak current needs to be
: taking the TD area to be F2, the TD peak current Ip needs to exceed the sum
Iv + IG + IOFF .
TD pair standby power VTDIv is reduced by both lowering valley current and
lowering valley voltage, since valley voltage determines VTD. As an estimate for
how low the valley current needs to be, the leakage current per bit in an ultralow
power 65 nm node 6T-CMOS SRAM is of the order of 2 pA/bit [49]. To achieve
this leakage current in the TSRAM TD pair, the valley current density needs to be
13
10-10
10-9
10-8
10-7
0 10 20 30 40 50 60 70
nMO
S le
akag
e cu
rren
t (A
)
Min. feature size F (nm)
Red - HP
W=L=FBlue - LOP
IOFF
IG
IOFF
IG
Figure 2.7: Predicted nCMOS transistor gate leakage current IG and drain-to-sourceleakage IOFF vs. minimum feature size as given by the 2008 ITRS roadmap.
less than 0.5 nA/µm2, for a diode pair of 65×65 nm2 area. Since Ip needs to exceed
Iv + IG + IOFF , the difference Ip − Iv = Iv(PVR− 1) needs to exceed IG + IOFF , so
that for a given transistor leakage IG+IOFF , in order to minimize the valley current
Iv, the PVR for any TD needs to be maximized .
In summary, the heterostructures and I-V behavior of InP-based RTDs and
RITDs have been outlined for TSRAM cells. TSRAM cells use the bistability of
TDs to enable the charge on a capacitor to be sustained in the presence of leakage.
Transistor leakage sets the targets for the TD design since the tunnel diode must be
able to handle the worst case transistor leakage. Maximizing peak-to-valley current
ratio offers benefits in reducing the power dissipation in the TSRAM TD pair.
14
CHAPTER 3
TUNNEL DIODES FOR TSRAM
This chapter describes the design and demonstration of TDs for application
in TSRAM. Methods to reduce the TD valley currents while keeping high PVRs
through structural changes in the device are investigated. Two TD structures, the
RTD and the RITD, and the effect of structural changes in the barrier thicknesses,
doping densities, and alloy composition are explored through current-voltage and
capacitance-voltage measurements.
3.1 Prior Art
Experiments in tailoring TD structures for TSRAM application, i.e. reducing
the TD valley voltages and currents, include exploration of InP-based RTD struc-
tures by van der Wagt et al. [28], and Si-Ge p-n TDs by Jin et al. [24]. In van der
Wagt’s work, an InAlAs pre-barrier layer was added to the AlAs-InGaAs-InAs dou-
ble barrier RTD heterostructure, its thickness being the design variable. Increasing
the pre-barrier layer thickness decreased the electron transmission probability and
the currents, with the valley current reduced by two orders of magnitude to 0.5
nA/µm2 and the valley voltages reduced from 450 to 260 mV, by an increase from
15 to 26 monolayers in the pre-barrier thickness. The corresponding decrease in
the peak tunneling current was proportionately larger, resulting in a decrease in the
PVR from 18 to 3. The TD structure in Jin’s work was a δ-doped p-n Si-Si0.6Ge0.4
15
heterojunction diode, with an undoped Si spacer region of variable thickness be-
tween the p and n layers. By increasing the spacer layer thickness from 1 to 16
nm, the valley currents were reduced by four orders of magnitude to 0.1 nA/µm2.
The PVR for the lowest current diode was 1.6 and the valley voltage was 250 mV.
In both van der Wagt and Jin’s approaches, the reduction in the valley currents to
below 1 nA/µm2 is congruent with reducing the TSRAM TD pair leakage current.
However the low PVRs, 3 and 1.6 respectively, calls for further improvements in the
TD structures since there is increasing benefit of high PVR in TSRAM application
for maintaining the storage node state in the presence of transistor leakages.
In designing high PVR TDs, a TD design that has been widely investigated is
the p-n InGaAs-InAlAs double quantum well (QW) RITD [1, 2, 42, 43, 50]. This
structure holds the records for the highest PVR of 144 of all TDs [1, 2] applicable to
SRAM with peak voltages under a volt. The experiments on this structure have so
far concentrated on, apart from maximizing the PVR, on increasing the peak current
density with the barrier and QW widths being the design variables. With its high
PVR, this structure is an attractive prospect for TSRAM application. However, the
valley currents need to be reduced by more than an order of magnitude from the
values of about 20 [1], and 7 [2] nA/µm2 to less than 0.5 nA/µm2.
In this work, two TD structures are investigated for SRAM : (a) a triple barrier
intraband RTD, and (b) an InGaAs-InAlAs double QW RITD. For the RTD struc-
ture, the effects of the barrier thicknesses on the I-V are investigated specifically.
For the InGaAs-InAlAs RITD, the effects of barrier thicknesses, doping densities
and alloy compositions are explored.
16
-0.5
0
0.5
1
1.5
60 65 70 75 80 85 90 95 100
Ene
rgy
(eV
)
Position (nm)
n+ InGaAs
EF
InAlAs barrier
InGaAs/InAs quantum wells
AlAs barrier
TALT
TCB
TALB
Figure 3.1: Computed energy band diagram for the triple barrier RTD , using W.R. Frenseley’s BandProf.
3.2 Intraband Resonant Tunnel Diode
The first TD structure investigated in this work was an InP-based triple barrier
RTD, following the patent of van der Wagt [51]. The layer structure and the energy
band diagrams are shown in Table 3.1, and Figure 3.1, respectively. The struc-
ture is composed of two AlAs-InGaAs-InAs-InGaAs-AlAs double barrier QW RTD
structures, separated by an InAlAs barrier layer. The AlAs/InAlAs/AlAs central
heterostructure also forms a QW, but the quantization states associated with this
well are at such high energy that they do not play a role at the low biases of interest
for this TD. Compared to a double-barrier RTD, Figure 2.1 of Chapter 2, because of
the additional central heterostructure barriers in the triple-barrier RTD, the trans-
mission coefficient and the tunneling current is reduced. The epitaxial layers were
grown on a lattice-matched n-InP substrate.
17
3.2.1 Experiment Description
In a first set of five molecular beam epitaxy (MBE) growths, the effect of the
top AlAs barrier thickness TALT and the center InAlAs barrier thickness TCB on the
RTD I-V characteristic was explored, Table 3.1. For growths 1 through 5, the barrier
thicknesses TCB and TALT are increased in steps of 2 A, which is approximately the
AlAs monolayer thickness. An empirical relation between the peak current density
Jp and the top AlAs barrier thickness in an AlAs/InGaAs/InAs double barrier RTD
have been established by Moise et al. ([52], Figure 10) where a monolayer increase
in the AlAs barrier thickness resulted in 56 % decrease in the peak current density.
Using this relation, the increase in the AlAs barrier thickness should decrease the
peak current from growth 399 to 638 by about 70 %. The increase in TCB from
growth 381 to 399 is also expected to decrease the transmission coefficient and the
peak current.
The device fabrication consisted of defining the emitter contacts by contact
lithography and lifting-off Ti/Pt/Au contact metal, followed by etching in 1 H2SO4:
8 H2O2: 160 H2O through the RTD layer to define the emitter mesa. The n-InP
substrate allowed electrical measurements of the diodes from the top emitter contact
through the back of the wafer.
3.2.2 Current-voltage Characteristics
The RTD current density vs. voltage J-V characteristics is shown in Figure 3.2
for the set of five growths detailed in Table 3.1. The measurements were performed
from the top emitter contact through a grounded wafer chuck, with positive bias in
Figure 3.2 referring to a positive polarity on the emitter.
All wafers show an asymmetry for positive and negative biases, with a larger
peak current and a stronger NDR for the reverse bias. It should be noted that
18
Table 3.1
EPITAXIAL LAYER STRUCTURE FOR THE RTD. THESE STRUCTURES
WERE GROWN BY MOLECULAR BEAM EPITAXY BY INTELLIGENT
EPITAXY OF RICHARDSON, TEXAS.
Layer Material xThickness
(Å) Dopant
Density
(/cm3) Type
Emitter In(x)Ga(1-x)As 0.53 500 Si 1.0E+19 n+Emitter In(x)Ga(1-x)As 0.53 200 Si 1.0E+18 n+
In(x)Ga(1-x)As 0.53 20 UID - iBarrier AlAs T ALT UID - i
In(x)Ga(1-x)As 0.53 6 UID - iNotch InAs 18 UID - i
In(x)Ga(1-x)As 0.53 6 UID - iBarrier AlAs 20 UID - i
Center Barrier In(x)Al(1-x)As 0.54 T CB UID - i
Barrier AlAs 20 UID - iIn(x)Ga(1-x)As 0.53 6 UID - i
Notch InAs 18 UID - iIn(x)Ga(1-x)As 0.53 6 UID - i
Barrier AlAs 19 UID - iIn(x)Ga(1-x)As 0.53 20 UID - i
Collector In(x)Ga(1-x)As 0.53 200 Si 1.0E+18 n+Collector In(x)Ga(1-x)As 0.53 100 Si 1.0E+19 n+Etch stop InP 30 Si 1.0E+19 n+
In(x)Ga(1-x)As 0.53 2000 Si 1.0E+19 n+
Substrate InP n+
Growth 381 398 399 635 638T CB (Å) 20 22 24 24 24
T ALT (Å) 20 20 20 22 24* UID stands for unintentionally doped
19
0
50
100
150
200
250
300
-1.5 -1 -0.5 0 0.5 1 1.5
381398399635638
Cur
rent
Den
sity
(nA
/µm
2 )
Bias (V)
TALB
= 1.9 nm
20 x 20 µm2 emitter
TALT
TCB
(nm)
20 2020 2220 2422 2424 24
Figure 3.2: Current density vs. voltage characteristics of the RTD growths 381-638,the growth variables being TCB and TALT . The bottom barrier thickness TALB beingfixed at 19 A.
the RTD epitaxial structures for growth 381 through 399 are symmetric. The 1
nm difference between the top and bottom AlAs layer thicknesses TALB, TALT , in
Table 3.1 is to account for the fact that the growth of the bottom AlAs barrier
requires opening the shutter for the Al source for the first time during the growth,
and owing to a higher Al flux, a shorter growth time is used, which is listed as a
thinner layer in the epitaxial run description in Table 3.1. The asymmetry in the I-V
characteristics shows, however, that the RTD structure is asymmetric, which can be
attributed to differences in top and bottom AlAs layer thicknesses. For a double-
barrier RTD structure, since an applied bias lowers the anode potential relative to
the cathode, lowering the effective height of the anode side barrier, it is the cathode
barrier thickness that primarily determines the peak transmission coefficient and
20
current. Thus the peak current for one bias polarity is determined by the thickness
of the barrier receiving the negative polarity for that bias. Applying this argument
to the triple barrier RTD, the larger reverse bias peak current suggests that the
top AlAs barrier thickness TALT is smaller than the bottom AlAs barrier thickness
TALB for all the growths. Though TALB has been set at 19 A for all the growths,
the lower forward bias peak current suggests that the actual bottom AlAs layer
thickness comes out to be thicker than TALT , possibly because of the high starting
Al flux during the bottom AlAs growth. The peak voltages are observed to vary
between growths 381 to 638, from 250 mV for growth 381 to 310 mV for 635, which
is a 25 % increase. Since the anode-cathode potential drops across a larger length
from growths 381 to 638 because of increased heterostructure thickness, a higher
potential needs to be applied to bring down the QW energy state into alignment
with the emitter states. The increase in the triple barrier structure (top AlAs to
bottom AlAs) thickness from growth 381 to 638 is about 5 %, and assuming a linear
voltage drop across the structure, is too less to account for the 25 % increase in the
peak voltage. Another explanation for the variation in the peak voltages could be
the shifts caused by a series resistance, and a variation in this resistance across the
growths could lead to uncertainties in the measurements in the peak voltages.
From growths 381 to 638, the peak current is expected to reduce monotonically
because of the increase in TCB and TALT . However this is not found to be the
case for growths 381 to 399, as observed from the trends in the reverse bias I-V
characteristics, summarized in Figure 3.3(a). Three measurements are taken for
each growth along the radius of a quarter of a 75 mm diameter wafer. Within the
variation across the sample, the change in the central InAlAs barrier thickness TCB is
observed to cause a 20 % increase in Jp, the peak current density, from growth 381 to
399. The changes in Jv, the valley current density and the PVR are relatively weaker.
21
0
50
100
150
200
0
2
4
1.9 2.1 2.3 2.5
PV
R
Center InAlAs barrier thickness (nm)
Pea
k re
vers
e c
urre
nt d
ensi
ty (
nA/µ
m2 )
20 x 20 µm2 emitter
JV
JP
PVR
381 398 399Growths
TALT
= 2 nm
0
50
100
150
200
0
2
4
1.9 2.1 2.3 2.5
Pea
k re
vers
e c
urre
nt d
ensi
ty (
nA/µ
m2 )
PV
R
Top AlAs barrier thickness (nm)
JV
JP
PVR
399 635 638Growths
TCB
= 2.4 nm20 x 20 µm2 emitter
(a) (b)
Figure 3.3: Dependence of the reverse bias peak and valley current densities andthe PVR on design parameters : (a) central InAlAs barrier thickness, and (b) topAlAs barrier thickness.
As a rough estimate, the transmission coefficient and the current can be assumed
to have an exponential dependence on TCB, i.e. Jp ∼ exp(−√
2m∗(Φ− E)TCB/~),
where m∗ and E are the electron effective mass and energy, respectively, Φ is the
height of the InAlAs potential barrier, and ~ is the reduced Planck’s constant.
Taking Φ as the difference between the InAlAs conduction band and the emitter
Fermi level equal to 0.37 eV from Figure 3.1 and m∗ = 0.09 the In0.52Al0.48As
effective mass [53], for an increase in TCB from 2 to 2.4 nm from growth 381 to 399,
the peak current should decrease by 32 %. Instead, Jp increases with TCB which
is surprising. If the presence of a device periphery leakage current increasing from
growth 381 to 399 is assumed to account for increasing Jp, then it is also expected
to raise Jv. Similarly, the presence of a defect assisted tunneling contributing to
the current also requires Jv to increase along with Jp. The lack of a noticeable
change in Jv with the increase in Jp rules out these possibilities, and the increase of
22
Jp with TCB remains an anomalous result. A stronger dependence of peak current
density Jp on the top AlAs barrier thickness TALT is shown in Figure 3.3(b), with
Jp reducing monotonically with TALT by 48 %, which is reasonably close to the
expected decrease of 70 % from the empirical relation in [52].
The dependence of valley current on top AlAs barrier thickness, TALT , is com-
paratively weaker than the peak current, see Fig. 3.3(b), Since the peak current
decreases more than the valley current, the PVR also decreases, from 3.2 to 2 for an
increase in TALT from 2 to 2.4 nm. The decrease in Jv compared to Jp suggests that
the valley current is dominated by thermionic emission current over the barriers,
which is independent of the barrier thicknesses.
From the I-V characteristics for growths 381-638, improvements in the RTD
structures are needed for application as TSRAM. At a maximum value of 3, the
PVRs are low. From the trend of Figure 3.3(b), increasing the barrier thickness
TALT to decrease Jv would further lower the PVR because of the comparatively
larger decrease in Jp. The low PVR of 3 observed in the triple-barrier InP-based
RTD heterostructures is consistent with the results of van der Wagt [40], which
showed a PVR of about 5 for comparable current densities. With the potential for
orders of magnitude higher PVR in the RITD, the exploration of TDs shifted to
interband tunneling junctions.
3.3 Resonant Interband Tunnel Diode
The effects of the barrier thicknesses and doping density on the electrical prop-
erties of the InAlAs-InGaAs RITD were explored, starting with a basic structure.
The device layer structure, Figure 3.4(a), is as follows, starting from the bottom:
n+ InP substrate, a 2000 A n-InGaAs collector contact, a 200 A n-InGaAs collector,
a 40 A InGaAs QW, a central InAlAs barrier (variable thickness), a 40 A InGaAs
23
QW, a 200 A p-InAlAs emitter, and a 800 A p-InGaAs emitter contact. The n
and p-dopants were Si and Be, respectively, and the doping densities for both the
n+ and p+ InGaAs contacts were 3×1019 cm−3; and the two QWs and the central
barriers were not intentionally doped.
p+ InGaAs
p+ InAlAs
n+ InAlAs
n+ InGaAs
Undoped InGaAs quantum well
Undoped InAlAs center barrier
Undoped InGaAs quantum well
Tunnel barrier
Valence band degeneracy
Conduction band degeneracy
Tunneling e
Tunnel barrier
Tunnel barrier
TCB
p+ emitterNA cm-3
n+ collectorND cm-3
EF
qvp=q(EV(Xp)-EF)
qvn=q(EF(Xn)-EC)
EC
EV
XnXp
qvp
qvn
(a)
(b)
Figure 3.4: InAlAs-InGaAs resonant interband tunnel diode, (a) layer structure and(b) energy band diagram.
24
The energy band diagram for the layer structure shown in Figure 3.4 will be
used to discuss how the barrier thicknesses and doping densities affect the tunneling
transport. As electrons tunnel from the n to the p side, there are as many as three
barriers in the tunneling path: the central interband tunnel barrier, and the two
heterojunction depletion barriers at positions Xp and Xn. To facilitate discussion,
the band degeneracies vp, vn are defined in Figure 3.4 at the edges of the InGaAs
QWs, at positions Xp and Xn. At these points, vp and vn are the differences between
the Fermi level and the valence and conduction band extrema, respectively. With
quantization the degeneracy will mean the difference between the Fermi level and
the QW ground state. The interband tunneling probability depends on the effective
EG and m∗, and the electric field in the central barrier. The tunneling current is
the product of this tunneling probability and the band alignment between valence
and conduction bands. While the band alignment is primarily dependent on the
doping densities which determine the degeneracies vp, vn, the electric field and the
tunneling probability depend on both the doping densities and the central barrier
thickness. The valley voltage can be approximated by the sum vp + vn. Since the
valley current, which is a combination of the forward biased p-n junction current,
and the defect-assisted tunneling excess current [44], both of which are dependent
on the valley voltage vp + vn, it is dependent on the doping densities. The peak
voltage is dependent on vp, vn by the following approximate relations from [54].
Vp = vmin for vmax ≥ 2vmin
Vp =vmax + vmin
3for vmax ≤ 2vmin (3.1)
where vmax and vmin are the larger and smaller of vp and vn, respectively.
25
Table 3.2
DOPING DENSITY AND BARRIER THICKNESSES FOR A SET OF FIVE
RITD WAFER GROWTHS, THE FILLED BOXES IN THE TABLE
HIGHLIGHT THE VARIATIONTCB N D N A N effGrowth IQE run# nm1 217755 2 3 3 1.52 217945 4 3 3 1.53 217946 4 1 3 0.754 217947 4 0.5 3 0.435 217948 4 0.5 1 0.331019 cm-33.3.1 Experiment Description
A set of 5 MBE wafers were grown by IQE Inc., Bethlehem, PA. The doping
densities NA and ND, and the central barrier thickness TCB were varied as indicated
in Table 3.2. The first two growths being epitaxially identical to the ones used in
[1, 2], respectively, serve the purpose of a control and have TCB as the variable.
From growths 2 to 5, the effective doping density Neff = NDNA/(ND + NA) is
monotonically decreased. The decreasing effective doping density Neff for growths
2-5 results in reducing band overlap and electric fields, and wider depletion region
barriers and reduced tunneling probabilities. From growths 1 to 5, both the electric
field and the band overlap decrease monotonically. Thus from growth 1 to 5, a
monotonic decrease in the valley voltage, current and the peak current is expected.
The devices were fabricated using a contact lithography and lift-off process. After
defining a Pd/Ti/Pd/Au emitter contact to the p-InGaAs, a wet etch in a 1 H2SO4 :
8 H2O2 : 160 H2O solution was done to form the device mesa. A Ti/Pt/Au contact
26
is then deposited on the backside of the n-InP substrate, which allows measuring
the devices from the top emitter contacts to the back of the wafer.
3.3.2 Current-voltage Characteristics
0
50
100
150
200
250
300
0 0.2 0.4 0.6 0.8 1Voltage (V)
Cur
rent
(m
A)
(a)
(b)
This work Growth 1
0
2000
4000
6000
0 0.2 0.4 0.6 0.8 1Voltage (V)
Cur
rent
(m
A)
This work Growth 1
Tsai 1994
This work Growth 2
Day 1993
Figure 3.5: Comparison of (a) growth 1 and (b) growth 2 I-V characteristics withidentical epitaxial structures by Tsai [2], and Day [1], respectively. The I-V charac-teristics for growths 1 and 2 have been scaled to compare with the device sizes in[2], Day [1], which were 150 and 100 µm diameter circles, respectively.
27
On repeating the structure growths of Day [1], and Tsai [2] in growths 2 and 1,
respectively, significant differences in the current magnitudes were found, as shown
in Figure 3.5. The devices shown in Figure 3.5 for growths 1 and 2 were 18 µm
dia circles, and in order to compare with the device sizes of 150 [2], and 100 [1]
µm circles, the I-V characteristics for growths 1 and 2 have been scaled by factors
(150/18)2, and (100/18)2, respectively. It can be observed that for growths 1 and
2, the current is a few orders of magnitude higher than reported in [1, 2].
Table 3.3
COMPARISON OF THE PEAK CURRENTS AND PVR FOR GROWTHS 1
AND 2 WITH DAY [1], and TSAI [2]Area (µm2) J P (µA/µm2) PVRThis Work 254 312 35Day 1993 7850 2 104Tsai 1994 17662 1 144This work 254 34 50Day 1993 7850 1.7 68Growth Structure 1Growth Structure 2A summary of the I-V characteristics comparison is shown in Table 3.3. For
apparently identical structures, Day and Tsai had reported a relatively close agree-
ment, with a factor of 2x in the peak current density, and PVRs of 104 and 144,
respectively and attributed to differences in “growth temperature and interface”.
In this work, for the same structure, the observed Jp is two orders of magnitude
higher at 312 µA/µm2, while the PVR is 35. Similarly for growth 2, the observed Jp
28
and PVR of 34 µA/µm2 and 50 are significantly different than observed by Day [1].
Apart from differences in the layer thicknesses, composition, and interfaces, as the
following discussion will show, the RITD I-V characteristics are significantly affected
by doping densities with a four order change in Jp for a 3x change in Neff ,, and
their uncertainties might be the reason for the I-V differences observed in Table 3.3.
Shown in Figure 3.6(a) are the computed band diagrams for the set of 5 RITDs,
and in Figure 3.6(b) the measured J-V curves for all 5 growths. The peak current
decreases monotonically from growth 1 to 5, as generally expected with decreasing
effective doping density, spanning over 5 orders of magnitude. The J-V characteris-
tics were corrected for series resistance as follows: from the I-V relation, the forward
current I is that of a forward-biased p-n junction, and increases exponentially (or
log(I), linearly) with voltage, with a slope of 60η mV/decade, η being the diode
ideality factor. Deviation of log(I) from the linear relationship is attributed to the
voltage drop across the series resistance consisting of contact resistances, geometrical
resistance of the n-InP substrate, resistance of the epi-substrate initiation interface
and resistance of the probe system. From this voltage drop ∆V for a current I, the
resistance is calculated as ∆V/I, and found to be under 5 Ω for all the devices, and
is 2-3 Ω larger than typical probe/contact resistances. For growths 1, 2 and 3, the
RITD oscillations in the NDR region were masked in Fig. 3.6(b).
Growths 4 and 5 are particularly interesting. No NDR is observed for growth 4,
whose I-V characteristics are that of a backward diode, while strong NDR is observed
for growth 5, which has a 3x lower p-doping density than growth 4. An explanation
for the different I-V shapes for growths 4 and 5 is found from the discussion by
Kane ([54], pages 85-86), of the dependence of the overlap between the electron and
hole states in a p-n homojunction TD on vp and vn. It has been showed that, for
the condition vmax ≥ 2vmin, where vmax, vmin are the larger and smaller of vp and
29
0 20 40 60
EF
4Growth
Position (nm)
5
-1
0
1
En
erg
y (e
V)
EF
InAlAsT
CB 4 nm
2
p+ InAlAsN
A 3
Growth
n+ InAlAs N
D
4p+InGaAs
n+InGaAs
1
10-7
10-6
10-5
10-4
10-3
10-2
10-1
-1 -0.5 0 0.5 1
Cur
ren
t D
ensi
ty (
mA
/µm
2 )
Voltage (V)
18 µmdiameter
Growth
2
3
4
5
1
120 mV
/decade
(a)
(b)
Figure 3.6: The effect of the structural variation on the device characteristics forgrowths 1-5, (a) Computed energy band diagrams using W. R. Frensley’s BandProf,(b) Current-voltage measurements after being corrected for the voltage drop acrossthe series resistance. For growths 1, 2 and 3, the data in the NDR region has beenmasked to remove data resulting from circuit oscillations.
30
vn, respectively, the electron-hole states overlap takes a trapezoidal or flat-topped
shape for forward bias. Physically it means that when the degeneracy of one band
is less than half the degeneracy of the other, the energetic width of the overlapped
states remains constant over a bias range corresponding to the crossing of the small
band degeneracy through the larger band degeneracy. Through this band crossing
the overlap density and the current does not change significantly. Applying this
argument for the QW degeneracies vp and vn for growths 4 and 5, it can be seen
that the condition of asymmetric vp and vn is satisfied for growth 4, where the p-
doping is six times higher than the n-doping but not in growth 5, where it is only
twice as high. As observed from the band diagrams of Figure 3.6(a), for growth
5, vp and vn are similar in magnitude, giving rise to a sharp NDR, for growth 4,
vp is significantly higher than vn, which can be expected to produce a flat-topped
backward diode I-V characteristic.
Despite the complexity of the heterostructure, the current magnitude is roughly
described by the analytic description of Kane [54], assuming a pure InGaAs p-n
tunnel junction. For a uniform junction electric field, the tunnel current density of
a p-n homojunction, assuming a triangular potential barrier is
Jt =qm∗R18~3
exp
−πm∗R
12EG
32
2√
2~qξ
(E⊥2
)D (3.2)
where,
D =
∫[f1(E1)− f2(E2)]
[1− exp
−2EsE⊥
]dE (3.3)
and m∗R the effective electron-hole reduced mass, ξ the electric field, E1 and E2
are the carrier energies measured from the n-conduction and p-valence band edges
respectively, f1 and f2 the Fermi distribution functions, Es is the smaller of E1 and
E2, and E⊥ =√
2~qξ/πm∗R12EG
32 . The integral in Eq. (3.3) is the effective density
overlap function D between the p and n-sides; the limits of integration are functions
31
of the applied bias and the p-valence and n-conduction band degeneracies vp and
vn, respectively. For growths 1-5, the tunnel current density for reverse bias can be
calculated using Eq. (3.2) in the following way, under reverse bias the band overlap
is just the difference between the Fermi levels between the p and n sides, equal to
qVa where Va is the applied voltage; the electric field can be found from the energy
band diagrams at the applied bias and a constant EG and m∗R can be assumed.
101
102
103
104
105
0.6 0.8 1 1.2 1.4
Cur
rent
den
sity
(A
/cm
2 )
Electric field (MV/cm)
Calculated for
Growth23
3
4
5
EG = 0.75 eV
Va = -0.2 V
m*R=0.089
1
Figure 3.7: Reverse bias tunneling currents for growths 1-5 plotted against themaximum electric field at the junction. The solid line is a curve fit using the methodof least squares to the data, using Eq. (3.2) to calculate the tunneling current.
In Figure 3.7 the measured tunneling current density and the calculated junction
electric field for growths 1-5 at a reverse bias of 0.2 V are shown. A least-squares
fit of Eq. (3.2) to the measured values is then found, with EG set to that of InGaAs
(0.75 eV), and using m∗R as the curve-fitting parameter, for which the fitted value
is found to 0.089. This reduced effective mass is larger than the reduced bulk
masses for both InGaAs and InAlAs, found from m∗ = memh/(me + mh)= 0.023
and 0.043, respectively, and calculated using isotropic Γ-valley electron and the light
32
hole conductivity masses for these materials [53]. The larger experimentally-fitted
mass could result from non-parabolicity of the band structure giving rise to higher
effective masses as energy increases. Overall the dependence of current magnitude
on the junction electric field are well described by this Kane formula.
The appearance of strong NDR for growth 5 and a backward diode I-V char-
acteristic for growth 4 points to the need of symmetrical p and n doping densities
as in growth 5, leading to comparable vp and vn and thus strong NDR. The effect
of symmetry in vp and vn on the I-V can further be understood by numerically
evaluating the overlap density integral D of Eq. (3.3) for different doping densities.
As an example, consider an InGaAs homojunction p-n diode with degeneracies Vp,
Vn. If Vp, Vn are varied by changing the doping densities such that the sum Vp + Vn
is constant, then there is no change in the built-in voltage and the electric field,
so that the current density Jt ∝ D (see Eq. (3.2)) and the dependence of the J-V
characteristics on Vp and Vn is described by D vs. Va characteristic. In Figure 3.8,
the computed overlap density D at 300 K is plotted as a function of bias for three
different p, n doping densities. The valley voltage Vp+Vn is set to 0.3 V. The details
of the calculation are as follows: D is found by a trapezoidal numerical integration
method, the band degeneracies are calculated by using the Joyce-Dixon polynomial
expressions for the energy distribution function [55], the depletion approximation is
used to find the junction electric field, and the InGaAs material parameters have
been taken from [56]. It can be seen that for qVn = qVp = 0.15 eV, D has a trian-
gular profile in the forward bias, sharply peaking at the bias 0.15 V, while making
Vn, Vp asymmetric results in trapezoidal profiles for D. This shows that to get a
strong NDR, it’s necessary to have a doping densities that result in symmetric band
degeneracies .
A summary of the peak and valley voltages, currents, and PVR vs. growth
33
-0.058
0
0.058
0.12
0.18
0.23
-0.1 0 0.1 0.2 0.3
Effe
ctiv
e st
ates
ove
rlap
D (
eV)
Voltage (V)
p-n InGaAs homojunctionV
n+V
p = 0.3 V
T = 300 K
ND=3.8e18
NA=4.2e19
ND=3e18
NA=6e19
ND=2.3e18 cm-3
NA=8.4e19 cm-3
Vn= 0.15 eV
Vn= 0.12 eV
Vn= 0.09 eV
Figure 3.8: Computed effective overlap density integral D as a function of bias fordifferent doping densities.
is provided in Figure 3.9. From the computed energy band diagrams, the QW
degeneracies vp and vn are found and are used to find an estimate for Vv = vp + vn
and Vp from the relations in Eq. 3.1, and are plotted in Figure 3.9.
By reducing the effective doping density alone from 1.5 (growth 2) to 0.3×1019
cm−3 (growth 5), the valley current reduces by more than three orders of magnitude
to 0.3 nA/µm2 for growth 5. The reduction in the valley voltage is also signifi-
cant, from 780 mV for growth 1 to 290 mV for growth 5. The measured Vp and Vv
are observed to follow the predicted trend reasonably, though their values are typi-
cally larger than calculated, which could be due to uncertainties in the corrections
for the series resistance, which shifts the measured peak and valley voltages. The
sharp increase in the calculated Vp for growth 3 is because it’s the only growth in
the set for which the relation vmax ≤ 2vmin holds, which leads to a maximum in
the band alignment at a larger bias Vp = (vp + vn)/3. From the 120 mV/decade
34
10-1
101
103
105
0
50
100
150
200
Cur
rent
den
sity
(nA
/µm
2 )
Jp
PVR
PV
R
Jv
0
0.4
0.8
Vol
tage
(V
)
Growth1 2 3 4 5
Blue - peakRed - valley
Marker- measured Line - calculated
(a)
(b)
Figure 3.9: (a) Peak, valley current densities and PVR, and (b) peak and valley forgrowths 1-5 .
slopes of the post-valley currents of all growths in Figure 3.6(b), the post valley I-V
characteristics are well described by the forward biased p-n InAlAs diode current.
The valley current then depends on the value of the valley voltage, approximately
Jv ∝ exp(qVvalley/2kBT ), kB being the Boltzman’s constant. Since the valley volt-
ages decrease from growths 1 to 5, the valley current also decreases. The change in
the PVR is not monotonic and it peaks at a value of 70 for growth 2, decreasing to
14 for growth 5, showing that the decrease in Jp is larger than that of Jv.
35
3.3.3 Matching RITDs to TSRAM MOSFETs
10-12
10-11
10-10
10-9
10-8
10-7
10-6
10-5
10-4
0 20 40 60 80 100
Cur
rent
(A
)
Min. feature size F (nm)
RITD 1 35 Growth PVR
HP
LOP
Markers - IG+I
OFF
Line - (Jp - J
v) F2
RITD 2 69RITD 3 50
RTD 399 3
RITD 5 14
Figure 3.10: The difference in the peak and valley currents for a diode area F2 afunction of the minimum feature size F, compared against the high performance(HP) and low operating power (LOP) CMOS transistor leakage currents.
A comparison of the range of currents achieved for the RTD and RITD growth
sets with the Si-MOSFET leakage currents is made in Figure 3.10. As discussed
in Section 2.3, the difference in the peak and valley currents need to exceed the
transistor leakages. The comparison shows the difference in peak and valley currents
(Jp−Jv)F2 for RITD growths 1, 2, 3, and 5 and the RTD growth 399 plotted against
the transistor technology feature size F, the sum of the transistor leakages IG, IOFF
from Figure 2.7 are plotted for comparison. For the RITD growth 4, since the peak
and valley currents were approximately the same, the currents are not plotted in
Figure 3.10. For the RTD growth set discussed in Section 3.3.2, because of the
relatively small variation in currents, growth 399 is a good representative of the
growth set. It is observed that the range of Jp, Jv for the TD growth sets envelopes
the transistor leakages with future scaling and can be used to match to transistors
36
with both higher and lower leakages. Of the growth set, RITD growths 2 and 3,
which have the highest PVR of the set at 69 and 50, respectively are observed to be
the closest to the transistor leakages. A possible future research direction therefore
could be further exploration of these two structures to maximize the PVR.
3.3.4 Capacitance-Voltage Characterization
For an RITD heterostructure, capacitance-voltage (C-V) characteristics are im-
portant to understand the charge separation across the junction. The diode capaci-
tances for growths 1-5 were measured from the small signal impedance of the diodes
as a function of bias in an Agilent 4294A Precision Impedance Analyzer, and using
a two-element parallel conductance-capacitance (G-C) model. In this technique,
the accuracy of the capacitance extracted C requires that the magnitude of the ca-
pacitive admittance |Y | = ωC = 2πfC, f being the measuring frequency is large
compared to the parallel conductance G, or in other words, the phase angle θ of
the measured admittance |Y |∠θ needs to be close to 90. This is because for given
measurement conditions such as voltage stimulus level, averaging, etc, the measure-
ment system has an uncertainty ∆θ. Since the relative error ∆θ/θ is dependent on
θ and is infinite at θ = 0, and a minimum at θ = 90, the resulting errors in C are
lowered with increasing θ.
The extracted conductance and capacitance for growths 1-5 as a function of the
bias for a 500 kHz, 10 mV stimulus are shown in Fig. 3.11. The measurements were
done top-to-chuck, i.e. by putting one probe on the top emitter contact and the other
probe on the wafer chuck. An open-short-50 Ω-load calibration was performed using
the Cascade Microtech 106-683 impedance standard substrate. A measurement av-
eraging factor of 8 was used at every bias point. Current-voltage measurements were
also done simultaneously, shown in Fig. 3.11(a). In Figure 3.11(b), the measured
37
10-8
10-6
10-4
10-2
18 µm diameter
Growth 12
3
4
5
Cur
rent
(A
)
10-8
10-6
10-4
10-2
100
Markers-4294A data
Growth 1
34
5
2
Lines- dI/dV
G (
S)
0
1
2
3
4
5
-0.2 0 0.2 0.4 0.6 0.8
4
5
C (
pF)
Bias (V)
10 mV, 500 kHz
Marker - MeasuredLine - Calculated
4
5
(a)
(b)
(c)
Figure 3.11: Current-voltage characteristics and small-signal parallel conductanceand capacitance as a function of bias for growths 1-5. The markers and lines in (b)represent the measured conductance (markers) and the I-V extracted conductance(lines); the solid markers denote the NDR region
38
small signal conductance G is compared with the differentiated conductance GIV
obtained from the I-V characteristics, with solid markers denoting the values in the
NDR region. It’s observed that except for growth 1, the highest conductance diode,
the agreement between G and GIV is good for the bias range. In Figure 3.11(c),
the measured capacitance for growths 4 and 5 is plotted as a function of bias. For
growths 1-3, the phase angle θ for the entire bias range was found to be too close
to 0, and the capacitance couldn’t be extracted accurately (they come out to be
negative).
An estimate for the capacitances of growth 4 and 5 can be made from the junction
depletion width. For simplicity, the depletion approximation and non-degenerate
doping conditions are assumed to provide a rough estimate. The junction capaci-
tance is
C = Aε1/W (3.4)
where ε1 is the InAlAs dielectric constant, A is the area and W the effective width
of the depletion region. If TW and ε2 are the InGaAs QW thickness and dielectric
constant, respectively, and tp and tn are the widths of the p and n depletion regions,
respectively, W can be found from
W = tp + tn + ti = tp(1 +ND/NA) + ti (3.5)
where the intrinsic layer ti = TCB + 2TW ε1/ε2. For an applied bias Va, the voltage
drop across the junction can be calculated as,
Vbi − Va − 2kBT/q = ξ
(ti +
tp2
(1 +
NA
ND
))(3.6)
where Vbi is the built-in voltage. Substituting ξ = qNAtp/ε1 in Eq. (3.6), and solving
for tp, we get,
tp =
√X2 + 4Y +X
2(3.7)
39
where,
X =2tiND
ND +NA
Y =2ε1ND
qNA(ND +NA)(Vbi − Va − 2kBT/q) (3.8)
Using the energy band diagrams to compute Vbi, C is found from Eqs. (3.7), (3.4)
and (3.5), and is plotted in Figure 3.11(c).
From Figure 3.11(c), it can be observed that the forward bias capacitance is sig-
nificantly larger than the calculated p-i-n heterojunction capacitance. The higher
observed capacitance suggests that the charge separation distance is less than de-
pletion width, which is consistent with the fact that in forward bias, the QW charge
changes with bias because of electron and hole injection from the n and p sides,
respectively. Another reason for the higher measured capacitances could be the un-
intentional doping in the intrinsic layer, which can lead to smaller depletion widths.
An upper limit for the capacitance can be found by considering that the minimum
effective charge separation distance is the central barrier thickness 4 nm, giving
a value of 7 pF for the diode area (254 µm2), which is approximately twice the
measured values of the capacitance.
3.3.5 Temperature Dependence of the I-V
Measurement of the temperature-dependence of the I-V characteristics was un-
dertaken to understand the valley current and PVR in these RITDs. The post-valley
current is composed of a thermionic component plus, according to Chynoweth [44]
a defect-assisted tunnel current Jx component (in Si). The diode current is the sum
of the diffusion and recombination currents, given as, for qVa kBT ([57], pages
40
84-92),
JD = NCNV
(Dn
LnND
+Dp
LpNA
)e(qVa−EG)/kBT
+qW
2σvthNtNCNV e
(qVa−EG)/2kBT (3.9)
where W is the depletion region width, Dn and Dp are the n and p-minority carrier
diffusion coefficients, Ln and Lp are the n and p minority carrier diffusion lengths,
NC , NV are the conduction and valence band effective density of states, σ is the
electron-hole capture cross section, vth is the thermal carrier velocity, and Nt is the
trap density. The first term in Eq. (3.9) is the diffusion current density Jdiff and is
associated with a 60 mV/decade slope in the log(Jdiff ) vs. Va characteristic. The
second term is the recombination current density Jrec, and is associated with a 120
mV/decade slope in the log(Jrec) vs. Va characteristic. From the 120 mV/decade
post-valley currents in Figure 3.6(b), it is observed that Jrec is the dominant diode
current. Neglecting the temperature dependence of W =√
2ε(EG + vp + vn)/qNeff
and vth =√
3kBT/m∗ compared to the exponential relation, JD can be described as
∝ e(qVa−EG)/2kBT . On the other hand, the dependence of Jx on temperature is due
to the change in the indirect bandgap with temperature, and has been shown to be
weak compared to an exponential relation in Si [44]. Thus from the temperature
dependence of Jv, the contributions of JD and Jx on the valley current can be
established.
The temperature-dependent I-V characteristics for a 0.75×0.75 µm2 diode of
growth 5 are shown in Figure 3.12. As the temperature is lowered from 300 to
77 K, a monotonic decrease in the valley current and a small increase in the peak
current is observed. The increase in the peak current with lowering temperatures
is consistent with a sharper energy distribution. The Arrhenius plot of the cur-
rent at different post-valley voltages is shown in Figure 3.13. The valley currents
41
0
1 10-9
2 10-9
3 10-9
0 0.2 0.4 0.6 0.8 1
77 K127 K187 K237 K287 K300 K
Cur
rent
(A
)
Voltage (V)
Growth 5
0.75 x 0.75 µm2
Figure 3.12: Effect of temperature on the growth 5 tunnel diode I-V characteristic
tend to follow an exponential relation with 1/T for higher T and saturate as T is
lowered. This is consistent with the valley current having a component JD that is
exponentially dependent on T and a component Jx which is almost independent of
temperature. The dependence of Jv on temperature shows that at low temperatures
it is dominated by the excess current Jx, and with rise in temperature JD becomes
significant. From Figure 3.13, the slopes M for Jv vs. 1000/T curves for the highest
three temperatures can be found, from which EG can be calculated from the relation
log(Jv) ' log(JD) ∝ (qVa − EG)/2kBT as EG = Va + 2000kBM . This calculation
for Va=0.4, 0.6, 0.8 and 1 V gives EG = 0.76, 0.90, 1.04, and 1.23 eV, respectively,
which is in reasonable agreement for the bandgaps of InGaAs (0.75 eV) and InAlAs
(1.49 eV ).
42
10-2
10-1
100
101
102
0 2 4 6 8 10 12
Val
ley
curr
ent d
ensi
ty (
nA/µ
m2 )
1000/T (K-1)
0.8 V
0.6 V
0.4 V
Va = 1 V
Figure 3.13: Arrhenius plot of the valley current of growth 5 at different valleyvoltages.
3.3.6 Alloy Composition Experiment
From the relation Jv ∝ e(qVa−EG)/2kBT , it is clear that the bandgap EG is a
significant parameter for the valley current. The bandgap also affects the peak
current according to Eq. (3.2). To determine if an increase in EG would decrease the
valley current by a larger proportion than the peak current, leading to a higher PVR,
ways to increase EG by changing the InAlAs material composition were explored.
A new set of epitaxial structures was designed using the InAlAs alloy composition
as a variable. Since changing the alloy composition from the lattice-matched values
results in an epitaxial strain and increases the growth complexity, as a first step,
43
only the top p-InAlAs alloy composition was changed. Regrowing the lowest current
density device structure of growth 5 as the control growth 6, the mole fraction x
in p-InxAl1-xAs was reduced from the lattice-matched value of 0.52 to 0.48 and
0.44 in a set of 3 growths, shown in Table 3.4. From the computed energy band
diagrams, the corresponding increase in EG are 140 and 220 meV, respectively from
the lattice-matched value.
Table 3.4
ALLOY COMPOSITION VARIATION IN THE SECOND RITD WAFER
GROWTH SET, THE SHADED BOX SHOWS THE VARIATIONIQE N D N A T CB EGGrowth run# nm n p eV6 218119 1 3 4 x=0.52 x=0.52 1.457 218149 3 3 4 x=0.52 x=0.48 1.598 218152 1 3 4 x=0.52 x=0.44 1.671019 cm-3 In xAl 1-xAsUsing a contact lithography-based process described previously, diodes were fab-
ricated for the new epitaxial structures. The I-V characteristics each for growth 5
and 6, which are epitaxially identical, and grown under the same nominal conditions,
is shown in Figure 3.14, for three devices across a sample area of roughly 1×1 cm2
for each sample. A double bias sweep is used for the measurements, which shows
a small hysteresis in the reverse direction for one of the RITDs for growth 5. The
high sensitivity of the heterostructure to growth conditions is again observed, by the
decrease in both the peak and valley current densities from growth 5 to 6, which are
grown about 6 months apart. For growth 6, the valley current is reduced by an order
of magnitude to 0.07 nA/µm2, which is the lowest value ever reported for TSRAM
44
TDs. The valley voltage is also reduced to 250 mV. However, there is a degradation
of the PVR from 14 for growth 5 to 4 for growth 6, because of a proportionately large
decrease in the peak current. From Figure 3.14, wafer radial variations are small in
growths 5 and 6. The difference must lie in the layer thicknesses and doping den-
sities, and/or other factors affecting the epitaxial quality like interface roughness,
point defect production and background impurity incorporation.
10-2
10-1
100
101
102
103
104
105
-1 -0.5 0 0.5 1
Cur
rent
Den
sity
(nA
/µm
2 )
18 µm dia
3 devicesmeasured
across 1x1 cm2
double sweep
5
Identicalgrowthstructures
20x20 µm2
6
Voltage (V)
Figure 3.14: Current density vs. voltage characteristics for identical device struc-ture growths 5 and 6, grown about 6 months apart. The difference in the I-Vcharacteristics for the same growth is significantly larger than the linear variation.
The effects of the p-InAlAs In mole fraction x on the I-V characteristics is shown
in Figure 3.15. Surprisingly, the peak and valley current densities for both x=0.48
and x=0.44 were raised relative to the lattice-matched InAlAs composition of growth
6. The highest PVR for x=0.48 and x=0.44, are only marginal higher at 8 and 9
respectively from the value of 4 for the control growth 6. With an increase in Vbi (see
Figure 3.15(a)) and the electric field in the intrinsic region from growth 6 to 8, an
45
Ef
NA=1x1019 cm-3
0.14 eV
ND=5x1018 cm-3
4 nm0.22 eV
∆EG
(a)
(b)
10-2
10-1
100
101
102
-0.2 0 0.2 0.4 0.6 0.8 1
Cur
rent
Den
sity
(nA
/µm
2 )
Voltage (V)
20x20 µm2
Black 0.52 0Blue 0.48 0.14Red 0.44 0.22
x ∆∆∆∆EG(eV)
Growth 6
8
7
Figure 3.15: The effect of the p-InxAl1-xAs alloy composition variation on the de-vice characteristics (a) Computed energy band diagrams using W. R. Frensley’sBandProf, (b) Current density vs. voltage measurements.
increase in the peak current is expected. The increase in the zero bias electric field
in the intrinsic region, calculated from the energy band diagram is from 0.77 to 0.79
MeV/cm. From the calculated tunneling current vs. electric field characteristics in
Figure 3.7, this increase should lead to about 30 % increase in the tunnel current,
which doesn’t adequately account for about an order of magnitude increase in the
peak current observed in Figure 3.15(b). The increase of the peak current with
46
decrease in x is also contrary to the effect of stress in the lattice; with increasing x,
the reducing lattice constant in InxAl1-xAs results in a tensile stress in the InGaAs
QW in the direction parallel to the current flow. Zhao ([58], pages 84-85) has
shown that in both GaAs and InAs, the effect of a tensile stress in the direction of
the current flow results in a decrease in the peak tunneling current, which should
also be expected for InGaAs. An explanation for the increase in the peak current
could be the variability in the doping density with the p-InAlAs alloy composition,
compared to the lattice-matched growth. A possible reason for the increase in the
valley current for x=0.44 could be the strain and dislocation density because of
the p-InAlAs layer, as its thickness of 200 A is more than twice the critical layer
thicknesses of 98 A for x=0.44, calculated by the Matthews-Blakeslee formula [59].
For x=0.48, the calculated critical layer thickness is 225 A, barely larger than the
InAlAs layer thickness. Dislocations due to strain would lead to an increased defect
density in the p-InAlAs and a larger excess current. The increase in the PVR with
EG shows that its effect on the tunneling current is stronger than its effect on the
thermionic and excess currents.
3.3.7 0.25 V Tunnel Diode Memory
The low peak and valley voltages of the TDs for growth 5 enable supply voltages
as low as 0.25 mV in a series TD pair used in a TSRAM cell, shown in Fig. 3.16. The
growth 5 valley current density of 0.3 nA/µm2 is in the same range of the previous
best results of 0.125 and 0.6 nA/µm2 by Jin [24] and van der Wagt [40], respectively,
with a significantly higher PVR of 14 compared to 1.6 and 3, respectively.
In summary, two InP-based TD structures, the RTD and the p-n RITD were ex-
plored for application in TSRAM cells. The effects of the epitaxial layer thicknesses,
doping densities and alloy composition on the device properties were established
47
0
1
2
3
4
5
0 0.1 0.2 0.3C
urre
nt d
ensi
ty (
nA/µ
m2 )
250 mV
Bias (V)
Growth 5
PVR 14 VTDVTD
Figure 3.16: Load line diagram for a growth 5 tunnel diode pair connected in series,needing a supply voltage of only 0.25V for bistable bias points.
through I-V and C-V measurements. In the InAlAs-InGaAs RITD structure, the
doping density can be used to engineer tunnel currents over 5 orders of magnitude.
This tuning was achieved by changes in the effective doping density from 1.5 to
0.33 ×1019 cm−3, and so requires precise doping control. Tunnel diodes with val-
ley voltages and current densities as low as 0.25 V and 0.07 nA/µm2, respectively,
were demonstrated, and would allow the construction of TSRAM cells with supply
voltages scaled down to 0.25 V. The range of TD currents achieved were shown to
encompass the design space for matching with CMOS transistor leakages. The effect
of temperature and alloy composition on the device properties were studied.
48
CHAPTER 4
TUNNEL DIODE AND TRANSISTOR FABRICATION PROCESSES
This chapter describes fabrication processes for TD/transistor devices and cir-
cuits, and TSRAM RITD submicron devices, including an approach for self-aligned
HBT base-emitter and the RTD emitter-collector contacts employing dielectric spac-
ers and a BCB etch-back. With this self-aligned process, access resistances in HBTs
and RTDs can be reduced with metal separation determined by the dielectric spacer
thickness. Wet and dry reactive ion etches (RIE) and post RIE surface cleans are
also discussed. Electrical characterization of discrete HBT and RTDs fabricated us-
ing this process are presented. The spacer formation and BCB etch-back processes
are also used in developing the submicron device process for InGaAs-InAlAs RITDs,
and the effects of submicron scaling on the RITDs are studied.
4.1 InP-Based Tunnel Diode and Transistors
An InP-based material system was adopted to fabricate the RTD and HBT-
based circuits because of the high performance of InP-based RTDs and HBTs.
Shown in Table 4.1, and Figure 4.1 are representative layer structure and en-
ergy band diagrams for the RTD and HBT structure used in these studies. InP-
based AlAs/InGaAs/InAs RTDs have high uniformity [60] good design flexibility for
achieving high current density and low peak voltage [61], an important aspect for low
power applications. InP-based double heterojunction bipolar transistors (DHBTs)
49
have been demonstrated with simultaneously high current gain cut-off frequencies,
ft and fmax = 560 GHz [13], and high breakdown voltages BVCEO ≥ 6 V [15]. Of
the two InP HBT systems being widely investigated currently, the InP/GaAsSb/InP
HBT has a preferable “type II” staggered band alignment compared to the “type
I” straddling band alignment of the InP/InGaAs/InP DHBTs.
Table 4.1
HBT/RTD LAYER STRUCTURE GROWN BY MOLECULAR BEAM
EPITAXY BY INTELLIGENT EPITAXY OF RICHARDSON, TEXAS
Layer Material xThickness
(Å) Dopant
Density
(/cm3) Type
Emitter In(x)Ga(1-x)As .53 400.0 Si 3.0E+19 n+Emitter In(x)Ga(1-x)As .53 50.0 Si 2.0E+18 n+
In(x)Ga(1-x)As .53 20.0 UID - iBarrier AlAs 16.0 UID - i
In(x)Ga(1-x)As .53 14.7 UID - iNotch InAs 21.3 UID - i
In(x)Ga(1-x)As .53 14.7 UID - iBarrier AlAs 16.0 UID - i
In(x)Ga(1-x)As .53 20.0 UID - iHBT emitter In(x)Ga(1-x)As .53 50.0 Si 1.0E+18 n+HBT emitter In(x)Ga(1-x)As .53 600.0 Si 1.0E+19 n+HBT emitter InP 250.0 Si 3.0E+19 n+HBT emitter InP 500.0 Si 3.0E+17 n
Base GaAs(x)Sb(1-x) .51 400.0 C 5.0E+19 p+InP 1,500.0 Si 2.0E+16 n-
SubCollector In(x)Ga(1-x)As .53 100.0 Si 3.0E+19 n+SubCollector InP 2,000.0 Si 3.0E+19 n+
etch stop In(x)Ga(1-x)As .53 100.0 UID - iSubstrate InP
The latter straddling alignment introduces a barrier to electrons moving into
50
-3
-2
-1
0
1
2
0 100 200 300 400 500
Ene
rgy
(eV
)
Position
RTD HBT
Ef
Figure 4.1: Energy band diagram of an InP-based RTD/HBT structure, computedusing W. R. Frensley’s BandProf. The resonant tunnel diode is grown above theheterojunction bipolar transistor, in the same epitaxial growth sequence.
the collector from the base which must be eliminated to achieve current gain at low
collector biases. Although the effects of this electron barrier in InP/InGaAs/InP
can be overcome by base-collector step-grading schemes [62, 63], in this research,
the InP/GaAsSb/InP system was adopted for its simple band alignment and since
it has been less explored compared to the InP/InGaAs/InP HBT.
4.2 Self-Aligned HBT/RTD Contact Process
Self-aligned HBT emitter-base contact processes allow the emitter-base separa-
tion to be set to a value that is independent of the lithographic limits, the benefit of
which is a decrease in the extrinsic base resistance which leads to a higher maximum
power gain frequency fmax of the device. Similarly. for RTDs, reducing the extrinsic
collector series resistance leads to a higher TD fmax (see the discussion in Appendix
51
A). Two commonly used self-aligning methods for HBT base-emitter contacts are,
(a) undercut and lift-off [64, 65] and (b) use of dielectric spacers [66, 67, 68, 38].
In the former method, the base-emitter separation is determined by the extent of
the undercut during the wet etch of the emitter mesa, and as low as 50 nm of base-
emitter separation has been achieved [69]. In the later method, a dielectric spacer
is first created around the emitter mesa by conformal deposition and subsequent
anisotropic etch of a dielectric film. Then the base contact is defined using methods
such as selective electroplating [68], base regrowth [66, 67], etc. As a manufacturable
technology, the dielectric spacer method is preferable as it avoids the yield-limiting
issues encountered in an undercut and lift-off process: (a) excessive undercut lead-
ing to lifting-off of narrow emitters, and (b) base-emitter short-circuits. Cut-off
frequencies ft, and fmax in excess of 300 GHz have already been demonstrated [38]
in a manufacturable technology, using dielectric spacers of about 200 nm thickness.
The dielectric-spacer self-aligned approach is limited only by the thickness of the
spacer that can be formed, which can be as thin as a dielectric monolayer, and as
low as 25 nm spacers have been demonstrated [13].
In this research, a self-aligned contact process employing dielectric spacers and
an etch-back process1 is developed, where the base contact is formed by a blanket
metal deposition followed by a dry etch to remove it from the top of the emitter
mesa, with a flowable dielectric benzocyclobutene (BCB)2 as an etch mask. A scaled
drawing of the process is shown in Figure 4.2. The emitter contacts are formed by
a lift-off metallization process. After etching the emitter mesa, using the emitter
contacts as the etch mask, a conformal SiO2 or Si3N4 layer is formed by plasma-
enhanced-chemical-vapor-deposition (PECVD). The sidewall dielectric spacers are
formed by an anisotropic RIE in fluorinated plasmas. This is followed by a blanket
1Extends the studies of Qingmin Liu, formerly at University of Notre Dame, IN.2Cyclotene 3022-35, advanced electronic resin, the Dow Chemical Company.
52
Ti/AuHBT emitter
collectorbase
200 nm
spacerTi/Au
TungstenTi/Au
Ti/AuTungsten
BCB
BCB
Ti/AuTungsten
Tungsten
200nm
spacerTi/AuHBT emitter
collectorbase
(a)
(b)
(c)
(d)
(e)
(f)
Figure 4.2: Self-aligned HBT emitter-base contact process using BCB etch-back,drawn to scale with 2 µm emitter width .
53
deposition of the W base contact metal, shown in Figure 4.2(c). The sample is then
spin-coated with BCB and cured in an inert environment to reflow the BCB and
improve the planarization. The BCB is reactive- ion etched in SF6/O2 plasma to
expose the emitter metal, Figure 4.2(e), followed by RIE of the base metal with
SF6 selectively as the base contact metal everywhere else is protected by the BCB,
the etch selectivity of W to BCB being about 10:1. The BCB is removed by RIE
in SF6/O2 to reveal the base contact metal, which is separated from the emitter
contact by the dielectric spacer shown in Figure 4.2(f), and is then patterned to
define the base contacts. The base contact metal also serves as the RTD collector
contact, which is defined in the same self-aligned process step.
The HBT collector contacts are defined using a lift-off process. Semiconductor
etches are used to define device mesas and provide device isolation. The schematic
cross-section of the fabricated HBT and RTDs is shown in Figure 4.3. A resistor
and metal-dielectric-metal capacitor process are also included. A detailed drawing
of the process is described in Appendix B. A GCA-6300 wafer-stepper-based mask
set has been designed to construct RTD and HBT-based devices and circuits. The
frequency estimates for the RTD and HBTs for the self-aligned process are provided
in Appendix A.
4.2.1 Dielectric Spacer Process
To form a dielectric sidewall spacer, it’s necessary to have anisotropic dielectric
RIE processes. Silicon dioxide (SiO2) [38] and silicon nitride (Si3N4) ([68, 13]) are
two commonly used dielectrics for spacer formation. The Si3N4 reactive-ion etch
processes of this investigation stem from the work or Hicks et al. and Mele et al.
using fluorinated plasmas [70, 71].
The Si3N43 deposition was done in an Unaxis 790 PECVD system, and a parallel-
3The stoichiometry of the silicon nitride in this process was not confirmed
54
W400 nm
Ti/Pt/Au
Spacer 200 nm
Ti/Pt/Au
150 nm
InP Substrate
WTi/Pt/Au W W
InGaAs Subcollector InGaAs Subcollector
RTD
GaAsSb Base
InP Emitter
InP Collector 150 nm
InGaAs
RTD HBT
InP Subcollector
Figure 4.3: Schematic cross-section of adjacent HBT and RTDs on InP.
plate PlasmaTherm-790 RIE system (electrode diameter 23.4 cm) was used for the
etching. The deposition conditions were SiH4/NH3/N2 4/4/36 sccm, 500 mTorr, 200
W, 250 C. A number of etch recipes were explored, and characterized with etch
rates listed in Table 4.2. To find the etch rate, Si3N4 films on pilot Si samples were
patterned with AZ-1813 photoresist as the etch mask and were etched for different
times. After removing the photoresist, the samples were step-profiled to give the
etch depth, and a least squares linear fit to the etch depth vs. etch time curve was
used to find the etch rate. The etch depth versus time characteristic for the SF6/Ar
recipe is shown in Figure 4.4. The different values of the etch depths for the same
etch time correspond to measurements at different positions on the same sample. In
Figure 4.4, the least squares fit to the data is shown by the black line. Figure 4.4 also
shows a way to calculate the uncertainty in the etch rate from the uncertainty in the
etch depths. For subsequent process development, the SF6/Ar etch conditions were
selected for the its higher etch rate, and also to avoid the deposition of carbonaceous
55
surface films that can be formed in carbon-fluorine-based plasmas such as CHF3 or
CF4 [72].
Table 4.2
PLASMA-ENHANCED-CHEMICAL-VAPOR-DEPOSITION AND REACTIVE
ION ETCH CONDITIONS FOR SILICON NITRIDE
Growth Conditions
Etch Gases Etch ConditionsEtch Rate
(Å/s)
SF6/Ar 2/18 sccm, 15 mTorr, 160 W, 400 V 18
CHF3/SF6/Ar 5/5/40 sccm, 40 mTorr, 60 W, 200 V 13
CHF3/O2/Ar 15/5/30 sccm, 40 mTorr, 57 W, 200 V 7
CHF3 20 sccm, 15 mTorr, 250 W, 470 V 5
CHF3/Ar 5/35 sccm, 20 mTorr, 50 W, 200 V 3
SiH4/NH3/N2
(4/4/36 sccm), 500 mTorr, 200
W, 250 ºC
Silicon nitride sidewalls were formed on lifted-off 300 nm Ti/Au metal patterns
on a GaAs sample (quarter of a 75 mm wafer), by depositing PECVD Si3N4 and
etching in SF6/Ar. The deposited Si3N4 thickness was 300 nm. To ensure that the
nitride is not under-etched, an etch time longer than the required time, calculated
as the ratio of the nitride thickness and etch rate, was used. The over-etch factor,
defined as the ratio of the etch time used to the expected time to complete the
etch, was set to 1.15. A scanning electron microscope (SEM) micrograph shows
the nitride sidewall formed after RIE on the side of Ti/Au metal, Figure 4.5. The
wafer was cleaved through the metal to create this cross-section; a short section of
the nitride has broken off during the cleave. From the SEM, the thickness of the
nitride sidewall can be estimated to be approximately 150 nm, which is half of the
56
0
500
1000
1500
2000
2500
3000
0 20 40 60 80 100 120 140 160
Etc
h de
pth
(Å)
Time (s)
Etch of PECVD Si3N
4 in
SF6/Ar 2/18 sccm
15 mT, 160 W, 400 V18 Å/s
17 Å/s
22 Å/s18
Figure 4.4: Silicon nitride etch depth as a function of time in an SF6/Ar plasma.
deposited Si3N4 thickness. This suggests that the SF6/Ar RIE is etching laterally
with an etch rate that is approximately half of the vertical etch rate.
The SF6/Ar RIE was used in the InP-based HBT/RTD fabrication process to
form spacers on approximately 4000 A tall HBT and RTD emitter mesas, sitting
on the GaAsSb base, using identical PECVD deposition condition and thickness
as described above. The in-process SEM micrographs of emitter patterns after the
formation of spacers are shown in Figure 4.6((a)-(d), top view, (e), (f) viewed at
45 to the vertical), for six different process runs. To keep the vertical component of
the RIE the same, prior to the nitride etch, the RIE RF power was adjusted to give
the same DC bias of 400±5 V, the necessary change in the RF power was about 50
% at maximum. Using Si3N4 on Si pilot wafers, etch depth vs. etch time data were
generated and the etch rate was calculated from the least squares fit. An over-etch
57
Ti/Au
Nitride sidewall
GaAs surface
Figure 4.5: Scanning electron micrograph of a Si3N4 sidewall on a GaAs substrate .
factor of 1.15 was used for etching the HBT/RTD wafers.
In Figure 4.6(a), which shows a 2×2 µm2 emitter with a 175 nm wide nitride
spacer, the presence of a debris on both the Ti/Pt/Au emitter and the GaAsSb
is observed. This debris is there in the samples of Figures 4.6(b), (c), (e) and (f)
but not in Figure 4.6(e), where all the Si3N4, including the spacer is etched off,
which suggests that this debris is residual nitride, removed completely for the over-
etched sample in Figures 4.6(e). It is also observed that the thickness and profile of
the spacer varies significantly across process runs. In Figure 4.6(b), it’s about 175
nm wide with a reasonably smooth profile. However, in Figure 4.6(c), the spacer
profile is jagged and the thickness varies from 82 to 164 nm, and in Figure 4.6(d),
it’s almost completely etched off. Figure 4.6(d) also shows a jagged profile for the
emitter pattern, which could be due to the lithographic pattern edge roughness or
could result from the Ti/Pt/Au lift-off process. The nonuniformity of the spacer
58
2.16 µm
175 nm
GaAsSb base
Ti/Pt/Au Emitter
Si3N4
spacer
175 nm
GaAsSb baseTi/Pt/Au
Emitter
Si3N4
spacer
164 nm
82 nm
GaAsSb base
Ti/Pt/Au Emitter
Si3N4
spacer
GaAsSb base
Ti/Pt/Au Emitter
Si3N4
spacer
GaAsSb base
Ti/Pt/Au Emitter
Si3N4
spacer
Ti/Pt/Au Emitter
Si3N4
spacer
1 µm 200 nm
200 nm
1 µm
200 nm
500 nm
(a)
(f)
(d) (c)
(e)
(b)
Figure 4.6: In-process scanning electron micrographs of Si3N4 spacers around HBTemitters showing run-to-run in the spacer thickness and the nonuniformity of thesidewall profile, (a), (b), (c), and (d) top view; (e) and, (f) are viewed at a 45
angle. In (d) the Si3N4 spacer is almost etched off .
59
0
5
10
15
20
25
1 2 3 4 5Process run
Etc
h ra
te (
Å/s
)
Figure 4.7: Variation in the Si3N4 RIE etch rate in SF6/Ar plasma (2/18 sccm, 15mTorr) from run-to-run, the RF power is adjusted to keep the DC bias in the range400±5 V . For each run, the etch rate was found from the best least-squares linearfit to the etch depth vs. time curve, taken for three data points.
profile is also observed from the 45-angle views in Figure 4.6(e) and (f).
The nonuniform thickness and profile of the Si3N4 spacer sidewall could be due
to the process-to-process variability of the etch rate, shown in Figure 4.7, and calcu-
lated from the least squares fit to the etch depth vs. time curve of Si3N4-on-Si-pilots
prior to the etch, for each run, three pilot samples were etched using photoresist
masks, and step-profiled after removing the photoresist. The variation in the etch
rates in Figure 4.7 is consistent with Figure 4.4, where the Si3N4 etch rate varies by
±20 %, 20±4 A/s, from the highest and lowest etch rates. Owing to this uncertainty
in etch rate, the Si3N4 over-etch needed to guarantee a desired etch depth in the
presence of etch rate uncertainty, can be calculated:
Consider a nominal nitride deposition thickness l, with an uncertainty ±δl. For
a nominal etch rate of v with uncertainty ±δv, the nominal etch time required is
l/v. Using an over-etch factor γ, the actual depth of the etch is γ(v ± δv)l/v. The
60
over-etch ∆l which is the difference between the actual etch depth and the actual
deposition thickness, is
∆l = (v ± δv)lγ
v− (l ± δl) = l[(1± δv/v)γ − (1± δl/l)] (4.1)
To ensure that accounting for the etch rate and deposition thickness variation,
there is no under-etching, γ needs to be chosen such that ∆l ≥ 0, or
l[(1± δv/v)γ − (1± δl/l)] ≥ 0
⇒ γ ≥ 1± δl/l1± δv/v (4.2)
using −εlm ≤ δl/l ≤ +εlM , −εvm ≤ δv/v ≤ +εvM as the upper and lower bounds
of the normalized nitride thickness and etch rate uncertainties, respectively, from
Eq. (4.2), the minimum value for γ can be calculated as,
γmin ≥1 + εlM1− εvm
(4.3)
Similarly, for the over-etch to be smaller than an allowable value M , ∆l ≤M ,
l[(1± δv/v)γ − (1± δl/l)] ≤ M
⇒ γ ≤ 1 +M/l ± δl/l1± δv/v (4.4)
from which, the maximum value of γ can be calculated as,
γmax ≤1 +M/l − εlm
1 + εvM(4.5)
Eqs. (4.3), (4.5) define the bounds for the over-etch factor γ to ensure that there
is no under-etching, and the over-etch is below M , provided,
1 +M/l − εlm1 + εvM
>1 + εlM1− εvm
⇒ M
l>
εlM + εlm + εvM + εvm + εlMεvM − εlmεvm1− εvm
(4.6)
61
The above analysis not only applies to the Si3N4 process where l and v refer to the
deposited Si3N4 thickness and the Si3N4 RIE rate, but to any etch process with
uncertainties in the target etch depth and the etch rates. Equation (4.6) provides
the maximum over-etch possible for an etch recipe with the maximum uncertainties
in the etch depth l and etch rate v. Spoken differently, for a given target depth l
and allowable over-etch M , Eq. (4.6) also provides a relation for how small the etch
rate and etch depth uncertainties need to be. For the Si3N4 sidewall process, the
deposited Si3N4 thickness was found to be 3000±100 A, measured by patterning and
etching Si3N4-on-Si samples in 1: 10 buffered HF solution and then step profiling
the Si3N4 patterns. Using these uncertainties as εlm = 0.03, εlM = 0.03, and the
maximum and minimum etch rates in Figure 4.7, M for the sidewall process was
calculated using Eq. (4.6) to be 1476 A, which corresponds to about 50 % over-
etch for the deposition thickness of 3000 A. Since the nitride etch has a lateral
component, this over-etch due to the etch rate uncertainty also translates into a
lateral over-etch, and could be an explanation of the variability of the nitride spacer
thickness observed in Figure 4.6.
A SiO2-based spacer process was explored to see if it led to thicker and more
reproducible sidewalls than the Si3N4 process. A SiO2 PECVD deposition process
was used with the following conditions: SiH4/N2/N2O 8/72/900 sccm, 900 mTorr,
250 C. The RIE conditions were CF4/O2 15/3 sccm, 10 mTorr, 150 W (330-350
V). The etch rate was first calibrated in the same way as the Si3N4 etch described
above, the etch characteristics are shown in Figure 4.8.
Using this etch, SiO2 spacers were formed on 300 nm Ti/Au patterns on GaAs
substrates, the cross-sectional SEM image is shown in Figure 4.9(a). Also shown in
Figure 4.9 are the in-process SEM images of 4000 A tall HBT emitter mesas after
forming SiO2 spacers using this process. The SiO2 deposition thickness was 300 nm.
62
0
500
1000
1500
2000
0 50 100 150 200 250 300 350 400
Etc
h de
pth
(Å)
Time (s)
PECVD SiO2 RIE in
CF4/O
2 15/3 sccm
10 mT, 150 W, 330-350 V5 Å/s
Figure 4.8: Silicon dioxide etch depth as a function of time in a CF4/O2 plasma.
From the cross-sectional view, the spacer profile is observed to be tapered, with the
thickness at the bottom being considerably larger than at the top, which points to
a lateral component of the etch. As the top portion of the spacer is exposed to
the RIE plasma for a longer time than the bottom portion, it gets etched deeper
laterally by the chemical component of the etch. The SiO2 thicknesses in Figure 4.9
are observed to be significantly higher than that of the Si3N4 spacer, for the same
dielectric deposition thickness. However, the sample surface after the RIE shows
evidence of a residue, which could be SiO2 residue or a carbonaceous polymer film
formed during the etch. This residue was readily removed in a 2 s etch in 1 H2SO4
: 8 H2O2 : 160 H2O to etch approximately 100 A of the semiconductor before
depositing the HBT base/RTD collector contact metal.
63
200 nm
260 nm
Ti/Au
GaAs
SiO2
GaAsSb base
Ti/Pt/Au Emitter
SiO2
spacer
280 nm
GaAsSb base
Ti/Pt/Au Emitter
SiO2
spacer
(a)
(c) (b)
Figure 4.9: Scanning electron micrograph of a silicon dioxide sidewall, (a) cross-section view of a Ti/Au pattern a GaAs substrate, (b), and (c) HBT samples withthe spacer around the HBT emitters, top and angled (45 to the vertical) views,respectively.
64
4.2.2 BCB Etch-back Process
An important aspect of the self-aligned process is the ability to control the BCB
etch-back so as to expose the HBT base contact metal overlapping the emitter. The
BCB is etched by RIE in a SF6/O2 plasma to expose the W self-alignment metal,
see Fig. 4.2(e). An over-etch of course can remove the BCB entirely. An under-etch
of the BCB and it is possible that the emitter and W layers will remain shorted.
To make sure the BCB is etched back only to a sufficient depth, an iterative BCB
etching procedure combined with measuring the BCB height on the emitter mesa
was used. From the etch-back schematic shown in Figure 4.2, it can be observed
that before the BCB is completely etched from the top of the emitter, the difference
in the BCB surface levels between the emitter mesa and the surroundings should
remain constant. In Figure 4.10(a) a micrograph and step profile measurements of
the sample before the completion of the etch-back are shown. Once the W on the
emitter is exposed, this difference should increase with further etching, as shown
in the step-profile measurement of Figure 4.10(b). The end of the BCB process
can thus be determined by etching and step-profiling the BCB surface through the
emitter mesa iteratively till the step height becomes larger than the value prior to
the etch.
The etch-back process details are as follow: prior to spinning the BCB, the height
of the HBT emitter mesas, blanket-deposited with W, are about 4000 A. After
spinning and curing the BCB, whose thickness is 1.3 µm with a ±500 A variation
across the sample, the step-profile of the mesas with BCB on top is reduced by the
reflow of BCB, and varies from 400 to 1200 A for 60×60 µm2 emitter mesas across
the sample, which is a quarter of a 75 mm wafer. The BCB is then reactive-ion-
etched in SF6/O2 3.33/30 sccm, 300 mTorr, 60 W, 20 V DC bias, with an etch
rate of 1700-2000 A/minute. After etching the BCB till the emitter mesa heights
65
60 µm
(b)
(a)
(c)
(d)
Step-profile
BCB
HBT emitter
W
Au
Au
W
44 nm
98 nm
111 nm
28 nm
BCB
BCB
Figure 4.10: In-process optical micrographs and step-profile measurements of theHBT samples at various stages of the etch-back process: (a) before the BCB etch-back, (b) after the BCB etch-back, (c) after the tungsten etch, and (d) after theBCB removal etch.
66
become larger than the initial step height of the BCB over the emitter metallization.
Once the W layer is exposed it is etched in SF6 20 sccm, 20 mTorr, 50 W (W
etch rate 2000 A/minute) in a timed etch to break the short between emitter and
W, shown in Figure 4.10(c). The BCB is then removed from the sample and the
emitter-base contacts are electrically tested for isolation, shown in Figure 4.10(d).
The micrographs of the sample at various stages of the process and the step-height
measurements are shown in Figure 4.10. As can be observed in Figure 4.10(a) to
(c), there is a significant change in the color of the emitter mesa patterns as the
material on top of the mesa changes from BCB to Au, which serves as a guide to
determine the etch completions, along with the step-profile measurements.
The variability in the spacer formation process required modifications to the BCB
etch-back process to ensure electrically isolated self-aligned contacts. In-process
electrical measurements showed instances of short circuits between the emitter and
base contacts after the etch-back process. Emitter-base short circuit conditions
are illustrated in Figure 4.11. If the spacer is vertically over-etched as shown, the
W on top of the spacer is not completely removed in the BCB etch-back process,
connecting the base and emitters as shown in Figure 4.11(a). In such a case, the W
can be etched back iteratively till the contacts are electrically isolated, as shown in
Figure 4.11(b).
The I-V characteristics of two HBT base-emitter junctions after the etch-back
process for two different samples is shown in Figure 4.12. The effect of the pro-
cess variation on the device electrical properties is evident from comparing the I-V
characteristics; for the device in Figure 4.12(a), the contacts were isolated by the
BCB etch-back process without the need of a W etch-back, while for the device
in Figure 4.12(b), the I-V characteristics show a leakage current, and need a W
etch-back to reduce this leakage. The non-zero current at zero bias is on account
67
of the measurements being done in ambient light, which causes the generation of
electron-hole pairs in the p-n junction.
Ti/AuTungsten
Emitter and baseconnected
Ti/AuTungsten
(b)
(a)
Figure 4.11: Scaled schematic of a modified BCB etch-back process, (a) over etch ofthe dielectric spacer causes the emitter and the base contact metal to be connected,(b) Etching back the tungsten in RIE to a sufficient depth isolates the two contacts.
4.3 Semiconductor Etches
For the top-down fabrication approach in the current process, semiconductor
etch processes are needed to create the device mesas and provide isolation between
individual devices. The choice of etch processes are motivated by etch characteris-
tics such as selectivity between different epitaxial layers, isotropy and uniformity.
Etchants that selectively etch one epitaxial layer with respect to another are prefer-
able as they avoid the possibility of under or over-etching due to variations in the
effective etch rate resulting from e.g. surface preparation, temperature differences,
etc. Isotropic etches result in undercuts which can be advantageous in certain cases,
for example, in HBTs, emitter etch-undercuts are essential for the self-aligned base
contact process approach in [64], and for the subcollector etch, undercut of the base
68
10-13
10-11
10-9
10-7
10-5
10-3
10-1
-1 -0.5 0 0.5 1
Cur
rent
(A
)
Voltage (V)
sample# s3.1
20 x 20 µm2 emitterNo tungsten etchback
70 mV/decade
10-13
10-11
10-9
10-7
10-5
10-3
10-1
-1 -0.5 0 0.5 1
Cur
rent
(A
)
Voltage (V)
sample# s4.1
60 x 60 µm2 emitter
70 mV/decade
180 nm tungsten etchback
No tungsten etchback
(b) (a)
Figure 4.12: Current-voltage characteristics of HBT base-emitter junctions after theBCB etch-back process, (a) the contacts are electrically separated without havingto do a tungsten etch-back, (b) inadequate isolation between the contacts requiresa tungsten etch-back process which reduces the leakage current.
reduces the area of the base-collector junction and the associated parasitic capac-
itance. However, etch-undercuts on micron and submicron emitters can lead to a
complete lifting-off of the emitters, which can limit the use of isotropic etches with
device scaling. For minimizing or eliminating etch undercuts, anisotropic plasma
etching is preferred. For the mesa etches in the current process, both RIE and wet
etches were developed. The etch characteristics and their applicability are described
in the following.
An InGaAs/InP RIE process was established for the HBT and RTD devices
mesas which consisted of InP and related materials such as InGaAs. Methane-
hydrogen plasmas have been known to etch InP and InGaAs [73, 74, 75]. Using
a Ti/Au/Ti lift-off metal pattern as the etch mask, InP-lattice-matched InGaAs
samples (quarters of a 50 mm wafer) were etched in the RIE 790 system. The etch
depth was found by step profiling the metal patterns before and after etching. The
69
etch depth vs. etch time characteristic shown in Figure 4.13, is linear and begins
without delay. Three measurements were made corresponding to three different
positions on the sample at each etch time. Also shown in Figure 4.13 is a SEM
of an InGaAs sample revealing vertical sidewall profiles. The sample was etched
in 4/20/10 CH4/H2/Ar at 75 mTorr and 300 W followed by etching off 25 nm in 1
H2SO4 : 8 H2O2 : 160 H2O. The SEM micrograph shows no evidence of undercutting
the metal. The InGaAs surface also appears to be rough, which could be due to
polymer formation in the CH4/H2 plasma [73, 74].
0
20
40
60
80
100
120
140
160
0 1 2 3 4 5 6 7
Etc
h D
epth
(nm
)
Etch Time (minute)
CH4/H
2/Ar 4/20/10sccm
75 mT 300 W~430 V DC
Etch rate ~25 nm/minute
Ti/Au/Ti
InGaAs
Ti/Au/Ti
InGaAs
(b) (a)
Figure 4.13: Etch characteristics of InGaAs in CH4/H2/Ar plasma, (a) Etch depthvs. time characteristic, (b) SEM micrograph of the cross-section with a post-RIEwet etch of InGaAs.
The CH4/H2/Ar etch was used in the four mesa etching steps of the RTD/HBT
process detailed in Appendix B: (a) RTD emitter mesa etch following the RTD
emitter contact metallization, (b) HBT emitter mesa etch following the HBT emitter
contact metallization, (c) HBT subcollector etch through the GaAsSb base and the
InP subcollector to the InGaAs HBT collector contact layer, and (d) the isolation
70
etch from the HBT collector contact through the InP substrate. The RIE etch time
was adjusted for a depth 200 A lower than the required mesa depth and a wet
etch was used to complete the etch to keep the post-etch sample surface free of any
RIE-induced damage. Following the procedure in [74], during the RIE, the HBT
samples were placed on a 100 mm Si wafer to prevent sputtering of the cathode
stage on the samples because of the high DC bias. The Si wafer was pre-coated
with a hydrocarbon polymer by exposing it to a CH4/H2/Ar plasma prior to the
etching of the HBT samples, a process which also served as the seasoning step. The
cathode stage, which was observed to reach a temperature of 80 C because of this
seasoning step, was allowed to cool down to below 40 C before etching the samples.
The use of CH4/H2/Ar RIE for the device mesas was found to result in surfaces
with etch residue and debris, shown in Figure 4.14 (a) is an optical micrograph of an
HBT sample surface after the RIE of the InP subcollector and finishing with an wet
etch. The wet etch processes after the RIE were observed to be nonuniform across
the surface with no etching around the large spots shown in Figure 4.14(a). The
presence of debris on the surface after RIE is also obvious in Figure 4.14(b) which
is a micrograph of an InP surface after a CH4/H2/Ar etch, where step profiling the
surface is observed to leave a mark on the surface. A possible source of this debris
on the surface is the formation of hydrocarbon polymers in the methane-hydrogen
plasma, which depends on the RIE process conditions such as the pressure, gas flow
rates and power density [73]. Methods to minimize polymer deposition in CH4/H2
plasmas include addition of O2 to the plasma and periodic O2 plasma cleaning of
the sample [74].
To remove the polymer from the sample surface, the following descum processes
were used: an O2 plasma descum process, and soaking in chemical solutions such
71
InP Ti/Au
100 µm Mark left by step profiler
stylus
InGaAs
(b) (a)
Figure 4.14: Optical micrographs of InGaAs/InP surfaces after RIE in CH4/H2/Arplasma, (a) InGaAs collector surface after RIE and wet etch of the InP subcollector,(b) InP surface after RIE, a visible mark is left by the step-profile stylus on thesample surface.
as AZ-1165 photoresist stripper and etch residue remover ACTrNE-144, which is a
fluoride-based solution designed to remove organic and oxidized etch residues. Of
the three methods, soaking of the samples in ACTrNE-14 led to a significant im-
provement in the surface quality. The effect of ACTrNE-14 on etched InP samples
is evident from the optical and SEM micrographs shown in Figure 4.15. The two InP
samples shown in Figure 4.15(a) are cleaved from the same InP wafer after the RIE
process, the right one having been soaked in ACTrNE-14 at room temperature for
15 minutes. Without the ACTrNE-14 soak, the InP surface is observed to be dark
and grainy. The difference is more obvious in the SEM micrographs of the same two
samples shown in Figure 4.15(b) and (c). The etch residue on the InP surface from
the RIE is observed to be spherical particles with as large as 40 nm diameter, and
is observed to be completely removed by ACTrNE-14. The InP surface after the
removal of the etch residue by ACTrNE-14 soak, shown in Figure 4.15(c), is also
4Air Products and Chemicals Inc.
72
Ti mask600 umInP No soak 15 minute soak in ACTNE14
38 nm
200 nm 200 nm
Ti
InP
(a)
(c) (b)
Figure 4.15: Effect of ACTrNE-14 descum on reactive ion etched InP surface (a)Optical micrographs of InP surfaces with and without the soak, (b), (c) SEM mi-crographs of samples without and with the descum process.
observed to be nonuniform with the average roughness being on the order of a 1000
A. A reason for this nonuniformity could be micromasking of the etch by the etch
residue. Thus while the etched InP surface can be cleared of the etch residue by
73
this cleaning step, it’s still highly nonuniform on account of the deposition of debris
in the RIE step, and calls for alternative etch processes.
To avoid the issues of polymer deposition and resulting surface roughness asso-
ciated with RIE, device mesas can be alternatively etched by employing wet etches.
The semiconductor layer materials to be etched can be divided into two categories
based on their wet etch properties: (a) InGaAs, GaAsSb, AlAs, InAs, which can be
etched selectively with respect to InP in an 1 H2SO4 : 8 H2O2 : 160 H2O (1-8-160)
solution, and (b) InP, which can be selectively etched in 1 HCl: 1 H3PO4 : 1 H2O (1-
1-1) with respect to the materials in the former category. These two etchants were
employed for the four mesa etches in the process, and resulted in smooth etched
surfaces with average surface roughness being less than 10 A.
The InP etch was observed to cause device mesa undercuts of the order of microns
which resulted in lifting off the 2×2 and 4×4 µm2 emitter HBTs. The effects of the
mesa undercuts is shown in Figure 4.16(a), an SEM micrograph of an array of
HBT emitters after the emitter mesa etch and sidewall process shows a couple of
emitters missing or displaced due to excessive undercuts. The optical micrograph in
Figure 4.16(b) shows a HBT after electrical probing which tore off the W base and
the Ti/Au emitter contacts, showing the undercut. The emitter undercut is observed
to be orientation-dependent, with the largest undercuts parallel to the <0 1 0> and
<0 0 1> plane directions, which is consistent with InP etching characteristics in
HCl: H3PO4 solutions [76]. Figure 4.16(b), there is no evidence of the presence of a
subcollector mesa underneath which has been completely removed by the undercut.
For the sizes of the devices shown, the extent of the undercut to cause lifting-off
of the devices should be at least a couple of microns, significantly larger than the
mesa etch depths which were less than 2000 A. Apart from the isotropic nature of
the etch, the undercuts were further increased by the amount of over-etching that
74
was required to fully etch the device mesas. For the etchants 1-8-160, and 1-1-1, the
progress of the etch is visible to the bare eye by the changes in the color of sample
surface which darkens as the etch progresses and ends in a mirror-finish surface when
the etch stops because of selectivity. From the changes in the surface color, the mesa
etching for the samples were observed to be nonuniform, with the etch being faster
near the edges than at the center, which could be due to nonuniformities in the
crystal growth. In order to complete the etch across the wafer, a significant over-
etching had to be done, for example, to etch the 1500 A InP subcollector, an 150
s etch was needed which was five times than the calculated etch time of 30s, using
the etch rate of InP in 1-1-1 on test InP samples which was 50 A/s.
10 µm
HBT emitter array with sidewall
Emitters lifted off by wet etching
HBT
Ti/Pt/Au Collector
5 µm
W base Emitter mesa
(b) (a)
Figure 4.16: Effect of mesa undercut on the HBT, (a) SEM micrograph of an HBTemitter array showing HBT emitters lifted off by excessive undercuts during HBTmesa etch, (b) Optical micrograph of an HBT shows the tearing off of the W basecontact upon electrical probing, no subcollector mesa is observed underneath, show-ing the effect of the undercut during the subcollector mesa etch, the emitter contactmetal is also absent, showing the HBT mesa.
75
0
0.0005
0.001
0.0015
0.002
0 0.5 1 1.5 2 2.5 3
I C (
A)
VCE
(V)
4 x 4 µm2
emitter
IB = 10 µA
IB = 50 µA
RC+R
C=290 Ω
10-11
10-9
10-7
10-5
10-3
10-1
0 0.2 0.4 0.6 0.8 1
Cur
ren
t (A
)
VBE
(V)
nc=1.29 (0.4-0.6V)
nb=1.34 (0.4-0.6V)
20 x 20 µm2
Forward gummel char.
IB
IC
(b) (a)
Figure 4.17: Current-voltage characteristics of fabricated HBTs (a) Forward Gum-mel characteristics, (b) Output characteristics.
4.4 Device Measurements and Characteristics
The output characteristics and Gummel plots of two self-aligned HBTs are shown
in Figure 4.17. From the Gummel plot, the ideality factors η for the base and
collector currents are found to be 1.3. The common-emitter current gain is in the
range of 40-45 which is comparable to the current gains for GaAsSb-based HBTs
[15]. The output characteristics for a 4×4 µm2 emitter HBT shows the presence of
large series resistances . From the saturation region of the output characteristics,
the sum of the emitter and collector series resistance RC+RE can be found in the
following way: in the saturation region, for constant base current, the change in VCE
appears as the voltage drop across the series resistance since the voltage drops across
both the forward-biased junctions can be assumed to be constant, thus the slope
of the collector current ∂IC/∂VCE gives RC+RE for constant base current. From
76
Figure 4.17(a) RC+RE is calculated to be 290 Ω, which is unexpectedly high. The
emitter and collector resistances consists of components such as contact resistances,
intrinsic semiconductor resistances etc, and are described in detail in Appendix A.
Since for the device geometry and the emitter and collector doping densities, the
epitaxial resistances are calculated to be under 1 Ω, a source of the series resistance
could be the contact resistances.
The contact resistances for the four device contact layers: HBT emitter, base,
collector, and the RTD emitter layers were measured by the transfer-line-method
(TLM) measurements, and are shown in Figure 4.18. All the TLM measurements
except for the RTD emitter contacts were done with a mesa around the TLM pads
to confine the carriers within a finite width, which explains the comparatively poor
fit of the RTD emitter TLM resistances to a linear dependence with the gap lengths
Figure 4.18(d), the linear fit being excellent for the rest. The HBT emitter and col-
lector specific contact resistances ρC are as low as 8×10−8 Ω-cm2, and the transfer
lengths LT are well under a micron, which is reasonable for Ti/Pt/Au contacts on
n-InGaAs. However, the specific contact resistance for the W contact to p-GaAsSb
is relatively high at 7.7 × 10−5 Ω-cm2 which calls for exploration of annealing proce-
dures. The low specific contact resistances for HBT emitter and collector contacts
show that the source of the high series resistance of Figure 4.17(b) is not in the
contacts, a possible source could be poor contact between the bondpad interconnect
to the emitter and collectors.
The I-V characteristics of RTDs also show the isolation of the emitter-collector
contacts by the self-aligned process, Figure 4.19. A double sweep I-V characteristics
of a 3×3 µm2 RTD is shown in Figure 4.19(a) where the bias swept from 0 to 1 V
and back. The peak current density for the RTD is 0.1 mA/µm2, and the PVR is
2. The benefit of the double bias sweep is that the effect of any series resistance
77
0
5
10
15
20
25
30
0 5 10 15 20 25 30 35
y = 0.65042 + 0.75626x R= 0.99996
Res
ista
nce
(Ohm
)
Gap length (µm)
59 Ω/sq.
ρC=8.6e-8 Ωcm2
LT=0.38 µm
HBT emittercontact
0
50
100
150
200
250
300
0 5 10 15
y = 55.964 + 16.091x R= 0.99528
Res
ista
nce
(Ohm
)Gap length (µm)
1581 Ω/sq.
ρC=7.7e-5 Ωcm2
LT=2.2 µm
HBT basecontacts
0
1
2
3
4
5
6
7
8
0 5 10 15 20 25 30 35
y = 0.31 + 0.17725x R= 0.99999
Res
ista
nce
(Ohm
)
Gap length (µm)
14 Ω/sq.
ρC=8.5e-8 Ωcm2
LT=0.77 µm
HBT collectorcontact
0
0.5
1
1.5
2
2.5
3
0 2 4 6 8 10
y = 0.235 + 0.21964x R= 0.97127
Res
ista
nce
(Ohm
)
Gap length (µm)
17 Ω/sq.
ρC=8e-8 Ωcm2
LT=0.69 µm
RTD emittercontact
(b) (a)
(d) (c)
Figure 4.18: Transfer line method measurements for the contact resistances, (a)HBT emitter, (b) HBT base, (c) HBT collector, and (d) RTD emitter.
78
0
0.0005
0.001
0.0015
0.002
0 0.5 1 1.5 2
Cur
ren
t (A
)
Bias (V)
2 3x3 µm2 RTDs in seriesbridge oscillator circuit
0
0.001
0.002
0.003
0.004
0.005
0 0.2 0.4 0.6 0.8 1
Cur
rent
(A
)
Bias (V)
3x3 µm2 RTDdual bias sweep
Jp= 0.13 mA/µm2
PVR=2
(b) (a)
Figure 4.19: Current-voltage characteristics of RTDs in double bias sweep (a) one3×4 µm2 RTD shows no hysteresis in the double sweep showing the lack of a signif-icant series resistance, (b) two 3×4 µm2 RTDs in series, showing slightly differentpeaks, and hysteresis, pointing to a significant series.
is indicated in hysteresis of the I-V characteristics for the forward and reverse bias
sweeps. This can be understood by considering the load line diagram of an NDR
device in series with a resistance, the value of the resistance determining the biases
at which the RTD switches from peak to valley regions and back. The lack of any
hysteresis in the I-V characteristics in Figure 4.19(a) shows the series resistance to
be insignificant compared to the NDR of the device. However, the I-V characteristics
of two RTDs in series shows a significant hysteresis in the I-V characteristics, shown
in Figure 4.19(b) suggesting a significant series resistance. The two RTDs are from a
dual transmission line bridge circuit, demonstrated in [77]. For two identical RTDs in
series, there should be only one peak in the current, corresponding the peak current
of the two RTDs. The presence of two current peaks indicate the peak currents to
be different for the two RTDs, which could be because of differences in the RTD
79
areas or epitaxial nonuniformities across the wafer. The sharp drop in the post-peak
current and the lack of a finite NDR region is because of the series resistance. This
lack of an NDR region prevents any oscillations the RTD-transmission line oscillator
when the RTDs are biased at their peak voltages, which was found to be the case
when the oscillator circuit was tested.
4.5 RITD Submicron Device Process for TSRAM
n+ InP substrate
Pd/Ti/Pd/Aucontact
n+ InGaAsn+ InAlAs p+ InAlAs
p+ InGaAs
200 nm
SiO2
p+ InGaAs
200 nm
n+ InGaAsn+ InAlAs p+ InAlAs
200 nm
n+ InGaAsn+ InAlAs p+ InAlAs
BCB
200 nm
n+ InGaAsn+ InAlAs p+ InAlAs
p+ InGaAs
BCB
n+ InAlAs
200 nm
Ti/Au Bondpad
BCB
200 nm
n+ InGaAsn+ InAlAs p+ InAlAs
p+ InGaAs
Ti/Au
(a) (c) (b)
(d) (f) (e)
Figure 4.20: Submicron process flow (a) emitter contact definition, (b) formation ofSiO2 spacer sidewall, (c) emitter mesa wet chemical etch, (d) planarization by BCB,(e) BCB etch-back, exposing the emitter contacts, and (f) Contact metallization forthe bondpad, connecting to the emitter contacts, and the Ti/Au back contact.
Using the SiO2 spacer formation and BCB etch-back processes established for the
80
HBT/RTD process, a fabrication process for InAlAs-InGaAs RITDs was developed,
using electron beam lithography (EBL). A scaled drawing of the device cross section
is shown in Fig. 4.20, outlining the process sequence. After defining the emitter
pattern by EBL, which consists of squares with sides of 0.25, 0.5, 0.75, 1 and 10
µm, a lift-off process was used to deposit the Pd/Ti/Pd/Au contact. The 1 H2SO4
: 8 H2O2 : 160 H2O wet etch is then used to form the device mesa. Since the
undercut resulting from the isotropic etch of the mesa, which needs to be etched to
a depth of 1400 A, is sufficient to lift-off the submicron emitter, a SiO2 spacer is
formed around the emitter prior to the wet etch to increase the effective emitter size,
using the same PECVD deposition and RIE conditions described in Section 4.2.1.
To contact the submicron emitters, a BCB etch-back is used in the following way:
BCB is first spun on the sample, followed by curing in an N2 environment which
causes the polymer to reflow and improve the planarity of the surface, the BCB
is then etched back in RIE till the emitter contacts are exposed. The end of the
etch-back is determined by doing etch and step profile measurements, iteratively.
This process provides an easy way to contact discrete devices without a via process,
saving a mask and precise alignment. Also in this process, one bondpad contact
can be used to contact many devices allowing the testing of many devices in parallel
which is useful for measuring submicron devices with nA/µm2 current densities.
In process SEM micrographs of the process, Figure 4.21, show the devices at
various stages of the fabrication process. The undercut of the emitter mesa in the
wet etch is evident in Figure 4.21(b), with the SiO2 spacer compensating for the
reduction in the emitter dimension caused by the undercut. The purpose of the
spacer is to allow isotropic wet etches for the mesa etch, and since the spacer sets a
limit on the pitch of the emitter patterns, with increased scaling it can be replaced
by anisotropic plasma etches.
81
1 µm 500 nm
SiO2
Emitter contact
Ti/Au Bondpad 500 nm 500 nm
Emitter contact
SiO2
BCB
Emitter contact
InGaAs
InGaAs undercut
(a)
(c)
(b)
(d)
Figure 4.21: In-process SEM micrographs for the submicron fabrication process :(a) top view of the emitter contacts after lift-off, (b) emitter mesas after wet etch,with the SiO2 spacer sidewall, (c) emitter contact posts sticking out after the BCBetch-back, (d) Ti/Au bondpad contacts connecting to the emitter contacts. Figuresb, c, and d are images viewed at an angle of 45 to the vertical.
A measure of the process capability to yield submicron devices can be found from
the I-V characteristics of single devices and arrays of diodes, measured in parallel.
In Figure 4.22 the I-V characteristics of 1, 9, 100 and 1024 diodes of in parallel show
that the current scales with the number of devices, as expected. By comparing the
peak currents for the number of diodes in parallel, a measure of the apparent device
yield in % can be found by the expression
y =1
N
(INI1−N
)× 100 (4.7)
82
where N is the number of devices in an array, I1 and IN are the measured peak
currents for a single device, and an array of N diodes. The expression y gives the
percentage of diodes in parallel contributing to the peak current in an array. In
Figure 4.22(b), the apparent yield is plotted against N for the 4 arrays for growths
1-5 with the exception of the 10×10 array for growth 5, which was lost in the EBL
development step. The measurements of growth 2 in Figure 4.22(a) show that the
current is increasing by a factor of about 10 each as expected with each array size
increase. In fact the yield is 90-95 % for growth 2. What Eq. (4.7) doesn’t account
for is the difference in size that are yielded when the same EBL exposure is applied
to a single device or an array. However, one might expect larger features to result
for devices in arrays and by this formula then the yield would be overestimated.
The lower yield results arrays for other growths suggest that improvements in this
process should be sought.
Further, the submicron device I-V characteristics show a degradation of the PVR
with scaling of the device area. When the peak currents for the growths showing
NDR are plotted as a function of the device area, shown in Fig. 4.23, a least-squares
linear curve fit shows a linear dependence on area. However, the valley currents are
observed to deviate from a linear relationship as the area is reduced, Fig. 4.23. This
results in a decrease in the PVRs for submicron devices, shown in Figure 4.23(c)
where, e.g. in growth 5, the PVR is reduced from 14 for a 10×10 µm2 area to 5
for a 0.25×0.25 µm2 area. The degradation of the PVR with area can be accounted
for, postulating that a peripheral leakage current exists; for a square device of side
83
10-9
10-8
10-7
10-6
10-5
10-4
10-3
10-2
10-1
-1 -0.5 0 0.5 1
Cur
rent
(A
)
Bias (V)
Growth 2
0.25x0.25 µm2
top to backmeasurement
1024 devices in parallel
100
9
1
0
20
40
60
80
100
App
aren
t yie
ld (
%)
Devices in parallel (N)
1
2
3Growth
1 9 100 1024
0.25x0.25 µm2
5
(a) (b)
Figure 4.22: Current-voltage measurements for arrays of diodes connected in paral-lel, the diode current is observed to scale with the number of devices in parallel.
a, the peak, valley currents and the PVR are,
Ip = Jpa2 + Jsp(4a)
Iv = Jva2 + Jsv(4a)
PVR =Jpa
2 + 4Jspa
Jva2 + 4Jsva=Jpa+ 4JspJva+ 4Jsv
(4.8)
where Jp and Jv are the intrinsic peak and valley current densities, respectively, Jsp
and Jsv are the bias-dependent peripheral leakage current densities at the peak and
valley voltages, respectively. Differentiating Eq. (4.8) with respect to the dimension
84
10-10
10-8
10-6
10-4
10-2
Cur
rent
(A
)
Growth 1
3
5
Peak current2
2
10-11
10-9
10-7
10-5
10-3
Cur
rent
(A
)
Growth 1
3
5
Valley current
2
2
0
40
80
0.1 1 10 100
PV
R
Device area (µm2)
Growth
1
3
5
2
2
(a)
(c)
(b)
Figure 4.23: Dependence of the current and PVR on area for growths 1-5: (a) peakcurrents scale linearly with area, (b) valley currents deviate from a linear relationshipwith area, and (c) PVR degrades with area.
85
a, we get,
d(PVR)
da=
(Jva+ 4Jsv)Jp − (Jpa+ 4Jsp)Jv(Jva+ 4Jsv)2
=4(JsvJp − JspJv)
(Jva+ 4Jsv)2(4.9)
Since Jp > Jv, and Jsv > Jsp as Jsv is the leakage current at a higher voltage, the
numerator in Eq. (4.9) and thus d(PVR)/da are positive for all a, or in other words,
the PVR decreases as a is decreased. Also, from Eq. (4.8), it can be seen that in the
limit a → ∞, the PVR reduces to the intrinsic value of Jp/Jv, which is consistent.
While these relations are written for a square diode, it is easy to verify its validity
for any device geometry of dimension a where the device area is proportional to a2,
and the periphery is proportional to a.
To see whether the peripheral leakage currents could be modified by post growth
annealing, samples were annealed in nitrogen for temperatures between 200 and
300 C. In Figure 4.24, the effect of these anneals on the I-V characteristics of
a 0.75×0.75 µm2 diode is shown. The PVR of the device as fabricated was 38,
compared to 49 for 10×10 µm2 diodes on the same wafer. The device was annealed
in nitrogen in three consecutive annealing steps, for temperatures and times as
indicated in the inset of Figure 4.24. The fabrication process already involves a
BCB curing step at 200C for 30 minutes, and this is the first entry in the figure
inset. The anneal at 200 C for 30 minutes resulted in an increase in the series
resistance presumably due to contact degradation. The 250 C anneal increased the
valley current and the 300 C anneal permanently altered the tunnel junction. It
should be noted that the device mesa periphery is “passivated” by BCB, which is
widely used for III-V devices [14, 17]. However, the PVR degradation with scaling
and its exacerbation with post growth annealing calls for further exploration of this
passivation approach.
86
0
1 10-4
2 10-4
0 0.5 1 1.5 2
As fabricated
200 30
250 10
300 10 C
urre
nt (
A)
Bias (V)
Growth 1
0.75 x 0.75 µm2
Annealed in N2
Annealing stepsTemp (ºC) Time (min)
Figure 4.24: Effect of post growth anneals on a submicron diode for growth 1.Repeated post growth anneals in nitrogen does not recover the PVR and results insignificant degradation in the device conductance and the PVR.
In summary, a spacer sidewall and BCB etch-back-based self-aligned contact pro-
cess for HBT and RTD was developed. From electrical measurements of in-process
and fabricated HBT and RTDs, the capability of the process for self-aligned contacts
was demonstrated. Further improvements in the process are needed to improve the
device yield, especially in the device mesa etch processes, for which exploration of
alternative residue-free RIE recipes are needed. A submicron InAlAs-InGaAs RITD
fabrication process for TSRAM using SiO2 spacer and BCB etch-back was devel-
oped demonstrating reasonable device yield, which helped explore RITD scaling.
Annealing steps to suppress peripheral leakage currents in submicron devices were
examined and point out the need for further developments of the submicron device
process.
87
CHAPTER 5
CONCLUSIONS AND RECOMMENDATIONS FOR FURTHER STUDY
InP-based tunneling devices and fabrication processes were investigated for low
power memory and processes were developed for both memory and TD/transistor
integration. For TSRAM, the electrical properties for both InP-based RTD and
RITD heterostuctures across a wide design space were explored to enable matching
to transistor leakages. High speed tunnel diode circuits, which are typically inte-
grated with transistors, need reduction of parasitics. A self-aligned contact process
to reduce the access resistance in HBTs and RTDs was advanced.
5.1 TSRAM Diodes
Tunnel diode structures were investigated from a perspective of application in
TSRAM, for which three TD figures of merits, i.e. peak current, PVR, and valley
voltage are of primary interest. The design space for the peak current is defined by
the leakage currents in the TSRAM cell transistors; reduction in the valley voltage
and maximizing the PVR are necessary for reducing the standby power. Two TD
structures, the triple barrier AlAs/InGaAs/InAs RTD and the double QW InGaAs-
InAlAs RITD were explored. The investigation of the RTD structure was a contin-
uation of previous research in this structure and material for TSRAM [40]. Effects
of the barrier thicknesses on the I-V were explored. For the range of variations
studied, the peak currents were not observed to change significantly enough to map
88
out the transistor leakage currents. The observed PVRs were low at a maximum of
3, consistent with the previous results on similar structures.
The exploration of the RITD structure, which among TDs, is a relatively less
explored structure, was the first such study of this material structure for TSRAM.
Structural changes in the barrier thicknesses, doping densities and alloy composi-
tions were studied, a particularly significant sensitivity of the I-V characteristics to
the doping density variation was observed. Despite the complexity of the RITD
heterostructure, the interband tunneling and valley currents were found to be ad-
equately described by simple interband tunneling and p-n junction theory, respec-
tively. With respect to all the three TD figures-of-merits, this structure was observed
to be particularly attractive for TSRAM. A range of RITD peak currents spanning
5 orders, from 0.3 mA to 0.07 nA/µm2 were demonstrated, which encompasses
the design space in matching RITD peak currents with projected CMOS transistor
leakages, and also facilitates the exploration of other transistor technologies, e.g.
HFETs, which may have higher or lower leakage currents, for TSRAM. The PVRs
observed for this structure were as high as 70, and at a value 14 for Jv = 0.3 nA/µm2,
is a significant improvement over InP-RTDs and Si-TSRAM TDs of similarly low
valley currents. As low as 0.07 nA/µm2 valley current density was demonstrated,
which is the lowest ever reported for TSRAM. The valley voltage was also lowered
so as to enable TSRAM TD pair supply voltages to be scaled down to as low as 250
mV. The RITD structure also showed a significant dependence on growth-to-growth
variation, which shows that a precise control of the growth conditions is necessary.
The effect of variation in the p-InAlAs alloy composition on the I-V was studied,
where an increase in the valley currents was observed, possibly due to the strain
and increase in dislocation density because of the lattice-mismatch.
Submicron scaling of the RITDs, facilitated by the development of an EBL-
89
based process, yielding 10×10 to 0.25×0.25 µm2 TDs with device yields in excess
of 90 %, showed the presence of peripheral leakage currents. Annealing processes
to understand and suppress the leakages were studied, and common passivating
dielectric such as BCB was observed not to suppress these currents.
5.2 Self-aligned HBT/RTD Contact Process
Dielectric spacers and BCB etch-back-based processes were developed for self-
aligned fabrication of monolithically integrated HBT and RTDs. Silicon nitride
and oxide spacer processes were demonstrated through exploration of fluorinated
RIE processes. The choice of dielectric and RIE recipes, and process variability
were found to significantly affect the spacer thickness and profile. Through exper-
iment and analysis, it was shown that to establish a reproducible spacer process,
sufficient control over the dielectric thickness and etch rate uncertainties are nec-
essary. Emitter-base and emitter-collector contact isolation in HBTs and RTDs
were successfully achieved through the spacer/etchback process, and HBTs and
RTDs of 3×3 µm2 sizes were fabricated and electrically characterized. Dry and
wet etches for InP-based semiconductors, and their advantages and drawbacks were
explored. Methane-hydrogen-based dry etches, while observed to result in vertical
device mesas without undercuts, also resulted in rough surfaces which needed spe-
cial surface cleans. On the other hand, wet etches, though free of surface damage,
were observed to cause undercuts large enough to lift-off devices.
5.3 Further Study
The investigation of the RITD structure produced a few interesting results, one
being the significant dependence of the I-V characteristics on growth-to-growth vari-
ation. The PVRs for the same epitaxial structure was observed to change by 3x for
90
different growths, suggesting that further improvements in the PVR are possible by
a careful study and control of the growth conditions. Another interesting observa-
tion was the increase in the peak currents and PVR with the Al mole fraction in
p-InAlAs, which also needs to be studied further for improving the PVR and also for
better understanding of the physics of this structure. Further investigation of strain
and dislocation density in the structure is needed to find ways to lower the valley
current. The RITD designs in this research have primarily focussed on the doping
and the composition of doped p and n regions. The intrinsic QW/barrier region
provides additional variables for further improvements in the valley current. For
example, the valley voltage and current can be changed by changing the QW band
degeneracies through changes in the QW width. Changes in parameters such as
the bandgap and effective mass in the intrinsic region can also be explored through
changes in the alloy composition or material. Considering that the QW and central
barriers are only a few monolayers thick, material changes in this layer may be easier
from a growth point of view.
Further study is also needed in the submicron scaling of the RITDs, especially in
determining the source of the peripheral leakage current and methods to suppress it.
To establish whether the leakage is intrinsic or related to the current process, the use
of a submicron device process devoid of BCB and high temperature curing steps can
be used. Alternate passivating agents such as Si3N4 and polymide can be explored.
For the RTD/HBT self-aligned process, the device yield can be improved by reducing
the mesa undercuts through exploration of low surface-damage anisotropic plasma
etches. Alternatively, the transistor layouts can be oriented to adjust to the mesa
undercuts due to wet etches.
91
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99
APPENDIX A
RTD/HBT FREQUENCY PERFORMANCE ESTIMATION
A.1 HBT Cut-off Frequency
The frequency performance of an HBT is dependent on intrinsic transistor pa-
rameters as well as parasitic resistances and capacitances. To estimate the frequency
performance, the analytic model of Sunderland and Dapkus [78] is adopted here.
The unity current gain cut-off frequency, ft is given by,
ft =1
2π
1
τe + τb + τscl + τc, (A.1)
where τe is the emitter time constant, and represents the charging time of the
emitter and the collector capacitances through the differential base-emitter junction
resistance and the emitter series resistance [78],
τe =
(Re +
kBT
qIe
)(Ce + Cc), (A.2)
where Re is the emitter series resistance, Ce and Cc are the emitter-base and base-
collector junction capacitance, respectively, q is the electron charge, and Ie is the
DC emitter current. The base transit time τb for the electrons, also given by [78], is
τb =W 2b
2.43Db
, (A.3)
where Wb is the base layer thickness and Db is the minority diffusion coefficient
for electrons in the base. The space-charge transit time through the base-collector
100
depletion region τscl, assuming an electric field high enough for velocity saturation
is [78]
τscl =Xd
2vs, (A.4)
where Xd is the base-collector depletion layer width and vs is the saturation velocity
of the carriers. The last time constant τc is the charging time for the base-collector
capacitance through the collector series resistance Rc [78],
τc = RcCc. (A.5)
The maximum frequency of oscillation, fmax, for an HBT, defined as the fre-
quency at which the unilateral power gain of the device is unity, is given by
fmax =
√ft
8πRbCC, (A.6)
where Rb is the base series resistance. Apart from an explicit dependence on Rb,
the power gain cut-off frequency is a also a function of Re and Rc, through its
dependence on ft.
The parasitic resistances originate from the metal semiconductor contacts, the
geometrical resistance of the semiconductor layers, and the spreading resistances in
the base and subcollector, as shown in Figure A.1. The emitter resistance Re is the
sum of the emitter contact resistance REE, and the semiconductor resistance Res of
the emitter layer. The base resistance Rb is a series combination of the base spread-
ing resistance Rbi, the base contact resistance RBB, and the extrinsic base resistance
Rbx, which is dependent on the base-emitter separation. The collector resistance Rc
consists of the semiconductor resistance Rcs, the subcollector semiconductor resis-
tance Rscs, the lateral subcollector extrinsic resistance Rscx, the subcollector spread-
ing resistance Rsci, and the contact resistance RCC , all added in series. Analytic
expressions from ([79], pages 143-280) have been used for these resistances. In order
101
REE
Res
RbiRbx
RBB
RCC
Rcs
RsciRscx
Base
contact
Collector
contact
Subcollector
Collector
Emitter
contact
Base
Emitter
Spacer
Depletion
region
Rscs
Figure A.1: Heterojunction bipolar transistor schematic cross-section showing thephysical origin of the parasitic resistances.
to establish that these formulae are capable of providing reasonable estimates of ft
and fmax, a comparison is made to the recently published HBT results of Griffith
and Rodwell [65]. Using their reported material structure and device geometries,
including measured mobilities, and contact resistivities, the cut-off frequencies, ft,
and fmax, were calculated to be 508 and 489 GHz, respectively. The estimated ft
is 13 % higher than the measured value of 450 GHz. The overestimation of ft is
possibly due to an underestimation of the base transit time of 0.05 ps, using Eq.
(A.3), for which, the electron velocity in the base is v = Wb/2τb = 3.15× 107 cm/s,
which is larger than the electron steady state saturation velocity of 1 × 107 cm/s
in InGaAs [80]. The estimated power-gain cut-off frequency is 471 GHz, which is
within 4 % of the measured value of 490 GHz.
With this reasonable agreement, the model can be applied to the target device
geometries of this work. The material parameters and operating conditions used for
these calculations are listed in Table A.1, and the layer structure is the same as in
Table 4.1.
102
Table A.1
MATERIAL PARAMETERS AND OPERATING CONDITIONS USED TO
COMPUTE CUT-OFF FREQUENCIES FOR INP/GAASSB/INP HBTS
Parameter Description ValueρσE Specific emitter contact resistance (Ω cm2) 8.4×10−8 [65]ρσB Specific base contact resistance (Ω cm2) 1×10−7 [81]ρσSC Specific subcollector contact resistance (Ω cm2) 8.4×10−7 [65]εr Dielectric constant (InP/GaAsSb) 12.5/14.16vs Saturation velocity in InP (with overshoot) (cm/s) 4 × 107[81]
ΦBE Emitter-base built in voltage (V) 0.85µnCap Emitter cap electron mobility (cm2/Vs) 3469 [82]µnE Emitter electron mobility (cm2/Vs) 2882 [82]µnC Collector electron mobility (cm2/Vs) 3950 [82]µnSC Subcollector electron mobility (cm2/Vs) 837 [82]µnB Base electron mobility (cm2/Vs) 800 [83]µpB Base hole mobility (cm2/Vs) 28 [83]VBE Emitter-base voltage (V) 0.5Je Emitter current density (mA/µm2) 5
103
A top view of the layout for a 2×2 µm2 emitter HBT is shown in Figure A.2.
The base contact surrounds the emitter to minimize the extrinsic base resistance
for a given base-emitter separation. The collector contact wraps around the emitter
on three sides to make the lift-off process more reliable. Given the geometries of
Figure A.2, a current gain cut-off frequency of 240 GHz is estimated (0.1 µm nitride
sidewall thickness).
BASE
COLLECTOR
EMITTER
2 µm
VIA
VIA2
Figure A.2: Layout of a 2×2 µm2 emitter heterojunction bipolar transistor for the0.5 µm misalignment rule.
For the material structure and device geometries of the HBT discussed in Table
A.1, the base transit time is the most significant, τb = 0.39 ps, followed by the
collector space-charge transit time τscl = 0.23 ps, emitter charging time τe = 0.06 ps,
and collector charging time of τc = 0.01 ps. The cut-off frequency can be increased
104
by scaling down the base and collector thicknesses, lowering the base and collector
transit times. For example, lowering the base thickness to 25 nm [81] reduces the
base transit time to 0.12 ps and results in an ft of 350 GHz. Reducing the collector
thickness to 78 nm [65] decreases the space-charge transit time to 0.11 ps, increasing
ft to 307 GHz.
A reduction in the base resistance can be achieved through design of the emitter
dimensions. For the 2×2 µm2 device of Figure A.2, for a base-emitter separation
of 1 µm, the most significant resistive component is the extrinsic base resistance,
Rbx = 130 Ω, followed by the spreading resistance Rbi = 43 Ω and the base contact
resistance RBB = 3 Ω. With the nitride-sidewall-etch-back process, the base-emitter
separation can be minimized. Decreasing the base-emitter separation to 0.1 µm,
results in the extrinsic resistance being reduced to 13 Ω, and a decrease in the total
base resistance by 66 %. As the base-emitter separation is reduced to the nm range,
the base resistance is dominated by the spreading resistance. Further decrease in the
base resistance can be achieved with rectangular emitter geometries, which decreases
both the spreading and extrinsic resistances. For example, for an RTD emitter area
of 4 µm2, with a spacer thickness of 0.1 µm, the base spreading resistance can be
reduced to 1 Ω for a 0.2×20 µm2 emitter device compared to the 43 Ω for a 2×2
µm2 emitter device.
The effects of the nitride spacer thickness on the power gain cut-off frequency
of a 4 µm2 emitter HBT can be observed in Figure A.3. For the 2×2 µm2 device,
power gain cut-off frequency increases from 150 to 226 GHz as the spacer thickness
is decreased from 500 to 35 nm. For the same emitter area, further improvement in
the frequency performance can be achieved by using rectangular emitter geometries.
As the emitter widths are reduced, the power gain cut-off frequency is observed to
increase, Figure A.3, reaching 835 GHz for a 0.2×20 µm2 emitter at a spacer width
105
of 35 nm.
0
200
400
600
800
1000
0 0.1 0.2 0.3 0.4 0.5
f max (GHz)
Emitter-base separation (µm)
Emitter width = 2 µm
1 µm
0.4 µm
0.2 µm
Figure A.3: High frequency performance of a 4 µm2 emitter HBT as a function ofthe emitter-base separation and emitter width.
The HBT cut-off frequencies can be increased by vertical and lateral scaling. To
increase the current gain cut-off frequency, the most important parameters are the
base and collector transit times, which can be decreased by reducing the base and
collector layer thicknesses. For improvement in the maximum power gain cut-off
frequencies, apart from the reduction in the extrinsic base resistance by the nitride
spacer, an important factor is the emitter geometry which affects both the spreading
and extrinsic base resistances.
A.2 RTD Maximum Frequency of Oscillation
The high frequency performance of an RTD is characterized by a maximum
frequency of oscillation fmax, defined as the frequency above which the real part of
106
the diode impedance is no longer negative. The maximum frequency of oscillation
occurs when the real part of the RTD impedance becomes zero,
fmax =1
2πCD
√−GD
RS
−G2D. (A.7)
The differential conductance GD, is dependent upon the applied voltage. An upper
limit for fmax in Eq. (A.7) is found by assigning GD the maximum value of the
negative differential conductance.
The series resistance RS consists of five components as shown in Figure A.4.
The component REE and Res represent the RTD emitter contact and emitter layer
resistances, respectively, Rci represents the spreading resistance in the collector,
Rcx represents the extrinsic collector resistance dependent on the emitter-collector
separation, and RCC represents the collector contact resistance.
REE
Res
RciRcx
RCC
RTD emitter contact
Collectorcontact
Collector
Emitter
Figure A.4: Schematic cross section of an RTD showing the physical origin of theseries resistances.
RS = REE +Res +Rci +Rcx +RCC . (A.8)
The emitter contact and layer resistances are given by
REE =ρce
LEWE
, (A.9)
107
and
Res = ρeTe
LEWE
, (A.10)
where ρce is the specific contact resistance of the emitter contact, LE and WE are the
emitter contact length and width, respectively, ρe is the resistivity of the emitter
material, and Te is the emitter layer thickness. The spreading resistance Rci is
analogous to the base spreading resistance in an HBT and for collector contacts on
four sides of the emitter, is
Rci =Rsc
12( LE
WE+ WE
LE), (A.11)
where Rsc is the sheet resistance of the RTD collector layer. The extrinsic collector
resistance Rcx depends on the emitter-collector separation, and is given by
Rcx =Rsc
2(LE +WE)/d+ 4, (A.12)
where d is the emitter-collector separation. The collector contact resistance is given
by
RCC =
(√RscρccLC
)coth
[WC
√Rsc/ρcc
], (A.13)
where LC and WC are the collector contact length and widths, respectively, and ρcc
is the specific contact resistance for the collector contact.
As seen from Eq. (A.7), minimizing the series resistance for given values of the
differential conductance and the device capacitance results in a higher fmax. To find
the dependence of RTD maximum frequency on the device area, Eq. (A.7) can be
rewritten as,
fmax =g
2πc
√1
RSgA− 1. (A.14)
where A is the device area, g and c are the absolute differential conductance and the
geometrical junction capacitance per unit area, respectively. Decreasing the area A
108
increases the series resistance RS, in particular, the emitter contact and semicon-
ductor resistances, REE, and Res are inversely proportional to A Eqs. (A.9), and
(A.10), and for square emitter geometries, the extrinsic resistance Rcx is inversely
proportional to the emitter length Eq. (A.12), and the spreading resistance Rci is
independent of area. For a square emitter RTD, the series resistance can be divided
into three components,
RS =R1
A+
R2√A
+R3, (A.15)
where R1 and R2 are the coefficients of the resistive components dependent on the
emitter area and lengths, respectively, R3 is the coefficient of the area-independent
component. The product RSA becomes
RSA = R1 +R2
√A+R3A, (A.16)
The product RSA decreases with the decrease in area, leading to an increase in the
RTD maximum frequencies, according to Eq. (A.14).
With the self-aligned emitter-collector contact process, the series resistance RS
can be decreased by reducing the nitride spacer thickness. The resistance compo-
nents for the RTD of Figure A.5 are calculated using Eqs. (A.8-A.13). The RTD
structure is the same as in Figure 4.1. The material parameters used for the calcu-
lations are listed in Table A.2.
The emitter is 3 µm × 3 µm, the collector contact surrounds the emitter to
minimize the extrinsic resistance. For this device, with an emitter-collector sepa-
ration of 1 µm, the resistive components are, Rcx = 2.74 Ω, Rci = 1.83 Ω, RCC =
1.75 Ω, REE = 1.1 Ω, Res = 0.01 Ω, the significant components being the collector
spreading and extrinsic resistances, and the contact resistances. By reducing the
base-emitter separation to 0.1 µm, the extrinsic resistance is reduced to 0.35 Ω,
resulting in a decrease of 32 % in the total series resistance RS. For the same spacer
109
COLLECTOR
EMITTER
2 µm VIA
EMITTER
Figure A.5: Layout of a 3×3 µm2 emitter resonant tunneling diode.
thickness and emitter area, using a rectangular emitter reduces both the spreading
and extrinsic resistances, Eqs. (A.11), and (A.12). For a spacer thickness of 0.1 µm,
using an 0.3×30 µm2 emitter device results in a decrease of the series resistance to
2.97 Ω from 5 Ω for the 3×3 µm2 device. With minimized spreading and extrinsic
resistances, the series resistance is determined by the emitter and collector contact
capacitances.
By reducing the spacer thickness, the RTD maximum frequency of oscillation
can be increased, as shown in Figure A.6. For the calculation of fmax, the maximum
value of the differential conductance GD is calculated from the slope of the RTD
I-V characteristics. Decreasing the emitter-collector separation from 1 µm to 35
nm increases the fmax from 231 GHz to 308 GHz, which is an increase of 33 %.
The RTD maximum frequencies increase with decrease in the emitter width, for the
same emitter area, as seen for the 1 µm × 9 µm and 0.3 µm×30 µm, Figure A.6.
For an emitter-collector separation of 35 nm, using a 0.3 µm×30 µm emitter device
instead of a 3 µm×3 µm leads to an increase of 35 % in the RTD fmax.
110
Table A.2
INGAAS/ALAS DEVICE AND MATERIAL PARAMETERS USED FOR
COMPUTING THE MAXIMUM OSCILLATION FREQUENCY
Parameter Description ValueNde Emitter doping density (cm−3) 1×1019
Ndc Collector doping density (cm−3) 1×1019
µne Emitter electron mobility (cm2)/V s 3560 [82]µnc Collector electron mobility (cm2)/V s 3560 [82]ρce Emitter specific contact resistance(Ω cm2) 1×10−7 [82]ρcc Collector specific contact resistance (Ω cm2) 1× 10−7 [82]c Device capacitance(fF/µm2) 4.83g Max. negative differential conductance (Ω−1µm−2) 0.01Γr Full width at half maximum (eV) 0.1
0
100
200
300
400
500
0 0.1 0.2 0.3 0.4 0.5
f max(GHz)
Emitter-collector separation ( µm)
3 x 3 µm2
1 x 9 µm2
.3 x .30 µm2
Figure A.6: High frequency performance of a 9 µm2 RTD as a function of theemitter-collector separation for different emitter geometries.
111
A decrease in the RTD area leads to increased RTD maximum frequencies. This
is because the resistive components like the extrinsic resistance and the collector
contact resistance don’t scale with the RTD emitter area, and the product RSA
decreases with reduction in area, Eq. (A.16). This is observed in Figure A.7,
where the RTD maximum frequency of oscillation is plotted as a function of area,
for square emitter geometries and an emitter-collector separation of 35 nm. The
product RSA is also plotted as a function of area, which is observed to decrease
with reduction in area. As a consequence, the maximum frequency of oscillation
increases, in accordance with Eq. (A.14). With a 0.2 µm×0.2 µm emitter area, an
fmax of 696 GHz is estimated for a emitter-collector separation of 35 nm.
0
10
20
30
40
50
0
100
200
300
400
500
600
700
0 2 4 6 8 10
Rs x Area (Ohm µm
2)
fmax (G
Hz)
Area (µm2)
Emitter-collector separation 35 nm
Figure A.7: Maximum RTD oscillation frequencies as a function of the emitterarea, the emitter-collector separation being 35 nm. Square emitter geometries areassumed.
The maximum frequency of oscillation for the RTD can be increased by, reduc-
112
ing the nitride spacer thickness and using rectangular emitter geometries. As the
spreading and extrinsic resistances are minimized, the RTD maximum frequencies
are limited by the emitter and collector contact resistances. The maximum frequen-
cies can be improved with reduction in device areas, which is observed to be the
most important parameter in improving the RTD maximum oscillation frequency.
113
APPENDIX B
HBT/RTD PROCESS FLOW
114
Process Flow for InP-based Resonant Tunneling Diodes and Heterojunction Bipolar
Transistors Using Optical Lithography
A ten mask process is used to fabricate the InP-based HBTs and RTDs. First, the
RTD emitter metallization is done in a lift-off process (Figure B1). Using the emitter
contact as a mask, CH4/H2 based reactive ion etching of the semiconductor is done to
form the RTD emitter mesa (Figure B2). Anisotropic RIE etching is used to form vertical
sidewalls, finishing with a wet etch.
`
InGaAs 40 nm N+ 1 x 1019 cm-3
InGaAs 40 nm N+ 1 x 1019 cm-3
InP 50 nm N+ 1 x 1019 cm-3
InP 50 nm N 8 x 1017 cm-3
GaAsSb 50 nm P+ 5 x 1019 cm-3
InP 150 nm N 2 x 1016 cm-3
InP 25 nm N+ 1 x 1019 cm-3
InGaAs 400 nm N+ 1 x 1019 cm-3
Semi insulating InP
5 nm InGaAs N 2 x 1019 cm-3
2 nm AlAs undoped1 nm InGaAs undoped
2 nm InAs undoped1 nm InGaAs undoped
2 nm AlAs undoped2 nm InGaAs undoped
5 nm InGaAs N 2 x 1019 cm-3
Ti/Pt/Au
200 nm
1 μm
100 nm
Figure B1. RTD emitter metallization (Mask 1)
115
`InGaAs 40 nm N+ 1 x 1019 cm-3
InP 50 nm N+ 1 x 1019 cm-3
InP 50 nm N 8 x 1017 cm-3
GaAsSb 50 nm P+ 5 x 1019 cm-3
InP 150 nm N 2 x 1016 cm-3
InP 25 nm N+ 1 x 1019 cm-3
InGaAs 400 nm N+ 1 x 1019 cm-3
Semi insulating InP
InGaAs
1 μm
100 nm
Ti/Pt/Au
200 nm
Figure B2. RTD device mesa etching
This is followed by the HBT emitter metallization process in a lift-off process (Figure
B3). Reactive ion etch is then done to etch down to the HBT base layer (Figure B4), with
the RTD device mesa being protected by a photoresist etch mask. CH4/H2 based reactive
ion etches are used to etch InP.
`InGaAs 40 nm N+ 1 x 1019 cm-3
InP 50 nm N+ 1 x 1019 cm-3
InP 50 nm N 8 x 1017 cm-3
GaAsSb 50 nm P+ 5 x 1019 cm-3
InP 150 nm N 2 x 1016 cm-3
InP 25 nm N+ 1 x 1019 cm-3
InGaAs 400 nm N+ 1 x 1019 cm-3
Semi insulating InP
InGaAs
Ti/Pt/Au
260 nm
1 μm
100 nm
Ti/Pt/Au
200 nm
Figure B3. HBT emitter metallization (Mask 2)
116
`InGaAs 40 nm N+ 1 x 1019 cm-3
InP 50 nm N+ 1 x 1019 cm-3
InP 50 nm N 8 x 1017 cm-3
GaAsSb 50 nm P+ 5 x 1019 cm-3
InP 150 nm N 2 x 1016 cm-3
InP 25 nm N+ 1 x 1019 cm-3
InGaAs 400 nm N+ 1 x 1019 cm-3
Semi insulating InP
InGaAs
`
1 μm
100 nm
Ti/Pt/Au
200 nmTi/Pt/Au
260 nm
Figure B4. HBT emitter mesa etch (Mask 3)
Nitride spacers are then formed by blanket depositing silicon nitride followed by
anisotropic reactive ion etching (Figure B5). To form the HBT base (and RTD collector)
contact, tungsten is blanket deposited on the sample.
`InGaAs 40 nm N+ 1 x 1019 cm-3
InP 50 nm N+ 1 x 1019 cm-3
InP 50 nm N 8 x 1017 cm-3
GaAsSb 50 nm P+ 5 x 1019 cm-3
InP 150 nm N 2 x 1016 cm-3
InP 25 nm N+ 1 x 1019 cm-3
InGaAs 400 nm N+ 1 x 1019 cm-3
Semi insulating InP
InGaAs
`
Si3N4 300 nm Si3N4 300 nm
1 μm
100 nm
Ti/Pt/Au
200 nmTi/Pt/Au
260 nm
Figure B5. Silicon nitride sidewall formation
117
`InGaAs 40 nm N+ 1 x 1019 cm-3
InP 50 nm N+ 1 x 1019 cm-3
InP 50 nm N 8 x 1017 cm-3
GaAsSb 50 nm P+ 5 x 1019 cm-3
InP 150 nm N 2 x 1016 cm-3
InP 25 nm N+ 1 x 1019 cm-3
InGaAs 400 nm N+ 1 x 1019 cm-3
Semi insulating InP
InGaAs
`
Si3N4 300 nm Si3N4 300 nm
500 nm W
1 μm
100 nm
Ti/Pt/Au
200 nmTi/Pt/Au
260 nm
Figure B6. HBT base metal deposition
The surface is planarized by spinning on BCB followed by a reflow (Figure B8). The spin
recipe is adjusted so that the BCB thickness is enough to cover the topographical
variations (more than 400 nm). This is followed by etching back the BCB and the
exposed tungsten till the HBT emitter contact level (Figure B9). In practice, this is
determined by step-profile measurements, observing the appearance of the emitter Au
contacts, and through electrical tests do ensure that the emitter and base contacts are
insulated by the spacer.
118
`InGaAs 40 nm N+ 1 x 1019 cm-3
InP 50 nm N+ 1 x 1019 cm-3
InP 50 nm N 8 x 1017 cm-3
GaAsSb 50 nm P+ 5 x 1019 cm-3
InP 150 nm N 2 x 1016 cm-3
InP 25 nm N+ 1 x 1019 cm-3
InGaAs 400 nm N+ 1 x 1019 cm-3
Semi insulating InP
InGaAs
`
Si3N4 300 nm Si3N4 300 nm
Benzocyclobutene (BCB) 1000 nm
1 μm
100 nm
500 nm W
Ti/Pt/Au
200 nmTi/Pt/Au
260 nm
Figure B7. BCB planarization
`InGaAs 40 nm N+ 1 x 1019 cm-3
InP 50 nm N+ 1 x 1019 cm-3
InP 50 nm N 8 x 1017 cm-3
GaAsSb 50 nm P+ 5 x 1019 cm-3
InP 150 nm N 2 x 1016 cm-3
InP 25 nm N+ 1 x 1019 cm-3
InGaAs 400 nm N+ 1 x 1019 cm-3
Semi insulating InP
InGaAs
`
Si3N4 300 nm Si3N4 300 nm
1 μm
100 nm
500 nm W
Benzocyclobutene (BCB)
Ti/Pt/Au
200 nmTi/Pt/Au
260 nm
Figure B8. Etchback of BCB.
119
`InGaAs 40 nm N+ 1 x 1019 cm-3
InP 50 nm N+ 1 x 1019 cm-3
InP 50 nm N 8 x 1017 cm-3
GaAsSb 50 nm P+ 5 x 1019 cm-3
InP 150 nm N 2 x 1016 cm-3
InP 25 nm N+ 1 x 1019 cm-3
InGaAs 400 nm N+ 1 x 1019 cm-3
Semi insulating InP
InGaAs
`
Si3N4 300 nm Si3N4 300 nm
1 μm
100 nm
500 nm W
Benzocyclobutene (BCB)
Ti/Pt/Au
200 nmTi/Pt/Au
260 nm
Figure B9. Tungsten etch.
The HBT base contacts are defined by a reactive ion etch process of tungsten (Figure
B10). This is followed by wet-etching to the InP subcollector layer (Figures B11-B12).
This etch is done with W as the etch mask, so GaAsSb and InP etchants not attacking W
are used. To stop at the InGaAs subcollector, selective etchants for InP over InGaAs such
as HCl: H3PO4 is used. The base can be undercut to reduce the base-collector capacitance.
`InGaAs 40 nm N+ 1 x 1019 cm-3
InP 50 nm N+ 1 x 1019 cm-3
InP 50 nm N 8 x 1017 cm-3
GaAsSb 50 nm P+ 5 x 1019 cm-3
InP 150 nm N 2 x 1016 cm-3
InP 25 nm N+ 1 x 1019 cm-3
InGaAs 400 nm N+ 1 x 1019 cm-3
Semi insulating InP
InGaAs
`
W
260 nm W
400 nm
1 μm
100 nm
Ti/Pt/Au
200 nmTi/Pt/Au
260 nm
Figure B10. HBT base contact definition (Mask 4)
120
`InGaAs 40 nm N+ 1 x 1019 cm-3
InP 50 nm N+ 1 x 1019 cm-3
InP 50 nm N 8 x 1017 cm-3
InP 150 nm N 2 x 1016 cm-3
InP 25 nm N+ 1 x 1019 cm-3
InGaAs 400 nm N+ 1 x 1019 cm-3
Semi insulating InP
InGaAs
`
GaAsSb 50 nm GaAsSb 50 nm
1 μm
100 nm
W
260 nm W
400 nm
Ti/Pt/Au
200 nmTi/Pt/Au
260 nm
Figure B11. Etching of the HBT base
`InGaAs 40 nm N+ 1 x 1019 cm-3
InP 50 nm N+ 1 x 1019 cm-3
InP 50 nm N 8 x 1017 cm-3
InP 150 nm N 2 x 1016 cm-3
InP 25 nm N+ 1 x 1019 cm-3
InGaAs 400 nm N+ 1 x 1019 cm-3
Semi insulating InP
InGaAs
`
GaAsSb 50 nm
1 μm
100 nm
GaAsSb 50 nm
W
260 nm W
400 nm
Ti/Pt/Au
200 nmTi/Pt/Au
260 nm
Figure B12. Etching of the HBT collector
The next step is to define the HBT and RTD device mesas by a wet etch process (Figure
B13) to etch down to the semi-insulating InP substrate. A lift-off metallization process is
used to deposit the resistor metal on the semi-insulating substrate (Figure B14).
121
`InGaAs 40 nm N+ 1 x 1019 cm-3
InP 50 nm N+ 1 x 1019 cm-3
InP 50 nm N 8 x 1017 cm-3
InP 150 nm N 2 x 1016 cm-3
InP 25 nm N+ 1 x 1019 cm-3
InGaAs 400 nm N+ 1 x 1019 cm-3
Semi insulating InP
InGaAs
`
GaAsSb 50 nm
1 μm
100 nm
GaAsSb 50 nm
W
260 nm W
400 nm
Ti/Pt/Au
200 nmTi/Pt/Au
260 nm
Figure B13. Isolation etching (Mask 5)
`InGaAs 40 nm N+ 1 x 1019 cm-3
InP 50 nm N+ 1 x 1019 cm-3
InP 50 nm N 8 x 1017 cm-3
InP 150 nm N 2 x 1016 cm-3
InP 25 nm N+ 1 x 1019 cm-3
InGaAs 400 nm N+ 1 x 1019 cm-3
Semi insulating InP
InGaAs
`
GaAsSb 50 nm
50 nm
Nichrome
1 μm
100 nm
GaAsSb 50 nm
W
260 nm W
400 nm
Ti/Pt/Au
200 nmTi/Pt/Au
260 nm
Figure B14. Resistor metal deposition (Mask 6)
This is followed by a lift-off process which deposits the HBT collector contact, the
contact for the resistor, and the bottom electrode for the capacitor (Figure B15). Silicon
nitride is then deposited to insulate the devices and to form the dielectric for the capacitor
(Figure B16).
122
`InGaAs 40 nm N+ 1 x 1019 cm-3
InP 50 nm N+ 1 x 1019 cm-3
InP 50 nm N 8 x 1017 cm-3
InP 150 nm N 2 x 1016 cm-3
InP 25 nm N+ 1 x 1019 cm-3
InGaAs 400 nm N+ 1 x 1019 cm-3
Semi insulating InP
InGaAs
`
GaAsSb 50 nm
Ti/Pt/Au
300 nm
Ti/Pt/Au
300 nm
Ti/Pt/Au
300 nm
GaAsSb 50 nm
1 μm
100 nm
W
260 nm W
400 nm
Ti/Pt/Au
200 nmTi/Pt/Au
260 nm
Figure B15. Capacitor metal deposition (Mask 7)
`InGaAs 40 nm N+ 1 x 1019 cm-3
InP 50 nm N+ 1 x 1019 cm-3
InP 50 nm N 8 x 1017 cm-3
InP 150 nm N 2 x 1016 cm-3
InP 25 nm N+ 1 x 1019 cm-3
InGaAs 400 nm N+ 1 x 1019 cm-3
Semi insulating InP
InGaAs
`
GaAsSb 50 nm
Ti/Pt/Au
300 nm
Ti/Pt/Au
300 nm
Ti/Pt/Au
300 nm
Si3N4 200 nm
GaAsSb 50 nm
1 μm
100 nm
W
260 nm W
400 nm
Ti/Pt/Au
200 nmTi/Pt/Au
260 nm
Figure B16. Silicon nitride depositon
The top electrode for the capacitor is formed in a lift-off metallization process (Figure
B17). This is followed by etching the via through the nitride (Figure B18). The last step
of the process is to deposit the interconnect metal (not shown in this document).
`InGaAs 40 nm N+ 1 x 1019 cm-3
InP 50 nm N+ 1 x 1019 cm-3
InP 50 nm N 8 x 1017 cm-3
InP 150 nm N 2 x 1016 cm-3
InP 25 nm N+ 1 x 1019 cm-3
InGaAs 400 nm N+ 1 x 1019 cm-3
Semi insulating InP
InGaAs
`
GaAsSb 50 nm
Ti/Pt/Au
300 nm
Ti/Pt/Au
300 nm
Ti/Pt/Au
300 nm
Si3N4 200 nm
Ti/Pt/Au
300 nm GaAsSb 50 nm
1 μm
100 nm
W
260 nm W
400 nm
Ti/Pt/Au
200 nmTi/Pt/Au
260 nm
Figure B17. Capacitor metal deposition (Mask 8)
123
`InGaAs 40 nm N+ 1 x 1019 cm-3
InP 50 nm N+ 1 x 1019 cm-3
InP 50 nm N 8 x 1017 cm-3
InP 150 nm N 2 x 1016 cm-3
InP 25 nm N+ 1 x 1019 cm-3
InGaAs 400 nm N+ 1 x 1019 cm-3
Semi insulating InP
InGaAs
`
GaAsSb 50 nm
Ti/Pt/Au
300 nm
Ti/Pt/Au
300 nm
Ti/Pt/Au
300 nm
Ti/Pt/Au
300 nm GaAsSb 50 nm
1 μm
100 nm
W
260 nm W
400 nm
Ti/Pt/Au
200 nmTi/Pt/Au
260 nm
Figure B18. Etching of the silicon nitride to form via (Mask 9)
124
APPENDIX C
PUBLICATIONS
125
Device Research Conference 2008, pages 65-66.
Structural Sensitivity of Interband Tunnel Diodes for SRAM Surajit Sutar, Qin Zhang, and Alan Seabaugh, University of Notre Dame
Department of Electrical Engineering, University of Notre Dame, Notre Dame, IN-
46556, phone-(574)631-4473, fax-(574)631-4393, [email protected]
As III-V channel MOSFETs are developed to lower supply voltage and power1, the use of high peak-to-
valley-current ratio (PVCR) III-V tunnel diodes for tunnel SRAM2,3 becomes feasible. Tunneling-based static random access memory (TSRAM)3 requires tunnel diodes with low peak current density JP (<10
nA/µm2), low peak voltage (<100 mV) and high PVCR, exceeding 100. While tunnel diodes with low peak
currents and voltages3 (1.5 nA/µm2 at under 100 mV and PVCR of 3) and high PVCR4 (144 at 1600
nA/µm2 and >700 mV) have been reported, a device that simultaneously meets all the requirements for
TSRAM is yet to be demonstrated. Here, we present a study to outline the design space and trade-offs for
high PVCR, low-voltage, low-current tunnel diodes with best results for peak currents and voltages being
4.3 nA/µm2, 50 mV with PVCR of 15, and demonstrate a fabrication process yielding submicron interband
tunnel diodes for the first time. The PVCR of submicron diodes is observed to degrade for submicron
device mesas indicating the need for passivation to maintain the PVCR.
InP-based p-n double quantum-well (QW) resonant interband tunnel diodes5, grown by IQE Inc.,
Bethlehem, PA, were fabricated using a contact lithography/lift-off process for the Pd/Ti/Pd/Au contact for
the p-InGaAs emitter, followed by a wet etch to define the device mesa. The devices were measured top-to-back, with a Ti/Pt/Au back contact to the n-InP substrate. A set of five wafers were grown with a
systematic variation in the epitaxial structure (with the first two growths replicating epitaxial structures
used previously published6). Growths 1 and 2 differ in the thickness of the center InAlAs barrier TCB, 2, 4
nm, respectively. Growths 2, 3, 4 and 5 contain a monotonic decrease in the effective doping density NEff
=NDNA/(ND+NA), NA and ND being the p emitter and the n collector doping densities, respectively. The
structure sequence was designed to lower the peak voltage and tunneling currents: the increase in TCB
decreases the tunneling transmission coefficient, the decrease in NEff decreases both the electron-hole state
overlap (thus the peak voltage) and the tunneling transmission coefficients of the barriers formed by the p
and n depletion regions. As NEff is lowered from 1.5 (growth 2) to 0.3 x 1019 cm-3 (growth 5), JP is reduced
from 34 µA/µm2 to 4.3 nA/µm2, while the peak voltage decreases from 240 to 50 mV. An exception to this
trend is growth 4 (NEff = 0.42 x 1019 cm-3), where no negative differential resistance (NDR) is observed. This can be accounted by the asymmetric p and n side space charge barriers in growth 4, resulting from
asymmetric doping densities (ND = 0.5 x 1019, NA = 3 x 1019 cm-3), which leads to a reduced transmission
coefficient7 and a lower resonant tunneling current. In contrast, growth 5, which has an even lower NEff but
more symmetric doping densities (ND = 0.5 x 1019, NA = 1 x 1019 cm-3) shows NDR. For low tunneling
current, the PVCR is limited by the fact that the valley current JV is determined by the forward biased p-n
junction diode current, and reaches a value 15 for growth 5. With the increase in TCB from 2 to 4 nm, JP is
reduced from 312 (growth 1) to 34 µA/µm2 (growth 2). As a comparison, for the same epitaxial structures,
the values of JP reported by Day et al.6 were 2 and 1.7 µA/µm2, respectively. The observed PVCRs were 39
(growth 1) and 50 (growth 2), compared to 104 and 68. This large variation in the peak currents and
PVCRs for the same device structures points to a high sensitivity of the tunneling current on the growth
conditions. Submicron emitter RTDs were fabricated in the way described above, with the following changes:
electron beam lithography to form the emitter patterns, a PECVD SiO2 sidewall on the emitters to prevent
the emitters from lifting-off during wet etch, and a Benzocyclobutene (BCB) planarization and etchback
step, followed by a Ti/Au bondpad lift-off process to contact the submicron emitters. The peak currents are
observed to scale with area for sizes 10 x 10 µm2 to 250 x 250 nm2. However, the valley currents deviate
from a linear relationship with area for submicron scaling, lowering the PVCRs, with the submicron device
PVCR for growth 5 being as low as 5. Subsequent annealing in N2 didn’t improve the PVCRs and degraded
1 S. Datta et al., Electron Dev. Lett, 28, 685-687 (2007).
2 J. P. A. van der Wagt et al., IEEE Electron Dev. Lett. 19, 7-9 (1998).
3 J. P. A. van der Wagt, Proc. IEEE 87, 571-595 (1999).
4 H. H. Tsai, et al., IEEE Electron Device Letters, 15, 357-359 (1994).
5 M. Sweeny, et al., Appl. Phys. Lett,. 54, 546-549 (1989).
6 D. J. Day, et al., J. Appl. Phys, 73, 1542-1544 (1993).
7 B. Ricco et al., Phys. Rev. B, 29, 1970-1981 (1984).
126
Device Research Conference 2008, pages 65-66.
the tunneling current. The trend of the valley currents with area shows a leakage component and calls for
suitable in-process passivation schemes.
The support of Intel is gratefully acknowledged.
-2
-1
0
1
2
Energ
y (
eV
)
p+ InGaAs
n+
InGaAs
EF
InAlAs center barrer
thickness TCB
4 nm
4p+ InAlAsemitter
NA 3x10
19 cm
-3
32
Growth
n+ InAlAs
collector
ND
-2
-1
0
1
2
0 10 20 30 40 50 60 70
Energ
y (
eV
)
Position (nm)
p+ InGaAs
n+ InGaAs
EF
InAlAs center barrer
thickness TCB
4 nm
p+ InAlAsemitter
NA 1x10
19 cm
-3
Growth 5
ND 5x10
19 cm
-3
Figure 1. Energy band diagrams for InP-based p-n interband
tunnel diodes (a)In growths 2, 3, and 4 the collector doping, ND, is
varied, 3, 1, 0.5 x 1019
cm-3
respectively, to change both interband
overlap and the n-side space-charge-barrier, (b) Growth 5 is the
same as growth 4 with lower p emitter doping. Growth 1 (not
shown) is the same as growth 2, with the center InAlAs barrier
thickness TCB reduced from 4 to 2 nm.
Figure 2. Current-voltage (I-V) characteristics for growths 1-5, the
peak (JP)and valley (JV) currents decrease with both the decrease
in TCB(growth 1-2) and the effective doping density NEff(growth 2-
5).
Figure 3. Variation of JP and JV and peak-to-valley current ratio
(PVCR):Increasing TCB from 2 to 4 nm decreases JP, JV by an
order of magnitude; decreasing NEff by a factor of 5 decreases JP
and JV by 4 orders of magnitude.
Figure 4. For the same epitaxial structures, JP and PVCR are
found to vary widely. This can be understood by the high
sensitivity of tunnel current to changes in TCB and NEff.
Figure 5. Submicron tunnel diode process: (a) scaled cross-
section of the fabricated devices, emitters formed by electron
beam lithography and lift-off, SiO2 sidewall formed to allow for
undercut during wet etch, top Ti/Au bondpad layer to contact the
emitters after a BCB planarization and etchback, (b) SEM
micrograph of 0.25x0.25 µm2 emitters after wet etching.
Figure 6. Peak and valley currents as a function of device area,
peak currents agree well with a least squares linear fit with device
area, valley currents deviate from the linear fit with scaling,
resulting in the degradation of PVCR beginning near micron
sizes.
(a)
(b)
(a)
(b)
10-8
10-7
10-6
10-5
10-4
10-3
10-2
10-1
-1 -0.5 0 0.5 1
Curr
en
t (A
)
Voltage (V)
18 m diameteremitter
Growth 12
3
4
5
10-8
10-6
10-4
10-2
100
0 0.5 1 1.5 20
50
100
150
200
Cu
rren
t d
en
sity (
mA
/m
2)
NEff
(1019
cm-3
)
Jp
Jv
PVCR
PV
CR
TCB 4 nm
10-8
10-6
10-4
10-2
100
0 1 2 3 4 50
50
100
150
200
Cu
rre
nt
de
nsity (
m2)
Barrier thickness (nm)
18 m dia emitter
ND=3e19 cm
-3
NA=3e19 cm
-3
Jp
Jv
PVCR
PV
CR
10-12
10-10
10-8
10-6
10-4
10-2
0.01 0.1 1 10 100
Cu
rren
t (A
)
Device area ( m2)
Growth 1
2
3
5
Peak current
0.01 0.1 1 10 100Device area ( m
2)
Growth 1
2
3
5
Valley current
Area ( m2) J P ( A/ m2) PVCR
Day 1993 7850 2 104
Tsai 1994 17662 1 144
Wafer 1 254 312 39
Day 1993 7850 1.7 68
Wafer 2 254 34 50
127
Device Research Conference 2008, pages 65-66.
Figure 7. Submicron interband tunnel diode showing PVCR of
38, which is less than the value of 49 obtained for 10 x 10 µm2
diodes for the same wafer. Repeated post growth anneals in
nitrogen does not recover the PVCR and results in significant
degradation in the device conductance and the PVCR.
0
1 10-4
2 10-4
0 0.5 1 1.5 2
200 30
200 30
250 10
300 10
Cu
rren
t (A
)
Bias (V)
Growth 1
0.75x0.75 m2
Annealed in N2
Annealing steps
Temp (ºC) Time (min)
128
October 14, 2004 14:55 WSPC/INSTRUCTION FILE4q0930LesterEastman
International Journal of High Speed Electronics and Systemsc© World Scientific Publishing Company
TUNNEL DIODE/TRANSISTOR DIFFERENTIAL COMPARATOR
QINGMIN LIU, SURAJIT SUTAR, AND ALAN SEABAUGH
Department of Electrical Engineering, University of Notre DameNotre Dame, IN 46556, USA
A new tunnel diode/transistor circuit topology is reported, which both increases speedand reduces power in differential comparators. This circuit topology is of special interestfor use in direct digital synthesis applications. The circuit topology can be extendedto provide performance improvements in high speed logic and signal processing appli-cations. The circuits are designed based on InP/GaAsSb double heterojunction bipolartransistors and AlAs/InGaAs/AlAs resonant tunneling diodes. A self-aligned and scal-able fabrication approach using nitride sidewalls and chemical mechanical polishing isoutlined.
Keywords: Differential comparator; flip-flop; tunnel diode; resonant tunneling diode;heterojunction bipolar transistor; nitride sidewall; chemical mechanical polishing.
1. Introduction
As minimum feature sizes are reached in transistor technologies, circuit performancecan be expected to saturate. Therefore, it is important to find new ways to augmentthe performance of integrated circuit technology. Integrated tunnel diodes enabledesign options which can result in a decrease in power dissipation and an increasein speed and function per area.1
Since 1957, the tunnel diode has been widely investigated for high-speed circuitapplications, due to its intrinsic high switching speed, and its “N-shaped” current-voltage (I−V) characteristic featuring negative differential resistance (NDR).2,3
Today, methods for integrating tunnel diodes with transistors in compound semi-conductor technologies are well known.4,5,6 In silicon technology both Si and SiGep+n+ tunnel diodes have been fabricated using CMOS-compatible processes.7,8
Monolithic integration of a Si-based tunnel diode and a heterojunction bipolartransistor (HBT) have also been demonstrated.9
In this paper, we report on a circuit topology, utilizing high speed tunnel diodesintegrated with transistors to lower the static power dissipation in a differentialcomparator and simultaneously increase the circuit speed. A novel scalable fabri-cation approach using nitride sidewalls and chemical mechanical polishing is alsooutlined for fabricating this tunnel diode/transistor (TDT) differential comparator.The circuit is currently under fabrication, and the testing results will be reportedin the future.
1
129
October 14, 2004 14:55 WSPC/INSTRUCTION FILE4q0930LesterEastman
2 Q. Liu et al.
2. Circuits Design
The schematic of the TDT differential comparator is shown in Fig. 1(a). Two tunneldiode pairs, D1-D3 and D2-D4, are connected to the outputs of the differential pairQ1 and Q2. Emitter followers Q3 and Q4 are used to buffer the output signal.
Q1 Q2
ITAIL
−VEE
VCC
Q4Q3
VOUT
RL
I1 I2
RL
VOUT
CK
VIN VIN
D1
D3
D2
D4X
Q1 Q2
ITAIL
−VEE
VCC
Q4Q3
VOUT
RLI1 I2
RL
VOUTVIN VIN
RC RC
X
(a) (b)
Fig. 1. Schematic diagrams of (a) tunnel diode/transistor (TDT) and (b) conventional bipolartransistor differential comparator.
When the clock is at a low level, the tunnel diode pair is in a monostable state.In this state, no matter what the applied input signal, the output voltage is low.When the clock switches to a high level, the tunnel diode pair switches to a bistablestate. The output voltage latches to either a high or low voltage state, determinedby the tunnel diode peak currents and the transistor collector current occurring atthe rising edge of the clock. The peak currents, IP3 and IP4, of diodes, D3 and D4,are designed to be greater than the peak currents, IP1 and IP2, of diodes, D1 andD2, with the following relationships IP3 < IP1+ITAIL and IP4 < IP2+ITAIL. If theinput to transistor Q1 is low, the tail current, ITAIL, flows through transistor Q2.When the clock switches from low to high, the output voltage at node X switchesto the high level, because diode D1 has a smaller peak current and switches first.If, on the other hand, the input to transistor Q1 is high, the tail current, ITAIL,flows through Q1. When the clock switches from low to high, the output voltage atnode X remains low, because IP3 < IP1 + ITAIL and diode D3 switches instead ofD1. This circuit functions as an edge-triggered return-to-zero (RZ) D flip-flop withcomplementary input and output.
The TDT circuit, Fig. 1(a), has smaller output open-circuit time constant ofthe differential pair and faster switching speed than a conventional transistor-onlycurrent-mode-switching differential amplifier,10 Fig. 1(b). In transistor-only com-parator circuits, speed improvements are usually obtained by increasing the tail
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October 14, 2004 14:55 WSPC/INSTRUCTION FILE4q0930LesterEastman
Tunnel Diode/Transistor Differential Comparator 3
current and decreasing the pull-up collector resistor. The tunnel diodes enable thedifferential pair current-switching at a lower tail current than the transistor-onlydifferential pair. The tunnel diodes, therefore, lower the static power dissipationand simultaneously increase the circuit speed.10
3. Direct Digital Synthesis
This TDT differential comparator is of special interest for use as a switching elementin direct digital synthesis applications. A recently developed algorithm, based onlist decoding, for DDS provides an improved signal-to-noise ratio (SNR), comparedwith conventional Σ∆ approaches.11,12 In both list decoding and Σ∆ approaches, aspecially designed digital bitstream is output through a single-bit digital-to-analogconverter (DAC) and a reconstruction filter to form the analog signal. The Fourierspectrum of the desired signal is embedded in the pattern of the bitstream. A high-speed and high-linearity single-bit DAC is required to achieve high SNR, becausethe severe distortion of the output signal is usually generated from the nonlinearityof the DAC. The circuits, proposed in this paper, are designed for use in such DDSapplications.
To compare the power dissipation and linearity of both TDT and transistor-onlycircuits, we simulated both circuits (Fig. 1) in Agilent ADS. The transistor SPICEmodel we used in the simulation is for a high speed InP-based heterojunction bipolartransistor (HBT) with fT /fMAX of 140/340 GHz. Broekaert’s RTD model13 is usedfor an InP-based RTD with a speed index of 316 mV/ps. The input bitstream hasa 100 Gbps bit rate, and an amplitude of 400 mV with rising and falling timeof 1 ps. The synthesized passband signal frequency is approximately 37.3 GHz.The simulated spectrum of the synthesized signal in both TDT and transistor-onlycircuits is shown in Fig. 2. Approximately 60 dBc spur free dynamic range (SFDR)is obtained for both circuits, showing these two circuits have approximately thesame linearity. The power dissipation of both circuits are also compared and shownin Table 1. The power dissipation is reduced by approximately 4× in the TDTdifferential pair and 1.6× in the full TDT circuit.
Table 1. Comparison of the power dissipation in theTDT and conventional HBT differential compara-tors of Fig. 1.
Power dissipation TDT (mW) HBT (mW)
Differential pair 3 12.5Clock 0.5 0
Emitter followers 25.5 34Total 29 46.5
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4 Q. Liu et al.
32 34 36 38 40 42
20
40
60
80
100
Frequency (GHz)
dB
(a)
32 34 36 38 40 42
20
40
60
80
100
Frequency (GHz)
dB
(b)
Fig. 2. Simulated output spectrum of the synthesized passband signal for (a) tunneldiode/transistor and (b) transistor-only differential comparator showing 60 dBc SFDR around37.3 GHz. This simulation uses high speed InP-based HBT and RTD models.
4. Fabrication Approach
A fabrication approach using AlAs/InGaAs/AlAs RTDs and InP/GaAsSb HBTs isdescribed. The material layer structure is grown by molecular beam epitaxy (MBE).The energy band diagram of the structure is shown in Fig. 3.
-2
-1
0
1
2
0 100 200 300 400 500
Ene
rgy
(eV
)
Position (nm)
GaAsSbHBTBase
InPHBT
Collector
InPHBT
Emitter
AlAs/InGaAsRTD
EF
EC
EV
InGaAsHBT
Subcollector
Fig. 3. Simulated energy band diagram of InP-based RTD/HBT structure, computed using theSchrodinger-Poisson solver, BandProf, of W. R. Frensley.
The process uses silicon nitride sidewalls and chemical mechanical polishing(CMP) to get scalable self-aligned contacts for the RTD and HBT. A schematiccross section of the RTD/HBT fabrication process is shown in Fig. 4. The RTD and
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Tunnel Diode/Transistor Differential Comparator 5
GaAsSb Base 40 nm
Mo400 nm Mo
130 nm
Au 130 nm
Si3N4 200 nm
Ti/Pt/Au 150 nm
150 nm
InP Substrate
Mo 100 nmMo
260 nm
Au 100 nmMo
260 nmMo
400 nm
InGaAs Subcollector 50 nm
InGaAs Subcollector50 nm
RTD Layers (from top to bottom):45 nm InGaAs, 2 nm AlAs, 1 nm InGaAs,
2 nm InAs, 1 nm InGaAs, 2 nm AlAs, 7 nm InGaAs
GaAsSb Base 40 nm
InP Emitter 100 nm
InP Collector 150 nm InP Collector 150 nm
InP Emitter100 nm
InGaAscap
RTD HBT
InP Subcollector, 300 nm InP Subcollector, 300 nm
Fig. 4. Integrated resonant tunneling diode and heterojunction bipolar transistor fabrication ap-proach, drawn to scale in the y-direction.
HBT emitter contacts are formed by lift-off. After defining the RTD and HBT mesasusing reactive ion etching (RIE), silicon nitride sidewalls are formed by depositinga plasma-enhanced chemical vapor deposition (PECVD) Si3N4 film, followed byan RIE process using CHF3. A blanket deposition of Mo is used to form self-aligned RTD collector and HBT base contacts. Chemical mechanical polishing isemployed to polish the molybdenum and electrically isolate the HBT emitter andbase contacts, as well as the RTD emitter and collector contacts. The isolation isprovided by the silicon nitride sidewall. An RIE process with CF4/O2 is used toetch the molybdenum and define the RTD collector and HBT base contacts. TheHBT collector contact is formed by lift-off. The silicon nitride sidewalls can bescaled to minimize the HBT base resistance and RTD series resistance and enhancethe speed of the devices.
5. Conclusions
A new tunnel diode/transistor differential comparator is described for loweringpower dissipation while simultaneously increasing speed. A fabrication approachfor InP/GaAsSb HBTs and AlAs/InGaAs/AlAs RTDs using a novel scalable pro-cess, featuring nitride sidewalls and chemical mechanical polishing is also outlined.This circuit topology can be applied to all materials systems which can integrate aresonant or Esaki tunnel diode and therefore is applicable to Si and SiGe BiCMOStechnologies, GaAs, InP, InAs, and GaN-based transistor technologies.
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6 Q. Liu et al.
Acknowledgments
We would like to thank the Office of Naval Research under contract N00014-02-1-0924 for supporting this work. We would also like to thank Patrick Fay, OliverCollins, and Ajay Gupta for valuable advice and discussion.
References
1. A. Seabaugh, X. Deng, T. Blake, B. Brar, T. Broekaert, R. Lake, F. Morris, and G.Frazier, “Transistors and tunnel diodes for analog/mixed signal circuits and embeddedmemory”, in 1998 Int. Electron Dev. Mtg. Tech. Dig., December 1998, pp. 429–432.
2. W. F. Chow, Principles of Tunnel Diode Circuits, John Wiley, NY, 1964.3. J. O. Scanlan, Analysis and Synthesis of Tunnel Diode Circuits, John Wiley, NY, 1966.4. J. C. Yen, Q. Zhang, M. J. Mondry, P. M. Chavarkar, E. L. Hu, S. I. Long, and U. K.
Mishra, “Monolithic integrated resonant tunneling diode and heterostructure junctionfield effect transistor circuits”, Solid-State Electron. 39 (1996) 1449–1455.
5. T. Waho, K. J. Chen, and M. Yamamoto, “Resonant-tunneling diode and HEMT logiccircuits with multiple thresholds and multilevel output”, IEEE J. Solid-State Circ. 33(1998) 268–274.
6. A. Seabaugh, B. Brar, T. Broekaert, F. Morris, P. van derWagt, and G. Frazier,“Resonant-tunneling mixed-signal circuit technology”, Solid-State Electron. 43 (1999)1355–1365.
7. J. Wang, D. Wheeler, Y. Yan. J. Zhao, S. Howard, and A. Seabaugh, “Silicon tunneldiodes formed by proximity rapid thermal diffusion”, IEEE Electron Dev. Lett. 24(2003) 93–95.
8. L. -E. Wernersson, S. Kabeer, V. Zela, E. Lind, J. Zhang, W. Seifert, T. Kosel, and A.Seabaugh, “SiGe Esaki tunnel diodes fabricated by UHV-CVD growth and proximityrapid thermal diffusion”, Electron. Lett. 40 (2004) 83–85.
9. S. -Y. Chung, N. Jin, P. R. Berger, R. Yu, P. E. Thompson, R. Lake, S. L. Rommel, andS. K. Kurinec, “Three-terminal Si-based negative differential resistance circuit elementwith adjustable peak-to-valley current ratios using a monolithic vertical integration”,Appl. Phys. Lett. 84 (2004) 2688–2690.
10. Q. Liu and A. Seabaugh, “Design approach using tunnel diodes for lowering power indifferential comparators”, submitted, IEEE Trans. Circ. Syst. II (2004).
11. A. K. Gupta and O. M. Collins, “A new interpretion and extension of Σ∆ modula-tion”, in Proc. IEEE Int. Symp. Info. Theory, Washton, D.C., 2001, pp. 194.
12. A. K. Gupta and O. M. Collins, “Viterbi decoding and Σ∆ modulation”, in Proc.IEEE Int. Symp. Info. Theory, Lausanne, Switzerland, 2002, pp. 292.
13. T. P. E. Broekaert, B. Brar, J. P. A van der Wagt, A. C. Seabaugh, F. J. Morris, T. S.Moise, E. A. Beam, and G. A. Frazier, “A monolithic 4-Bit 2-Gsps resonant tunnelinganalog-to-digital converter”, IEEE J. Solid-State Circ., 33 (1998) 1342–1349.
134
APPENDIX D
HBT/RTD PROCESS TRAVELER
135
InP RTD/HBT Process Traveler HBT RTD mask
S. Sutar/A. Seabaugh
Purpose/Changes from the last run:
Retain the SiO2 based sidewall spacer process.
Retain the all wet etch process, try a more aggressive rinsing of the wafer after InP
wet etch. For the HBT emitter mesa etch, in order to minimize the possible enhanced
etching because of metal mask-etchant interaction, form a 100 nm SiO2 sidewall on the
emitter before etching.
For lift-off process, use 5000 rpm spin speed to get 2 µm features. To reduce chances of
wafer breakage make sure the wafer backside is clean.
No top Ti layer on the RTD HBT emitter contact as there is no MHA RIE step.
RTD Emitter RTD Emitter Mask – Layer 1
Inspect under microscope, note surface condition
Solvent clean
Soak in hot acetone (boiling point 56.5 ºC) hot plate 60 ºC, 3 min
Soak in hot methanol (boiling point 64.7 ºC) hot plate 60 ºC, 3 min
Remove surface oxide
Prepare 1-10 etchant 1HCl:10H2O – add acid to water, wait to cool.
Rinse in DI water (DI) 1 min.
Soak in 1-10 ___ s.
DI rinse 1 min
Blow dry with N2
Microscope inspection – step profile roughness if necessary
AZ5214E image reversal photoresist process
Measure room temperature _____ ºC Humidity _____%
Spin AZ5214E 5000 rpm (1000 rpm/s ramp) 30 s (1.2 µm)
Hot plate soft bake 105 °C 30 s
Stepper temperature ________ ºC (19 ºC) Calibration date ___________
Expose (GCA 6300 stepper1) ____________________ s (2 s)
Hot plate reversal bake 110 °C 60 s
Measure intensity on Karl Suss MJB3 (expect 14 mW/cm2) ______ W/cm
2
Flood-expose in Karl Suss, 250 mJ/cm2 (250/intensity = 18 s) ________ s
Develop in AZ917-MIF2 45 s
Rinse in DI 30 s
Blow dry with N2
Descum in O2 plasma in Tegal Barrel asher3: ______ mTorr (300), gas flow
setting ____(2), forward power____W (100), reflected power____W(10), time
____s (60)99.999% O2 purity.
1 Exposure wavelength for g-line stepper is 436 nm
2 MIF,metal ion free, active chemistry TMAH, tetramethylammonium hydroxide, (CH3)4NOH
3 Tegal company Model 421.
136
Soak in 1-10 5 s
DI rinse 10 s
Blow dry with N2
Load without delay
Evaporate RTD emitter FC18004 # (2)
Pump chamber to < 2 x 10-6
Torr Record base pressure ___ x 10-7
Torr
FC1800 system set points – check and record actual setting
Metal Ti Pt Au Ti Pt Au
Tooling* 120 120 120 V (kV) 8 8 8
Density (g/cm3) 4.5 21.4 19.3 I (A)
Z-ratio 0.628 0.245 0.381 Long. freq. (Hz) 3 3 3
Rate (Å/s) 4 0.5 5 Lat. freq. (Hz) 3 3 3
Thickness (Å) 100 100 1800 Long. Ampl. (A) 0.1 0.1 0.1
Lat. Ampl. (A) 0.3 0.1 0.3
Evaporation parameters Beam parameters
* This tooling is for the angled holder housing two 100 mm diameter plates with clips.
Evaporation notes:
Prepare hot acetone (boiling point 56.5 ºC) hot plate 60 ºC
Vent and unload wafers
Lift-off
Transfer wafers into hot acetone
Soak in acetone 10 min and start timer Record actual soak time _____ min
Acetone spray ___ min to complete lift-off
Microscope inspect to see if more acetone spray is needed
Soak in methanol 2 min
Blow dry with N2
Alpha-Step5
Step profile emitter metal height. Expect 2200 Å.
Cell 1 2 3
Thickness (Å)
Measure the RTDE emitter TLM (2-probes/pad) contact width 76 µm
4 Airco Temescal electron-beam evaporator
5KLA-Tencor Alpha Step 500 surface profiler
137
2
4
8
16
32
Resistance
( )
Contact
separation ( m)
Sheet res.
( /sq.)
Specific Contact
resistance
( /sq.)Correlation
coefficient
Resistance
( )
Resistance
( )
Resistance
( )
Resistance
( )
RTD Emitter Mesa Etch
Solvent clean as previously described.
Blow dry in N2
Prepare 1-8-160 etchant 1H2SO4: 8H2O2:160 H2O InGaAs etch rate ~ 40-60 Å/s
o 320 ml DI + 16 ml H2O2 + 2 ml 1H2SO4 - add acid to water
o Cool before etching
RTD layers should be removed if a 63 nm etch depth is achieved.
Rinse in DI 1 min
Etch in 1-8-160 ______ s to remove ______ Å
Rinse 1 min in DI
Blow dry with N2
Step profile, mesa height, Expect 2830 Å.
Cell 1 Cell 2 Cell 3
Thickness/Roughness (Å)
If etch depth is less than 623 Å, continue to etch to achieve an ideal etch depth of
750 Å
Final mesa height:
Cell 1 Cell 2 Cell 3
Thickness/Roughness (Å)
Ideal etch depth 750 Å. Ok if between 623 and 1223 Å
Microscope inspect
Measure RTD I-V to assure that etch depth is sufficient
Etch in 1-8-160 as necessary to complete
138
HBT Emitter Metallization HBT Emitter Mask – Layer 2
Microscope inspection
Solvent clean
Blow dry with N2
AZ5214E image reversal photoresist process
Measure room temperature ______ ºC Humidity _____%
Expose/develop GaAs pilot (Spin PR1813 800 rpm 3 s, 2500 rpm 30 s bake 90 °C
1 min) to find the misalignment corrections:
Left X_______ Left Y______ Right X ______ Right Y ___
Spin AZ5214E 5000 rpm (1000 rpm/s ramp) 30 s (1.2 µm)
Hot plate soft bake 105 °C 30 s
Stepper temperature ________ ºC (19 ºC) Calibration __________
Expose (GCA 6300 stepper) ____________________ s (2.9 s)
Hot plate reversal bake 110 °C 60 s
Measure intensity on Karl Suss MJB3 (expect 14 mW/cm2) ______ W/cm
2
Flood-expose in Karl Suss, 250 mJ/cm2 (250/intensity = 18 s) ________ s
Develop in AZ917-MIF 45 s
Rinse in DI 30 s
Blow dry with N2
Microscope inspect
Redevelop as necessary ____ s, DI rinse 30 s
Blow dry with N2
Microscope inspect, note condition
Descum in O2 plasma in Tegal Barrel asher6: ______ mTorr (300), gas flow
setting ____(2), forward power____W (100), reflected power____W(10), time
____s (30)99.999% O2 purity.
Rinse in DI 1 min
Soak in 1-10 ____ s
Rinse in DI 10 s
Blow dry with N2
Load without delay
Evaporate HBT emitter (FC1800 # )
Pump chamber to < 2 x 10-6
Torr Record base pressure ____ x 10-7
Torr
FC1800 system set points – check and record actual setting
Adjust HBT emitter thickness metal to be RTD metal thickness + RTD etch depth
6 Tegal company Model 421.
139
Metal Ti Pt Au Ti Pt Au Ti
Tooling* 120 120 120 V (kV) 8 8 8 8
Density (g/cm3) 4.5 21.4 19.3 I (A)
Z-ratio 0.628 0.245 0.381 Long. freq. (Hz) 3 3 3 3
Rate (Å/s) 4 0.5 5 Lat. freq. (Hz) 3 3 3 3
Thickness (Å) 100 100 2800 Long. Ampl. (A) 0.1 0.1 0.1 0.1
Lat. Ampl. (A) 0.3 0.1 0.3 0.3
Evaporation parameters Beam parameters
*
This tooling is for the angled holder housing two 100 mm diameter plates with clips.
Evaporation notes:
Prepare hot acetone (boiling point 56.5 ºC) hot plate 60 ºC
Vent and unload wafers
Lift-off
Transfer wafers into hot acetone
Soak in acetone 10 min and start timer Record actual soak time _____ min
Acetone spray ___ min to complete lift-off
Microscope inspect to see if more acetone spray is needed
Soak in methanol 2 min
Blow dry with N2
Alpha-Step
Step profile HBT emitter metal height. Expect 3500 Å.
Cell 1 2 3
Thickness (Å)
HBT Emitter Mesa Etching RTD Mesa Mask – Layer 3
Solvent clean if necessary
Microscope inspect
Load the sample into the PECVD7. Deposit SiO2 1000 Å , Recipe TDT_SIO2dep: SiH4
(90% N2) 80 sccm, N2O 900 sccm, 900 mTorr, 25 W 300ºC deposition rate 320 nm in 6
min
Sidewall spacer etching
Check to see whether O2 plasma was the last plasma process, if not
o Clean chamber with O2 30 sccm, 80 mTorr, 300 W, 400 dCV, 30 min
Condition RIE: CF4/O2 16/4 sccm 10 mTorr, 150 W (320-350 V) for 5 min, DC
bias observed _____ V.
Etch the HBT/RTD sample (CF4/O2 15/3 sccm 10 mTorr, 150 W 320-350V)for
_____min___s , DC _____ V), etch rate 210-250 Å/m); overetch factor _______
Selectivity stops on InGaAs.
7 Unaxis-7900
140
Shipley S1813 positive photoresist process
Solvent clean if necessary.
Spin S1813 at 800 rpm 3 s, followed by 2500 rpm 30 s (PR thickness 1.8 µm).
Soft hot plate bake 90 °C for 1 min.
Stepper temperature (19 ºC) ________ calibration date ___________
Expose _____s (1.2)
Develop in AZ917-MIF 40 s
Rinse in DI 30 s.
Blow dry with N2
Microscope inspect
Redevelop as necessary ____ s, rinse in DI 30 s
Blow dry with N2
Microscope inspect
Hot plate postbake on clean lollypop 120 oC 1 min
Descum in O2 plasma in Tegal Barrel asher8: ______ mTorr (300), gas flow
setting ____(2), forward power____W (100), reflected power____W(10), time
____s (30)99.999% O2 purity.
HBT Selective Wet Etch to the Base
Prepare 4-1 etchant 4 H3PO4: 1 HCl etchant; cool before etching (InP etch rate: ~
1500 Å/25 s), prepare 1-10 etchant 1HCl: 10 H2O.
Prepare 1-8-160 etchant as previously described. InGaAs etch rate ~ 40-60 Å/s
Rinse in DI 1 min
Etch in 1-8-160 to etch the remaining InGaAs HBT emitter contact layer, etch
time ____ s (etch visible ?______________________________)
Rinse in DI 1 min.
Cell 1 Cell 2 Cell 3
Thickness/Roughness (Å)
Soak in 1-10 30 s to remove any surface oxide.
Rinse 1 min in D.I.
Etch in 1-1-1 to etch the 75 nm InP emitter __s ( ), selectivity stops on InAlAs.
(etch visible
?_____________________________________________________________)
Rinse 1 min in DI
Blow dry with N2
Cell 1 Cell 2 Cell 3
Thickness/Roughness (Å)
The removal of the InAlAs layer by wet etching is postponed to a step just before
depositing the W base metal.
Sidewalls and BCB Process
8 Tegal company Model 421.
141
Microscope inspection
Season the PECVD chamber with 100 nm of of SiO2
Load the sample and a Si wafer into the PECVD9. Deposit SiO2 3200 Å (Recipe
TDT_SIO2: SiH4 (90% N2) 80 sccm, N2O 900 sccm, 900 mTorr, 25 W 300ºC
deposition rate 320 nm in 6 min) Sidewall etching
Check to see whether O2 plasma was the last plasma process, if not
o Clean chamber with O2 30 sccm, 80 mTorr, 300 W, 400 dCV, 30 min
Condition RIE: CF4/O2 16/4 sccm 10 mTorr, 150 W (320-350 V) for 5 min, DC
bias observed _____ V.
Determination of etch rate for SiO2 in RIE, and HF etch10
Cleave the pilot SiO2 on Si wafer into five pieces.
Apply S1813 photoresist lines on a piece using a paintbrush.
o Hot plate bake 120 °C for 1 min. Etch it in buffered HF (1HF:10 H2O) 5
minutes.
o Remove the photoresist by spraying acetone followed by a solvent clean as
previously described.
o Step profile, SiNx deposition thickness _____________________
Etch the other 4 wafer pieces in CF4/O2 15/3 sccm 10 mTorr, 150 W (320-350V)
for 4 different etch times, respectively.
Visually inspect the wafer pieces to determine if SiO2 is present from the color of
the surface. Note the time for which SiO2 is etched off. Etch time
_____min_____s
Measure the thickness of the remaining SiO2 on these pieces by etching in
buffered HF as described above.
RIE time DC bias
min:s Location 1 Location 2 Location 3 V
Thickness (A)
Etch rate (A/s)
Sidewall formation by RIE
Etch the HBT/RTD sample (CF4/O2 15/3 sccm 10 mTorr, 150 W 320-350V)for
_____min___s , DC _____ V);
Selectivity stops on InAlAs.
Inspect under SEM.
Measure the HBTE TLM(2-probes/pad) contact width 76 µm
9Unaxis-7900
10 Instead of etching away the SiNx, ellipsometry can be used to determine the SiNx thickness on Si.
142
2
4
8
16
32
Resistance
( )
Contact
separation ( m)
Sheet res.
( /sq.)
Specific Contact
resistance
( /sq.)Correlation
coefficient
Resistance
( )
Resistance
( )
Resistance
( )
Resistance
( )
Tungsten Sputtering PE-2400
Solvent clean.
Prepare 1-8-160 etchant as previously described. InGaAs etch rate ~ 40-60 Å/s
DI rinse 1m.
Dip in 1:8:160 2s to remove the 10 nm InAlAs.
Load into PE-240011
without delay, along with a Si sample.
Base pressure ____________, table spacing _______ (2.5 in)
W Sputtering: Ar: 148 sccm, 20 mTorr, forward power: _____ W (1150), reflected
power ______ W (<25), for _____ min (10 min for 400 nm), DC _____V (1150)
Apply S1813 photoresist lines on the W on Si sample using a paintbrush.
o Hot plate bake 120 °C for 1 min. Etch it in H2O2 for 5 min.
o Remove the photoresist by spraying acetone followed by a solvent clean as
previously described.
o Step profile, W deposition thickness
___________________________________
Step profile the HBT/RTD wafer, measure HBT emitter mesa height Step height/Roughness (A)
Cell 1 Cell 2 Cell 3
11
Perkin-Elmer 2400
143
BCB planarization
Solvent clean if necessary
Descum in O2 plasma in Tegal Barrel asher12
: ______ mTorr (300), gas flow
setting ____(2), forward power____W (100), reflected power____W(10), time
____s (30) 99.999% O2 purity
DI water rinse 30s.
Microscope inspection
Spin ADP-3000 at 500 rpm for 5s followed by 2000 rpm for 20s.
Spin BCB 3022-35 at 1000 rpm for 3s followed by 4000 rpm for 30s (find the
BCB thickness for this spin speed by using a Si dummy) (1.3 µm):
Cure in Rapid thermal Processor RTP-600S:
Step profile HBT emitter patterns
Cell 1 Cell 2 Cell 3
Step height/Roughness (A)
BCB RIE Etch
Check to see whether O2 plasma was the last plasma process, if not
o Clean chamber with O2 30 sccm, 80 mTorr, 300 W, 400 dCV, 30 min
o Watch for plasma color change – Note time if observed ____ min
Condition RIE : SF6/O2 3.33/30 sccm, 300 mTorr, 60 W for 2 min, ___(12) V
Etch dummy BCB on Si wafer for ________________ to determine the BCB etch
rate =__________
Etch (SF6/O2 3.33/30 sccm, 300 mTorr, 60 W (BCB etch rate 1530 Å/m) ), DC
____V (12), microscope inspect and step profile till W appears and the step
profile height becomes larger than the initial value. (6.5+0.5+0.5+0.4 min).
12
Tegal company Model 421.
Step Time (min) Temp (C) N2 flow (SLPM)
Idle 3 0 30
Ramp 5 50 30
Hold 5 50 30
Ramp 15 100 30
Hold 15 100 30
Ramp 15 150 30
Hold 15 150 30
Ramp 15 200 30
Hold 30 200 30
Ramp 15 250 30
Hold 3 250 30
Idle 3 0 30
144
Time
Cell 1 Cell 2/ 4 um line Cell 3
Step height (A)
W RIE Etch
Condition RIE : SF6 20 sccm, 20 mTorr, 50 W for 5 min
Etch in SF6 20 sccm, 20 mTorr, 50 W (2000 Å/m) for ____ min (2+1+0.25 min),
DC_______V (60-70V).
Microscope inspect, etch is complete when Au appears
Step profile
Cell 1 Cell 2 Cell 3
Thickness/Roughness (Å)
BCB Removal
Condition RIE : SF6/O2 2/38 sccm, 300 mTorr, 60 W for 2 min
Etch SF6/O2 2/38 sccm 300 mTorr, 60 W for _____ m (2), DC____V (42);
Microscope inspect.
Step profile, mesa height
Cell 1 Cell 2 Cell 3
Thickness/Roughness (Å)
Measure HBT emitter-base resistance, make sure emitter and base are not shorted
(BE junction diodes)
Etch-back the base W if the emitter and base are short, till they are electrically
isolated.
HBT Base Contacts RTD HBT BASE Mask – Layer 4
Solvent clean if necessary
Microscope inspection
Shipley S1813 positive photoresist process
Spin S1813 at 800 rpm 3 s, followed by 2500 rpm 30 s (PR thickness 1.8 µm).
Soft hot plate bake 90 °C for 1 min
Stepper temperature (19 ºC) ________ calibration date ___________
Expose/develop GaAs pilot (Spin PR1813 800 rpm 3 s, 2500 rpm 30 s bake 90 °C
1 min) to find the misalignment corrections:
Left X______ Left Y______ Right X ______ Right Y ______
Expose _____s (1.2)
Develop in AZ917-MIF 40 s
Rinse in DI 30 s.
Blow dry with N2
145
Microscope inspect
Redevelop as necessary ____ s
Rinse in DI 30 s
Blow dry with N2
Microscope inspect
Hot plate postbake on clean lollypop 120 oC 1 min
Descum in O2 plasma in Tegal Barrel asher13
: ______ mTorr (300), gas flow
setting ____(2), forward power____W (100), reflected power____W(10), time
____s (30)99.999% O2 purity
Load without delay into Plasma-Therm RIE 790
Base contact definition RIE
Check to see whether O2 plasma was the last plasma process, if not
o Clean chamber with O2 30 sccm, 80 mTorr, 300 W, 400 dCV, 20 min
Condition chamber (SF6 20 sccm 20 mTorr, 50 W for 2 min)
Etch the W in SF6 20 sccm, 20 mTorr, 50 W for _____s (45) (2600 Å/m),
DC___V (80); (Etch stops at GaAsSb)
Step profile HBT emitter patterns.
Cell 1 Cell 2 Cell 3
Thickness/Roughness (Å)
Subcollector etch (RIE and wet etch)
Prepare 4 H3PO4: 1 HCl (4:1) InP etchant, wait for the solution to cool.
Prepare 1-8-160 etchant as previously described. InGaAs etch rate ~ 40-60 Å/s
Prepare 1HCl: 10 DI solution, wait for the solution to cool.
Rinse in DI 1 miu.
Etch in 1-8-160 ____s (5) to etch the 40 nm GaAsSb base, the etch stops on InP
subcollector.
Step profile HBT emitter patterns.
Cell 1 Cell 2 Cell 3
Thickness/Roughness (Å)
Rinse 1 min in D.I.
Soak in 1:10 HCl:DI 1 minute to remove any surface oxide, rinse 30 s in DI
Etch the 150 nm InP subcollector layer in 4:1 ___s (InP etch rate: ~ 55 Å/s),
selectivity stops at the InGaAs collector contact layer.
Rinse 1 min in D.I.
Blow dry with N2.
Step profile
13
Tegal company Model 421.
146
Cell 1 Cell 2 Cell 3
Thickness/Roughness (Å)
Isolation Etching ISOLATION MASK – Layer 5
Solvent clean if necessary
Microscope inspection
Shipley S1813 positive photoresist process
Spin S1813 at 800 rpm 3 s, followed by 2500 rpm 30 s (PR thickness 1.8 µm).
Soft hot plate bake 90 °C for 1 min
Stepper temperature (19 ºC) ________ calibration date ___________
Expose _____s (1.2)
Develop in AZ917-MIF 40 s
Rinse in DI 30 s.
Blow dry with N2
Microscope inspect
Redevelop as necessary ____ s
Rinse in DI 30 s
Blow dry with N2
Microscope inspect
Hot plate postbake on clean lollypop 120 oC 1 min
Descum in O2 plasma in Tegal Barrel asher14
: ______ mTorr (300), gas flow
setting ____(2), forward power____W (100), reflected power____W(10), time
____s (30)99.999% O2 purity
Wet chemical etching
Prepare 1-8-160 etchant as previously described. InGaAs etch rate ~ 40-60 Å/s
Prepare 4-1 as previously described. InP etch rate: ~ 55 Å/s
Rinse 1 min in D.I.
Etch in 1-8-160 _______s (2) (etch 100 Å InGaAs) where the etch stops on InP
HBT subcollector
Rinse 1 min in D.I.
Blow dry with N2
Step profile
14
Tegal company Model 421.
147
Cell 1 Cell 2 Cell 3
Thickness/Roughness (Å)
Soak in 1:10 HCl:DI 1 minute to remove any surface oxide, rinse 30 s in DI
15
Etch in 4-1 ___min___s (etch 2000 Å InP) where the etch stops on InGaAs
Rinse 1 min in D.I.
Blow dry with N2
Step profile
Cell 1 Cell 2 Cell 3
Thickness/Roughness (Å)
Etch in 1-8-160 ____s (5) (etch 100 Å InGaAs) where the etch stops on InP
substrate.
Rinse 1 min in D.I.
Blow dry with N2
Step profile
Cell 1 Cell 2 Cell 3
Thickness/Roughness (Å)
Etch in 4-1 ______s (5).
Rinse 1 min in D.I.
Blow dry with N2.
Step profile
Cell 1 Cell 2 Cell 3
Thickness/Roughness (Å)
Spray with acetone to remove resist
Solvent clean as previously described
Step profile, measure etch depth ___________________________ Å
Resistor Metal Deposition RESISTOR MAKS – Layer 6
Solvent clean if necessary
Microscope inspection
AZ5214E image reversal photoresist process
Measure temperature _____ ºC humidity _____%
Spin AZ5214E 5000 rpm (1000 rpm/s ramp) 30 s (1.4 µm)
Hot plate soft bake 105 °C 30 s
Stepper temperature (19 ºC) ________calibration date ____________
Expose (GCA 6300 stepper16
) ____________________ s (2.9s)
Hot plate reversal bake 110 °C 60 s
15
Matine et al, 10th
Conf. on Indium Phosphide and Related Materials, May 1998, pp. 195-198. 16
Exposure wavelength 436 nm
148
Measure intensity on Karl Suss MJB3 (expect 14 W/cm2) ______ W/cm2
Flood-expose in Karl Suss, 250 mJ/cm2, (250/intensity = 18 s) ________ s
Develop in AZ917 (TMAH) 45 s
Rinse in DI 30 s
Blow dry with N2
Microscope inspect
Redevelop as necessary ____ s, DI rinse 30 s
Blow dry with N2
Microscope inspect, note condition
Descum in O2 plasma in Tegal Barrel asher17
: ______ mTorr (300), gas flow
setting ____(2), forward power____W (100), reflected power____W(10), time
____s (30)99.999% O2 purity
Load without delay
Ti evaporation (FC180018
# )
Pump chamber to < 2 x 10-6
Torr Record base pressure ___ x 10-7
Torr
FC1800 system set points – check and record actual setting
Metal Ti Ti
Tooling* 120 V (kV) 8
Density (g/cm3) 4.5 I (A)
Z-ratio 0.628 Long. freq. (Hz) 3
Rate (Å/s) 2 Lat. freq. (Hz) 3
Thickness (Å) 300 Long. Ampl. (A) 0.1
Lat. Ampl. (A) 0.3
Evaporation parameters Beam parameters
* This tooling is for the angled holder housing two 100 mm diameter plates with clips.
Record evaporation observations
Prepare hot acetone (boiling point 56.5 ºC) hot plate 60 ºC
Vent and unload wafers
Lift-off
Prepare hot acetone - hot plate 60 ºC – adjust to near boil
Transfer without delay into hot acetone 10 min and start timer
Record actual time for metal to lift-off ____ min
Spray vigorously with acetone
Microscope inspect to see if more acetone spray is needed
Soak in methanol 2 min
Blow dry with N2
Step profile19
emitter metal height
17
Tegal company Model 421. 18
Airco Temescal electron-beam evaporator 19
KLA-Tencor Alpha Step 500 surface profiler
149
Cell 1 2 3
Thickness (A)
HBT Collector Contacts: HBT COLLECTOR Mask – Layer 7
Solvent clean if necessary
Microscope inspection
AZ5214E image reversal photoresist process
Measure temperature _____ ºC humidity _____%
Expose/develop GaAs pilot (Spin PR1813 800 rpm 3 s, 2500 rpm 30 s bake 90 °C
1 min) to find the misalignment corrections:
Left X_______ Left Y______Right X ______ Right Y ______
Spin AZ5214E 5000 rpm (1000 rpm/s ramp) 30 s (1.4 µm)
Hot plate soft bake 105 °C 30 s
Stepper temperature (19 ºC) ________calibration date ____________
Expose (GCA 6300 stepper) ____________________ s (2.9 s)
Hot plate reversal bake 110 °C 60 s
Measure intensity on Karl Suss MJB3 (expect 14 mW/cm2) ______ W/cm
2
Flood-expose in Karl Suss, 250 mJ/cm2 (250/intensity = 18 s) ________ s
Develop in AZ917-MIF 45 s
Rinse in DI 30 s
Blow dry with N2
Microscope inspect
Redevelop as necessary ____ s, DI rinse 30 s
Blow dry with N2
Microscope inspect, note condition
Descum in O2 plasma in Tegal Barrel asher20
: ______ mTorr (300), gas flow
setting ____(2), forward power____W (100), reflected power____W(10), time
____s (30)99.999% O2 purity
Rinse in DI 1 min
Soak in 1HCl:10H2O ____ s
Rinse in DI 10 s
Blow dry with N2
Load without delay
Ti/Pt/Au Evaporation (FC180021
# )
Pump chamber to < 2 x 10-6
Torr Record base pressure ___ x 10-7
Torr
FC1800 system set points – check and record actual setting
20
Tegal company Model 421. 21
Airco Temescal electron-beam evaporator
150
Metal Ti Pt Au Ti Pt Au
Tooling* 120 120 120 V (kV) 8 8 8
Density (g/cm3) 4.5 21.4 19.3 I (A)
Z-ratio 0.628 0.245 0.381 Long. freq. (Hz) 3 3 3
Rate (Å/s) 2 0.5 5 Lat. freq. (Hz) 3 3 3
Thickness (Å) 200 100 2000 Long. Ampl. (A) 0.1 0.1 0.1
Lat. Ampl. (A) 0.3 0.1 0.3
Evaporation parameters Beam parameters
* This tooling is for the angled holder housing two 100 mm diameter plates with clips.
Record evaporation observations
Prepare hot acetone (boiling point 56.5 ºC) hot plate 60 ºC
Vent and unload wafers
Lift-off
Transfer wafers into hot acetone
Soak in acetone 10 min and start timer Record actual soak time _____ min
Acetone spray ___ min to complete lift-off
Microscope inspect to see if more acetone spray is needed
Soak in methanol 2 min
Blow dry with N2
Alpha-Step
Step profile HBT collector metal height. Expect 2300 Å.
Cell 1 Cell 2 Cell 3
Thickness/Roughness (Å)
Measure the HBTCollector TLM (contact width 80 µm) Contact separation ( m) 0 2 4 8 16 32
location
1
2
3 Measure the HBTCollector TLM (contact width 76 µm)
Electrically test the 20x20, 40x40 and 60x60 µm2 HBTs.
Contact separation ( m) 0 2 4 8 16 32
location
1
2
3
151
Via Process22
VIA MASK – Layer 9
Solvent clean if necessary
Microscope inspection
Deposit SiNx 3000 Å on the sample and a Si wafer in the PECVD23
(Receipe
SINXB: SiH4 (90% N2) 40 sccm, NH3 4 sccm; 200 W, 500 mTorr. Deposition
rate: 20 nm/min)
Shipley S1813 photoresist process
Spin HMDS at 800 rpm for 3 sec followed by 2500 rpm for 30 sec
Spin PR 1813 at 800 rpm for 3 sec followed by 2500 rpm for 30 sec (PR thickness
1.8 µm)
Soft bake 90 °C for 1 min
Stepper temperature (19 ºC) ________calibration date ___________
Expose/develop GaAs pilot (Spin PR1813 800 rpm 3 s, 2500 rpm 30 s bake 90 °C
1 min) to find the misalignment corrections:
Left X_______ Left Y______Right X ______ Right Y ______
Expose ____ s (2.4)
Develop in AZ917-MIF 40 s
Rinse in DI 30 s.
Blow dry with N2
Microscope inspect
Redevelop as necessary ____ s
Rinse in DI 30 s
Blow dry with N2
Microscope inspect
Descum in O2 plasma in Tegal Barrel asher24
: ______ mTorr (300), gas flow
setting ____(2), forward power____W (100), reflected power____W(10), time
____s (30)99.999% O2 purity
NO HARD BAKE !
SiNx RIE Etch
Check to see whether O2 plasma was the last plasma process, if not
o Clean chamber with O2 30 sccm, 80 mTorr, 300 W, 400 dCV, 30 min
o Watch for plasma color change – Note time if observed ____ min
Condition RIE: SF6 20 sccm 20 mTorr, 50 W for 2 min
Determination of SiNx etchrate25
Cleave the pilot SiNx on Si wafer into five pieces.
Apply S1813 photoresist lines on a piece using a paintbrush.
22
The capacitor mask layer 8 can be postponed till after the bondpad metalization 23
Unaxis-7900 24
Tegal company Model 421. 25
Instead of etching away the SiNx, ellipsometry can be used to determine the SiNx thickness on Si.
152
o Hot plate bake 120 °C for 1 min. Etch it in buffered HF (1HF:10 H2O) 10
minutes.
o Remove the photoresist by spraying acetone followed by a solvent clean as
previously described.
o Step profile, SiNx deposition thickness
___________________________________
Etch the other wafer pieces in SF6 20 sccm 20 mTorr, 50 W for 4 different etch
times, respectively.
Measure the thickness of the remaining SiNx on these pieces by etching in
buffered HF as described above or using ellipsometry. RIE time
min:s Location 1 Location 2 Location 3
Thickness (A)
Etch rate (A/min) (1080) Etch in SF6 20 sccm 20 mTorr, 50 W for _____min (4), DC ____ V (90-80);
overetch factor ______ (1.3)
Etch stops when Au appears
Spray with acetone to remove resist
Solvent clean as previously described
Step profile Cell 1 Cell 2 Cell 3
Etch depth (Å)
Roughness (A)
Bond pad26
BONDPAD MASK– Layer 11
Solvent clean if necessary
Microscope inspection
AZ5214E image reversal photoresist process
Measure temperature _____ ºC humidity _____%
Expose/develop GaAs pilot (Spin PR1813 800 rpm 3 s, 2500 rpm 30 s bake 90 °C
1 min) to find the misalignment corrections:
Left X_______ Left Y______ Right X ______ Right Y ______
Spin HMDS 5000 rpm (1000 rpm/s ramp) 30 s.
Spin AZ5214E 5000 rpm (1000 rpm/s ramp) 30 s (1.4 µm)
Hot plate soft bake 105 °C 30 s
Stepper temperature (19 ºC) ________calibration date ____________
Expose (GCA 6300 stepper27
) ____________________ s (2.9 s)
Hot plate reversal bake 110 °C 60 s
Measure intensity on Karl Suss MJB3 (expect 14 mW/cm2) ______ W/cm
2
Flood-expose in Karl Suss, 250 mJ/cm2 (250/intensity = 18 s) ________ s
Develop in AZ917-MIF 45 s
26
The second via mask Layer 10 is not used 27
Exposure wavelength 436 nm
153
Rinse in DI 30 s
Blow dry with N2
Microscope inspect
Redevelop as necessary ____ s, DI rinse 30 s
Blow dry with N2
Microscope inspect, note condition
Remove organics in Jelight UV Ozone cleaner 1 min inlet pressure ____ psi
Load without delay
Ti/Au Evaporation (FC180028
# )
Pump chamber to < 2 x 10-6
Torr Record base pressure ___ x 10-7
Torr
FC1800 system set points – check and record actual setting
Metal Ti Au Ti Au
Tooling* 120 120 V (kV) 8 8
Density (g/cm3) 4.5 19.3 I (A)
Z-ratio 0.628 0.381 Long. freq. (Hz) 3 3
Rate (Å/s) 2 5 Lat. freq. (Hz) 3 3
Thickness (Å) 200 3000 Long. Ampl. (A) 0.1 0.1
Lat. Ampl. (A) 0.3 0.3
Evaporation parameters Beam parameters
* This tooling is for the angled holder housing two 100 mm diameter plates with clips.
Record evaporation observations
Prepare hot acetone (boiling point 56.5 ºC) hot plate 60 ºC
Vent and unload wafers
Lift-off
Transfer wafers into hot acetone
Soak in acetone 10 min and start timer Record actual soak time _____ min
Acetone spray ___ min to complete lift-off
Microscope inspect to see if more acetone spray is needed
Soak in methanol 2 min
Blow dry with N2
Alpha-Step
Step profile HBT emitter metal height. Expect 3200 Å.
Cell 1 2 3
Thickness (Å)
Electrically test the small RTDs and HBTs
Capacitor metalization CAPACITOR METAL MASK – Layer 8
28
Airco Temescal electron-beam evaporator
154
Solvent clean if necessary
Microscope inspection
AZ5214E image reversal photoresist process
Measure temperature _____ ºC humidity _____%
Spin HMDS 5000 rpm (1000 rpm/s ramp) 30 s.
Spin AZ5214E 5000 rpm (1000 rpm/s ramp) 30 s (1.4 µm)
Hot plate soft bake 105 °C 30 s
Stepper temperature (19 ºC) ________calibration date __________
Expose (GCA 6300 stepper29
) ____________________ s (2.9 s)
Hot plate reversal bake 110 °C 60 s
Hot plate reversal bake 110 °C 60 s
Measure intensity on Karl Suss MJB3 (expect 14 mW/cm2) ______ W/cm
2
Flood-expose in Karl Suss, 250 mJ/cm2 (250/intensity = 18 s) ________ s
Develop in AZ917-MIF30
45 s
Rinse in DI 30 s
Blow dry with N2
Microscope inspect
Redevelop as necessary ____ s, DI rinse 30 s
Blow dry with N2
Microscope inspect, note condition
Remove organics in Jelight UV Ozone cleaner31
(UVO) 1 min Inlet pressure ____ psi
Load without delay
Ti/Pt/Au Evaporation (FC180032
# )
Pump chamber to < 2 x 10-6
Torr Record base pressure ___ x 10-7
Torr
FC1800 system set points – check and record actual setting
Metal Ti Au Ti Au
Tooling* 120 120 V (kV) 8 8
Density (g/cm3) 4.5 19.3 I (A)
Z-ratio 0.628 0.381 Long. freq. (Hz) 3 3
Rate (Å/s) 2 5 Lat. freq. (Hz) 3 3
Thickness (Å) 200 1000 Long. Ampl. (A) 0.1 0.1
Lat. Ampl. (A) 0.3 0.3
Evaporation parameters Beam parameters
* This tooling is for the angled holder housing two 100 mm diameter plates with
clips.
Evaporation notes:
Prepare hot acetone (boiling point 56.5 ºC) hot plate 60 ºC Seek highest setpoint
29
Exposure wavelength 436 nm 30
MIF,metal ion free, active chemistry TMAH, tetramethylammonium hydroxide, (CH3)4NOH 31
Jelight model 144AX, Hg lamp source, O2 is ultrahigh purity 99.999% 32
Airco Temescal electron-beam evaporator
155
Vent and unload wafers
Lift-off
Transfer wafers into hot acetone
Soak in acetone 10 min and start timer Record actual soak time _____ min
Acetone spray ___ min to complete lift-off
Microscope inspect to see if more acetone spray is needed
Soak in methanol 2 min
Blow dry with N2
Alpha-Step33
Step profile emitter metal height. Expect 1200 Å.
Cell 1 2 3
Thickness (Å)
Electric Test:
33
KLA-Tencor Alpha Step 500 surface profiler
156
APPENDIX E
SUBMICRON TSRAM PROCESS TRAVELER
157
III-V Tunnel SRAM Process
Experiment design/purpose
Process IQE wafers with a Pd/Ti/Pd/Au contact for the p-InGaAs emitter, with wet
etched mesa, using SiO2 sidewall.
Use the RTP for BCB curing
Preparation
Clean and label wafer trays
Scribe labels on wafer backsides (not on cleave plane)
Deposit a 20/150 nmTi/Au contact on the back of the samples for ohmic back
contact.
Emitter Formation
Clean III-V RTD and pilot wafers
Inspect under microscope and note surface cleanliness
Solvent clean Actual Time
Soak in hot acetone (boiling point 56.5 ºC) 5 min – hot plate 55 ºC ______ min
Soak in hot methanol (flashpoint 64.7 ºC) 5 min – hot plate 55 ºC ______ min
Surface oxide removal
Prepare 6-1 etchant: 6H2O:1HCl – add acid to water – wait to cool
Removes metals, lifts off organics, leaves oxide rich surface
Rinse in H2O (DI) 1 min
Soak in 6-1 15 s
Rinse in DI 30 s
Blow dry with N2
Inspect under microscope
PMMA and copolymer MMA(8.5)MAA1 coating
Set hotplates to 150 °C and 180 °C
Load wafer on spinner, turn vacuum on. Use glass pipette and
Dispense one-quarter pipette of copolymer MMA(8.5)MAA onto wafer
Ramp 2000 rpm/s, spin 1000 rpm, 90 s, expect 2500 Å thickness
Note the time to uniformity, expect 65 s, is this true?
Hot plate bake 150 °C, 75 s, use Al lollypop
Load wafer on spinner, turn vacuum on. Use glass pipette and
Dispense one-quarter pipette of copolymer MMA(8.5)MAA onto wafer
Ramp 2000 rpm/s, spin 1000 rpm, 90 s, expect 2500 Å thickness
Hot plate bake 150 °C, 75 s, use Al lollypop
Load sample on spinner, turn vacuum on. Use a new glass pipette and
Dispense one-quarter pipette of PMMA 9502 onto sample
1 polymethylmethacrylate C5H9O2, methyl mannose C7H14O6, and methylarsonic acid CH5AsO3
2 950,000 molecular weight
158
Ramp 2000 rpm/s, spin 4000 rpm, 45 s, expect 1250 Å thickness
Hot plate bake 180 °C, 75 s
This resist stack has a thickness, measured by step profiling after exposure and
develop of 650 nm; 625 nm is expected.
Electron-beam lithography Elionix ELS-7700, 75 keV Mask: TSRAM Layer 1 Emitter
Compute e-beam write time using Excel workbook below
Aperture 1
Alignment mark position A1 (0, 0), B (1600, 0)
Actual
# of Pattern Beam Dose Chip Dot space Time Write Write
Die* Area (μm2) I (pA) μC/cm2 Size (μm) Dots nm/dot μs/dot minutes total minutes
1 54000 200 280 300 60000 5 0.35 12.6
16 100 200 1100 300 60000 5 1.375 1.5
Settings Calculations
* Die is as laid out in Mentor Graphics
Expose each piece separately
Record the die position, Dx: _____ Dy: _____
Record actual write time in table above
Develop
Mix developer3 (50 ml MIBK: 150 ml IPA: 18 drops MEK)
Develop wafers in 1MIBK: 3IPA: 0.015MEK solution for 30 s
Bottle rinse in IPA 30 s
Blow dry in N2
Inspect under microscope to make sure alignment marks are visible
Develop as needed, record total develop time for each piece
o _____ ______ s
o _____ ______ s
o _____ ______ s
o _____ ______ s
Descum in O2 plasma in Tegal Barrel asher4: ______ mTorr (300), gas flow
setting ____(2), forward power____W (100), reflected power____W(10), time
____s (30) 99.999% O2 purity.
Rinse in DI 1 min
Etch in 6H2O:1HCl etchant 5 s
Rinse in DI 1 min
Blow dry in N2
Load without delay into evaporator
3 Methyl isobutylketone C6H12O, methylethylketone C4H8O, isopropyl alcohol C3H8O
4 Tegal company Model 421.
159
Evaporate RTD emitter (FC18005 # 1 )
Pump chamber to < 2 x 10-6
Torr Record base pressure ___ x 10-7
Torr
Load sample, use clips
FC1800 system set points – check and record actual setting
Metal Pd Ti Pd Au Pd Ti Au
Tooling* 370 370 370 370 V (kV) 8.5 8.5 8.5
Density (g/cm3) 12.04 4.50 12.04 19.30 I (A) 0.08 0.08
Z-ratio 0.36 0.63 0.36 0.38 Long. freq. (Hz) 3 3 3
Rate (Å/s) 2.00 5.00 2.00 7.00 Lat. freq. (Hz) 3 3 3
Thickness (Å) 100 400 400 2400 Long. Ampl. (A) 0.1 0.1 0.1
Lat. Ampl. (A) 0.3 0.3 0.3
Evaporation parameters Beam parameters
* This tooling is for the flat bar.
Record evaporation observations
Vent and unload wafer
Lift-off
Heat acetone (boiling point 56.5 ºC) on hot plate to 55 ºC
Transfer wafers into acetone
Vertically soak wafer in acetone, 5 min Record actual soak time _____ min
Acetone spray to complete lift-off
Soak in room temperature methanol 2 min
Blow dry with N2
Alpha-Step6 Metal Height
Step profile metal height and surface roughness in 3 locations
Expect a thickness of 350 nm.
Step height/roughness (Å)
left
center
right
average Microscope inspect
Emitter TLM Measurements
Contact width 50 microns
5 Airco Temescal electron-beam evaporator
6 KLA Tencor Model 500
160
Contact separation 2 4 8 16 32 m
location
Probe resistance
Probe resistance
Probe resistance
Probe resistance
Sp. Contact res ( cm2) Sheet R ( /sq.) Correl. Coeff.
Sp. Contact res ( cm2) Sheet R ( /sq.) Correl. Coeff.
Sp. Contact res ( cm2) Sheet R ( /sq.) Correl. Coeff.
Sp. Contact res ( cm2) Sheet R ( /sq.) Correl. Coeff.
If contact resistance is greater than 10-6
cm, then perform contact anneal and
remeasure contact resistance.
Solvent Clean Actual Time
Soak in hot acetone (boiling point 56.5 ºC) 5 min – hot plate 60 ºC ______ min
Soak in hot methanol (flashpoint 64.7 ºC) 5 min – hot plate 60 ºC ______ min
SiO2 sidewall process
Load the sample and a Si wafer into the PECVD7. Deposit SiO2 ____ Å (Recipe
SIO2DEP: SiH4 (90% N2) 80 sccm, N2O 900 sccm, 900 mTorr, 25 W 250ºC
deposition rate 45 nm/ min
Sidewall etching
Check to see whether O2 plasma was the last plasma process, if not
Clean chamber with O2 30 sccm, 80 mTorr, 300 W, 400 dCV, 30 min
Condition RIE: CF4/O2 16/4 sccm 10 mTorr, 150 W (320-350 V) for 5 min, DC
bias observed _____ V.
Determination of etch rate for SiO2 in RIE, and HF etch8
Cleave the pilot SiO2 on Si wafer into five pieces.
Apply S1813 photoresist lines on a piece using a paintbrush.
o Hot plate bake 120 °C for 1 min. Etch it in buffered HF (1HF:10 H2O) 5
minutes.
o Remove the photoresist by spraying acetone followed by a solvent clean as
previously described.
o Step profile, SiO2 deposition thickness _____________________
Etch the other 4 wafer pieces in CF4/O2 15/3 sccm 10 mTorr, 150 W (320-350V)
for 4 different etch times, respectively.
Visually inspect the wafer pieces to determine if SiO2 is present from the color of
the surface. Note the time for which SiO2 is etched off. Etch time
_____min_____s
7 Unaxis-7900
8 Instead of etching away the SiNx, ellipsometry can be used to determine the SiNx thickness on Si.
161
Measure the thickness of the remaining SiO2 on these pieces by etching in
buffered HF as described above.
RIE time Thickness (A) DC bias
min:s Location 1 Location 2 Location 3 V
Etch rate (A/s)
Sidewall formation by RIE
Etch the sample (CF4/O2 15/3 sccm 10 mTorr, 150 W 320-350V)for
_____min___s , DC _____ V);
Wet Etch to form the RTDs
Prepare 1-8-160 etchant as previously described. InGaAs etch rate ~ 40-60 Å/s
Rinse in DI 1 min
Etch in 1-8-160 to etch through the RTD, etch time ____ s
Rinse in DI 1 min.
Step height (Å) time (s)
left
center
right
Average
Etch depth
Surface roughness (Å) Microscope inspect,
SEM image (angled view) the samples to observe the extent of the undercut.
Measure I-V of test patterns. Low peak voltage with high PVR is an indication
that the etch depth has been reached. Repeat wet etch and I-V as needed to
complete.
BCB planarization
Solvent clean if necessary
Descum in O2 plasma in Tegal Barrel asher9: ______ mTorr (300), gas flow
setting ____(2), forward power____W (100), reflected power____W(10), time
____s (30)
99.999% O2 purity
DI water rinse 30s.
Microscope inspection
Spin ADP-3000 at 500 rpm for 5s followed by 2000 rpm for 20s.
Spin BCB 3022-35 at 1000 rpm for 3s followed by 4000 rpm for 30s (find the
BCB thickness for this spin speed by using a Si dummy) (1.3 µm):
Cure in Rapid thermal Processor RTP-600S: 9 Tegal company Model 421.
162
Step height (Å)
left
center
right BCB RIE Etch
Check to see whether O2 plasma was the last plasma process, if not
o Clean chamber with O2 30 sccm, 80 mTorr, 300 W, 400 DCV, 30 min
Condition RIE : SF6/O2 3.33/30 sccm @ 300 mTorr, 60 W for 2 min, ___ (15)
DCV
Etch SF6/O2 3.33/30 sccm @ 300 mTorr, 60 W, for _____ min, ___ (15) DCV
BCB etch rate is 2000 Å/min.
Microscope inspect
Step profile the TLM pads (50 µm width), and the RTD array structures. Etch is
completed when the step profile height increases.
Step profile metal height and surface roughness in 3 locations.
Step Time (min) Temp (C) N2 flow (SLPM)
Idle 3 0 30
Ramp 5 50 30
Hold 5 50 30
Ramp 15 100 30
Hold 15 100 30
Ramp 15 150 30
Hold 15 150 30
Ramp 15 200 30
Hold 20 200 30
Idle 3 0 30
163
BondPad Formation
Solvent Clean Actual Time
Soak in hot acetone (boiling point 56.5 ºC) 3 min – hot plate 55 ºC ______ min
Soak in hot methanol (flashpoint 64.7 ºC) 3 min – hot plate 55 ºC ______ min
Ti/Au BondPad Lift-off Process
PMMA and Copolymer MMA(8.5)MAA10
Coating
Set hotplates to 150 °C and 180 °C
Load wafer on spinner, turn vacuum on. Use glass pipette and
Dispense one-quarter pipette of copolymer MMA(8.5)MAA onto wafer
Ramp 2000 rpm/s, spin 1000 rpm, 90 s
(Expect ~2500 Å thickness – Coating should become uniform after 65 s)
Hot plate bake 150 °C, 75 s
Load sample on spinner, turn vacuum on. Use a new glass pipette and
Dispense one-quarter pipette of PMMA 95011
onto sample
Ramp 2000 rpm/s, spin 4000 rpm, 45 s (expect ~1250 Å thick layer)
Hot plate bake 180 °C, 75 s
Electron-Beam Lithography Elionix ELS-7700, 75 keVMask: TSRAM Layer 2 BondPad
Compute e-beam write time using Excel workbook below
Aperture 2, Spot size 8 nm Actual
# of Pattern Beam Dose Chip Dot space Time Write Write
Die* Area (μm2) I (pA) μC/cm2 Size (μm) Dots nm/dot μs/dot min. total minutes
1 325000 400 320 300 60000 5 0.2 43.3
Settings Calculations
10
polymethyl methacrylate C5H9O2, methyl mannose C7H14O6, and methylarsonic acid CH5AsO3 11
950,000 molecular weight
Time
Left Right Center
Step height (Å)
164
* Die is what is laid out under Mentor Graphics
Expose each piece separately
Record the die position, Dx: _____ Dy: _____
Record actual write time in table above
Develop
Mix developer12
(50 ml MIBK: 150 ml IPA: 18 drops MEK)
Develop wafers in 1MIBK: 3IPA: 0.015MEK solution for 30 s
Bottle rinse in IPA 30 s
Blow dry in N2
Inspect under microscope to make sure alignment marks are visible
Develop as needed, record total develop time for each piece
o _____ ______ s
o _____ ______ s Descum in O2 plasma in Tegal Barrel asher
13: ______ mTorr (300), gas flow
setting ____(2), forward power____W (100), reflected power____W(10), time
____s (30)
99.999% O2 purity.
Load without delay
Evaporate Bondpad (FC180014
# 2 )
Pump chamber to < 2 x 10-6
Torr Record base pressure ___ x 10-7
Torr
FC1800 system set points – check and record actual setting
Metal Ti Au Ti Au
Tooling* 180 180 V (kV) 8.5 8.5
Density (g/cm3) 4.5 19.3 I (A) 0.08 0.08
Z-ratio 0.628 0.381 Long. freq. (Hz) 3 3
Rate (Å/s) 5 7 Lat. freq. (Hz) 3 3
Thickness (Å) 200 1700 Long. Ampl. (A) 0.1 0.1
Lat. Ampl. (A) 0.3 0.3
Evaporation parameters Beam parameters
* This tooling is for the flat bar
Evaporation notes:
Vent and unload wafers
Lift-off
Heat acetone with hot plate set to 55 ˚C
Vertically soak wafer for 5 min Record actual soak time _____ min
12
methyl isobutylketone C6H12O, methylethylketone C4H8O, isopropyl alcohol C3H8O 13
Tegal company Model 421. 14
Airco Temescal electron-beam evaporator
165
Acetone spray to complete lift-off
Soak in room temperature methanol 2 min
Blow dry with N2
Measure I-V
166