tridas week, november 2000darin acosta1 status of the csc track-finder d.acosta, a.madorsky,...
DESCRIPTION
Tridas Week, November 2000Darin Acosta3 OPTICAL SP 1 Muon Sorter 3 / port card 3 / sector ME1 ME2-ME3 ME4 SR DT TF SP Muon Port Cards MS MB1 PC From DT Track-Finder 36 Sector Receivers 12 Sector Processors To Global Muon Trigger GMT RPC 44 44 88 12 sectors (UCLA) (Florida) (Rice) (Vienna) From DT Track-Finder (Rice) Level-1 Trigger ArchitectureTRANSCRIPT
Tridas Week, November 2000
Darin Acosta1
Status of the CSC Track-FinderD.Acosta, A.Madorsky, S.M.Wang
University of Florida
B.Cousins, J.Hauser, J.Mumford, B.TannenbaumUniversity of California, Los Angeles
M.Matveev, T.Nussbaum, B.P.PadleyRice University
A.Atamanchouk, V.Golovtsov, B.Razmyslovich, V.SedovSt. Petersburg Nuclear Physics Institute
Tridas Week, November 2000
Darin Acosta2
OutlineOutline
Results of CSC Track-Finder Crate Tests
Future R&D
Status of CSC Trigger Simulation
Future Algorithm Improvements
Tridas Week, November 2000
Darin Acosta3
OPTICAL
SP
1 Muon Sorter
3 / port card
3 / sector
ME1
ME2-ME3
ME4
SR
DT TF
SP
Muon Port Cards
MS
MB1
PC
From DT Track-Finder
36 Sector Receivers
12 Sector Processors
To Global Muon Trigger
GMT
RPC
4
4
8
12 sectors
(UCLA) (Florida) (Rice)
(Vienna)
(Vienna)
From DT Track-Finder
(Rice)
Level-1 Trigger ArchitectureLevel-1 Trigger Architecture
Tridas Week, November 2000
Darin Acosta4
Tests of Current PrototypesTests of Current Prototypes
Prototypes of all Track-Finder components (except the CSC Muon Sorter) have been constructed:
Sector Processor: UFlorida Sector Receiver: UCLA Muon Port Card: Rice Clock and Control Board: Rice Channel-Link backplane: UFlorida
All boards were completed in July
Since the last CMS week, we have focused on completing integration tests of the complete system
Tridas Week, November 2000
Darin Acosta5
Extrapolation Units XCV400BG560
Final Selection Unit XCV150BG352
Bunch Crossing Analyzer
XCV50BG256
Track Assemblers 256k x 16 SRAM
Assignment Units XCV50BG256 &
2M x 8 SRAM
Sector Processor PrototypeSector Processor Prototype
12 layers
10K vias
17 FPGAs
12 SRAMs
25 buffers
Florida
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Darin Acosta6
Sector Receiver PrototypeSector Receiver PrototypeOptical Receivers
and HP GlinksSRAM LUTs
Front FPGAs Back FPGAs
UCLA
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Darin Acosta7
Track-Finder Crate TestsTrack-Finder Crate TestsSP SR CCB
Bit3 VME Interface
Custom backplane
MPC
100m optical fibers
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Darin Acosta8
Test Results: Sector ProcessorTest Results: Sector ProcessorVME Interface
All LUTs and FPGA programs downloaded in less than 30s through SBS Bit3 PCI to VME interface
JTAG serialized on board @ 25 MHz
Functionality Internal dynamic test @ 40 MHz works with 100%
agreement with ORCA simulation 180K single muons (and 60K triple muons) Internal FIFOs are 256 b.x. deep
Latency is 15 b.x. (not including Channel-Link input) Firmware updated to latest (last week’s) ORCA
algorithms CSC region works flawlessly, but still working on
DT/CSC overlap region Plan to test even larger data samples (and random
data) to look for any rare errors
Tridas Week, November 2000
Darin Acosta9
Test Results: Sector ReceiverTest Results: Sector ReceiverFunctionality
Three boards built and tested Internal dynamic test @ 40 MHz works with ORCA
data and pseudo-random data Tested 30K cycles of 256 random events
Some rare (10-6) errors encountered and under study
One board with slower SRAM (10ns vs. 8ns) works fine even with 2 memories cascaded with 25 ns clock
Emulation software is similar to ORCA, but not same code
Although LUT contents were generated from ORCA
Tridas Week, November 2000
Darin Acosta10
System Tests Done in Last MonthSystem Tests Done in Last Month
Port Card Sector Receiver MPC and SR communicate via HP GLinks and optical
fiber Data successfully sent from input of one MPC,
through 100m of optical cables, to output of SR 1.6M random events processed with no errors
Sector Receiver Sector Processor SR and SP communicate via Channel-Link backplane Data successfully sent from input of one SR,
through custom backplane, into the SP Some errors encountered from unmasked inputs,
but tracks were reconstructed correctly from the SR input
Successfully sent data from three SRs connected to the SP to emulate an entire trigger sector
Tridas Week, November 2000
Darin Acosta11
System Tests (Continued)System Tests (Continued)Port Card Sector Receiver Sector Processor
Successfully sent data from the input of two MPCs (representing ME2 and ME3), through one SR, and reconstructed tracks correctly in the SP
Complete chain test
The Clock and Control Board prototype coordinated these tests: Distributed clock and control signals with
programmable delays Sent BC0 to initiate tests
Lots of software had to be developed (and coordinated between institutes) for these tests to happen
Tridas Week, November 2000
Darin Acosta12
Future Plans: BackplaneFuture Plans: BackplaneWe plan to replace Channel-Link transmission as much as possible from the CSC trigger path because of its long latency (~3.5 b.x.) In particular, for the custom point-to-point
backplane in the Track-Finder crate (and probably the front-end peripheral crates)
Florida proposal is to use GTLP at 80 MHz Doubled frequency achieves 2 signal reduction
(vs. 3 from Channel-Link) Can be bussed (although we plan point-to-point) No differential signals (fewer traces) Can be driven by Xilinx Virtex I/O directly,
or from driver chips by Fairchild and TI
Prototype backplane successfully tested in Florida
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Darin Acosta13
GTLP Test FixtureGTLP Test Fixture
Backplane connector
Pattern generator
Shift register
Comparator
GTLP transmitter
GTLP receiver
Error counter and display
50 Backplane traces (~220 mm)
Clock generator (160 MHz) AMP Z-pack
2-mm 5-row
Virtex, or Fairchild GTLP16612
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Darin Acosta14
GTLP Backplane TestsGTLP Backplane TestsAlternating and random patterns driven up to 160 MHz with no errors
80 MHz signal
160 MHz signal
Virtex
Drivers
Backplane traces
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Darin Acosta15
Future: A Compact Muon TriggerFuture: A Compact Muon TriggerCurrent technology will allow us to merge all 17 FPGAs of prototype Sector Processor into just one: Xilinx Virtex XCV2000E (~2.5M gates) available now or Virtex 2, available soon
This opens the possibility of merging the Sector Processor and Sector Receivers onto a single board Would allow for a single crate Track-Finder (currently 6) Reduces latency (up to 10 b.x.) No Channel-Link connection between SR and SP No cable to Muon Sorter Would allow communication between sectors (through
backplane) to cancel ghost tracks at boundaries Under investigation by Florida
Depends on new optical link technology to reduce connections from peripheral crate 1.6 Gbit links with 80 MHz clock Under investigation by Rice
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Darin Acosta16
From MPC (chamber 4)
From MPC (chamber 3)
From MPC (chamber 2)
From MPC (chamber
1B)
From MPC (chamber 1A)
From / To Barrel
From Clock and Control
Board
To Muon Sorter
Small Form Factor
Transceivers Deserializer
Chips Front
FPGAs Memory Look-up Tables
Sector Processor
FPGA chip
Pt-assignment
LUTs
VME Interface
Preliminary layout of SR/SP module (2.5Gb/s link option)
Low power consumption: ~ 38.5W per 9U VME card Latency: ~ 15Bx SP structure is fully programmable Cost reduction: 1 SR/SP module instead of 3 SR and 1 SP 1 SR/SP module per 60 sector
Possible Board LayoutPossible Board Layout
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Darin Acosta17
Possible Crate LayoutPossible Crate Layout
SR /
SP
SR /
SP
SR /
SP
SR /
SP
SR /
SP
SR /
SP
SR /
SP
SR /
SP
SR /
SP
SR /
SP
SR /
SP
SR /
SP
CC
B/M
S
BIT
3 C
ontr
olle
r
Total latency: ~ 20Bx (from input of SR/SP card to output of CCB/MS card) Power consumption: ~ 500W per crate 17 optical connections per SR/SP card (15 - from endcap, 2 – from/to barrel) Custom backplane for SR/SPs < > CCB/MS connection
SR/SP Card (3 Sector Receivers +
Sector Processor) (60 sector)
CCB/MS Card (CCB +
Muon Sorter)
To Global Trigger
From TTC
From MPC (chamber 4)
From MPC (chamber 3)
From MPC (chamber 2)
From MPC (chamber 1B)
From MPC (chamber 1A)
From / To Barrel
Track-Finder crate (1.6 Gbits/s optical links)
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Darin Acosta18
State of the Track-Finder SimulationState of the Track-Finder Simulation It is working in ORCA 4.3.0 ! PT assignment has been re-tuned on CMSIM118 and parameterized by a set of functions This offers flexibility:
PT binning may be changed 50% or 90% thresholds (or anything else) can be used
Look-up table contents are still based on integers like hardware
Contents computed dynamicallyRecent problem with PT assignment at 1.5 fixed
L1 Ntuples re-made thanks to Norbert Rate under control there, but still under study in DT/CSC
overlap regionAll SW and HW algorithms tested and agree
Modifications made to ORCA to match prototype exactly, and all LUTs used by HW generated from ORCA code
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CSC Trigger Efficiency vs. EtaCSC Trigger Efficiency vs. EtaTitle:/cms/tmp2/acosta/ORCA/plot.ps (Portrait A 4)Creator:HIGZ Version 1.26/04Preview:This EPS picture was not savedwith a preview included in it.Comment:This EPS picture will print to aPostScript printer, but not toother types of printers.
Any 2 stations
ME1 or MB1 + any station
ME1 or MB1 + any 2 stations
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Darin Acosta20
PPTT Resolution and Efficiency Resolution and EfficiencyTitle:/cms/tmp2/acosta/ORCA/plot.ps (Portrait A 4)Creator:HIGZ Version 1.26/04Preview:This EPS picture was not savedwith a preview included in it.Comment:This EPS picture will print to aPostScript printer, but not toother types of printers.
Title:/cms/tmp2/acosta/ORCA/plot.ps (Portrait A 4)Creator:HIGZ Version 1.26/04Preview:This EPS picture was not savedwith a preview included in it.Comment:This EPS picture will print to aPostScript printer, but not toother types of printers.
5 < PT < 50 GeV 1.2 < < 2.0
90% Efficiency Threshold
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Darin Acosta21
CSC Trigger RateCSC Trigger RateTitle:/cms/tmp4/ming/cms/ORCA/ntuples_10_2000/ana/total_1Creator:HIGZ Version 1.26/04Preview:This EPS picture was not savedwith a preview included in it.Comment:This EPS picture will print to aPostScript printer, but not toother types of printers.
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Darin Acosta22
PT Assignment ImprovementsPT Assignment ImprovementsPrecision
Current SP prototype performs a 3-station PT measurement using a 2 MB SRAM 27% resolution up to 35 GeV (20% for PT < 5 GeV)
Resolution can improve further with 1 or 2 more bits of precision on 23
22% resolution up to 35 GeV Use larger SRAM or multiple chips
Likewise, anticipated improvements on resolution in CLCT and SR should extend this resolution up to 50 GeV
Stronger background rejection, higher efficiencyDT/CSC Overlap
Tracks bend back between MB1 and ME2 at low PT Ambiguity in assigning PT based on
Will investigate using bend and 12 for PT assignment in place of 3-station measurement for this region
Won’t help tracks without MB1 No bending between ME1 and ME2
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Darin Acosta23
ConclusionsConclusionsPrototype tests were a success (but a lot of work)It was a useful exercise to commission a crate of trigger electronics Validates the trigger architecture Gives us some idea of what to expect when we
commission the real system Learned of some (solvable) incompatibilities
Different VME addressing conventions Different patterns and sorting logic than expected
Provides guidance on how to improve future boards Additional VME registers to set board functions or
to spy on intermediate dataORCA software is basically in shape for the TDR
Expected efficiency and rate reduction achieved in endcap
Still expect future improvements and tuning to occur