©2013 – IEEE CASE 2013

Transient Scheduling of Single Armed Cluster Tools: Algorithms for Wafer Residency Constraints

James R. Morrison2013.08

©2013 – IEEE CASE 2013 – 2

Outline

• Introduction

• Literature Review

• LP Formulation

• Branch and Bound Algorithm

• Conclusion

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Introduction

• Motivation– World semiconductor revenue was $307 billion in 2011.* – It is expected to grow into $344 billion by 2014.** – With optimal scheduling policy, we can increase productivity AND improve wafer qual-

ity.

• Cluster tools

* Garner, Inc. http://www.gartner.com/it/page.jsp?id=1986016** International Data Corporation (IDC) http://news.softpedia.com/news/IDC-Estimates-Semiconductor-Market-at-344-Billion-by-2014-146865.shtml

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Introduction• Topic Non-cyclic scheduling of single armed cluster tools with wafer delay constraints

• Example of wafer delay constraint– Wafer delay = unloading time – finish processing time <= 10– Process time in Chamber 1 is 10– Process time in Chamber 2 is 50

• Objective1. Minimize total makespan while not violating the wafer delay constraints2. Minimize total wafer delays

• Method1. Given a robot sequence, how to set the robot activity timings? -> LP2. What is the optimal robot sequence that achieves the two objectives? ->B&B

Input load lock Chamber 1 Chamber 2 Output load lock

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Literature Review

Q1: Given a robot task sequence, how to schedule each activity?

– Scheduling analysis of time-constrained dual-armed cluster tools • IEEE Transactions on semiconductor manufacturing, 2003• Steady state analysis with LP

– A Petri Net method for schedulability and scheduling problems in single-arm cluster tools with wafer residency time constraints• IEEE Transaction on semiconductor manufacturing, 2008• Backward sequence, s-s only, complex calculation

Conclusion: We need to find a systematic approach that can solve the problem for the entire makespan.

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Literature Review

Q2: What is the optimal robot sequence that gives min makespan while meeting the wafer delay constraints?

• Try and error-based scheduling algorithm for cluster tools of wafer fabrications with residency time constraints– Journal of Central South University, 2012– Not optimal, heuristics

• A Petri net-based modeling and scheduling with a branch and bound algorithm– Proceedings of the IEEE Conference on Systems, Man, and Cybernetics, 2012.– Imposed time window for some specific PM as a constraint.– Minimizing wafer delay is not the objective.

Conclusion: We want to find an optimal robot sequence that minimizes total makespan AND total wafer delays.

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LP Formulation: Notations

• Variables

• Key strategy– Given the robot action sequence, we delay some wafer loading to minimize

wafer delays.

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LP Formulation: Objective Functions

• Two stage linear programming

1) LP 1– Objective

• Minimize total makespan– Constraints

• Not violating wafer delay constraints (next page)2) LP 2

– Objective• Minimize total wafer delays

– Constraints• Same with LP 1• Makespan <= Minimum makespan

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LP Formulation: Constraints

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LP Formulation: Performance

•

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Branch and Bound (B&B)

• Enumeration of all candidate solutions

1,1,1,1

1,1,0,2

1,0,1,2

0,1,1,2 1,0,0,3

0,1,0,3 0,1,0,3

2,0,0,2

1,1,0,2

1,0,1,2

0,1,1,2 1,0,0,3

0,1,0,3 0,1,0,3

4,0,0,0

3,1,0,0

3,0,1,0

3,0,0,1

2,1,0,1

2,0,1,1

2,1,1,0

2,1,0,1

2,0,1,1

0,1,1,2 1,0,0,3

0,1,0,3 0,1,0,3

1,0,1,2

1,1,1,1

1,1,0,2

0,1,1,2 1,0,0,3

0,1,0,3 0,1,0,3

1,0,1,2

2,0,0,2

1,1,0,2

0,0,1,3

0,0,0,4

0,0,1,3

0,0,0,4

0,0,1,3

0,0,0,4

0,0,1,3

0,0,0,4

0,0,1,3

0,0,0,4

0,0,1,3

0,0,0,4

0,0,1,3

0,0,0,4

0,0,1,3

0,0,0,4

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Branch and Bound (B&B)

• Problem– Have too many nodes. – We need to discard fruitless candidates as early as possible.

• How?– Upper Bound (UB)– Lower Bound (LB)– Feasibility Check

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Upper bound in B&B• Upper bound is found by heuristics.

• Idea: use robot sequences inspired by s-s sequence.– The number of branches to be considered is reduced dramatically.

• Complete enumeration of all the possible sequences.• For m=6, there are less than 120 different sequences.

– Run LP for every possibilities.• For m=5, n=25, less than 8 seconds is needed.

– It is upper bound because• The sequence is feasible for wafer delay constraints.• It gives relatively small makespan so that sequences have larger makespan can be discarded.

• Example– =30, =50, =40, =80, =100– =====1– ε = δ = 1– Solution: s-s robot sequence=5,4,1,3,2,0; makespan=2886, total wafer delay=0

©2013 – IEEE CASE 2013 – 14

Lower bound in B&B

• Lower bound is found by utilizing the existing literature.

• Idea: apply [2012, Uno, et al.]* dynamic programming (DP) – For each node, run DP to find the minimum makespan.– It is lower bound because

• there is no other sequence that gives smaller makespan.– If LB>UB, then discard the node.

• Example

* Uno Wikborg, and Tae-Eog Lee. “Non-cyclic scheduling for timed discrete event systems with application to single-armed cluster tools using Pareto-optimal optimization”, accepted for publication in IEEE Transactions on Automation Science and Engineering

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Feasibility check for B&B

• Idea: use LP to check feasibility for the survived nodes.– For the survived nodes, we track its sequence from origin to the end. – Then LP is applied to ensure the wafer delay constraints.– If LP results in an infeasible solution, discard the node.

• Example– When m=4, n=25, about 560 nodes are discarded from the feasibility check.

• B&B application examplesTime unit: second

Example Processing time (δ,ε) Computation time

#1 (2,1) 10 7937 (7937,69) (7937,69) 1

#2 (1,1) 10 7056 (7056,0) (7056,0) 2

#3 (1,2) 0 7949 (8045,0) - -

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Branch and Bound Performance Evaluation

• Computational efficiency

• Tightness of LB and UB

1 5 9 13 17 21 25 29 33 370

0.20.40.60.81

1.2Computation time

No. of trials for m`=3

Time(s)

1 6 11 16 21 26 31 36 41 46 51 56 6105

101520

Computation time

No. of trials for m`=5

Time(s)

1 7 13 19 25 31 37 43 49 55 61 670

0.20.40.60.81

1.21.41.6

100(V_ub - V_lb) / V_ub

No. of trials (m`=5)

%

1 4 7 10 13 16 19 22 25 280

0.5

1

1.5

2

100(V_ub - V_lb) / V_ub

No of trials (m`=6)

%

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Conclusion

• Contribution– If a robot sequence is given, we know whether it`s schedulable under any

wafer residency delay constraints and how to schedule it.– If we want to find a robot sequence that minimizes throughput while not vio-

lating wafer residency delay constraints, apply B&B.– If B&B shows low computational efficiency, use heuristics to get a good solu-

tion.

• Future work– We may extend the work into the following features.

• Dual arm cluster tools• Wafer reentrance or different wafer flow patterns• Multi cluster tools