track g test strategy - delta
DESCRIPTION
TRANSCRIPT
May 4, 2011
TEST re-defined
Reduction of test cost for ASICs to the minimum,
using the strength of Asia and Europe
By Gert Jørgensen
VP Sales & Marketing
May 2011
May 4, 2011
Content of presentation
1. Short introduction to DELTA
2. Test cost analysis of ASIC projects
3. Test activities needed to optimise QA
4. The DELTA solution to minimise cost
5. Minimise test cost – a case studie
6. Some facts and conclusions
• More than 28 years at DELTA
• Master of Science from 1982
• Experience as:
- Test engineer
- Quality assurance
- ASIC designer
- Project leader
• Business development (1995)
- Turned DELTA from
consultancy to IC-supplier
• Helps major customers:
- To drive innovations and
technology intro’s
DELTA Microelectronics May 4, 2011
Business:
– ASIC supply chain, from specification/GDSII to silicon
– Full turnkey or individual service
Founded: 1976 Microelectronic Testing
1984 Microelectronic Design
1992 OEM manufacturer
2010 IMEC / TSMC and IBM SVAR
2010 More than 25 mill Chips delivered
2011 GF – Global Solutions EMEA channel partner
Locations: Denmark and UK
Geographical coverage:
Europe incl. Israel
DELTA Microelectronics
DELTA Microelectronics May 4, 2011
ASIC mode
• Full turnkey solution
• Customer buys good-tested ICs
• ASIC vendor takes full responsibility
• Higher cost
COT mode
• Customer uses different vendors
• Customer takes full responsibility
• Lower cost
Overview
DELTA Microelectronics May 4, 2011
Spec/RTL/GDSII to Silicon
Local European partner
Proven experienced team
Flexible entry/exit points
Competitive pricing model
Prototypes to high volume
DELTA’s Offering - Predictable Path to Success One Stop Shop
Spec
May 4, 2011
Test cost analyses
May 4, 2011
Test cost in ASIC projects
30
30
15
25
Total Devellopment
Design HW-platform
Design Software
Packaging
Test and QA
Methodes to reduce this section
28 ASIC projects performed during the last 2 years at DELTA
May 4, 2011
Electrical test of ASIC activities
Wafer test
Package test
May 4, 2011
Physical test system
May 4, 2011
Hardware vertical probecard
2 x 2 mm
May 4, 2011
Test solution implementation Phase 1
Phase 2
Phase 3
Phase 4
More information at our Booth
May 4, 2011
Reduction of test cost for ASICs to the minimum, using the strength of Asia and Europe
Now DELTA’s Proposal and Ideas - Road map for lower test cost
May 4, 2011
Testing - different focus in a life-circle of ASIC project
Prototype
Local support, Dedicated project
& account manager, Qualification
testing, Debug, Characterisation,
Quickest time to results
Medium Volume
Optimisation for low cost
and high volume, Yield
improvement,
Production-ready
High Volume
Know-how transfer to
Asia in 1 week
Prototype - First volume - High Volume
May 4, 2011
Case story
A DELTA customer is developing chips for
WLAN and VOIP to mobile phones.
DELTA is test house for the two chips,
and it consist of
Baseband-chip and RF transceiver-chip.
May 4, 2011
Test cost reduction
HW investments in Octal for
BB
Origional summer
2010
After initial Tuning
SW : Xpress data mode
to 93K verigy
RF chip: 2.450 / h BB chip: 2.680 / h
Investments 20K EUR
Test engineer Test system
RF chip: 3.520 / h BB chip: 3.802 / h
Investments 25K EUR
Test engineer Test system / software update
RF chip: 3.940 / h BB chip: 3.802 / h
FINAL RESULT RF chip: 3.940 / h BB chip: 6.000 / h
Octal site on BB Investments 60K EUR
Test engineer Test system Octal probecard
May 4, 2011
Baseband and RF runs
Number of hours:
• BB 9 mill / 6K = 1.500 hours - P600 hours
• RF 9 mill / 3,9K = 2.300 hours - Portscale hours
In total 3.800 hours - 60% of one test system
Conclusion:
DELTA has the capacity to test 18 mill chips if price and
commitment can be agreed.
Baseband runs Octal on Verigy P600
RF runs Quad on Portscale
May 4, 2011
Cost of test versus commitment
Model 1
250 USD 0,041667 0,063451777 0,105118777
Model 2
200 USD 0,033333 0,050761421 0,084094421
Model 3
175 USD 0,029167 0,044416244 0,073583244
Model 4
145 USD 0,024167 0,03680203 0,060969030
BB: 6000 RF: 3900 Total cost
6,1 USD cent per chip set (two devices) depending on commitments
May 4, 2011
• For debug and ramp to production the local solution is optimum due to
flexible engineering resources
• You need to obtain prices lower than 161 USD per hour in Asia to beat
local price rates valid for Verigy Portscale
• Asia presents low hourly rate with no throughput commitment –
all the way down to 100 USD
• Local test houses is able to present committed test cost
per device to competitive prices.
Thank you!
Conclusions