traceability: from transactions to rtl dave whipp
TRANSCRIPT
Traceability: From Transactions to RTL
Dave Whipp
NVIDIA Confidential
Abstraction is not Sloppiness
Spice
Switches
Gates
RTL
ESL
“System” Models
volts, ohms, seconds
ones, zeros, edges, loads
cells
clocks, cycles
transactions: events, races
clouds?
To use multiple abstractions within a flow we need to know how each description
maps to its neighbors
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From Transactions to RTL
What features are invariant?
Interface Structures?Interface Traffic?
Architectural State?
End Result?
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Multi-Unit Assemblies
A EB C D F G
a2b b2c c2d d2e e2f f2g
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Multi-Unit Assemblies
A
E
B C D
F G
a2b b2c c2d
d2ee2f f2g
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Multi-Unit Assemblies
A
E
B C D
F G
a2b b2c c2d
d2ee2f f2g
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Multi-Unit Assemblies
BE
CF
D
a2be
be2cf
cf2dd2be
cf2gG
A
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Comparing “Shapes”
A EB C D F G
D
GA
BE
CF
How do we tell our tools that these are the same thing?
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Comparing Interfaces
Simple “diff”
Normalization (masking, snapping)
Binning (collating, sorting)
Accumulating
In-memory FIFOs + scoreboard
File-based post-processing
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Step 1: Capture transactions
RTL
1010 011010 101011 011010 111011 101011 11
C-Model
tid=A seq=1tid=A seq=2tid=A seq=3tid=B seq=1tid=B seq=2tid=B seq=3time
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Step 2 : Normalize
RTL
1010 011010 101011 011010 111011 101011 11
C-Model
tid=A seq=1tid=A seq=2tid=A seq=3tid=B seq=1tid=B seq=2tid=B seq=3time
normal
A1A2B1A3B2B3
normal
A1A2A3B1B2B3
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Step 3 : Binning
RTL
1010 011010 101011 011010 111011 101011 11
C-Model
tid=A seq=1tid=A seq=2tid=A seq=3tid=B seq=1tid=B seq=2tid=B seq=3
normal
A1A2B1A3B2B3
normal
A1A2A3B1B2B3
bin
A1A2
B1A3
B2B3
bin
A1A2A3
B1B2B3
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Step 4: Accumulation
Binning may not be enough
Random Memory Accessdon’t want to sort on every address
Different Algorithmsend result is same – checksum?
“Spaghetti” Perl scripts often evolve
We need to formalize the interface traffic to compare two very different models
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Transaction Assertions in YACC
valid_interface_traffic:
| valid_interface_traffic packet;
packet: begin middle end;
begin: BEGIN;
middle:
| middle MIDDLE;
end: END
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Cycle Level Assertions in SVA
sequence packet;(cmd==BEGIN)##1 (cmd != BEGIN && cmd != END) [*0:$]##1 cmd == END
endsequence
a_well_formed_packet: assert @(posedge clk)cmd == BEGIN |-> sequence (packet)
clk
cmd BEG ENDMID MID
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Transaction Level Assertions in SVA
sequence packet;
(cmd==BEGIN)
##1 (cmd != BEGIN && cmd != END) [*0:$]
##1 cmd == END
endsequence
clk
valid
cmd BEG ENDMID MID
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Transaction Level Assertions in SVA
event sample;
always @(posedge clk)
if (valid && ! busy) -> sample
assert @(sample)
cmd == BEGIN |-> sequence (packet)
clk
valid
busy
cmd BEG ENDMID MIDDLE
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Transaction Assertions in Perl 6
grammar interface
{
rule valid_traffic { ^^ <packet>* $$ }
rule packet { <begin> <middle>* <end> }
}
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ESL Shape
A EB C D F G
D
GA
BE
CF
Topology: defining invariants of shape
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End-to-End flow definition
assert “logical pipeline”chain a2b b2c c2d d2e e2f f2g
assert “physical pipeline”chain a2be be2cf.b2c cf2d d2be be2cf.e2f cf2g
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Local in-order Properties
Every a2be must appear on be2cfEvery d2be must appear on be2cfEvery be2cf must be a result of a2be or d2be
Within a thread, transactions must remain in-orderthreads may be reordered
BE
d2be
a2bebe2cf
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Transaction Interaction Algebra
a2b -> b2c // propagate
(a2x | b2x) -> x2y // merge
a2b -> (b2x | b2y) // branch
(a2x & b2x) -> x2y // join
a2b -> (b2x & b2y) // fork
a2b -> null // eat
null -> a2b // generate
(a2b | null) -> b2c // input must propagate
a2b -> ( b2c | null ) // output must propagate
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Local in-order Properties
module BEequiv tid, thread
in a2be
in d2be
out be2cf
assert :out_of_order( thread ) :in_order( tag )
link ( a2be | d2be ) be2cf
BE
d2be
a2bebe2cf
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Local in-order Properties
module BEequiv tid, thread
in a2be
in d2be
out be2cf
assert :out_of_order( thread ) :in_order( tag )
link a2be be2cf.b2c
link d2be be2cf.e2f
BE
d2be
a2bebe2cf
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Summary
Bridging abstractions requires defined traceabilityESL RTL
ESL C-Model
Use Transaction Abstraction for ESLRTL and C-Model share a common shape
Transaction flow defines the equivalence class
Designer Freedoms are defined by ESLThis is a design activity
Verification “trusts” the ESL
BACKUP
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Interface Grammar
grammar bc_ef_iface {rule b2c { … }
rule e2f { … }
rule be2cf { <b2c> | <e2f> }
}
struct iface {field tag { enum B2C, E2F }
field be2cf [ *tag ]
}
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RTL Verification
Compare Vs reference modelreference model may be “Executable Specification”
architectural state
interface traffic
Internal Assertionsno reference model needed
“design” assertions
“verification” assertions
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Multi-Cycle Interface : RTL traffic
Module A
Module B
111000
34
datadatadatadatadata
-
keyvaluekey
value--
111110
time
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Multi-Cycle Interface: structural view
Module A
Module B34
struct a2b_iface {struct command {
union {struct key { bit valid, bit [7:0] key },struct value { bit more, bit [7:0] value }
}struct datum { bit valid, bit [7:0] data }
};
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Multi-Cycle Interface : grammar
Module A
Module B34
seq command = <key> <value>where $1.validattr more = $2.more
seq commands = <command> ** [0,64]where all( $1[ 0..$-1 ].more ) && ! $1[$].more
seq data = <datum> ** [0,128]where all( $1[*].valid )
seq a2b_info = <commands> & <data>
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Multi-Cycle Interface: C-model struct
Module A
Module B
struct A2B_info{ map<int8,int8> commands; vector<int24> data;};
34
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Topology
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Equivalence classes for transactions
Every implementation is a deformation of the ESLRTL
C-Model
We want to know up front how we’ll compare themImplementation-independent comprehension
“Races” in the transaction graphare like “holes” in a topology
may be non-deterministic