topic 5 - cmos inverter

8/19/2019 Topic 5 - Cmos Inverter

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EE603 – CMOS IC DESIGN

Topic 5 – CMOS Inverter


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Lesson Learning Outcome

1) To explain the properties and performance of static

CMOS Inverter

a. CMOS Voltage Transfer Characteristic (VTC)

b. Sitching Thresholdc. !oise Margin

d. "evice Variation

e. S#ppl$ Voltage Scaling

%) To explain the d$namic behavio#r of CMOS inverter

a. &arasitic Capacitances


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Inverter Switch Modes

'hen Vin is high and e#al to V"" the !MOS transistor is O! hile the

&MOS is O**. + direct path exists beteen Vo#t and the gro#nd node

res#lting in a stead$,state val#e of -V.'hen the inp#t voltage is lo (- V) !MOS transistor is O** hile

&MOS transistors in O!. + direct path exists beteen V""

and Vo#t

res#lting

in a stead$,state val#e of V"".


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CMOS !ro"erties

1. The voltage sing is e#al to the s#ppl$ voltage , o#tp#t levelshigh e#al V DD and o#tp#t levels lo e#al GND (*#ll rail,to,

rail sing) ⇒ high noise margins

%. The logic levels are not dependent #pon the relative device

sies so that the transistors can be minim#m sie.

/. 0o o#tp#t impedance (o#tp#t resistance in Ω range) hich

maes it less sensitive to noise and dist#rbances.

2. 3xtremel$ high inp#t resistance (MOS transistor gate is a

virt#all$ perfect ins#lator and dras no dc inp#t c#rrent.) ⇒

large fan,o#t.

4. !o direct path exists beteen the s#ppl$ and gro#nd rails #nder

stead$,state operating conditions ⇒ no static poer

dissipation.


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NMOS # !MOS O"eration in CMOS


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NMOS # !MOS I$% Curve


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NMOS # !MOS I$% Curve

Combining the VI characteristicsof the n-device and p-device

I"Sp 5 ,I"SnV6Sn 5 Vin 7 V6Sp 5 Vin , V""

V"Sn 5 Vo#t 7 V"Sp 5 Vo#t , V""

*or a "C operating points to be valid the

c#rrents thro#gh !MOS and &MOS

devices m#st be e#al.The "C points are located at the

intersection of corresponding load lines

as mared ith dots on the graph.


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CMOS Inverter %&C

CMOS Inverter %&C is "roduced 'rom (oth

NMOS and !MOS I% curve)


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CMOS IN%E*&E*

8 'hen designing static CMOS circ#its it is advisable

to balance the driving strengths of the transistors b$

maing the idth of the &MOS to or three timesthan the idth of !MOS in order to obtain

s$mmetrical characteristics.

8 The impact 9 to maximie the noise margins.

:elative transistor siing for better performance

of CMOS Inverter9

For ideal symmetrical inverter required that9


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CMOS IN%E*&E*

VM The sitching

threshold is defined as the

point here the

intersection of the VTC

c#rve and the line given b$Vo#t 5 Vin.

The sitching threshold

voltage presents the

midpoint of the sitchingcharacteristics.

+ good inverter m#st

have the val#e VM 5 V"";%

(to have comparable highand lo noise mar ins .

VM

Vo#t 5 Vin

Sitching Threshold


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CMOS IN%E*&E* !oise Margin

&+"ica inverter trans'er characteristics


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CMOS IN%E*&E*


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CMOS IN%E*&E*


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CMOS IN%E*&E*

Effect of Transistor Size on VTC

3ffect on sitching threshold9

VM5 V"";% exactl$ in the middle.

3ffect on noise margin9

VI= and VI0 both are close to VM and

noise margin is good.

If 9


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CMOS IN%E*&E*Im"act o' device variation on %&C Curve

The ?good@ transistor has9

smaller oxide thicness

smaller length

higher idth

smaller threshold voltage

The ?bad@ transistor has9

larger oxide thicness

larger length

loer idth

larger threshold voltage

Conclusion:

The variations ca#se a small shift

in the sitching threshold b#t that

the operation of the gate is not

affected.

&rocess variations (mostl$) ca#se ashift in the sitching threshold.


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CMOS IN%E*&E*

Im"act o' device variation on %&C Curve

:es#lt from changing (';0) p ; (';0)n ratio9

, Inverter threshold VM ≠ V"";%

, :ise and fall dela$s are #ne#al, !oise margins are not e#al


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CMOS IN%E*&E*Impact of s#ppl$ voltage scaling

8 The inverter characteristic can still

be obtained altho#gh the s#ppl$

voltage is small (not even large

eno#gh to t#rn the transistors on.)

8 =o does this happenA


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Impact of S#ppl$ Voltage Scaling

8 +t aro#nd 1-- mV the gate

characteristic ill deteriorate.

8 VO0 and VO= are no longer at the

s#ppl$ rails and the transition,

region gain approaches 1.

8 + digital circ#it m#st achieve

s#fficient gain to operate. So it

is necessar$ that the s#ppl$ m#st

be at least a fe times the

thermal voltage.

8


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CMOS Inverter - D+namic .ehaviour

&he Switch Mode o' D+namic CMOS Inverter


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&arasitic Capacitances of CMOS inverter

&arasitic capacitances infl#encing the transient behavio#r of

the cascaded inverter pair.


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&arasitic Capacitances B Miller 3ffect

The Miller effect + capacitor that has identical b#t opposite

voltage sings at both its terminals can be replaced b$ a capacitor

to gro#nd hose val#e is to times the original val#e.


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So#rces of parasitic capacitance9i. Intrinsic MOS transistor capacitances

ii.3xtrinsic MOS transistor (fan,o#t) capacitances

iii.'iring (interconnect) capacitance


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Sources o' !arasitic Ca"acitances

, MOS Intrinsic Capacitances

Structure ca"acitances

Channe ca"acitances Di''usion ca"acitances

I t i i C it


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Intrinsic Capacitances

MOS Structure Capacitance

Overlap Capacitance (linear)9

C6SO 5 C6"O 5 Cox xd '0 5 Co '0"

I t i i C it


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Overlap Capacitance

In realit$ the gate overlaps

so#rce and drain.So the parasitic overlap

capacitances9

C6S(overlap) 5 Cox ' 0"C6"(overlap) 5 Cox ' 0"

I t i i C it


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MOS Channel Capacitances, The gate,to,channel capacitance depends #pon the

8 operating region and the terminal voltages

I t i i C it


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MOS Channel Capacitances +verage Channel Capacitance

I t i i C it


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MOS Diffusion Capacitances, The D#nction (or diff#sion) capacitance is from the

reverse biased so#rce,bod$ and drain,bod$ p,n

D#nctions.

I t i i C it


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Source Junction View

E t i i C it


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Extrinsic Capacitance

Extrinsic (Fan-out) Capacitance The extrinsic or fano#t capacitance is the total gate

capacitance of the loading &MOS and !MOS transistors.

Cfano#t 5 Cgate (!MOS) E Cgate (&MOS)

5 (C6SOn E C6"On E 'n0nCox) E

(C6SOp E C6"Op E ' p0 pCox)

Simplification of the act#al sit#ation

8 +ss#mes all the components of Cgate are beteen Vo#t and 6!" (or V"")

8 +ss#mes the channel capacitances of the loading gates are

constant


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MOS Ca"acitance Mode


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Summar+1. 'hen designing static CMOS circ#its the idth of &MOS

m#st be made two or three times than the idth of !MOS

in order to obtain s$mmetrical sitching threshold VM and

noise margin.

%. The variations of !MOS and &MOS in CMOS ca#se a small

shift in the sitching threshold b#t that the operation of thegate is not affected.

/. The inverter characteristic can still be obtained altho#gh the

s#ppl$ voltage is scaled don as long as the minim#m

s#ppl$ voltage is higher than thermal voltage2. &arasitic capacitances sloer the sitching speeds

5F


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!ast /ears uestions

1. a) Setch a complete CMOS inverter circ#it diagram.

(% mars)

%. 3xplain the CMOS inverter operation.

(% mars)

/.


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topic 5 - cmos inverter

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