to aai, baba and smruti
TRANSCRIPT
CLOSED LOOP dv/dt CONTROL FOR EQUAL VOLTAGE SHARING BETWEEN
SERIES CONNECTED SIC MOSFETS
by
Vaibhav Uttam Pawaskar
APPROVED BY SUPERVISORY COMMITTEE:
Dr. Ghanshyamsinh Gohil, Chair
Dr. Bilal Akin
Dr. Poras T. Balsara
Dr. Babak Fahimi
Copyright c© 2019
Vaibhav Uttam Pawaskar
All rights reserved
To Aai, Baba and Smruti
CLOSED LOOP dv/dt CONTROL FOR EQUAL VOLTAGE SHARING BETWEEN
SERIES CONNECTED SIC MOSFETS
by
VAIBHAV UTTAM PAWASKAR, BE
THESIS
Presented to the Faculty of
The University of Texas at Dallas
in Partial Fulfillment
of the Requirements
for the Degree of
MASTER OF SCIENCE IN
ELECTRICAL ENGINEERING
THE UNIVERSITY OF TEXAS AT DALLAS
May 2019
ACKNOWLEDGMENTS
I would like to express my sincere gratitude to my supervisor Dr. Ghanshyamsinh Gohil for
providing me an opportunity to work on this thesis. I am very fortunate to work under
him due to his patience, consistent support and motivation. His method of approaching
problems are very logical and easy to understand which inspired me to learn and improvise.
I wish to thank my graduate committee members Dr. Bilal Akin, Dr. Poras T. Balsara
and Dr. Babak Fahimi for accepting my request and providing their time to be part of the
committee.
I also thank my friends and colleagues at the Power Electronics laboratory, Saurabh Kumar,
G. Veera Bharath, Thuan and Anad Patel for their help during several occasions.
My earnest gratitude to my parents and beloved family members for their continuous
support and prayers during all the stages of my life. I am always thankful for their blessings
which make me climb to new heights. Last but not the least, I am thankful to my wonderful
friends and roommates, Saroj Shinde, Pranjali Hirlekar, Harshita Dekate, Noopur Dulet,
Siddarth Debnath, Ajinkya Shinde for their moral support and preparing me delicious food
whenever I need. I would also like to thank my mentor, Deepika Ramalingam Ramesh, for
her help, motivational talks and advice regarding course selection right from the start of my
master’s until graduation.
April 2019
v
CLOSED LOOP dv/dt CONTROL FOR EQUAL VOLTAGE SHARING BETWEEN
SERIES CONNECTED SIC MOSFETS
Vaibhav Uttam Pawaskar, MSThe University of Texas at Dallas, 2019
Supervising Professor: Dr. Ghanshyamsinh Gohil, Chair
An efficient and cost-effective Medium-Voltage (MV) power semiconductor switch, which
is capable of high switching speed, is highly desirable for many existing and emerging
high power MV power conversion applications, such as solid-state transformers, MV motor
drives, renewable energy and storage integration with the medium voltage grid, Flexible
Alternating Current Transmission System (FACTS) devices etc. Emerging MV Silicon
Carbide (SiC) 10 kV/15 kV MOSFETs and IGBTs can be the potential candidate for these
applications. However, high cost, lack of the reliability data, and limited availability are the
major hurdles for the successful adoption of these devices. Efficient and cost-effective MV
switches can be also realized by series connection of reliable, and commercially available
Low-Voltage (LV) devices. The main concern of the series connected SiC devices is unequal
voltage distribution between devices during transient and steady state. This thesis deals
with this issue and proposes a closed loop active gate driver circuit which can control rate
of rise of drain-source voltage of SiC MOSFET during turn-off and turn-on interval without
any significant penalty on switching losses.
vi
TABLE OF CONTENTS
ACKNOWLEDGMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v
ABSTRACT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vi
LIST OF FIGURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix
LIST OF TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiii
CHAPTER 1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Passive voltage balancing techniques . . . . . . . . . . . . . . . . . . . . . 5
1.1.1 Normally off devices: IGBTs and MOSFETs . . . . . . . . . . . . . 5
1.1.2 Normally On Devices: JFETs . . . . . . . . . . . . . . . . . . . . . 8
1.2 Voltage Clamping Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.2.1 Active Voltage Clamping . . . . . . . . . . . . . . . . . . . . . . . . 12
1.2.2 Voltage Clamping Using Passive Elements . . . . . . . . . . . . . . 13
1.3 Gate Pulse Timing Control . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.3.1 Magnetic Coupling Between the Gate Pulses . . . . . . . . . . . . . 15
1.3.2 Gate Pulse Control Through Delay Compensation . . . . . . . . . . 16
1.4 Active gate control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.4.1 Gate Control Using Additional Capacitor . . . . . . . . . . . . . . . 19
1.4.2 Gate Control Using Active Gate Driver . . . . . . . . . . . . . . . . . 21
1.5 Thesis Organisation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
CHAPTER 2 SERIES CONNECTED SIC MOSFETS WITHOUT ACTIVE GATECONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.1 Causes of unequal voltage sharing . . . . . . . . . . . . . . . . . . . . . . . 28
2.2 Simulation results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
CHAPTER 3 CLOSE LOOP ACTIVE GATE DRIVER CIRCUIT . . . . . . . . . 32
3.1 Power MOSFET basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.2 New active gate driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.2.1 Active resistance control . . . . . . . . . . . . . . . . . . . . . . . . 35
3.2.2 Active gate voltage control . . . . . . . . . . . . . . . . . . . . . . . 40
3.3 Control modelling and stability analysis . . . . . . . . . . . . . . . . . . . 43
vii
3.4 Hardware implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
CHAPTER 4 EXPERIMENTAL VERIFICATION . . . . . . . . . . . . . . . . . 48
4.1 Active gate driver prototype . . . . . . . . . . . . . . . . . . . . . . . . . . 48
CHAPTER 5 CONCLUSION AND FUTURE WORK . . . . . . . . . . . . . . . 52
5.1 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5.2 Future work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
APPENDIX ACTIVE GATE DRIVER COMPONENT DESCRIPTION . . . . . . 54
REFERENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
BIOGRAPHICAL SKETCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
CURRICULUM VITAE
viii
LIST OF FIGURES
1.1 Applications of medium voltage switch for achieving reliable, cost-effective,environmental friendly, and efficient generation, transmission/distribution, andutilization of electric energy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 Overview of voltage balancing techniques used for the series connection of powerdevices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.3 Passive snubber technique to achieve voltage balancing for series connected powerdevices. The resistive parallel branch ensures static voltage balancing and otherparallel branch comprising of various combinations of the passive componentsthat facilitates dynamic voltage balancing. (a)Resistors with passive elements,(b) RC snubber, (c) RCD snubber, (d) passive clamping [5], and (e) improvedpassive clamping through additional resistor in series with capacitor [75]. . . . 6
1.4 Schematic of series connected SiC MOSFET. R1 and R2 are used for steadystate voltage sharing, C1 and C2 for gate control of MOSFET S2 and voltagesharing between them during switching transients. [56]. . . . . . . . . . . . . . . 7
1.5 Super-cascode structure to connect JFETs in series. (a) Schematic of super-cascode structure, consisting of 5 series connected SiC JFETs and low voltageSi MOSFET along with passive snubber circuit connected in parallel with eachswitch to achieve voltage balancing, (b) Series connected SiC JFETs and lowvoltage Si MOSFET with voltage-clamping diodes and load resistors for voltagebalancing. [36]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.6 Active voltage balancing control scheme used for comparing the voltage acrossswitch with reference voltage and detecting overvoltage [25]. . . . . . . . . . . 13
1.7 Voltage clamping of the power device using network comprises of zener diodes,current limiting resistor, and diode [71]. . . . . . . . . . . . . . . . . . . . . . . 14
1.8 Active clamping circuit that slows down the quickest power device by strategicallyadding external capacitor across gate and drain terminals.[59]. . . . . . . . . . . 14
1.9 A scheme for gate pulse synchronization through magnetic coupling [60]. . . . 15
1.10 Active voltage balancing circuit consisting of protection (active clamping) andfeedback control. Current through clamping circuit is converted to pulses bycomparator present in feedback circuit which have a pulse width equal to clampingtime. These are fed to microcontroller to perform control action. [31, 32]. . . . . 17
1.11 Active voltage balancing control method based on HRPWM. Depending uponfeedback obtained from voltage monitoring unit the gate signals are adjusted inmicrocontroller. [76]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
ix
1.12 Gate driver circuit used for dynamically balancing voltage of series connectedIGBTs by injection of positive gate current using a pre-charged capacitor.[17] . 19
1.13 Active dv/dt control used for series connected switches. Miller capacitor is usedto generate auxiliary gate current to control switching speed of device.[43]. . . 20
1.14 Schematic of the master-slave control [55]. Comparison of collector-emittervoltages of master and slave devices give error voltage and depending upon thesign of error voltage, current generator acts as either source or sink and generatesgate current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.15 (a) Closed loop control scheme to achieve desired switching trajectory, where thecommon reference is used for all series connected devices, (b) Common referencevoltage used in [53]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.16 (a) Common reference signal with temporary clamp. Temporary clamp is applied,for short duration, some time after the completion of the turn-off transient toensure good static voltage balancing [51, 74], (b) Reference voltage waveform forseries-connected SiC MOSFETs [54]. . . . . . . . . . . . . . . . . . . . . . . . . 24
1.17 Schematic of cascade active voltage control based on multi loop feedback system[51, 74]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.18 Structure of hybrid active gate drive consisting of fixed voltage source drive anddigitally controlled current source drive. Based on the inputs from the stagedetection circuit, control action is taken by FPGA to either inject or withdrawgate charge to ensure dynamic voltage balancing [75]. . . . . . . . . . . . . . . 25
2.1 Schematic of series connected SiC MOSFETs used for DPT. . . . . . . . . . . 28
2.2 Double pulse results of series connected MOSFETs in absence of active control. 30
2.3 Magnified view of dynamic state voltage sharing . . . . . . . . . . . . . . . . . 30
3.1 Equivalent circuit model of MOSFET considering the parasitics inductance andinternal capacitance of the terminals. . . . . . . . . . . . . . . . . . . . . . . . 32
3.2 Variation of capacitance between gate - drain with drain source voltage. . . . . 33
3.3 Turn-on voltage and current waveforms for the MOSFET considering idealfree-wheeling diode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.4 Turn-off voltage and current waveforms for the MOSFET considering idealfree-wheeling diode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.5 Schematic of active gate resistance control. It consists of turn-on and turn-offunits whose resistance is controlled by the control signals M1 - M6. . . . . . . 36
3.6 Division of turn-on waveforms of switch for active resistance control. . . . . . . 37
3.7 Division of turn-off waveforms of switch for active resistance control. . . . . . . 37
x
3.8 Double pulse results of series connected MOSFETS with active resistance control. 39
3.9 Magnified view of dynamic state voltage sharing. . . . . . . . . . . . . . . . . 39
3.10 Proposed closed loop active gate driver circuit. Gate voltage is shaped dependingupon reference signal (dv/dtref ) and feedback obtained from capacitor Cfb. . . 40
3.11 Double pulse results of series connected MOSFETs with proposed active gatedriver circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.12 Magnified view of dynamic state voltage sharing . . . . . . . . . . . . . . . . . 42
3.13 Block diagram representation of closed-loop gate driver circuit, where HPI(s),HAMP(s), Hsw(s) and Hfb(s) refers to transfer function of PI controller, outputamplifier, SiC MOSFET switch and positive feedback respectively. . . . . . . . 43
3.14 Root locus plot of the controller system after increasing the proportional gain 4times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.1 (AGD) Active gate driver prototype MARK-1. 1. and 2. Positive and NegativeDC bus terminals, 3. Midpoint of phase leg configuration, 4. 12 volts supply and12v to 3.3v converter, 5. Top switch, 6. +7.5/-7.5v bipolar supply, 7. IsolatedDC/DC converter +12v - +15v/-5v, 8. PWM input, 9. Isolated gate driver IC,10. Op-amp and Actuator switch, 11. and 12. Series connected switches. . . . 48
4.2 Voltage sharing in absence of active gate control with DC bus voltage at 1100V. 49
4.3 Magnified view of dynamic state voltage sharing during first turn-off instant at1100V DC bus voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.4 Voltage sharing with active gate control at 50V DC bus voltage. . . . . . . . . 50
4.5 Magnified view of dynamic state voltage sharing during first turn-off instant at50V DC bus voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.6 Voltage sharing with active gate control at 100V DC bus voltage. . . . . . . . 50
4.7 Magnified view of dynamic state voltage sharing during first turn-off instant at100V DC bus voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.8 Voltage sharing with active gate control at 250V DC bus voltage. . . . . . . . 50
4.9 Voltage sharing without active gate control at 250V DC bus voltage. . . . . . 50
4.10 Voltage sharing with active gate control at 500V DC bus voltage. . . . . . . . . 51
4.11 Voltage sharing without active gate control at 500V DC bus voltage. . . . . . . 51
A.1 (AGD) Active gate driver prototype MARK-1. 1. and 2. Positive and NegativeDC bus terminals, 3. Midpoint of phase leg configuration, 4. 12 volts supply and12v to 3.3v converter, 5. Top switch, 6. +7.5/-7.5v bipolar supply, 7. IsolatedDC/DC converter +12v - +15v/-5v, 8. PWM input, 9. Isolated gate driver IC,10. Op-amp and Actuator switch, 11. and 12. Series connected switches. . . . . 54
xi
A.2 Side view of AGD MARK-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
A.3 Bottom view of AGD MARK-1 . . . . . . . . . . . . . . . . . . . . . . . . . . 55
A.4 Test setup for the double pulse test, where 1. Function generator providing thereference waveform for the active gate driver, 2. 12V DC power supply, 3. LoadInductance, 4. MARK-1, 5. Oscilloscope, and 6. High voltage DC power supply. 56
xii
LIST OF TABLES
2.1 Parameters used for simulation. . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.1 Active resistors during different stages of switching transient depending uponapplied control signals. Control signal in high state corresponds to respectiveswitch in on-state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.2 Close loop gate driver parameter’s. . . . . . . . . . . . . . . . . . . . . . . . . 45
xiii
CHAPTER 1
INTRODUCTION
A quest for the environmental friendly, reliable, cost-effective, and efficient generation,
transmission/distribution, and utilization of electric energy has led to several emerging
Medium-Voltage (MV) power conversion applications, such as solid-state transformers, MV
high speed motor drives, renewable/storage integration at MV level, large data centers, fast
battery charges for electrical vehicles, next generation locomotives, and Flexible Alternating
Current Transmission System (FACTS) devices [19, 24, 29, 30, 35, 39, 40, 41, 42, 58, 64, 67,
77], outlined in Fig. 1.1. Efficient and fast MV power switch with high frequency switching
capability is critical in these applications to improve system level advantages, such as size,
weight, cost reduction and efficiency improvement. MV power conversion stage can be
realized by using
1. Multi-level converter topologies with low voltage devices.
2. MV power semiconductor devices (6.6 kV Si IGBTs, 10 kV/15 kV SiC MOSFETs
and IGBTs) with two-level topology.
3. MV power switch, realized by series-connected LV power devices (Si IGBTs, SiC
MOSFETs, SiC JFETs), arranged to achieve two-level topology.
Multi-level converters offer various advantages, such as superior harmonic quality,
relatively low switching losses, and low dv/dt [1, 34]. However, the multi-level converter
often leads to increased control complexity. Some of the multi-level converters, such as
Neutral Point Clamped (NPC) converter also suffers from unequal loss distribution among
the semiconductor devices [13], leading to under utilization of some of the semiconductor
devices. Many of the multi-level converters, such as Modular Multilevel Cascade Converter
1
Medium Voltage Power Switch
Generation
MV PV inverterWind TurbineMicro-turbine
Transmission/Distribution
Solid-state transformerMVDC distribution
Solid-state DC circuit breakerEnergy storageFACTs devices
Utilization
Oil and gasLocomotives
Electrical ship/aircraftLarge data center
Fast battery chargerPulse power/DefenseMV high speed drives
Figure 1.1. Applications of medium voltage switch for achieving reliable, cost-effective,environmental friendly, and efficient generation, transmission/distribution, and utilizationof electric energy.
Voltage Balancing Techniques
Passive techniques
Normally off devices:IGBTs, MOSFETs
Individual gate drivers[16, 68, 69, 70]
Single gate driver[56, 73]
Normally on devices:JFETs
Super Cascode[8, 10, 27, 61, 65]
Voltage clamping
Active voltage clamp[25, 26, 33, 47]
Using passive components[4, 12, 14, 59, 71]
Gate Pulse timing control
Magnetic coupling[60]
Gate pulse delaycompensation
[23, 31, 32, 63, 76]
Active Gate control
Using passive components[17, 43]
Active gate driver[15, 51, 52, 53, 54, 55, 72, 74, 75]
Figure 1.2. Overview of voltage balancing techniques used for the series connection of powerdevices.
(MMCC) and NPC, rely heavily on the usage of capacitors, which could increase the design
complexity and reduce converter lifetime [46].
Another technique to realize MV power conversion using simplified converter topology
is to use MV devices. Silicon (Si) Insulated Gate Bipolar Transistor (IGBT) has been used
in industry since its introduction. Due to availability of high current modules state-of-the
art Si IGBTs are capable of handling large power. However, the voltage blocking capability
of the IGBTs is limited to 6.5 kV. Due to unavoidable trade-off between switching loss and
on-state voltage drop, development of Si IGBTs for higher voltage ratings is hampered, as
manufacturers face limitations in obtaining fast MV Si IGBTs with low on state resistance
[14]. As a result, MV Si IGBTs are typically limited to switching frequency below 1 kHz
2
[45] and may not be the preferred choice for the emerging applications where efficient high
switching frequency operation is desirable. To overcome this constraint of Si based power
semiconductor performance limitation, it has become necessary to employ SiC based power
devices.
Because of superior properties of SiC, such as high breakdown electric field and lower
intrinsic carrier concentration, it is possible to realize SiC based power devices with low
conduction loss and low switching losses even for MV devices. SiC MOSFETs with voltage
blocking capability upto 15 kV and SiC IGBTs with the breakdown voltage of 27 kV are
reported [18, 50]. Use of these devices in MV power conversion can significantly simplify
the power circuit and at the same time achieve high switching frequency for many emerging
applications. Although the SiC MOSFET with 15 kV blocking voltage is reported, it is
believed that with present state of the technology, the on-state resistance of 15 kV SiC
MOSFET becomes prohibitively large to be employed in high power applications (blocking
voltage <10 kV is considered to be the optimal for majority carrier SiC devices). Moreover,
these devices are only available in research laboratories and it would take a long term for
their commercial availability. In addition, high cost due to production in small volume
could also hamper adoption of these devices. Reliability is also a major concern, as it is
shown that the SiC MOSFETs are more susceptible to cosmic ray induced failures as the
device voltage rating increases [11].
The probability of cosmic ray induced failures can be reduced through series connection
of LV power semiconductor devices. Moreover, proper implementation of series-connected
LV devices could be more efficient than the equivalent MV device [11]. In addition, due to
economy of scale and relatively easy material fabrication process realization of MV switch
through the series-connected LV devices is more economical [65]. However, there are several
challenges associated with the series connection of devices that need to overcome. One of the
major challenge in series connection of LV devices is to maintain equal voltage distribution
3
among the devices in dynamic and steady-state conditions. This would be discussed in
detail in Chapter 2.
Over the years, many methods have been proposed to minimize the voltage unbalance
of series connected power devices. Most of the methods are focused on Si IGBT whereas
very few recent publications have focused on SiC MOSFET as well. These techniques can
be classified in four major categories: Passive snubber, voltage clamping, gate pulse timing
control and active gate control circuits, as shown in Fig. 1.2.
Passive snubber is one of the most popular technique due to its ease of implementation
and robust performance. Passive network, such as series RC element, is connected in parallel
with the devices to achieve voltage balancing [70]. Passive snubbers are also used for the
voltage balancing in super-cascode configuration. Different MV switches with blocking
voltage of 4.5 kV, 5 kV, 6 kV, 6.5 kV, and 15KV (FREEDM) are demonstrated where LV
normally on SiC JFETs are connected in series [8, 10, 27, 61, 65]. However, the passive
elements in the snubber circuits should be selected judiciously since it leads to reduced
switching speed and higher losses.
To overcome limitations of the passive snubber, voltage clamping technique could be
utilized. This technique works on principal of clamping the voltage of switches to a desired
reference level which is lower than it’s rated voltage. The value of this reference is usually
depend upon feedback of voltage across individual devices. These methods are not capable
of adjusting the dv/dt of switch during dynamic state and may not ensure equal voltage
sharing during turn-on and turn-off intervals.
Some of the drawbacks of the previously discussed techniques can be overcome by
combining passive and active gate voltage control. Various ways of achieving active gate
control are summarized in Fig. 1.2. This approach mainly senses the voltage across each
device connected in series and affect their switching time by controlling the gate current
in a way to reduce voltage unbalance. Active gate-voltage control can be achieved using
4
simple arrangement of passive components [3, 56]. However accurate values of resistors and
capacitors are required to make it effective. In [17], voltage balancing for series-connected
IGBTs are achieved by controlling the gate capacitor charge profile during the turn-off
transient. Detection of miller zone is one of concern in this approach which wouldn’t be
required in [23], where providing accurate delay in gate signal helps to achieve equal voltage
sharing. Good voltage balancing can also be achieved by controlling the gate current through
miller capacitor [43], active gate driver [15], and multi level driver [20]. State of the art
voltage balancing techniques for series-connected power devices along with operation of
various approaches, merits and demerits are discussed as follows.
1.1 Passive voltage balancing techniques
The passive techniques for voltage balancing of series connection of both normally off devices
(IGBTs and MOSFETs) and normally-on devices (JFETs) are covered in this section.
1.1.1 Normally off devices: IGBTs and MOSFETs
Passive components with individual gate drivers
This technique uses passive circuit that is connected between two power terminals (collector
and emitter in IGBTs and drain and source in MOSFETs) of the semiconductor devices
to ensure voltage balancing and often employs two parallel branches. One of the parallel
branches comprises of high voltage resistor that ensures static voltage sharing. The other
parallel branch uses a combination of various passive components to achieve good dynamic
voltage balancing. Use of series connection of resistor and capacitor (RC) and combination
of resistor, capacitor, and diode (RCD) is often used for dynamic voltage balancing [16, 68],
as shown in Fig. 1.3. Passive snubber technique was mainly applied to series connection of
Si IGBTs until recently where it is also extended to series connection of SiC MOSFETs
[69, 70].
5
x
y
Series
connected
MOSFETs
Dynamic
voltage
balancing
branch
(a)
R
C
x
y
(b)
C
R
x
y
(c)
C
R
x
y
(d)
C
R
x
y
(e)
Figure 1.3. Passive snubber technique to achieve voltage balancing for series connectedpower devices. The resistive parallel branch ensures static voltage balancing and otherparallel branch comprising of various combinations of the passive components that facilitatesdynamic voltage balancing. (a)Resistors with passive elements, (b) RC snubber, (c) RCDsnubber, (d) passive clamping [5], and (e) improved passive clamping through additionalresistor in series with capacitor [75].
Compared to the RC snubber, RCD snubber could lead to lower losses. In RCD snubber,
the capacitor is charged through the low impedance path provided by the snubber diode
during turn-off transient. By effectively connecting snubber capacitor in parallel with the
power device and with proper selection of the snubber capacitors, good dynamic voltage
balancing can be achieved at the expense of longer turn-off time and higher turn-off losses.
During turn-on, the snubber capacitor is discharged through the resistor and power devices.
The snubber resistor should be chosen small enough to ensure full discharge of snubber
capacitor during turn-on, which also leads to large discharge current flow through the power
device. If employed in emerging applications, where high switching frequency operation is
desirable, frequent charge and discharge of snubber capacitor may significantly increase
6
Rg1
Rg2
C1R1
R2C2
G
S
S1
S2
M
D
Figure 1.4. Schematic of series connected SiC MOSFET. R1 and R2 are used for steady statevoltage sharing, C1 and C2 for gate control of MOSFET S2 and voltage sharing betweenthem during switching transients. [56].
snubber losses as well as losses in the power devices. Snubber components have to withstand
high voltage and current. As a result, snubber components with suitable voltage and power
rating are required that are often bulky and costly.
Size and losses of the RCD snubber can be reduced by using Passive Clamping (PC)
circuit [5], as shown in Fig. 3(d). The PC circuit is activated only when the device voltage
exceeds certain threshold voltage, as a result energy processed by the PC circuit and therefore
the associated snubber losses can be reduced. However, the dynamic voltage balancing,
when the device voltage is less than the clamping circuit threshold, is also compromised.
PC circuit can be improved by adding an additional resistor in series with capacitor, as
shown in Fig. 3(e). Addition of these resistor helps in reducing the peak voltage value of
snubber capacitor voltage and thereby reducing the energy losses [75].
Passive components with single gate drivers
Instead of using passive components with separate isolated gate drivers for series-connected
devices, truly three terminal power switch can be achieved by employing single gate driver
7
with the passive component arrangement [56], as shown in Fig. 1.4. The gate driver is
used for the lower device, whereas the gate terminals of remaining devices in the string
are controlled through combined operation of the gate driver and passive components.
Resistor R1 and R2 are arranged to ensure static voltage sharing, whereas capacitors C1
and C2 facilitates dynamic voltage balancing and gate control of power devices. This circuit
arrangement ensures relationship given in (1.1).
VRg2 + VC1 + VGS = VCgs2 + VMS (1.1)
where VRg2 , VC1 , and VCgs2 are the voltages across Rg2, C1, and gate-source capacitance of
MOSFET S2, respectively. VGS is the applied voltage and VMS is the voltage across the
drain-source terminals of S1. When the gate pulse is applied across gate source terminals of
S1 (VGS), it affects VMS, leading to charge and discharge of C1 during turn-off and turn-on,
respectively. The gate-source capacitor of S2 is charged due to the discharge current of C1,
resulting in increase in VCgs2 and therefore turning on S2. Similarly S2 can be turned off by
allowing C1 to charge by applying negative gate-source bias to S1.
1.1.2 Normally On Devices: JFETs
Junction gate Field Effect Transistors (JFETs) are normally on devices and can be connected
in series using Super Cascode structure to realize MV power switch. JFETs are cascaded
and the combination is connected in series with a LV Si MOSFET [8, 9, 10, 21] or SiC
MOSFET [65, 66], as shown in Fig. 1.5(a). Although the structure consists of many series
connected devices, the overall circuit still has three terminals, including only one control
terminal. The Super Cascode is controlled by applying appropriate gate signals to the
MOSFET, leading to extremely simple gate driver circuit requirement.
In Super Cascode configuration shown in Fig. 1.5(a), when positive voltage is applied
across the gate-source terminals of the MOSFET, MOSFET is turned on and its drain
8
J1
J2
J3
J4
J5
RGS1D1
CD1
RD1
RGS2D2
CD2
RD2
RGS3D3
CD3
RD3
RGS4D4
CD4
RD4
D5
CD5
RD5
Drain
SourceGate
LVMOSFET
(a)
J1R1
J2R2
J3R3
J4R4
J5R5
Drain
Source
D2
D3
D4
D5
C2
C3
C4
C5
Gate
(b)
Figure 1.5. Super-cascode structure to connect JFETs in series. (a) Schematic of super-cascode structure, consisting of 5 series connected SiC JFETs and low voltage Si MOSFETalong with passive snubber circuit connected in parallel with each switch to achieve voltagebalancing, (b) Series connected SiC JFETs and low voltage Si MOSFET with voltage-clamping diodes and load resistors for voltage balancing. [36].
source voltage drops to zero. As a result, the gate source potential of the JFET J1 reduces
to zero. Since JFET is normally on device, zero voltage across the gate source terminal
turns J1 on. With J1 and MOSFET in on-state, source of J2 is connected to the anode
of diode D1 whereas the cathode of diode D1 is connected to the gate terminal of JFET
J2. Therefore negative forward voltage drop of diode D1 appears across the gate source
terminal of J2 and it is turned on. Similarly other JFETs are also turned on sequentially.
This sequential turn-on mechanism could lead to over-voltages across upper JFETs, which
can be addressed by adding RC branch, as shown in Fig. 1.5(a). Due to the presence of
the capacitor CD1, the gate voltage of JFET J2 increases when J1 is turning on, pulling
down the source potential of JFET J2. This mechanism leads to synchronous turn on of all
9
JFETs. Adding voltage balancing capacitors help in synchronizing the switching but would
slow down the turn-off transient, resulting in increased switching loss. Accurate values of
these capacitors should be selected for synchronized operation and proper voltage balancing.
Resistor are connected in series with the capacitors to damp any voltage oscillations which
might be present due to the interactions between the capacitors and parasitic inductance,
as shown in Fig. 1.5(a).
To turn off the MV switch, MOSFET is turned-off first via its gate and its drain-source
voltage rises till the pinch-off voltage of J1 is reached, thus turning it off [7]. J1 blocks the
rising voltage till the avalanche voltage of diode is reached. Gate voltage of J2 remains
same but source voltage increases with increase in drain-source voltage of J1, making the
gate source of J2 negative and turning it off. Sequential turn-off occurs for the rest of
switches till the blocking voltage is reached. From the operation it is clear that as oppose to
conventional series connected circuits where all the switches remain off for equally sharing
the blocking voltage, here voltage is blocked step by step by each switch. Although the
potential of top device would be the highest, all devices would share equal blocking voltage.
The static voltage distribution is achieved by connecting resistor between the gate and
source terminals of the upper JFETs (RGS1 to RGS5), as shown in Fig. 1.5(a). The static
voltage distribution is determined by the avalanche voltage of diodes (D1 to D5) connected
between the gate terminals of two neighbouring JFETs, which can be controlled by allowing
desired leakage current through the diodes. Controlled leakage current through the diodes
can be achieved by selecting appropriate values of the resistors. Through proper selection
of the resistors, reliable sequential turn-off is also achieved, where the blocking voltage is
build up from the lower to the upper JFET. In this arrangement, the leakage current in
JFETs decreases from upper devices to lower devices and the current in balancing diodes
decreases from lower diodes to upper diodes. Moreover, the leakage current increases as
10
more number of JFETs are connected in series. These issues are addressed using the Super
Cascode structure presented in [36], as shown in Fig. 1.5(b).
For the arrangement shown in Fig. 1.5(b), voltage clamping diodes D2-D5 are used to
clamp the blocking voltage of JFET J1-J4 and gate potential of JFET J2-J5. The bias
currents of the voltage clamping diodes (D2 to D5) are determined by the voltage between
the drain and gate of the JFET and the corresponding resistor (R1 to R5). As a result,
the bias currents are independent of the device leakage current and threshold voltage,
eliminating the need for the pre-selection of JFETs. One of the major concern with this
topology is chance of avalanche breakdown of top JFET J5 since there is no arrangement to
clamp its voltage. Therefore the top JFET J5 would have to withstand the high voltage
repeatedly during switching.
The performance of the Super Cascode is optimized in [38] by proper sizing of the
balancing capacitor. The MV switch with the blocking voltage rating of 4.5KV is developed
and sequential switching with reduced switching losses is demonstrated. Device reliability
and short circuit capability are the issues which needs to be considered when using Super
Cascode switch. Appropriate gate driver with fast over-current protection and high common-
mode transient immunity is designed in [28] to overcome these issues. A 6 kV, 100 A Super
Cascode power module is designed [22], which is capable of switching at 175 kHz. 15 kV
Super Cascode switch through the cascade connection of SiC MOSFET and eleven SiC
JFETs is also demonstrated in [61, 65, 66]. The Super Cascode structure was also applied
to GaN transistors to realize 1.2 kV GaN switch using two 600V devices [57].
1.2 Voltage Clamping Methods
In voltage clamping methods, the over-voltage across the series connected power devices
can be avoided by clamping the device voltage to the predetermined voltage level. This is
11
often achieved using closed-loop control system. Various voltage clamping techniques for
series connected IGBTs and MOSFETs are reviewed in this section.
1.2.1 Active Voltage Clamping
In series-connected devices, voltage across the device, which turns off faster than other
series-connected devices, rises faster. If this device voltage is clamped to the set reference,
the remaining voltage naturally distributes across other series-connected devices [12, 33].
The clamping of the device is achieved through closed-loop control, where the device voltage
is compared with the set reference and if the device voltage exceeds the reference, the error
is amplified. The amplified signal is then used to control the device gate voltage to keep
the device in the active region until other devices are turnoff. The gain of the closed-loop
controller should be selected judiciously, since it affects the transient characteristics of
voltage limiter. Small gain would result in slow operation and large over-voltage. On the
other hand, large feedback gain may cause abrupt current change when the device is in
active state, which could lead to excessive power loss and device failure. This method
doesn’t require complex circuitry and is easy to implement but the device which clamps first
has higher power losses than the other since it has to undergo clamping with high voltage
and current. As a result, the efficiency is compromised.
One of the approaches to clamp the device (IGBT) voltage to the set level during
dynamic conditions is presented in [25, 26] as shown in Fig.1.6. The device is clamped by
injecting positive charge on the gate, which leads to the reduction in the collector-emitter
voltage. The positive charge is injected by supplying controlled positive gate current and
this current is regulated using the closed-loop control. The effectiveness of the method is
demonstrated though the hardware experiments where good voltage balancing is achieved
in the case of the device parameter mismatch and delay between the gate signals.
12
RG1
RG2
RF1RF2
R1
Rf
VCC
VEE
VCE∗
VCEfb +
−
Gate signal
Gate
Figure 1.6. Active voltage balancing control scheme used for comparing the voltage acrossswitch with reference voltage and detecting overvoltage [25].
1.2.2 Voltage Clamping Using Passive Elements
The need for high bandwidth high gain amplifier can be avoided by using a combination
of the passive elements along with the diodes to inject required amount of gate current to
achieve voltage clamping when needed [4]. One of the schemes for voltage clamping was
presented in [71]. The clamping circuit, shown in Fig.1.7, consists of several series connected
zener diodes, current limiting resistors, and diodes, which forms the feedback circuit. When
the device voltage exceeds the clamping voltage, set by the breakdown voltage of Zener
diodes VZ , clamping circuit conducts. As a result, current is injected into the gate terminal,
thereby achieving voltage clamping by operating the device in the active region. In this
scheme, the clamping voltage is decided by the breakdown voltage of combinations of Zener
diodes. In combination to the voltage clamping, RC snubber circuit is also required for
dynamic voltage balancing. Operation of the device in the active region during clamping
interval and use of the RC snubber circuit leads to increased losses.
The voltage balancing scheme to achieve good compromise between the voltage balancing
and losses was proposed in [59]. The circuit arrangement is shown in Fig. 1.8. It uses a
circuit comprising of zener diodes, resistors, and capacitor, which is connected across the
gate-collector terminals of the IGBT. When the device voltage is lower than the breakdown
voltage of the Zener diode Z1, additional circuit has very little influence on the turn-off
13
Feedback path
Vz
Feedback path
Vz
Controlsignal
Pulsetransformer
Figure 1.7. Voltage clamping of the power device using network comprises of zener diodes,current limiting resistor, and diode [71].
Z1
C1
R1
D1
Z2 R2
RG2
RG1
VCC
Gatesignal
Figure 1.8. Active clamping circuit that slows down the quickest power device by strategicallyadding external capacitor across gate and drain terminals.[59].
transient behavior. It only draws very small current, determined by the parasitic capacitance
of the semiconductor components of the voltage balancing circuit. Once the device voltage
reaches the breakdown voltage of the Zener diode Z1, Z1 conducts and it effectively connects
capacitor C1 across the gate-collector terminal, slowing down the device turn-off. This
operation continues until the device voltage reaches the sum of the breakdown voltages of
Z1 and Z2, after which the device voltage is clamped. Once Z2 is conducting, capacitor C1
discharges and resistor divider is formed by the series connection of D1, R1, R2, Z1, and
RG2 , which appears across the device and ensures proper static voltage balancing. Selection
14
GateDriver
G
S
Ig1
GateDriver
G
S
Ig2
Coupled
inductor
Controlsignal
Figure 1.9. A scheme for gate pulse synchronization through magnetic coupling [60].
of the breakdown voltage of Zener diode Z1 is very important since lower values would cause
excessive losses and higher value would result in poor voltage balancing.
1.3 Gate Pulse Timing Control
One of the main reasons behind unequal voltage sharing among series-connected devices
is the asynchronous gate pulses, leading to non-simultaneous switching of the devices.
Asynchronous gate pulses are often caused by the unequal delays in the gate pulses, mainly
introduced by the gate driver isolation circuit. Providing appropriate delay in the gate
signals could help achieving voltage balancing. Several methods of gate pulse timing control
are proposed in the past and those methods are summarized in this section.
1.3.1 Magnetic Coupling Between the Gate Pulses
A method to synchronize the gate pulses through magnetic coupling was proposed in [60]
and it is shown in Fig. 1.9. A coupled inductor is placed in the gate current path of
two series connected IGBTs. The strong magnetic coupling between two windings of this
coupled inductor offers very high impedance to the differential voltage applied across its
terminals. On the other hand, very small inductance (leakage inductance) is offered to the
15
voltage component that is common. As a result, equal gate currents Ig1 and Ig2 are ensured,
leading to synchronized gate voltages. The minimum value of the magnetizing inductance
to ensure gate pulse synchronization was derived as a function of input capacitance of the
device and worst case time difference in the gate pulses. The leakage inductance of the
coupled inductor could resonate with the input capacitance and it should be minimized to
avoid excessive ringing in the gate pulses. This scheme can be extended to ensure gate pulse
synchronization of multiple series connected devices as described in [60]. Experimental
results in [60] show good dynamic voltage sharing for four series connected IGBTs.
1.3.2 Gate Pulse Control Through Delay Compensation
Adjusting the gate signal to get the desired control during transient and steady state
has been proposed in [23]. Closed loop gate pulse delay control is used for controlling
collector-emitter voltage of each IGBT connected in series. Equal voltage sharing between
the switches is achieved by providing required delay during turn-on and turn-off transients
in respective gate signals. The voltage across the device is measured and compared with the
reference and based on the error signal, required turn-on delay time (Tdon) and turn-off delay
time (Tdoff) are calculated. To achieve precise delay compensation, the controller should be
synchronized with the switching signals. Good control over the turn-on and turn-off dv/dt
was observed for 3 IGBTs connected in series [23].
A control scheme based on the combination of voltage clamping and delay time compen-
sation was presented in [31, 32]. The voltage balancing was realized using protection circuit
(for voltage clamping) and status feedback circuit along with the controller unit as shown
in Fig. 1.10. Clamping circuit is very important part of the closed-loop control system. Not
only it clamps the devices to predefined voltage level in the event of the over-voltage but it
also provides the indication of the mismatch in the device voltages. When the device voltage
reaches the clamping voltage VC1 due to the unbalanced voltages, current is established,
16
Rs
R1
D1
VC1
VC2 R2C1
R3
R4
R5
−+ Vref
+
−tAC,i
FPGA
Gatecontrol
Figure 1.10. Active voltage balancing circuit consisting of protection (active clamping) andfeedback control. Current through clamping circuit is converted to pulses by comparatorpresent in feedback circuit which have a pulse width equal to clamping time. These are fedto microcontroller to perform control action. [31, 32].
which flows through the sample resistor Rs. Therefore, the voltage across the sampling
resistor can be used to detect the voltage unbalance. The status feedback circuit converts
the current in clamping circuit and modifies it to pulses acceptable by the FPGA/controller.
The width of the pulse is equal to the clamping interval. Using the clamping interval
information, compensation time is generated internally in the FPGA. One of the limitations
of this method is that it requires several pulses before the voltage balancing can be achieved,
leading to unbalanced voltages during startup.
In [76], feedback obtained from online voltage monitoring unit and processed by high
resolution pulse width modulator (HRPWM) in microcontroller to apply delay compensation,
is shown in Fig 1.11. It has three main blocks, Transient Voltage Suppression (TVS) diodes,
online voltage unbalance monitoring unit, and HRPWM based gate signal timing unit in
microcontroller. TVS diodes are used for protection and it should be fast enough to clamp
the device voltage in case of the overvoltage. Voltage monitoring unit senses the Vds voltage
during turn-on and turn-off instant by Drain-source Voltage Boundary Detection (DVBD)
17
GateDriver
DVBD
GateDriver
DVBD
Signalisolator
Signalisolator
Signalisolator
Signalisolator
H
H
L
L
-
+
HRPWM based tunablegate timing unit
Turn-off
adjustment
Turn-on
adjustment
Modula
tor
Figure 1.11. Active voltage balancing control method based on HRPWM. Dependingupon feedback obtained from voltage monitoring unit the gate signals are adjusted inmicrocontroller. [76].
circuit and RC divider with comparator circuit, respectively. DVBD indicates the rise in
Vds voltage of series connected devices. If one of the device gets turned-on earlier than other
devices, logic signals are generated accordingly which are fed to microcontroller to activate
HRPWM. Then, depending upon the switching instant and obtained Vds values of both
the devices, gate signals are adjusted to achieve equal voltage sharing. This scheme would
have a one switching cycle control delay, therefore voltage unbalance would be observed
initially. Another drawback is slow switching speed if the TVS diode junction capacitance is
comparatively higher. Another concern is jitter, which is observed in gate signal waveforms
generated by HRPWM, affecting the accuracy of the system. High resolution and fast
microcontrollers could be used to overcome this issue, but it would increase overall cost.
For better voltage balancing, this method requires Tdoffto be accurately defined in
range of nanoseconds and delay time resolution to be less than 1ns. This can be achieved
using digital delay line connected between FPGA and gate driver of one of the series
18
GateDriver
GateDriver
C
R1Rg1
Rg2
Monostable
Voltage
unbalancedetector
Precharge
circuit
Optocoupler
VCC
VEE
Controlsignal
Figure 1.12. Gate driver circuit used for dynamically balancing voltage of series connectedIGBTs by injection of positive gate current using a pre-charged capacitor.[17]
connected devices as proposed in [63]. Digital delay line can operate at much higher control
frequency than the FPGA and microcontroller, thereby leading to improved delay time
resolution. Good voltage balancing between series connected devices is demonstrated using
this approach [63].
1.4 Active gate control
In active gate driving control, the gate charge profile is precisely controlled to modify the
turn-off and turn-on transient to achieve dynamic voltage balancing. This can be achieved
in several different ways and these active gate driving techniques are summarized in this
section.
1.4.1 Gate Control Using Additional Capacitor
Dynamic voltage balancing in series-connected devices can be achieved by controlling the
turn-off and turn-on behavior of the series-connected devices through gate current control.
Turn-on transient can be accelerated and turn-off transient can be slowed down by injecting
19
GateDriver
Ig1Id1
Ic1
C1
GateDriver
Ig2Id2
Ic2
C2
CM
Q1 Q2
Q3 Q4
Ic
I3 I4
Ig′
I2I1
VCTRL
Figure 1.13. Active dv/dt control used for series connected switches. Miller capacitor isused to generate auxiliary gate current to control switching speed of device.[43].
positive gate current. On the other hand, the injection of the negative gate current facilitates
faster turn-off and slower turn-on. Thereby the control freedom offered by the gate current
injection can be utilized to achieve dynamic voltage balancing, where the positive gate
current can be injected into the gate terminal of the fastest device to slow it down during
turn-off. Similarly, suitable gate current control can also facilitate dynamic voltage balancing
during turn-on as well.
Control of gate current to achieve dynamic voltage balancing by inserting pre-charged
capacitor in the gate path was proposed in [17], as shown in Fig. 1.12. The voltage unbalance
detection circuit determines the faster device, which is slowed down during the turn-off
by injecting gate current in the miller effect zone by using a pre-charged capacitor C, as
shown in Fig. 1.12. This method requires accurate sizing of capacitor and proper timing for
insertion of this capacitor, which in turn requires miller effect zone detection.
Similar approach has been adopted in [43] to achieve dynamic voltage balancing between
series-connected devices. The impact of the parasitic capacitance between the gate and
ground is considered in the analysis and it is shown that the even with the identical devices
and gate drivers, the gate currents of series-connected devices are unequal due to the
difference in the rate of change of the gate voltages, which result in to unequal current
20
through the parasitic capacitors leading to unequal gate currents. The gate current of
the series-connected devices can be equalized by deriving current from additional miller
capacitor CM to compensate for the current through parasitic capacitance using the circuit
shown in Fig.1.13. In the arrangement shown in Fig. 1.13, the base voltage of transistor Q1
(VCTRL) is used to control the gate current of the faster device The control voltage VCTRL
is derived using the closed-loop control system, where the device voltages are measured
and used to generate the error signal which is then fed to the PI controller to generate
required control voltage VCTRL. VCTRL determines the current division between Q1 and
Q2 and thereby directs fraction of the current Ic to the gate of the top device to slow it
down. Thus, by controlling VCTRL good dynamic voltage balancing can be achieved. The
experimental results show good voltage balancing when series connected devices are used
as lower switch in bridge leg. However, the concept needs to be verified when the series
connected devices are used as an upper switch in bridge leg.
1.4.2 Gate Control Using Active Gate Driver
Turn-on and turn-off voltage profile of the device can be controlled by actively controlling
the gate charge profile. This can be achieved using multiple approaches, such as gate voltage
control, gate current control, and gate resistance control, which can be realized using active
gate driver.
Gate charge control by current source/sink action of the control circuit was employed in
[55]. By proper control of the current source, commutation of switches being controlled can
be accelerated or delayed to achieve dynamic voltage balancing. Control scheme for the
dynamic voltage balancing is based on the master-slave approach, where the upper-most
device is considered as master, whereas remaining devices are controlled as slaves. Master
device is controlled using traditional gate driver and its speed can be controlled by proper
selection of gate resistance. The gate driver unit of slave devices comprises of current source,
21
GateDriver
GateDriver
+Current
generator
VCES
VCEM
R3
R4
R1
R2
R12
R7
R8
R5
R6
R9
R11R10
VCEM
VCES
G
VCC
+
-
+
-
Figure 1.14. Schematic of the master-slave control [55]. Comparison of collector-emittervoltages of master and slave devices give error voltage and depending upon the sign of errorvoltage, current generator acts as either source or sink and generates gate current.
which is actively controlled using close-loop feedback control system, as shown in Fig. 1.14.
Voltage across of slave devices (VCEs) is measured and compared with the voltage across the
master device (VCEM). The error (eth) is amplified and used to control the current source.
The sign of eth would decide whether control circuit extracts or supplies charges from the
input capacitance of switch being controlled, leading to VCE control during turn-off and
turn-on transients. Hysteresis band is defined for the error value and the control action
is only taken when the error value is outside the hysteresis band, indicating imbalance in
voltage. One of the drawbacks of this approach is that the gate signal of slave devices
depends on the VCEMfeedback and propagation delay in control hardware may deteriorate
dynamic voltage balancing. This problem can be addressed by using common reference for
all switches [51, 72, 74].
One such approach was presented in [52], where the common reference is used for all
devices and closed loop control is implemented with device voltage feedback to track the
reference signal during turn-on and turn-off, as shown in Fig. 1.15(a). Analog reference
signal is derived locally in the gate driver unit to avoid distortion during transmission. The
22
Rg
H
+
-V ∗CE
Rg
H
+
-V ∗CE
(a)
I II III IV VV ∗CE
Clamp voltage
turn-offdv/dt
turn-ondv/dt
Pre-conditioningbias
Interval I & IV: On, II: Turn-offIII: Off, IV: Turn-on
(b)
Figure 1.15. (a) Closed loop control scheme to achieve desired switching trajectory, wherethe common reference is used for all series connected devices, (b) Common reference voltageused in [53].
reference signal could be a simple ramp signal as presented in [52] or could be more complex
waveform [53], divided into multiple intervals, each tailored to achieve desired device voltage
trajectory. One such reference waveform is shown in Fig. 1.15(b). It is used with the
closed loop control to achieve dynamic voltage balancing of series-connected IGBTs by
ensuring identical switching trajectories of all devices. The turn-off transient begins with
the pre-conditioning bias, where the IGBT is operated in the active region so that it can be
easily controlled. Once this stage is over, ramp is applied which determines turn-off dv/dt.
By setting appropriate ramp rate of the reference signal, rate of change of device voltage
dv/dt can be controlled. Since same ramp signal is applied to all series connected devices,
good dynamic voltage balancing can be achieved. Finally clamp voltage reference is applied
which dictates maximum device voltage. Turn-on transient is initiated by applying slow
ramp signal to synchronize all devices, followed by fast ramp signal to reduce turn-on losses.
By applying identical ramp signals during turn-on to all devices, equal turn-on dv/dt can
be achieved.
The reference signal was further modified by incorporating temporary clamp [51, 74],
as shown in Fig. 1.16(a). Temporary clamp is applied, for short duration, some time
23
I II III IV V
Temporary clamp
V ∗CE
turn-offdv/dt
turn-ondv/dt
Pre-conditioningbias
Interval I & IV: On, II: Turn-offIII: Off, IV: Turn-on
(a)
Temporary clamp
Overshootclamp
LimitclampV ∗
DS
Pre-conditioningbias
(b)
Figure 1.16. (a) Common reference signal with temporary clamp. Temporary clamp isapplied, for short duration, some time after the completion of the turn-off transient to ensuregood static voltage balancing [51, 74], (b) Reference voltage waveform for series-connectedSiC MOSFETs [54].
after the completion of turn-off transient. Application of temporary clamp removes stored
charges and reset the width of depletion region, leading to good static voltage sharing. This
approach is also applied to the series-connected SiC MOSFETs [54], where the reference was
modified as shown in Fig. 1.16(b). Overshoot clamp is applied to reduce voltage overshoot
during turn-off, followed by temporary clamp to achieve good static voltage balancing.
However, due to the higher switching speed of the SiC MOSFET, error amplifiers with
wider bandwidth and higher gain are required.
In closed loop control schemes discussed previously, it is very important that the device
voltage follows the reference signal to achieve voltage balancing. This can be achieved
through proper design of the closed-loop control system. The feedback control loop can
be enhanced using cascade control structure [72, 74], as shown in Fig. 1.17. Feedback of
collector-emitter voltage VCEfbis obtained by RC circuit, which is then compared with the
reference signal V ∗CE. The output of this error amplifier is the desired gate voltage, which is
compared with the actual gate voltage using another error amplifier. To improve stability
24
R1
Rg
dv/dt feedback
VCE feedback
VGE detector
V ∗CE
VCEfb +
-
+
-
Figure 1.17. Schematic of cascade active voltage control based on multi loop feedbacksystem [51, 74].
of feedback system and alter gate voltage to follow reference accurately, dvce/dt feedback
loop is also used.
Stage detectionCurrent source
drive
R1
R2
R3
C1
C2
C3
LeE
Rg
FPGAVCC
VEE
DAC
CS1
CS2
VCC
VEE
E
e
C
G
Figure 1.18. Structure of hybrid active gate drive consisting of fixed voltage source driveand digitally controlled current source drive. Based on the inputs from the stage detectioncircuit, control action is taken by FPGA to either inject or withdraw gate charge to ensuredynamic voltage balancing [75].
Another scheme for series connection of IGBTs, which employs common reference for
all devices, is presented in [75]. Turn-on and turn-off transients of the IGBT are divided
into number of stages that can be detected based on the information of rate change of
collector current and collector-emitter voltage. Collector-emitter voltage is measured using
25
the voltage divider network, as shown in Fig. 1.18, whereas the rate of change of collector
current information can be indirectly obtained by measuring voltage across the parasitic
inductance LeE, shown in Fig. 1.18. Measured information is then fed to the hysteresis
comparator. Hysteresis comparator output is given to FPGA that detects the device
turn-on/turn-off stages based on the sampled output of the comparators, which is used to
calculate the time interval of different turn-on and turn-off stages. Time interval of each
stage is used as a common reference for all devices. The gate driver is then commanded to
source/sink necessary gate current such that the IGBT follow the reference time interval.
To precisely control the gate charge, hybrid gate driver is employed. The hybrid gate driver
is realized through parallel connection of typical fixed voltage source drive and digitally
controlled current source drive, as shown in Fig. 1.18. The difference between reference
time interval and actual time interval is fed to the proportional controller, implemented in
FPGA. Output of the proportional controller determines the gate drive current, which is
used to control the current source drive through digital to analog converter. This scheme
performs well during steady-state conditions. However, during initial stage of operation or
step change in load current between adjacent switching cycles the voltage sharing becomes
unequal, thus an additional conventional active clamp circuit is required to overcome this
issue.
The major issue of increased switching losses and inability to control the dv/dt of the
device during dynamic state can be achieved by active gate control. Active gate control can
be achieved either by controlling the gate voltage, current or resistance such that device
switching time are affected in a way to achieve equal voltage balancing. Static voltage
balancing can be achieved by connecting small balancing resistors in parallel with each
switch. This thesis focuses on unequal voltage distribution between series connected SiC
devices during turn-off and turn-on period and proposes a closed loop active gate driver
26
circuit which can control rate of rise of drain-source voltage of SiC MOSFET without any
significant penalty on switching losses.
1.5 Thesis Organisation
In Chapter 1, detailed discussion on state of the art techniques used for series connection of
insulated gate power devices are reviewed.
Chapter 2, deals with series connection of SiC MOSFETs without active gate control.
The outcomes of such approach and the root of unequal voltage sharing between series
connected switches is discussed.
Chapters 3, introduces to power MOSFET’s basic operation and switching characteristics
along with discussion on active resistance control and proposed closed loop gate driver
circuit. Simulation results performed on SaberRd and modelling and stability analysis of
close loop circuit is dealt in detail.
Chapter 4, deals with hardware development for proposed gate driver circuit for series
connected SiC MOSFETs.
Chapter 5, provides summary and conclusion on voltage balancing techniques for series
connected insulated gate power devices along with outline for future work.
This thesis concludes with an appendix which includes discussion about active gate
driver component description and their selection criteria.
27
CHAPTER 2
SERIES CONNECTED SIC MOSFETS WITHOUT ACTIVE GATE
CONTROL
2.1 Causes of unequal voltage sharing
Connecting several switches in series would lead to higher voltage blocking capacity consid-
ering that each switch supports a share of applied voltage. For example, if ”N” switches
are connected in series and assuming the voltages are shared equally between the switches,
the series string could block voltage ”N” times the rated voltage of the individual switch.
SiC MOSFETs and other insulated gate power semiconductor switches are sensitive to gate
control, circuit parasitics and switch parameters. When these switches are connected in
series as shown in Fig. 2.1, without any control over the gate signal large voltage mismatch
is observed during switching transitions.
Lstray
Lload
esr
td
G1
G2
S1
S2
Vdc C
CG1
CG2
Figure 2.1. Schematic of series connected SiC MOSFETs used for DPT.
This is can be due to:
• Mismatch in various parts of gate driver systems resulting in a tiny delay during
triggering,
28
• Presence of parameter mismatch such as variations in rise or fall time of switch,
• Unequal propagation delay in signal isolators, thus equal voltage balancing between
the switches may not be ensured.
In [60] effects of unsynchronized gate timing signals for series connected IGBTs are studied,
which gave a relationship between imbalance rate of collector - emitter voltage and switching
timing difference between the switches. This imbalance rate is defined in terms of actual
voltages and switching time balanced voltages. Even with small difference in switching time,
resulted in device breakdown due to overvoltage.
Another reason which is widely ignored by researchers for unequal voltage balancing
is the difference in the rate of change of gate voltage of series connected devices which
drives current through parasitic capacitance’s present between gate terminal of switches
and ground [43]. Thus, the total gate current during transient state would be desired gate
current and current through this parasitic capacitance. This causes unequal gate currents
leading to unequal dv/dt of series-connected devices [52] resulting in reduced share of total
dc voltage for lower switch. This capacitance is mainly composed of parasitic capacitance
of gate driver power supply and internal capacitance of module package. Since the voltage
unbalancement may exceed the individual device rating which will cause subsequent failure
of this device and finally failure of entire series string of devices. These effects can be
minimized by choosing devices from the same batch and synchronized gate drive signals
[62].
Table 2.1. Parameters used for simulation.
Vdc Lstray Lload LG LD LS Rg Cfb CG1 CG2
[volts] [nh] [uh] [nh] [nh] [nh] [ohms] [pf] [pf] [pf]
1100 100 640 7 8 9 10 0.1 10 10
29
2.2 Simulation results
These elements of voltage mismatch were considered while simulating the Double pulse test
(DPT) circuit shown in Fig. 2.1, with and without active gate control.
6 7 8 9
·10−5
0
500
1,000
1,500
T(secs)
V(v
olt
s)
Vds1
Vds2
∆V= 283.89 Volts
Figure 2.2. Double pulse results of series connected MOSFETs in absence of active control.
6 6 6.01 6.01
·10−5
0
500
1,000
1,500
T(secs)
V(v
olt
s)
Vds1
Vds2
Figure 2.3. Magnified view of dynamic state voltage sharing
30
S1 and S2 represent the SiC MOSFETs, and G1 and G2 represent the gate driver units.
Time delay of td was deliberately added in the gate signal applied to switch S2 with respect
to switch S1. This delay was provided to emulate the difference in threshold voltage of
switches (mismatch in device parameter) and propagation delay due to signal isolators.
Table.2.1 shows the parameters used for simulation in which, LG, LD, LS, are the parasitic
inductance’s of gate, drain and source terminals of the switch. Rg, Cfb, CG1 and CG2 are
the gate resistance, feedback capacitor, and parasitic capacitance’s respectively. The results
obtained in the absence of active control are shown in Fig.2.2, in which voltage difference
of 283.89V is observed. This can be avoided along with reduced overshoot and ringing in
Vds using active gate driver circuit. Experimental results obtained through DPT from the
prototype developed, are provided in Chapter 4.
31
CHAPTER 3
CLOSE LOOP ACTIVE GATE DRIVER CIRCUIT
3.1 Power MOSFET basics
Power MOSFET is designed such that it can handle significant power levels. These are
majority carrier devices and when used in power electronics application’s, it has led to
realising higher switching frequencies resulting in reduction in size of inductors, capacitors,
filters and transformers. They are capable of withstanding high current and voltage without
undergoing destructive failure due to second breakdown [6]. Fig. 3.1 shows, the equivalent
circuit model of MOSFET which would be used for analysing it’s operation and deriving
transfer function. Lg, Ld, Ls, Rg denotes the parasitic inductance’s and internal gate
Lg Rg
Cgs
Cgd Ld
Ro Cds
Ls
G D
S
+
−vgs vgs
gm.
Figure 3.1. Equivalent circuit model of MOSFET considering the parasitics inductance andinternal capacitance of the terminals.
resistance. Cgs, Cds, and Cgd are the gate - source, drain - source and gate - drain capacitors
which can be found as follows -
Ciss = Cgs + Cgd (Cds shorted) (3.1)
Crss = Cgd (3.2)
Coss = Cds + Cgd (3.3)
32
Where, Ciss, Coss and Crss are the input, output and reverse transfer capacitance provided
by the manufacturer in the datasheet. The basic function of MOSFET when used as a
switch is to regulate drain current depending upon applied gate voltage. The gate - drain
capacitance varies with drain - source voltage, thus generally it is idealised in 2 discrete
values as shown in Fig. 3.2. In the case of ideal free-wheeling diode, when gate voltage is
Cgd2
Cgd1
Vgs = Vds
Idealization
Actual
Cgd
Vds
Figure 3.2. Variation of capacitance between gate - drain with drain source voltage.
applied to the switch, Vgs rises exponentially with the time constant
τ = Rg ∗ (Cgs + Cgd1) (3.4)
(considering only the gate resistance Rg and input capacitance’s). The time required for
Vgs to reach the threshold voltage from zero is defined as turn - on delay time. During
this period current flows through the input capacitance’s and drain current remains zero.
Drain current starts to rise when Vgs rises above threshold value. Vds remaining constant
until drain current reaches to load current value, after which Vgs gets clamped to a constant
value and Vds drops with 2 different slopes due to relation with gate - drain capacitance.
33
Vds continues to drop up to on-state value, depending upon its on-state resistance and load
current.
When diode reverse recovery is considered, drain current and Vgs rises above the rated
values causing increased turn-on time and losses. After the minority carriers are removed,
diode turns-off which would bring the drain current and Vgs back to the rated values along
with rapid decrease in Vds [44]. This ends the reverse recovery process and the remaining of
the transient continues as discussed earlier. Turn-off process would be similar as discussed
for turn-on, but with reverse sequence of events. The corresponding waveforms of the drain
- source (Vds), gate - source (Vgs) voltages and drain current (Id) are shown in Fig. 3.3 and
3.4, where Vg, Vgs,Io, Vgsth, and Vdson are the applied gate voltage to switch, gate voltage at
rated load current, threshold gate voltage and on-state drain - source voltage respectively.
Vg
Vgs,Io
Vgsth
Vds
Id
Vdson
τ 1 = Rg*(Cgd1 + Cgs)
τ 2 = Rg*(Cgd2 + Cgs)
Vgs
Discrete
slopes
Ig
Charge on
Cgs + Cgd
Charge on
Cgd
Figure 3.3. Turn-on voltage and current waveforms for the MOSFET considering idealfree-wheeling diode.
34
Vg Vgs,Io Vgsth
Vds
Id
τ 1 = Rg*(Cgd1 + Cgs)
τ 2 = Rg*(Cgd2 + Cgs) Vgs
Figure 3.4. Turn-off voltage and current waveforms for the MOSFET considering idealfree-wheeling diode.
3.2 New active gate driver
The actual switching time and gate charge profile would depend upon the gate drive voltage
and also on the gate resistance employed. Using the active gate driver circuit with the
closed-loop control, the gate charge profile would be precisely controlled to modify the
turn-off and turn-on transient to achieve dynamic voltage balancing between the series
connected switches. Schematic of active resistance and gate voltage control are shown in
Fig. 3.5 and 3.10 respectively.
3.2.1 Active resistance control
In active resistance control technique, dv/dt during turn-on and turn-off switching transients
of switch S1 is shaped by control signals (M1 - M6) which are provided to 6 auxiliary
switches as shown in Fig. 3.5. The switching transient is divided in stages and in each stage,
device switching is controlled by varying gate resistance [49]. Fig. 3.6 and 3.7 illustrate the
35
R4 R5 R6
R1 R2
VCC
VEE
Turn-on Unit
Turn-off Unit
S1
M1 M2 M3
M4 M5 M6
R3
Figure 3.5. Schematic of active gate resistance control. It consists of turn-on and turn-offunits whose resistance is controlled by the control signals M1 - M6.
division of turn-on and turn-off waveforms in 4 stages i.e., S1 - S4 and S5 - S8 respectively,
along with variation in turn-on and turn-off gate resistance. Table. 3.1 shows the active
resistors and equivalent gate resistance during the switching transient’s.
Table 3.1. Active resistors during different stages of switching transient depending uponapplied control signals. Control signal in high state corresponds to respective switch inon-state.
Stage Control signal in high state Active resistors Equivalent resistanceS1 M1 and M3 R1 and R3 R′1S2 M1 and M2 R1 and R2 R′2S3 M2 R2 R′3S4 M2 and M3 R2 and R3 R′4S5 M4 and M6 R4 and R6 R′5S6 M4 and M5 R4 and R5 R′6S7 M5 R5 R′7S8 M5 and M6 R5 and R6 R′8
During turn-off switching transient, large gate resistance (R′6, R′7) are introduced which
reduces the dv/dt of switch. Even though the slope is reduced during stage S6 and S7, low
36
values of resistance (R′5, R′8) ensure that turn-off time (Toff) and switching losses are not
increased. Similar analysis can be performed on turn-on process. Each series connected
switch needs to be connected with resistance control circuit for voltage sharing. Resistor’s
R1 - R6 are selected judiciously to make sure the turn-on and turn-off delay are small and
desired dv/dt is achieved. In this technique, stage selection also play’s an important role for
good voltage sharing between switches.
S1 S2 S3 S4
Id
Il
Idr1
Idr2
Vds
Vdc
Vdsf
Vdson
Rgon
Ton
R 1
R 2
R 3
R 4
Tdon
Figure 3.6. Division of turn-on wave-forms of switch for active resistancecontrol.
S5 S6 S7 S8
Id
Il
Idf
Vds
Vdc
Vdsr2
Vdson
Rgoff
Toff
R 5
R 6
R 7
R 8
Tdoff
Vdsr1
Figure 3.7. Division of turn-off wave-forms of switch for active resistancecontrol.
1. Stage-1 duration is decided by summation of turn-on delay time (Tdon) and time
required to reach Idr1, where Idr1 is 20% in magnitude of drain current (Id) at turn-on. Gate
resistance introduced during this stage is low to speed up turn-on process.
37
2. Stage-2 duration starts from Idr1 until the device current reaches 80% of magnitude,
i.e., Idr2. By properly selecting the value of Idr2, delay in gate driver operation can be
compensated [48].
3. Stage-3 duration starts from Idr2 till the drain-source voltage (Vds) reaches Vdsf. High
gate resistance is introduced in this stage to minimise the current overshoot. Vdsf is selected
in vicinity of 50% in magnitude of DC bus voltage (Vdc), since at this instant current reaches
its peak value.
4. Stage-4 duration starts from Vdsf until the turn-on process (Ton) ends. Low value of
resistance is selected as in stage-1 to speed up the turn-on process.
5. Stage-5 duration is decided by summation of turn-off delay time (Tdoff) and time
required to reach Vdsr1, where Vdsr1 is 20% in magnitude of device voltage. This would help
to reduce (Tdoff) time and increase initial slope of (Vds).
6. Stage-6 duration starts from (Vdsr1) until the device voltage reaches 80% of magnitude,
i.e., (Vdsr2). Similar to stage-2, selecting appropriate value of (Vdsr2) delay in gate driver
operation can be compensated.
7. Stage-7 duration starts from (Vdsr2) till Id reaches Idf. Idf is selected close to 50%
magnitude of device current, since at this instant voltage reaches its maximum value. High
gate resistance is introduced in the circuit to reduce voltage overshoot.
8. Stage-8 duration starts from Idf until the turn-off process (Toff) ends. Similar to
stage-5, low value of resistance is selected to speed up the turn-off process and to reduce
corresponding losses.
Similar schematic as shown in Fig. 2.1 and nonlinearities as discussed in Chapter 2
are considered for demonstrating equal voltage sharing between series connected switches
using open loop active resistance control circuit. The results obtained by this technique are
shown Fig. 3.8 and 3.9. For closed loop operation using active resistance control, device
information related to Vds and Id would be required for stage selection. This information can
38
6 7 8 9
·10−5
0
200
400
600
T(secs)
V(v
olt
s)
Vds1
Vds2
Figure 3.8. Double pulse results of series connected MOSFETS with active resistancecontrol.
6.01 6.01 6.01
·10−5
0
200
400
600
Vds1
Vds2
Figure 3.9. Magnified view of dynamic state voltage sharing.
be obtained by using simple voltage divider network connected between drain and source
terminals and shunt resistor connected to source of the switches respectively. Since for the
upper switch ground reference would be varying similar to its source terminal, the feedback
signals would require isolation. Along with isolators in feedback, reference generator to
39
generate appropriate values of Vdsf, Idsr1 Idsr2 during turn-on and Idf, Vdsr1, Vdsr2 during
turn-off, comparator block to compare reference and sensed device voltage and current would
be required. These signals would be sent to CPLD acting as a local controller generating
control signals (M1 - M6).
In series connected configuration, feedback loop used in the close loop control is an
important parameter which affects the performance of the circuit. Using drain-source
voltage (Vds) of SiC MOSFET, as a feedback parameter results in delay in control and hence
voltage imbalance during initial stage and also during step change in load conditions. This
delay is mainly due to the isolator and ADC/DAC blocks present in the close loop feedback
circuit. Using proposed active gate voltage circuit this drawback can be resolved.
3.2.2 Active gate voltage control
−
+
Cfb
Rg
dv′/dtref
R2
R3
R1VCC
VEE
RvCv
S1
Figure 3.10. Proposed closed loop active gate driver circuit. Gate voltage is shapeddepending upon reference signal (dv/dtref ) and feedback obtained from capacitor Cfb.
In the proposed circuit (Fig. 3.10), capacitor (Cfb) connected to drain of MOSFET,
gives the information of dv/dt through the current flowing through it during dynamic state.
40
Using this feedback approach initial voltage mismatch is absent, thus voltage clamping or
snubber circuit’s are not required for initial voltage balancing.
Conceptual description and operating principle
Two different approaches for device voltage balancing can be employed, 1) common dv/dt
reference for both the switches, 2) master-slave approach, where dv/dt of one of the switches
is used as a reference for another switch. In the first approach the feedback obtained from
Cfb is compared to a reference waveform generating error signal which gets reduced by use of
analog based PI-controller. Using fast operational amplifier and push-pull emitter-follower
circuit, PI controller with required bandwidth and gain can be achieved. The input reference
(dv/dtref) is kept constant for complete switching instant and is depended upon desired
dv/dt of switch and gain in feedback loop (KV ). Following equation gives relationship
between these parameters -
(dVdsdt
)ref = −((dv/dt)ref
KV
) (3.5)
dv/dtref is set to positive value when switch is turned-on and vice-versa [37]. Determination
of these values would be discussed later in this chapter. Results obtained through this
approach are shown in Fig. 3.11 and 3.12.
In the second approach, the feedback signals obtained would be given to a differential
integrator. Output of integrator would drive a voltage controlled current source connected to
the gate terminal of slave switch. Current would be either injected or withdrawn depending
upon the slope mismatch present between master and slave switch. Generally the top device
connected in series topology would turn-off quicker when compared to lower device, thus
connecting the proposed circuit to the upper device would help to reduce the dv/dt or vice
versa. Thus, in both ways dynamic voltage balancing can be achieved. Resistors connected
in parallel with the switch assist to attain steady state voltage balancing.
41
6 7 8 9
·10−5
0
500
1,000
T(secs)
V(v
olt
s)
Vds1
Vds2
Figure 3.11. Double pulse results of series connected MOSFETs with proposed active gatedriver circuit.
6 6.01 6.01 6.01 6.01 6.01
·10−5
0
500
1,000
T(secs)
V(v
olt
s)
Vds1
Vds2
Figure 3.12. Magnified view of dynamic state voltage sharing
Reference required in first approach can be generated on board through simple H-Bridge
converter. The magnitude of converter output and value of Cfb, together would decide the
dv/dt of the switches.
42
3.3 Control modelling and stability analysis
The block diagram of closed-loop system is shown in Fig. 3.13 and stability of closed-loop
system is analysed, based on gate driver and SiC MOSFET models obtained below.
Close loop gate driver model
HPI(s) HAMP(s) Hsw(s)
Hfb(s)
Vgs(s)dv/dtref(s) Vds(s)
+
dv/dt(s)
⊕
Figure 3.13. Block diagram representation of closed-loop gate driver circuit, where HPI(s),HAMP(s), Hsw(s) and Hfb(s) refers to transfer function of PI controller, output amplifier, SiCMOSFET switch and positive feedback respectively.
PI controller used in this approach is realized by using high bandwidth operational
amplifier therefore, the transfer function of amplifier is given as follows -
Hopamp(s) =ADC,opamp
sADC,opamp
2πfT,opamp+ 1
(3.6)
where, ADC,opamp and fT,opamp refers to DC gain and transit frequency. The amplifier is
in non-inverting configuration as shown in Fig. 3.10, therefore the transfer function of PI
controller would be
HPI(s) =Hopamp(s)(sKP +KI)
s(Hopamp(s) +KP ) +KI
(3.7)
where, KP and KI refers to proportional gain and integral part KIs−1
. Desired gate current
is achieved by an output amplifier which can be modeled as low pas filter with crossover
frequency at fC,AMP. The transfer function is given as follows -
HAMP(s) =1
s 12πfC,AMP
+ 1(3.8)
43
For controlling Vds slope of switch, information related to dv/dt is required. This is provided
by the feedback capacitor Cfb. This can be modelled as an high pass filter whose transfer
function would be given as -
Hfb(s) = KVs
sKV + 1(3.9)
where, KV is the feedback gain of close loop gate driver circuit and defines the corner
frequency fC,V of filter as follows,
fC,V =1
2πKV
(3.10)
Based on the equivalent circuit of MOSFET, as shown in Fig. 3.1, transfer function from
gate voltage (Vgs) to drain-source voltage (Vds) is given in equation 3.11 [72]. Considering
the double pulse circuit as shown in Fig. 2.1, Id is assumed to be constant during dv/dt
control since it would be altered by inductive load. Thus, Hsw(s) would be depended upon
the external circuit operating condition.
Hsw(s) =Vds(s)Vgs(s)
=n1s
3 + n2s2 + n3s+ n4
d1s3 + d2s2 + d3s+ d4
(3.11)
Where,
n1 = LsRoCt
n2 = LsCgs+ LsCgd(1 + gmRo)
n3 = RoCgd
n4 = −gmRo
d1 = RoCt(Lg + Ls)
d2 = RoRgCt + (Cgs+ Cgd(1 + gmRo))(Lg + Ls)
d3 = Ro(Cgd+ Cds) +Rg(Cgs+ Cgd(1 + gmRo))
d4 = 1
Ct = CgsCgd+ CgsCds+ CgdCds
44
The open loop and closed loop transfer function’s of the gate driver circuit from reference
signal dv/dtref to dv/dt are given in equation as follows -
Gopl(s) =dv/dt(s)dv/dtref(s)
= HPI(s) ∗HAMP(s) ∗Hsw(s) ∗Hfb(s) (3.12)
Gcpl(s) =Gopl(s)
1 −Gopl(s)
(3.13)
Stability analysis
Parameters required for calculating the transfer function (3.13) and the controller gains are
provided in Table 3.2. Values for small signal model of MOSFET and it’s parasitic elements
Table 3.2. Close loop gate driver parameter’s.
ADC,opamp fT,opamp fC,AMP KV KP KI
[dB] [MHz] [MHz] [ps]
100 350 100 25 5.1E3 196E116
are found from the datasheet and library files provided by the manufacturer. PI controller
is tuned to achieve desired voltage slope during switching transient for both the switches as
shown in Fig. 3.12.
For satisfactory control, the closed loop feedback system needs to be stable even with
variation in controller parameters. According to stability criterion, all poles of the charac-
teristic equation of feedback system should lie on left hand side of the s-plane. To inspect
the stability of the gate driver circuit and sensitivity, the root locus plot of the control loop
with increased proportional gain to 4 times the nominal value is shown in Fig. 3.14.
45
-3 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2
108
-5
-4
-3
-2
-1
0
1
2
3
4
5
108
0.94
0.8
0.090.180.280.52
0.090.180.280.40.52
0.66
0.8
0.94
0.4
0.66
1e+08
2e+08
3e+08
4e+08
5e+08
1e+08
2e+08
3e+08
4e+08
5e+08
Root Locus
Real Axis (seconds-1
)
Imagin
ary
Axis
(seconds
-1)
Figure 3.14. Root locus plot of the controller system after increasing the proportional gain4 times.
3.4 Hardware implementation
The proposed gate driver circuit shown in Fig. 3.10 can be divided in 3 sub-parts i.e.,
sensing circuit, obtaining error signal and a PI controller and an amplifier stage.
Sensing circuit
This is one of the essential element in feedback system which would decide the control action
to be taken on gate voltage of switch. Feedback capacitor, Cfb provides the proportional
information related to time derivative signal dv/dt. Desired rate of rise of drain-source
voltage can be found from Equation. 3.5. This value would be slightly reduced due to
tolerance considered for parasitic inductance’s and sensing capacitor in practical circuit.
Assuming very small input voltage applied to non-inverting terminal of opamp when
46
compared with Vds, the feedback signal would be given as follows -
iCfb= Cfb.
dVdsdt
(3.14)
Obtaining error signal
To obtain the error signal, a passive circuit as shown in Fig. 3.10, consisting of R1, R2 and
Cfb should be connected which gives following expression for error -
VE = dv′/dtref.R3
R2 + 2R3︸ ︷︷ ︸dv/dtref
(3.15)
+Cfb.R3.R2
R2 + 2R3︸ ︷︷ ︸KV
.dVds/dt
Thus, the control error is the sum of the reference signal and voltage slope feedback and its
gain.
PI controller and an actuator switch
Using fast operational amplifier PI is realized, where the proportional and integral gain can
be found using following equations -
KP = 1 +Rv
R1
(3.16)
KI =1
R1.Cv(3.17)
A push-pull emitter follower circuit can be used as an actuator switch modelled as output
amplifier, to provide required bandwidth and current gain in the gate loop, but the turn-on
and turn-off time of these switches would affect the operation of the gate driver circuit
and may limit fast switching of SiC MOSFETs. Dual N and P channel enhancement mode
field effect transistors is used instead to provide superior switching characteristics, reduced
on-state resistance, and achieve high rate of rise of voltage slope.
47
CHAPTER 4
EXPERIMENTAL VERIFICATION
4.1 Active gate driver prototype
1
2
4
6
7
8
9
5
10
11
3 12
Figure 4.1. (AGD) Active gate driver prototype MARK-1. 1. and 2. Positive and NegativeDC bus terminals, 3. Midpoint of phase leg configuration, 4. 12 volts supply and 12v to3.3v converter, 5. Top switch, 6. +7.5/-7.5v bipolar supply, 7. Isolated DC/DC converter+12v - +15v/-5v, 8. PWM input, 9. Isolated gate driver IC, 10. Op-amp and Actuatorswitch, 11. and 12. Series connected switches.
The prototype of proposed closed loop active gate driver is developed as shown in
Fig. 4.1, to verify the concept. It is designed similar to schematic of double pulse test as
shown in Fig. 2.1, in which G1 and G2 contains the various sensing and control circuits
as discussed in previous chapters. The reference signal required for gate driver circuits is
provided externally through a function generator. Voltage difference of 520 volts is observed
in practical circuit, which is much higher than that observed through simulation results.
This steady state voltage difference would be due to difference in output capacitance’s
of the switches. Device inbuilt parasitic capacitors would also affect the slope of rise of
48
−4 −2 0 2 4
·10−5
0
500
1,000
T(secs)
V(v
olt
s)
Vds1
Vds2
∆V= 520 Volts
Figure 4.2. Voltage sharing in absence ofactive gate control with DC bus voltage at1100V.
8 8.2 8.4 8.6 8.8 9 9.2
·10−6
0
500
1,000
T(secs)
V(v
olt
s)
Vds1
Vds2
Figure 4.3. Magnified view of dynamicstate voltage sharing during first turn-offinstant at 1100V DC bus voltage.
drain-source voltage and current at switching instant, thus effecting the voltage sharing as
well.
Thus, it has been verified that in absence of active gate control, the top device connected
in series blocks higher voltage which results in large voltage mismatch between switches
during steady state as well as in dynamic state is observed as shown in Fig. 4.2 and 4.3.
The results obtained through DPT test with the proposed gate driver control are shown in
Fig. 4.4 - 4.7, 4.8, 4.10.
Comparing the voltage sharing performance with and without gate driver, reduced
ringing and overshoot are observed in the voltage waveforms with active gate driver control
as shown in Fig 4.8 - 4.11. Good voltage sharing between series connected devices is observed
while testing the prototype at 50V and 100V DC bus supply. Further increasing the DC bus
voltage, steady state voltage difference is observed between the devices as shown in Fig 4.8
and 4.10. Since the controller is tuned to match the slopes during the dynamic switching
instant, in the absence of feedback during steady state, voltage difference is observed. As
discussed previously, equal steady state voltage balancing can be achieved through use of
balancing resistors. These high value resistors are connected between the drain - source
49
-1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1
T(secs) 10-3
-5
0
5
10
15
20
25
30
35V
(volt
s)Vds1
Vds2
Figure 4.4. Voltage sharing with active gatecontrol at 50V DC bus voltage.
5.6 5.65 5.7 5.75 5.8 5.85 5.9 5.95 6 6.05 6.1
T(secs) 10-4
-5
0
5
10
15
20
25
30
V(v
olt
s)
Vds1
Vds2
Figure 4.5. Magnified view of dynamicstate voltage sharing during first turn-offinstant at 50V DC bus voltage.
-2 0 2 4 6 8 10 12 14 16 18
T(secs) 10-4
-10
0
10
20
30
40
50
60
70
80
90
V(v
olt
s)
Vds2
Vds1
Figure 4.6. Voltage sharing with active gatecontrol at 100V DC bus voltage.
5.91 5.92 5.93 5.94 5.95 5.96 5.97 5.98
T(secs) 10-4
-10
0
10
20
30
40
50
60
70
80
V(v
olt
s)
Vds2
Vds1
Figure 4.7. Magnified view of dynamicstate voltage sharing during first turn-offinstant at 100V DC bus voltage.
-2 0 2 4 6 8 10 12 14 16 18
T(secs) 10-5
0
50
100
150
200
V(v
olt
s)
Vds2
Vds1
110
Volts
Figure 4.8. Voltage sharing with active gatecontrol at 250V DC bus voltage.
-2 -1.5 -1 -0.5 0 0.5 1 1.5 2
T(secs) 10-4
-50
0
50
100
150
200
250
300
350
V(v
olt
s)
Vds1
Vds2
168 Volts
Figure 4.9. Voltage sharing without ac-tive gate control at 250V DC bus voltage.
50
-2 0 2 4 6 8 10 12 14 16 18
T(secs) 10-5
-50
0
50
100
150
200
250
300
350
400
450V
(vo
lts)
Vds2
Vds1
260
Volts
Figure 4.10. Voltage sharing with active gatecontrol at 500V DC bus voltage.
-1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1
T(secs) 10-4
-100
0
100
200
300
400
500
600
V(v
olt
s)
Vds1
Vds2
350
Volts
Figure 4.11. Voltage sharing without ac-tive gate control at 500V DC bus voltage.
terminals of switches and the common point of the series connected. Care must be taken to
connect these resistors close to the switch terminals to avoid additional stray inductance’s
in the circuit. Further description and selection criteria of components for the active gate
driver circuit is provided in appendix.
51
CHAPTER 5
CONCLUSION AND FUTURE WORK
5.1 Summary
Proper static and dynamic voltage balancing is essential for realizing cost-effective MV
switch. Various techniques for voltage balancing of series-connected power devices are
discussed in this thesis. Passive snubber, voltage clamping, gate pulse timing control, and
active gate control are four main groups of voltage balancing techniques. Passive snubber
is one of the popular methods due to its simplicity and robust performance. Significant
snubber losses and increased size are drawbacks of this method. Voltage clamping methods
can avoid device over-voltage by clamping the device voltage to set voltage level less than
the device breakdown voltage. This is typically achieved by operating device, that exceeds
the set reference, in active region. As a result, device voltage can be limited at the expense
of increased losses.
One of the main reasons behind unequal voltage sharing among series-connected devices
is the asynchronous gate pulses, leading to non-simultaneous switching of the devices.
Gate pulse timing control schemes provide appropriate delay in the gate pulses to achieve
good dynamic voltage balancing. Same can be also achieved by controlling gate charge
profile. Active gate control schemes are effective in maintaining good voltage balancing,
without imposing significant penalty in terms of switching losses and size. However, control
complexities increases. As a result, high speed/resolution signal processing and controller is
required, leading to increased cost.
Also, in series connected configuration, feedback loop used in the close loop control is an
important parameter which affects the performance of the circuit. Using drain-source voltage
(Vds) of SiC MOSFET, as a feedback parameter results in delay in control and hence voltage
imbalance during initial stage and also during step change in load conditions. Thus, the
52
proposed gate driver circuit can resolve this drawback and achieve good voltage balancing
using simple passive components for sensing and analog based operational amplifier as PI
controller. The dv/dt of switches can be modified according to the reference, thus utilising
full potential of power device along with reduced overshoot and ringing.
In almost all the techniques, separate isolated gate drivers are required, resulting in
multi-terminal MV switch. Truly three terminal MV switch using series-connected LV
devices can be achieved by connecting JFETs in series using super cascode configuration.
5.2 Future work
Future work would mainly focus on further improving the performance of proposed gate
driver and resolving the issues faced during first prototype testing. Studies can be performed
on the design of second approach of implementation, where dv/dt of one of the switches
is used as a reference for another switch. This would result in using just one gate driver
circuit instead of two gate drivers and elimination of reference signal generation. Currently
there aren’t many techniques provided for active control of SiC MOSFETs devices. In this
case this study can be put in to use, actively controlling the rate of rise of drain-source
voltage resulting in reduction in overshoot, ringing and EMI produced by fast switching.
53
APPENDIX
ACTIVE GATE DRIVER COMPONENT DESCRIPTION
The prototype of closed loop active gate driver and the experimental setup are shown in
shown in Fig. A.1 and A.4, consisting of various sub-parts. i.e., high voltage side supply,
isolated gate driver, isolated bipolar supply and SiC MOSFET’s in phase leg configuration.
1
2
4
6
7
8
9
5
10
11
3 12
Figure A.1. (AGD) Active gate driver prototype MARK-1. 1. and 2. Positive and NegativeDC bus terminals, 3. Midpoint of phase leg configuration, 4. 12 volts supply and 12v to3.3v converter, 5. Top switch, 6. +7.5/-7.5v bipolar supply, 7. Isolated DC/DC converter+12v - +15v/-5v, 8. PWM input, 9. Isolated gate driver IC, 10. Op-amp and Actuatorswitch, 11. and 12. Series connected switches.
The prototype is designed to be tested with 1.1kV DC rail ((1), (2)), thus C2M0080170P
SiC MOSFET capable of withstanding 1.7kV and two C3M0030090K SiC MOSFETs capable
54
Figure A.2. Side view of AGD MARK-1
of withstanding 900V are selected for top (5) and bottom devices ((10), (11)) respectively.
For all the switches TO-247-4L package is used to reduce the common source inductance
Figure A.3. Bottom view of AGD MARK-1
55
5
6
Figure A.4. Test setup for the double pulse test, where 1. Function generator providing thereference waveform for the active gate driver, 2. 12V DC power supply, 3. Load Inductance,4. MARK-1, 5. Oscilloscope, and 6. High voltage DC power supply.
in the gate loop and enable faster switching [2]. To illustrate the effectiveness of proposed
gate driver circuit bottom switches are connected in series configuration. Air core inductor
of 640uH is selected as an inductive load for the double pulse test to be connected between
positive dc bus rail and the midpoint of phase leg. Thus, the top device is always kept in
off-state by applying negative voltage to gate-source terminal and the reference for lower
switches is generated externally through a function generator.
Since the ground reference for the series connected switches would be different, isolated
power supply and gate drivers are required. Isolated DC-DC power supply MGJ2D122005SC
(7) capable of providing +15v (VCC) and -5v (VEE) voltage levels and isolated gate driver IC
ISO5852S (9) are selected for the gate driver loops. Op-amp used for realising PI controller
should have high slew rate in order to effectively control gate voltage applied to switches,
thus THS3201DBVT (10) is selected. When this amplifier is operated in bipolar supply
56
mode it requires +/-7.5 supply voltages, which can be realised on board through use of
LT8471 Dual DC/DC converter (6). Feedback capacitor and passive components related to
PI controller should be selected with least tolerance and temperature coefficient ”C0G-NP0”
to reduce variation in gain values and DC bias characteristic of ceramic capacitors. Actuator
switch connected after the PI controller amplifier would also affect the dv/dt capability of
gate driver circuit. Thus, it should have minimum turn-on and turn-off time, low on-state
resistance and current source, sink capabilities. Thus, dual N and P channel enhancement
mode power field effect transistors FDS8958B (10) are used due to it’s superior switching
performance and minimum on-state resistance. To ensure the gate-source voltage of the
switch always remains below the recommended values zener diodes are used as voltage
regulators between these terminals.
57
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BIOGRAPHICAL SKETCH
Vaibhav Uttam Pawaskar was born in Maharashtra, India. He received a BE degree in
Electrical Engineering from Lokmanya Tilak college of Engineering, Koparkhairane, Navi-
Mumbai, India affiliated with University of Mumbai in 2017. After completing his bachelor’s
he started his master’s at The University of Texas at Dallas. Since 2018, he has been with
the Power Electronics lab under Dr. Gohil at UT Dallas. His research interests include
renewable energy, wide band-gap based power electronics converters, active gate driving
techniques for SiC devices, and voltage balancing techniques for series connected power
devices.
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CURRICULUM VITAE
VAIBHAV UTTAM PAWASKAR Dallas, Texas
OBJECTIVE
Actively seeking full time opportunities in Power
Electronics
EDUCATION
The University of Texas at Dallas, Richardson, Texas | GPA : 3.904/4.00
MS in Electrical Engineering May 2019
The University of Mumbai, India | GPA : 9.49/10.00
BE in Electrical Engineering May 2017
TECHNICAL SKILLS
Programming Languages :C, C++, Assembly Language (8085,8086),
PLC programming.
Software :SaberRd, PLECS, MATLAB/Simulink, Altium,
Ansys Fluent, LTSPICE, PSIM, SIMPLIS,
Orcad- PSPICE.
Hardware :FPGA board, STM32 Discovery board, ARM Cortex –
M3, MSP430, C200 & PIC – 18 microcontrollers.
Hand’s on experience :Inverter, DC/DC converter, AC/AC converter,
DCmotor, Sync/Async Machines, Oscilloscope,
DC regulated power supply, Digital freq counter.
PROFESSIONAL EXPERIENCE
Graduate Research Assistant | University of Texas Feb 2018 – Present
Designed active gate driver for equal voltage sharing between series connected SiC
MOSFETs – Master’s Thesis.
Worked along with professor in designing and testing 3-phase 80 kW SiC MOSFET based
inverter.
Hardware prototype development, including PCB design, gate driver design, and controller
programming.
Implemented various discontinuous modulation schemes using C-script for 1-phase inverter.
Designed and simulated 3-phase inverter with NPC, ANPC and FC topologies.
Designed PFC stage 6.6 kW for EV charger and 10kW telecom rectifier.
Improved power factor to 0.9 of 4.4 kW 1-phase grid connected PV system using H5 invertertopology. Evaluated power losses during unity pf operation and observed increase in losseswith increase in solar irradiance.
Inplant Trainee | Brihanmumbai Electric Supply and Transport, Mumbai Jun 2016 – Jul 2016
Trained in various departments of Electric Supply Branch of the B.E.S. &T. Undertaking.
Worked along with junior engineers in the scheduled maintenance of transformer.
Vacation Trainee | The Tata Power Co. Ltd, Trombay and TPSDI, Shahad Jun 2015 – Jul 2015
Studied detailed working and construction of switchyard.
Understand the protection scheme used in substation and working of switch gear.
Observed 500 MW Generator, control room, GIS systems etc.
PROFESSIONAL AFFILIATION & AWARDS
(Pathways to research) Scholarship Recipient | University of Texas Aug 2018 – May 2019
Vice Chairperson | IEEE organization Aug 2014 – May 2016
General Secretary | Student council of Electrical Engineering Aug 2014 – May 2016
JOURNAL PUBLICATION
1. Vaibhav Uttam Pawaskar and Ghanshyamsinh Gohil, “Study on Voltage Balancing
Techniques for series Connected Power Devices” IEEE transactions on Power Electronics (In
review).
2. Vaibhav U. Pawaskar, Saroj S. Shinde, Surabhi S. Hatagale, Snehal P. Sonawane and Madhwi
Kumari, “Ansys simulation of portable vertical axis wind blades for urban rooftop green energy,”
Industrial Engineering Journal, June 2017.
REFERNCE
Prof. Ghanshyamsinh Gohil
Assistant Professor, The University of Texas at Dallas
ECSN 3.506, 800 West Campbell Road,
Richardson, TX 75080, USA
E-mail: [email protected]
Phone: (+1) 972 883 5413
Web: http://utdallas.edu/~ghanshyam.gohil/