tiva c series tm4c123gh6pz microcontroller data sheet (rev. … · 2014. 2. 25. · 9.2.1...

Tiva™ TM4C123GH6PZ Microcontroller

DATA SHEET

Copyr ight © 2007-2013Texas Instruments Incorporated

DS-TM4C123GH6PZ-15553.2700SPMS377C

TEXAS INSTRUMENTS-PRODUCTION DATA

CopyrightCopyright © 2007-2013 Texas Instruments Incorporated. Tiva and TivaWare are trademarks of Texas Instruments Incorporated. ARM and Thumb areregistered trademarks and Cortex is a trademark of ARM Limited. All other trademarks are the property of others.

Portions Copyright © 2007Mentor Graphics Corporation. Used with permission. All rights reserved. Mentor Graphics is a registered trademark of MentorGraphics Corporation.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standardwarranty. Production processing does not necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductorproducts and disclaimers thereto appears at the end of this data sheet.

Texas Instruments Incorporated108 Wild Basin, Suite 350Austin, TX 78746http://www.ti.com/tm4chttp://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm

November 15, 20132Texas Instruments-Production Data

http://www.ti.com/tm4chttp://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm

Table of ContentsRevision History ............................................................................................................................. 38About This Document .................................................................................................................... 41Audience .............................................................................................................................................. 41About This Manual ................................................................................................................................ 41Related Documents ............................................................................................................................... 41Documentation Conventions .................................................................................................................. 42

1 Architectural Overview .......................................................................................... 441.1 Tiva™ C Series Overview .............................................................................................. 441.2 TM4C123GH6PZ Microcontroller Overview ..................................................................... 451.3 TM4C123GH6PZ Microcontroller Features ..................................................................... 481.3.1 ARM Cortex-M4F Processor Core .................................................................................. 481.3.2 On-Chip Memory ........................................................................................................... 501.3.3 Serial Communications Peripherals ................................................................................ 521.3.4 System Integration ........................................................................................................ 561.3.5 Advanced Motion Control ............................................................................................... 621.3.6 Analog .......................................................................................................................... 641.3.7 JTAG and ARM Serial Wire Debug ................................................................................ 661.3.8 Packaging and Temperature .......................................................................................... 661.4 TM4C123GH6PZ Microcontroller Hardware Details ......................................................... 671.5 Kits .............................................................................................................................. 671.6 Support Information ....................................................................................................... 67

2 The Cortex-M4F Processor ................................................................................... 682.1 Block Diagram .............................................................................................................. 692.2 Overview ...................................................................................................................... 702.2.1 System-Level Interface .................................................................................................. 702.2.2 Integrated Configurable Debug ...................................................................................... 702.2.3 Trace Port Interface Unit (TPIU) ..................................................................................... 712.2.4 Cortex-M4F System Component Details ......................................................................... 712.3 Programming Model ...................................................................................................... 722.3.1 Processor Mode and Privilege Levels for Software Execution ........................................... 722.3.2 Stacks .......................................................................................................................... 732.3.3 Register Map ................................................................................................................ 732.3.4 Register Descriptions .................................................................................................... 752.3.5 Exceptions and Interrupts .............................................................................................. 912.3.6 Data Types ................................................................................................................... 912.4 Memory Model .............................................................................................................. 912.4.1 Memory Regions, Types and Attributes ........................................................................... 942.4.2 Memory System Ordering of Memory Accesses .............................................................. 942.4.3 Behavior of Memory Accesses ....................................................................................... 942.4.4 Software Ordering of Memory Accesses ......................................................................... 952.4.5 Bit-Banding ................................................................................................................... 962.4.6 Data Storage ................................................................................................................ 982.4.7 Synchronization Primitives ............................................................................................. 992.5 Exception Model ......................................................................................................... 1002.5.1 Exception States ......................................................................................................... 101

3November 15, 2013Texas Instruments-Production Data


2.5.2 Exception Types .......................................................................................................... 1012.5.3 Exception Handlers ..................................................................................................... 1052.5.4 Vector Table ................................................................................................................ 1062.5.5 Exception Priorities ...................................................................................................... 1062.5.6 Interrupt Priority Grouping ............................................................................................ 1072.5.7 Exception Entry and Return ......................................................................................... 1072.6 Fault Handling ............................................................................................................. 1102.6.1 Fault Types ................................................................................................................. 1112.6.2 Fault Escalation and Hard Faults .................................................................................. 1112.6.3 Fault Status Registers and Fault Address Registers ...................................................... 1122.6.4 Lockup ....................................................................................................................... 1122.7 Power Management .................................................................................................... 1132.7.1 Entering Sleep Modes ................................................................................................. 1132.7.2 Wake Up from Sleep Mode .......................................................................................... 1132.8 Instruction Set Summary .............................................................................................. 114

3 Cortex-M4 Peripherals ......................................................................................... 1213.1 Functional Description ................................................................................................. 1213.1.1 System Timer (SysTick) ............................................................................................... 1223.1.2 Nested Vectored Interrupt Controller (NVIC) .................................................................. 1233.1.3 System Control Block (SCB) ........................................................................................ 1243.1.4 Memory Protection Unit (MPU) ..................................................................................... 1243.1.5 Floating-Point Unit (FPU) ............................................................................................. 1293.2 Register Map .............................................................................................................. 1333.3 System Timer (SysTick) Register Descriptions .............................................................. 1363.4 NVIC Register Descriptions .......................................................................................... 1403.5 System Control Block (SCB) Register Descriptions ........................................................ 1553.6 Memory Protection Unit (MPU) Register Descriptions .................................................... 1843.7 Floating-Point Unit (FPU) Register Descriptions ............................................................ 193

4 JTAG Interface ...................................................................................................... 1994.1 Block Diagram ............................................................................................................ 2004.2 Signal Description ....................................................................................................... 2004.3 Functional Description ................................................................................................. 2014.3.1 JTAG Interface Pins ..................................................................................................... 2014.3.2 JTAG TAP Controller ................................................................................................... 2034.3.3 Shift Registers ............................................................................................................ 2034.3.4 Operational Considerations .......................................................................................... 2044.4 Initialization and Configuration ..................................................................................... 2064.5 Register Descriptions .................................................................................................. 2074.5.1 Instruction Register (IR) ............................................................................................... 2074.5.2 Data Registers ............................................................................................................ 209

5 System Control ..................................................................................................... 2115.1 Signal Description ....................................................................................................... 2115.2 Functional Description ................................................................................................. 2115.2.1 Device Identification .................................................................................................... 2115.2.2 Reset Control .............................................................................................................. 2125.2.3 Non-Maskable Interrupt ............................................................................................... 2175.2.4 Power Control ............................................................................................................. 2175.2.5 Clock Control .............................................................................................................. 218


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5.2.6 System Control ........................................................................................................... 2265.3 Initialization and Configuration ..................................................................................... 2305.4 Register Map .............................................................................................................. 2305.5 System Control Register Descriptions ........................................................................... 2365.6 System Control Legacy Register Descriptions ............................................................... 428

6 System Exception Module ................................................................................... 4946.1 Functional Description ................................................................................................. 4946.2 Register Map .............................................................................................................. 4946.3 Register Descriptions .................................................................................................. 494

7 Hibernation Module .............................................................................................. 5027.1 Block Diagram ............................................................................................................ 5037.2 Signal Description ....................................................................................................... 5037.3 Functional Description ................................................................................................. 5047.3.1 Register Access Timing ............................................................................................... 5047.3.2 Hibernation Clock Source ............................................................................................ 5057.3.3 System Implementation ............................................................................................... 5067.3.4 Battery Management ................................................................................................... 5077.3.5 Real-Time Clock .......................................................................................................... 5087.3.6 Battery-Backed Memory .............................................................................................. 5107.3.7 Power Control Using HIB ............................................................................................. 5107.3.8 Power Control Using VDD3ON Mode ........................................................................... 5107.3.9 Initiating Hibernate ...................................................................................................... 5107.3.10 Waking from Hibernate ................................................................................................ 5107.3.11 Arbitrary Power Removal ............................................................................................. 5117.3.12 Interrupts and Status ................................................................................................... 5117.4 Initialization and Configuration ..................................................................................... 5127.4.1 Initialization ................................................................................................................. 5127.4.2 RTC Match Functionality (No Hibernation) .................................................................... 5137.4.3 RTC Match/Wake-Up from Hibernation ......................................................................... 5137.4.4 External Wake-Up from Hibernation .............................................................................. 5137.4.5 RTC or External Wake-Up from Hibernation .................................................................. 5147.5 Register Map .............................................................................................................. 5147.6 Register Descriptions .................................................................................................. 515

8 Internal Memory ................................................................................................... 5338.1 Block Diagram ............................................................................................................ 5338.2 Functional Description ................................................................................................. 5348.2.1 SRAM ........................................................................................................................ 5348.2.2 ROM .......................................................................................................................... 5358.2.3 Flash Memory ............................................................................................................. 5378.2.4 EEPROM .................................................................................................................... 5438.3 Register Map .............................................................................................................. 5488.4 Flash Memory Register Descriptions (Flash Control Offset) ............................................ 5508.5 EEPROM Register Descriptions (EEPROM Offset) ........................................................ 5688.6 Memory Register Descriptions (System Control Offset) .................................................. 585

9 Micro Direct Memory Access (μDMA) ................................................................ 5949.1 Block Diagram ............................................................................................................ 5959.2 Functional Description ................................................................................................. 595



9.2.1 Channel Assignments .................................................................................................. 5969.2.2 Priority ........................................................................................................................ 5979.2.3 Arbitration Size ............................................................................................................ 5979.2.4 Request Types ............................................................................................................ 5979.2.5 Channel Configuration ................................................................................................. 5989.2.6 Transfer Modes ........................................................................................................... 6009.2.7 Transfer Size and Increment ........................................................................................ 6089.2.8 Peripheral Interface ..................................................................................................... 6089.2.9 Software Request ........................................................................................................ 6089.2.10 Interrupts and Errors .................................................................................................... 6099.3 Initialization and Configuration ..................................................................................... 6099.3.1 Module Initialization ..................................................................................................... 6099.3.2 Configuring a Memory-to-Memory Transfer ................................................................... 6109.3.3 Configuring a Peripheral for Simple Transmit ................................................................ 6119.3.4 Configuring a Peripheral for Ping-Pong Receive ............................................................ 6139.3.5 Configuring Channel Assignments ................................................................................ 6159.4 Register Map .............................................................................................................. 6159.5 μDMA Channel Control Structure ................................................................................. 6179.6 μDMA Register Descriptions ........................................................................................ 624

10 General-Purpose Input/Outputs (GPIOs) ........................................................... 65810.1 Signal Description ....................................................................................................... 65810.2 Functional Description ................................................................................................. 66110.2.1 Data Control ............................................................................................................... 66310.2.2 Interrupt Control .......................................................................................................... 66410.2.3 Mode Control .............................................................................................................. 66510.2.4 Commit Control ........................................................................................................... 66610.2.5 Pad Control ................................................................................................................. 66610.2.6 Identification ............................................................................................................... 66610.3 Initialization and Configuration ..................................................................................... 66610.4 Register Map .............................................................................................................. 66810.5 Register Descriptions .................................................................................................. 671

11 General-Purpose Timers ...................................................................................... 71611.1 Block Diagram ............................................................................................................ 71711.2 Signal Description ....................................................................................................... 71811.3 Functional Description ................................................................................................. 72011.3.1 GPTM Reset Conditions .............................................................................................. 72011.3.2 Timer Modes ............................................................................................................... 72111.3.3 Wait-for-Trigger Mode .................................................................................................. 73011.3.4 Synchronizing GP Timer Blocks ................................................................................... 73111.3.5 DMA Operation ........................................................................................................... 73111.3.6 Accessing Concatenated 16/32-Bit GPTM Register Values ............................................ 73211.3.7 Accessing Concatenated 32/64-Bit Wide GPTM Register Values .................................... 73211.4 Initialization and Configuration ..................................................................................... 73411.4.1 One-Shot/Periodic Timer Mode .................................................................................... 73411.4.2 Real-Time Clock (RTC) Mode ...................................................................................... 73511.4.3 Input Edge-Count Mode ............................................................................................... 73511.4.4 Input Edge Timing Mode .............................................................................................. 73611.4.5 PWM Mode ................................................................................................................. 736


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11.5 Register Map .............................................................................................................. 73711.6 Register Descriptions .................................................................................................. 738

12 Watchdog Timers ................................................................................................. 78612.1 Block Diagram ............................................................................................................ 78712.2 Functional Description ................................................................................................. 78712.2.1 Register Access Timing ............................................................................................... 78812.3 Initialization and Configuration ..................................................................................... 78812.4 Register Map .............................................................................................................. 78812.5 Register Descriptions .................................................................................................. 789

13 Analog-to-Digital Converter (ADC) ..................................................................... 81113.1 Block Diagram ............................................................................................................ 81213.2 Signal Description ....................................................................................................... 81313.3 Functional Description ................................................................................................. 81413.3.1 Sample Sequencers .................................................................................................... 81413.3.2 Module Control ............................................................................................................ 81513.3.3 Hardware Sample Averaging Circuit ............................................................................. 81913.3.4 Analog-to-Digital Converter .......................................................................................... 81913.3.5 Differential Sampling ................................................................................................... 82213.3.6 Internal Temperature Sensor ........................................................................................ 82413.3.7 Digital Comparator Unit ............................................................................................... 82513.4 Initialization and Configuration ..................................................................................... 82913.4.1 Module Initialization ..................................................................................................... 82913.4.2 Sample Sequencer Configuration ................................................................................. 83013.5 Register Map .............................................................................................................. 83013.6 Register Descriptions .................................................................................................. 832

14 Universal Asynchronous Receivers/Transmitters (UARTs) ............................. 91014.1 Block Diagram ............................................................................................................ 91114.2 Signal Description ....................................................................................................... 91114.3 Functional Description ................................................................................................. 91214.3.1 Transmit/Receive Logic ............................................................................................... 91314.3.2 Baud-Rate Generation ................................................................................................. 91314.3.3 Data Transmission ...................................................................................................... 91414.3.4 Serial IR (SIR) ............................................................................................................. 91414.3.5 ISO 7816 Support ....................................................................................................... 91514.3.6 Modem Handshake Support ......................................................................................... 91614.3.7 9-Bit UART Mode ........................................................................................................ 91714.3.8 FIFO Operation ........................................................................................................... 91814.3.9 Interrupts .................................................................................................................... 91814.3.10 Loopback Operation .................................................................................................... 91914.3.11 DMA Operation ........................................................................................................... 91914.4 Initialization and Configuration ..................................................................................... 92014.5 Register Map .............................................................................................................. 92114.6 Register Descriptions .................................................................................................. 922

15 Synchronous Serial Interface (SSI) .................................................................... 97015.1 Block Diagram ............................................................................................................ 97115.2 Signal Description ....................................................................................................... 97115.3 Functional Description ................................................................................................. 972



15.3.1 Bit Rate Generation ..................................................................................................... 97315.3.2 FIFO Operation ........................................................................................................... 97315.3.3 Interrupts .................................................................................................................... 97315.3.4 Frame Formats ........................................................................................................... 97415.3.5 DMA Operation ........................................................................................................... 98215.4 Initialization and Configuration ..................................................................................... 98315.5 Register Map .............................................................................................................. 98415.6 Register Descriptions .................................................................................................. 985

16 Inter-Integrated Circuit (I2C) Interface .............................................................. 101416.1 Block Diagram ........................................................................................................... 101516.2 Signal Description ..................................................................................................... 101516.3 Functional Description ............................................................................................... 101616.3.1 I2C Bus Functional Overview ...................................................................................... 101616.3.2 Available Speed Modes ............................................................................................. 102116.3.3 Interrupts .................................................................................................................. 102316.3.4 Loopback Operation .................................................................................................. 102416.3.5 Command Sequence Flow Charts .............................................................................. 102416.4 Initialization and Configuration .................................................................................... 103216.4.1 Configure the I2C Module to Transmit a Single Byte as a Master .................................. 103216.4.2 Configure the I2C Master to High Speed Mode ............................................................ 103316.5 Register Map ............................................................................................................ 103416.6 Register Descriptions (I2C Master) .............................................................................. 103516.7 Register Descriptions (I2C Slave) ............................................................................... 105216.8 Register Descriptions (I2C Status and Control) ............................................................ 1062

17 Controller Area Network (CAN) Module ........................................................... 106517.1 Block Diagram ........................................................................................................... 106617.2 Signal Description ..................................................................................................... 106617.3 Functional Description ............................................................................................... 106717.3.1 Initialization ............................................................................................................... 106817.3.2 Operation .................................................................................................................. 106917.3.3 Transmitting Message Objects ................................................................................... 107017.3.4 Configuring a Transmit Message Object ...................................................................... 107017.3.5 Updating a Transmit Message Object ......................................................................... 107117.3.6 Accepting Received Message Objects ........................................................................ 107217.3.7 Receiving a Data Frame ............................................................................................ 107217.3.8 Receiving a Remote Frame ........................................................................................ 107217.3.9 Receive/Transmit Priority ........................................................................................... 107317.3.10 Configuring a Receive Message Object ...................................................................... 107317.3.11 Handling of Received Message Objects ...................................................................... 107417.3.12 Handling of Interrupts ................................................................................................ 107617.3.13 Test Mode ................................................................................................................. 107717.3.14 Bit Timing Configuration Error Considerations ............................................................. 107917.3.15 Bit Time and Bit Rate ................................................................................................. 107917.3.16 Calculating the Bit Timing Parameters ........................................................................ 108117.4 Register Map ............................................................................................................ 108417.5 CAN Register Descriptions ......................................................................................... 1085


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18 Universal Serial Bus (USB) Controller ............................................................. 111618.1 Block Diagram ........................................................................................................... 111718.2 Signal Description ..................................................................................................... 111718.3 Functional Description ............................................................................................... 111818.3.1 Operation as a Device ............................................................................................... 111818.3.2 Operation as a Host ................................................................................................... 112318.3.3 OTG Mode ................................................................................................................ 112718.3.4 DMA Operation ......................................................................................................... 112918.4 Initialization and Configuration .................................................................................... 113018.4.1 Pin Configuration ....................................................................................................... 113018.4.2 Endpoint Configuration .............................................................................................. 113118.5 Register Map ............................................................................................................ 113118.6 Register Descriptions ................................................................................................. 1137

19 Analog Comparators .......................................................................................... 123119.1 Block Diagram ........................................................................................................... 123219.2 Signal Description ..................................................................................................... 123219.3 Functional Description ............................................................................................... 123319.3.1 Internal Reference Programming ................................................................................ 123419.4 Initialization and Configuration .................................................................................... 123619.5 Register Map ............................................................................................................ 123719.6 Register Descriptions ................................................................................................. 1237

20 Pulse Width Modulator (PWM) .......................................................................... 124720.1 Block Diagram ........................................................................................................... 124820.2 Signal Description ..................................................................................................... 125020.3 Functional Description ............................................................................................... 125120.3.1 Clock Configuration ................................................................................................... 125120.3.2 PWM Timer ............................................................................................................... 125120.3.3 PWM Comparators .................................................................................................... 125220.3.4 PWM Signal Generator .............................................................................................. 125320.3.5 Dead-Band Generator ............................................................................................... 125320.3.6 Interrupt/ADC-Trigger Selector ................................................................................... 125420.3.7 Synchronization Methods .......................................................................................... 125420.3.8 Fault Conditions ........................................................................................................ 125520.3.9 Output Control Block .................................................................................................. 125620.4 Initialization and Configuration .................................................................................... 125720.5 Register Map ............................................................................................................ 125720.6 Register Descriptions ................................................................................................. 1260

21 Quadrature Encoder Interface (QEI) ................................................................. 132521.1 Block Diagram ........................................................................................................... 132521.2 Signal Description ..................................................................................................... 132721.3 Functional Description ............................................................................................... 132821.4 Initialization and Configuration .................................................................................... 133021.5 Register Map ............................................................................................................ 133121.6 Register Descriptions ................................................................................................. 1331

22 Pin Diagram ........................................................................................................ 134823 Signal Tables ...................................................................................................... 134923.1 Signals by Pin Number .............................................................................................. 1350



23.2 Signals by Signal Name ............................................................................................. 136123.3 Signals by Function, Except for GPIO ......................................................................... 137123.4 GPIO Pins and Alternate Functions ............................................................................ 138023.5 Possible Pin Assignments for Alternate Functions ....................................................... 138323.6 Connections for Unused Signals ................................................................................. 1387

24 Electrical Characteristics .................................................................................. 138924.1 Maximum Ratings ...................................................................................................... 138924.2 Operating Characteristics ........................................................................................... 139024.3 Recommended Operating Conditions ......................................................................... 139124.4 Load Conditions ........................................................................................................ 139324.5 JTAG and Boundary Scan .......................................................................................... 139424.6 Power and Brown-Out ............................................................................................... 139624.6.1 VDDA Levels ............................................................................................................ 139624.6.2 VDD Levels ............................................................................................................... 139724.6.3 VDDC Levels ............................................................................................................ 139824.6.4 VDD Glitches ............................................................................................................ 139924.6.5 VDD Droop Response ............................................................................................... 139924.7 Reset ........................................................................................................................ 140124.8 On-Chip Low Drop-Out (LDO) Regulator ..................................................................... 140324.9 Clocks ...................................................................................................................... 140424.9.1 PLL Specifications ..................................................................................................... 140424.9.2 PIOSC Specifications ................................................................................................ 140524.9.3 Low-Frequency Internal Oscillator (LFIOSC) Specifications .......................................... 140524.9.4 Hibernation Clock Source Specifications ..................................................................... 140524.9.5 Main Oscillator Specifications ..................................................................................... 140624.9.6 System Clock Specification with ADC Operation .......................................................... 140924.9.7 System Clock Specification with USB Operation .......................................................... 141024.10 Sleep Modes ............................................................................................................. 141124.11 Hibernation Module ................................................................................................... 141324.12 Flash Memory and EEPROM ..................................................................................... 141424.13 Input/Output Pin Characteristics ................................................................................. 141524.13.1 GPIO Module Characteristics ..................................................................................... 141524.13.2 Types of I/O Pins and ESD Protection ......................................................................... 141524.14 Analog-to-Digital Converter (ADC) .............................................................................. 141924.15 Synchronous Serial Interface (SSI) ............................................................................. 142324.16 Inter-Integrated Circuit (I2C) Interface ......................................................................... 142624.17 Universal Serial Bus (USB) Controller ......................................................................... 142724.18 Analog Comparator ................................................................................................... 142824.19 Current Consumption ................................................................................................. 1430

A Package Information .......................................................................................... 1433A.1 Orderable Devices ..................................................................................................... 1433A.2 Part Markings ............................................................................................................ 1434A.3 Packaging Diagram ................................................................................................... 1435A.4 Packaging Materials .................................................................................................. 1436


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List of FiguresFigure 1-1. Tiva™ TM4C123GH6PZ Microcontroller High-Level Block Diagram ......................... 47Figure 2-1. CPU Block Diagram ............................................................................................. 70Figure 2-2. TPIU Block Diagram ............................................................................................ 71Figure 2-3. Cortex-M4F Register Set ...................................................................................... 74Figure 2-4. Bit-Band Mapping ................................................................................................ 98Figure 2-5. Data Storage ....................................................................................................... 99Figure 2-6. Vector Table ...................................................................................................... 106Figure 2-7. Exception Stack Frame ...................................................................................... 109Figure 3-1. SRD Use Example ............................................................................................. 127Figure 3-2. FPU Register Bank ............................................................................................ 130Figure 4-1. JTAG Module Block Diagram .............................................................................. 200Figure 4-2. Test Access Port State Machine ......................................................................... 203Figure 4-3. IDCODE Register Format ................................................................................... 209Figure 4-4. BYPASS Register Format ................................................................................... 209Figure 4-5. Boundary Scan Register Format ......................................................................... 210Figure 5-1. Basic RST Configuration .................................................................................... 214Figure 5-2. External Circuitry to Extend Power-On Reset ....................................................... 214Figure 5-3. Reset Circuit Controlled by Switch ...................................................................... 215Figure 5-4. Power Architecture ............................................................................................ 218Figure 5-5. Main Clock Tree ................................................................................................ 221Figure 5-6. Module Clock Selection ...................................................................................... 228Figure 7-1. Hibernation Module Block Diagram ..................................................................... 503Figure 7-2. Using a Crystal as the Hibernation Clock Source with a Single Battery Source ...... 505Figure 7-3. Using a Dedicated Oscillator as the Hibernation Clock Source with VDD3ON

Mode ................................................................................................................ 506Figure 7-4. Using a Regulator for Both VDD and VBAT ............................................................ 507Figure 7-5. Counter Behavior with a TRIM Value of 0x8002 ................................................... 509Figure 7-6. Counter Behavior with a TRIM Value of 0x7FFC .................................................. 509Figure 8-1. Internal Memory Block Diagram .......................................................................... 533Figure 8-2. EEPROM Block Diagram ................................................................................... 534Figure 9-1. μDMA Block Diagram ......................................................................................... 595Figure 9-2. Example of Ping-Pong μDMA Transaction ........................................................... 601Figure 9-3. Memory Scatter-Gather, Setup and Configuration ................................................ 603Figure 9-4. Memory Scatter-Gather, μDMA Copy Sequence .................................................. 604Figure 9-5. Peripheral Scatter-Gather, Setup and Configuration ............................................. 606Figure 9-6. Peripheral Scatter-Gather, μDMA Copy Sequence ............................................... 607Figure 10-1. Digital I/O Pads ................................................................................................. 662Figure 10-2. Analog/Digital I/O Pads ...................................................................................... 663Figure 10-3. GPIODATA Write Example ................................................................................. 664Figure 10-4. GPIODATA Read Example ................................................................................. 664Figure 11-1. GPTM Module Block Diagram ............................................................................ 717Figure 11-2. Reading the RTC Value ...................................................................................... 724Figure 11-3. Input Edge-Count Mode Example, Counting Down ............................................... 726Figure 11-4. 16-Bit Input Edge-Time Mode Example ............................................................... 727Figure 11-5. 16-Bit PWM Mode Example ................................................................................ 729Figure 11-6. CCP Output, GPTMTnMATCHR > GPTMTnILR ................................................... 729



Figure 11-7. CCP Output, GPTMTnMATCHR = GPTMTnILR ................................................... 730Figure 11-8. CCP Output, GPTMTnILR > GPTMTnMATCHR ................................................... 730Figure 11-9. Timer Daisy Chain ............................................................................................. 731Figure 12-1. WDT Module Block Diagram .............................................................................. 787Figure 13-1. Implementation of Two ADC Blocks .................................................................... 812Figure 13-2. ADC Module Block Diagram ............................................................................... 813Figure 13-3. ADC Sample Phases ......................................................................................... 817Figure 13-4. Doubling the ADC Sample Rate .......................................................................... 817Figure 13-5. Skewed Sampling .............................................................................................. 818Figure 13-6. Sample Averaging Example ............................................................................... 819Figure 13-7. ADC Input Equivalency Diagram ......................................................................... 820Figure 13-8. ADC Voltage Reference ..................................................................................... 821Figure 13-9. ADC Conversion Result ..................................................................................... 822Figure 13-10. Differential Voltage Representation ..................................................................... 824Figure 13-11. Internal Temperature Sensor Characteristic ......................................................... 825Figure 13-12. Low-Band Operation (CIC=0x0 and/or CTC=0x0) ................................................ 827Figure 13-13. Mid-Band Operation (CIC=0x1 and/or CTC=0x1) ................................................. 828Figure 13-14. High-Band Operation (CIC=0x3 and/or CTC=0x3) ................................................ 829Figure 14-1. UART Module Block Diagram ............................................................................. 911Figure 14-2. UART Character Frame ..................................................................................... 913Figure 14-3. IrDA Data Modulation ......................................................................................... 915Figure 15-1. SSI Module Block Diagram ................................................................................. 971Figure 15-2. TI Synchronous Serial Frame Format (Single Transfer) ........................................ 975Figure 15-3. TI Synchronous Serial Frame Format (Continuous Transfer) ................................ 976Figure 15-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 .......................... 977Figure 15-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .................. 977Figure 15-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ......................................... 978Figure 15-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ............... 979Figure 15-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ........ 979Figure 15-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ......................................... 980Figure 15-10. MICROWIRE Frame Format (Single Frame) ........................................................ 981Figure 15-11. MICROWIRE Frame Format (Continuous Transfer) ............................................. 982Figure 15-12. MICROWIRE Frame Format, SSInFss Input Setup and Hold Requirements .......... 982Figure 16-1. I2C Block Diagram ........................................................................................... 1015Figure 16-2. I2C Bus Configuration ....................................................................................... 1016Figure 16-3. START and STOP Conditions ........................................................................... 1017Figure 16-4. Complete Data Transfer with a 7-Bit Address ..................................................... 1017Figure 16-5. R/S Bit in First Byte .......................................................................................... 1018Figure 16-6. Data Validity During Bit Transfer on the I2C Bus ................................................. 1018Figure 16-7. High-Speed Data Format .................................................................................. 1023Figure 16-8. Master Single TRANSMIT ................................................................................ 1025Figure 16-9. Master Single RECEIVE ................................................................................... 1026Figure 16-10. Master TRANSMIT of Multiple Data Bytes ......................................................... 1027Figure 16-11. Master RECEIVE of Multiple Data Bytes ............................................................ 1028Figure 16-12. Master RECEIVE with Repeated START after Master TRANSMIT ....................... 1029Figure 16-13. Master TRANSMIT with Repeated START after Master RECEIVE ....................... 1030Figure 16-14. Standard High Speed Mode Master Transmit ..................................................... 1031Figure 16-15. Slave Command Sequence .............................................................................. 1032


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Figure 17-1. CAN Controller Block Diagram .......................................................................... 1066Figure 17-2. CAN Data/Remote Frame ................................................................................. 1068Figure 17-3. Message Objects in a FIFO Buffer .................................................................... 1076Figure 17-4. CAN Bit Time ................................................................................................... 1080Figure 18-1. USB Module Block Diagram ............................................................................. 1117Figure 19-1. Analog Comparator Module Block Diagram ....................................................... 1232Figure 19-2. Structure of Comparator Unit ............................................................................ 1233Figure 19-3. Comparator Internal Reference Structure .......................................................... 1234Figure 20-1. PWM Module Diagram ..................................................................................... 1249Figure 20-2. PWM Generator Block Diagram ........................................................................ 1249Figure 20-3. PWM Count-Down Mode .................................................................................. 1252Figure 20-4. PWM Count-Up/Down Mode ............................................................................. 1253Figure 20-5. PWM Generation Example In Count-Up/Down Mode .......................................... 1253Figure 20-6. PWM Dead-Band Generator ............................................................................. 1254Figure 21-1. QEI Block Diagram .......................................................................................... 1326Figure 21-2. QEI Input Signal Logic ...................................................................................... 1327Figure 21-3. Quadrature Encoder and Velocity Predivider Operation ...................................... 1329Figure 22-1. 100-Pin LQFP Package Pin Diagram ................................................................ 1348Figure 24-1. Load Conditions ............................................................................................... 1393Figure 24-2. JTAG Test Clock Input Timing ........................................................................... 1394Figure 24-3. JTAG Test Access Port (TAP) Timing ................................................................ 1395Figure 24-4. Power Assertions versus VDDA Levels ............................................................. 1397Figure 24-5. Power and Brown-Out Assertions versus VDD Levels ........................................ 1398Figure 24-6. POK assertion vs VDDC ................................................................................... 1399Figure 24-7. POR-BOR0-BOR1 VDD Glitch Response .......................................................... 1399Figure 24-8. POR-BOR0-BOR1 VDD Droop Response ......................................................... 1400Figure 24-9. Digital Power-On Reset Timing ......................................................................... 1401Figure 24-10. Brown-Out Reset Timing .................................................................................. 1401Figure 24-11. External Reset Timing (RST) ............................................................................ 1402Figure 24-12. Software Reset Timing ..................................................................................... 1402Figure 24-13. Watchdog Reset Timing ................................................................................... 1402Figure 24-14. MOSC Failure Reset Timing ............................................................................. 1402Figure 24-15. Hibernation Module Timing ............................................................................... 1413Figure 24-16. ESD Protection on Fail-Safe Pins ...................................................................... 1416Figure 24-17. ESD Protection on Non-Fail-Safe Pins .............................................................. 1417Figure 24-18. ADC External Reference Filtering ..................................................................... 1421Figure 24-19. ADC Input Equivalency Diagram ....................................................................... 1422Figure 24-20. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing

Measurement .................................................................................................. 1424Figure 24-21. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............... 1424Figure 24-22. Master Mode SSI Timing for SPI Frame Format (FRF=00), with SPH=1 .............. 1425Figure 24-23. Slave Mode SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................ 1425Figure 24-24. I2C Timing ....................................................................................................... 1426Figure A-1. Key to Part Numbers ........................................................................................ 1433Figure A-2. TM4C123GH6PZ 100-Pin LQFP Package Diagram ........................................... 1435Figure A-3. 100-Pin LQFP PZ Package Carrier Tape ........................................................... 1436Figure A-4. 100-Pin LQFP PZ Package Plastic Reel ............................................................ 1437Figure A-5. 100-Pin LQFP PZ Package Tape and Reel Box ................................................. 1438



List of TablesTable 1. Revision History .................................................................................................. 38Table 2. Documentation Conventions ................................................................................ 42Table 1-1. TM4C123GH6PZ Microcontroller Features ............................................................ 45Table 2-1. Summary of Processor Mode, Privilege Level, and Stack Use ................................ 73Table 2-2. Processor Register Map ....................................................................................... 74Table 2-3. PSR Register Combinations ................................................................................. 80Table 2-4. Memory Map ....................................................................................................... 91Table 2-5. Memory Access Behavior ..................................................................................... 95Table 2-6. SRAM Memory Bit-Banding Regions .................................................................... 97Table 2-7. Peripheral Memory Bit-Banding Regions ............................................................... 97Table 2-8. Exception Types ................................................................................................ 102Table 2-9. Interrupts .......................................................................................................... 103Table 2-10. Exception Return Behavior ................................................................................. 110Table 2-11. Faults ............................................................................................................... 111Table 2-12. Fault Status and Fault Address Registers ............................................................ 112Table 2-13. Cortex-M4F Instruction Summary ....................................................................... 114Table 3-1. Core Peripheral Register Regions ....................................................................... 121Table 3-2. Memory Attributes Summary .............................................................................. 125Table 3-3. TEX, S, C, and B Bit Field Encoding ................................................................... 127Table 3-4. Cache Policy for Memory Attribute Encoding ....................................................... 128Table 3-5. AP Bit Field Encoding ........................................................................................ 128Table 3-6. Memory Region Attributes for Tiva™ C Series Microcontrollers ............................. 129Table 3-7. QNaN and SNaN Handling ................................................................................. 132Table 3-8. Peripherals Register Map ................................................................................... 133Table 3-9. Interrupt Priority Levels ...................................................................................... 163Table 3-10. Example SIZE Field Values ................................................................................ 191Table 4-1. JTAG_SWD_SWO Signals (100LQFP) ................................................................ 200Table 4-2. JTAG Port Pins State after Power-On Reset or RST assertion .............................. 201Table 4-3. JTAG Instruction Register Commands ................................................................. 207Table 5-1. System Control & Clocks Signals (100LQFP) ...................................................... 211Table 5-2. Reset Sources ................................................................................................... 212Table 5-3. Clock Source Options ........................................................................................ 219Table 5-4. Possible System Clock Frequencies Using the SYSDIV Field ............................... 222Table 5-5. Examples of Possible System Clock Frequencies Using the SYSDIV2 Field .......... 222Table 5-6. Examples of Possible System Clock Frequencies with DIV400=1 ......................... 223Table 5-7. System Control Register Map ............................................................................. 231Table 5-8. RCC2 Fields that Override RCC Fields ............................................................... 260Table 6-1. System Exception Register Map ......................................................................... 494Table 7-1. Hibernate Signals (100LQFP) ............................................................................. 503Table 7-2. Hibernation Module Clock Operation ................................................................... 512Table 7-3. Hibernation Module Register Map ....................................................................... 514Table 8-1. Flash Memory Protection Policy Combinations .................................................... 538Table 8-2. User-Programmable Flash Memory Resident Registers ....................................... 542Table 8-3. Flash Register Map ............................................................................................ 548Table 9-1. μDMA Channel Assignments .............................................................................. 596Table 9-2. Request Type Support ....................................................................................... 598


Table of Contents

Table 9-3. Control Structure Memory Map ........................................................................... 599Table 9-4. Channel Control Structure .................................................................................. 599Table 9-5. μDMA Read Example: 8-Bit Peripheral ................................................................ 608Table 9-6. μDMA Interrupt Assignments .............................................................................. 609Table 9-7. Channel Control Structure Offsets for Channel 30 ................................................ 610Table 9-8. Channel Control Word Configuration for Memory Transfer Example ...................... 610Table 9-9. Channel Control Structure Offsets for Channel 7 .................................................. 611Table 9-10. Channel Control Word Configuration for Peripheral Transmit Example .................. 612Table 9-11. Primary and Alternate Channel Control Structure Offsets for Channel 8 ................. 613Table 9-12. Channel Control Word Configuration for Peripheral Ping-Pong Receive

Example ............................................................................................................ 614Table 9-13. μDMA Register Map .......................................................................................... 616Table 10-1. GPIO Pins With Non-Zero Reset Values .............................................................. 659Table 10-2. GPIO Pins and Alternate Functions (100LQFP) ................................................... 659Table 10-3. GPIO Pad Configuration Examples ..................................................................... 667Table 10-4. GPIO Interrupt Configuration Example ................................................................ 668Table 10-5. GPIO Pins With Non-Zero Reset Values .............................................................. 669Table 10-6. GPIO Register Map ........................................................................................... 669Table 10-7. GPIO Pins With Non-Zero Reset Values .............................................................. 682Table 10-8. GPIO Pins With Non-Zero Reset Values .............................................................. 688Table 10-9. GPIO Pins With Non-Zero Reset Values .............................................................. 690Table 10-10. GPIO Pins With Non-Zero Reset Values .............................................................. 693Table 10-11. GPIO Pins With Non-Zero Reset Values .............................................................. 700Table 11-1. Available CCP Pins ............................................................................................ 718Table 11-2. General-Purpose Timers Signals (100LQFP) ....................................................... 718Table 11-3. General-Purpose Timer Capabilities .................................................................... 720Table 11-4. Counter Values When the Timer is Enabled in Periodic or One-Shot Modes .......... 721Table 11-5. 16-Bit Timer With Prescaler Configurations ......................................................... 723Table 11-6. 32-Bit Timer (configured in 32/64-bit mode) With Prescaler Configurations ............ 723Table 11-7. Counter Values When the Timer is Enabled in RTC Mode .................................... 723Table 11-8. Counter Values When the Timer is Enabled in Input Edge-Count Mode ................. 725Table 11-9. Counter Values When the Timer is Enabled in Input Event-Count Mode ................ 726Table 11-10. Counter Values When the Timer is Enabled in PWM Mode ................................... 728Table 11-11. Timeout Actions for GPTM Modes ...................................................................... 731Table 11-12. Timers Register Map .......................................................................................... 738Table 12-1. Watchdog Timers Register Map .......................................................................... 789Table 13-1. ADC Signals (100LQFP) .................................................................................... 813Table 13-2. Samples and FIFO Depth of Sequencers ............................................................ 815Table 13-3. Differential Sampling Pairs ................................................................................. 822Table 13-4. ADC Register Map ............................................................................................. 830Table 14-1. UART Signals (100LQFP) .................................................................................. 912Table 14-2. Flow Control Mode ............................................................................................. 917Table 14-3. UART Register Map ........................................................................................... 921Table 15-1. SSI Signals (100LQFP) ...................................................................................... 972Table 15-2. SSI Register Map .............................................................................................. 985Table 16-1. I2C Signals (100LQFP) .................................................................................... 1015Table 16-2. Examples of I2C Master Timer Period Versus Speed Mode ................................. 1021Table 16-3. Examples of I2C Master Timer Period in High-Speed Mode ................................ 1022



Table 16-4. Inter-Integrated Circuit (I2C) Interface Register Map ........................................... 1034Table 16-5. Write Field Decoding for I2CMCS[3:0] Field ....................................................... 1040Table 17-1. Controller Area Network Signals (100LQFP) ...................................................... 1067Table 17-2. Message Object Configurations ........................................................................ 1073Table 17-3. CAN Protocol Ranges ...................................................................................... 1080Table 17-4. CANBIT Register Values .................................................................................. 1080Table 17-5. CAN Register Map ........................................................................................... 1084Table 18-1. USB Signals (100LQFP) ................................................................................... 1118Table 18-2. Remainder (MAXLOAD/4) ................................................................................ 1129Table 18-3. Actual Bytes Read ........................................................................................... 1129Table 18-4. Packet Sizes That Clear RXRDY ...................................................................... 1130Table 18-5. Universal Serial Bus (USB) Controller Register Map ........................................... 1131Table 19-1. Analog Comparators Signals (100LQFP) ........................................................... 1232Table 19-2. Internal Reference Voltage and ACREFCTL Field Values ................................... 1234Table 19-3. Analog Comparator Voltage Reference Characteristics, VDDA = 3.3V, EN= 1, and

RNG = 0 .......................................................................................................... 1235Table 19-4. Analog Comparator Voltage Reference Characteristics, VDDA = 3.3V, EN= 1, and

RNG = 1 .......................................................................................................... 1236Table 19-5. Analog Comparators Register Map ................................................................... 1237Table 20-1. PWM Signals (100LQFP) ................................................................................. 1250Table 20-2. PWM Register Map .......................................................................................... 1258Table 21-1. QEI Signals (100LQFP) .................................................................................... 1327Table 21-2. QEI Register Map ............................................................................................ 1331Table 23-1. GPIO Pins With Default Alternate Functions ...................................................... 1349Table 23-2. Signals by Pin Number ..................................................................................... 1350Table 23-3. Signals by Signal Name ................................................................................... 1361Table 23-4. Signals by Function, Except for GPIO ............................................................... 1371Table 23-5. GPIO Pins and Alternate Functions ................................................................... 1380Table 23-6. Possible Pin Assignments for Alternate Functions .............................................. 1383Table 23-7. Connections for Unused Signals (100-Pin LQFP) .............................................. 1388Table 24-1. Absolute Maximum Ratings .............................................................................. 1389Table 24-2. ESD Absolute Maximum Ratings ...................................................................... 1389Table 24-3. Temperature Characteristics ............................................................................. 1390Table 24-4. Thermal Characteristics ................................................................................... 1390Table 24-5. Recommended DC Operating Conditions .......................................................... 1391Table 24-6. Recommended GPIO Pad Operating Conditions ................................................ 1391Table 24-7. GPIO Current Restrictions ................................................................................ 1391Table 24-8. GPIO Package Side Assignments ..................................................................... 1392Table 24-9. JTAG Characteristics ....................................................................................... 1394Table 24-10. Power-On and Brown-Out Levels ...................................................................... 1396Table 24-11. Reset Characteristics ....................................................................................... 1401Table 24-12. LDO Regulator Characteristics ......................................................................... 1403Table 24-13. Phase Locked Loop (PLL) Characteristics ......................................................... 1404Table 24-14. Actual PLL Frequency ...................................................................................... 1404Table 24-15. PIOSC Clock Characteristics ............................................................................ 1405Table 24-16. Low-Frequency internal Oscillator Characteristics .............................................. 1405Table 24-17. Hibernation Oscillator Input Characteristics ........................................................ 1405Table 24-18. Main Oscillator Input Characteristics ................................................................. 1406


Table of Contents

Table 24-19. Crystal Parameters .......................................................................................... 1408Table 24-20. Supported MOSC Crystal Frequencies .............................................................. 1409Table 24-21. System Clock Characteristics with ADC Operation ............................................. 1409Table 24-22. System Clock Characteristics with USB Operation ............................................. 1410Table 24-23. Sleep Modes AC Characteristics ....................................................................... 1411Table 24-24. Time to Wake with Respect to Low-Power Modes .............................................. 1411Table 24-25. Hibernation Module Battery Characteristics ....................................................... 1413Table 24-26. Hibernation Module AC Characteristics ............................................................. 1413Table 24-27. Flash Memory Characteristics ........................................................................... 1414Table 24-28. EEPROM Characteristics ................................................................................. 1414Table 24-29. GPIO Module Characteristics ............................................................................ 1415Table 24-30. Pad Voltage/Current Characteristics for Fail-Safe Pins ....................................... 1416Table 24-31. Fail-Safe GPIOs that Require an External Pull-up .............................................. 1417Table 24-32. Non-Fail-Safe I/O Pad Voltage/Current Characteristics ....................................... 1417Table 24-33. ADC Electrical Characteristics .......................................................................... 1419Table 24-34. SSI Characteristics .......................................................................................... 1423Table 24-35. I2C Characteristics ........................................................................................... 1426Table 24-36. Analog Comparator Characteristics ................................................................... 1428Table 24-37. Analog Comparator Voltage Reference Characteristics ...................................... 1428Table 24-38. Analog Comparator Voltage Reference Characteristics, VDDA = 3.3V, EN= 1, and

RNG = 0 .......................................................................................................... 1428Table 24-39. Analog Comparator Voltage Reference Characteristics, VDDA = 3.3V, EN= 1, and

RNG = 1 .......................................................................................................... 1429Table 24-40. Current Consumption ....................................................................................... 1430Table A-1. Orderable Part Numbers .................................................................................. 1433



List of RegistersThe Cortex-M4F Processor ........................................................................................................... 68Register 1: Cortex General-Purpose Register 0 (R0) ........................................................................... 76Register 2: Cortex General-Purpose Register 1 (R1) ........................................................................... 76Register 3: Cortex General-Purpose Register 2 (R2) ........................................................................... 76Register 4: Cortex General-Purpose Register 3 (R3) ........................................................................... 76Register 5: Cortex General-Purpose Register 4 (R4) ........................................................................... 76Register 6: Cortex General-Purpose Register 5 (R5) ........................................................................... 76Register 7: Cortex General-Purpose Register 6 (R6) ........................................................................... 76Register 8: Cortex General-Purpose Register 7 (R7) ........................................................................... 76Register 9: Cortex General-Purpose Register 8 (R8) ........................................................................... 76Register 10: Cortex General-Purpose Register 9 (R9) ........................................................................... 76Register 11: Cortex General-Purpose Register 10 (R10) ....................................................................... 76Register 12: Cortex General-Purpose Register 11 (R11) ........................................................................ 76Register 13: Cortex General-Purpose Register 12 (R12) ....................................................................... 76Register 14: Stack Pointer (SP) ........................................................................................................... 77Register 15: Link Register (LR) ............................................................................................................ 78Register 16: Program Counter (PC) ..................................................................................................... 79Register 17: Program Status Register (PSR) ........................................................................................ 80Register 18: Priority Mask Register (PRIMASK) .................................................................................... 84Register 19: Fault Mask Register (FAULTMASK) .................................................................................. 85Register 20: Base Priority Mask Register (BASEPRI) ............................................................................ 86Register 21: Control Register (CONTROL) ........................................................................................... 87Register 22: Floating-Point Status Control (FPSC) ................................................................................ 89

Cortex-M4 Peripherals ................................................................................................................. 121Register 1: SysTick Control and Status Register