Identity development

Physical Layout

Gate-Level Netlist

RTL-DescriptionRTL Description

rtl_config config

Logic Synthesis

rtl2gates synth

floorplan floorplan

rtl2pg synth

rcxt spef

final_chip final_design

Pre-processing/Compiling of micro-code definitions and of Verilog files.

RTL-to-Gates synthesis flow takes a RTL HW description and a standard cell

library as input, and produces a gate-level netlist as output. The resulting gate-level

netlist is a completely structural description with only standard cells at the leaves of

the design. This step also creates a SAIF (Switching Activity Interchange Format)

forward-annotation file starting from the top level of the design.

Creates floorplan information including core size, placement sites, port locations,

RAM locations, as well as routing and placement obstructions.

RTL-to-placed-gates synthesis step capable of driving Design Compiler in

topographical mode to perform physical synthesis using floorplan physical

constraints. The design hierarchy is flattened partly to improve timing, but also to

ensure that the path to RAMs and pads is fixed to allow floorplanning scripts to

access them. At this step clock gating is applied and Power Compiler is enabled

(i.e. the max. dynamic and leakage power is set). Finally SDC (Synopsis Design

Constraint) files are post-processed for use with JupiterXT and Astro.

Astro Place&Route flow performs placement, clock tree synthesis, routing,

postrouting, and physical optimisation. Clock tree synthesis solves complicated

clock tree synthesis problems, such as blockage avoidance and the correlation

between prerouting and postrouting. Routing includes global routing, track

assignment, detail routing, and search-and-repair. After global routing, track

assignment, or detail routing, the design is optimised for timing and crosstalk.

Electric circuit extraction, also netlist extraction, is the translation of an IC layout

back into the electrical circuit (i.e. netlist) it is intended to represent. StarXtract

extracts parasitics into a centralised database so they can be used for circuit

simulation, static timing analysis, signal integrity, power analysis and optimisation,

and logic to layout comparison. Parasitic devices are devices which were not

explicitly intended by the designer but are inherent in the layout of the circuit.

SPEF: Standard Parasitic Exchange Format

Static timing analysis using PrimeTime generates static delay files for various

operating conditions. Integrated circuits exhibit different performance

characteristics for different operating conditions, fabrication process variations,

power supply voltage, and temperature.

- check_setup: gates_slow.sdf [worst op. condition]

- check_hold: gates_fast.sdf [best op. condition]

- typical: gates_typical.sdf [typical op. condition]

Defines top cell boundary, inserts all bond-pads, and inserts an instance of the final

core cell.

Design

Compiler[dc_shell-t]

JupiterXT[JupiterXT]

Astro[Astro]

StarXtract[StarXtract]

PrimeTime

STA[pt_shell]

EnCore Processor Design Flow

JupiterXT[JupiterXT]

SoC Hierarchical Design Planning

JupiterXT helps to partition the logical netlist into the best

physical hierarchy for optimised synthesis and physical

implementation.

Astro[Astro]

Physical Optimisation, Placement and Routing

Solution for SoC Designs

Numerous technology-dependent steps are required to

complete a complex, ultra-deep-submicron integrated

circuit (IC) design. Logic and interconnect delays must be

analysed and minimised. Physical effects such as signal

crosstalk, power density, and supply voltage drop must be

handled. Ideal clocks can no longer be assumed, and

clock skew must be minimized. Physical effects are

critical because changes to one may seriously impact the

optimization of others.

The Astro product is an advanced physical design system

for optimisation, placement and routing, using a

specialised architecture that concurrently accounts for

physical effects while optimizing the resulting design.

StarXtract[StarXtract]

Parasitic Extraction

With shrinking process technologies, increasing die size

and clock frequency, interconnect parasitic effects have

begun to manifest themselves in signal delay and noise.

Consequently, interconnects now play an important role in

the design flow. Today, IC design is interconnect-limited

and the design flow is interconnect-driven. Star-RCXT is a

parasitic extraction tool that models advanced process

effects and has the capacity to handle large designs with

tens of millions of transistors and cells.

PrimeTime

STA[pt_shell]

Static Timing Analysis

Timing analysis solution for gate-level designs featuring

comprehensive analysis including setup/hold/recovery,

parasitic or SDF delay annotations and many more (see

Synopsis product data sheet).

Design

Compiler[dc_shell-t]

RTL Synthesis

RTL synthesis solution that performs advanced arithmetic

optimisation, critical path synthesis, register retiming etc.

It enables a developer to optimise a design for timing,

area, power and test.

ASIC Design Flow Steps [Makefile targets] Synthesis Tool Descriptions

Floor Planning

Automatic Place & Route

init_chip chip

layout extract

layout chip

Power

Compiler

Power

Compiler

Power Optimisation & Analysis

Power Compiler performs both RTL and gate-level power

optimisation and gate-level power analysis. By applying

Power Compiler's various power reduction techniques,

including clock-gating, operand isolation, multivoltage

leakage power optimization, and gate-level power

optimization, you can achieve power savings, and area

and timing optimisation in the front-end synthesis domain.

Synthesis Tools

gdsii stream_out

Physical Verification

drc all

lvs all

package stream_out

Configures GDSII (Graphic Data System II) stream-out flow for design rule

checking and layout versus schematic verification.

Design Rule Checking determines whether a particular chip layout satisfies a

series of recommended parameters called design rules. Design rule checking is a

major step during physical verification of the design. Design Rules are a series of

parameters provided by semiconductor manufacturers that enable the designer to

verify the correctness of the mask set. Design rules are specific to a particular

semiconductor manufacturing process specifying certain geometric and

connectivity restrictions to ensure sufficient margins to account for variability in

semiconductor manufacturing processes, so as to ensure that most of the parts

work correctly.

Layout vs. Schematic is the class of electronic design automation verification

software that determines whether a particular integrated circuit layout corresponds

to the original schematic or circuit diagram of the design. LVS checking software

recognizes the drawn shapes of the layout that represent the electrical

components of the circuit, as well as the connections between them. The software

then compares them with the schematic or circuit diagram. Typical errors

encountered during LVS include: shorts, opens, component mismatches, missing

components, property errors.

Instantiates top-level package, inserts an instance of the final core cell into the

package, places point-to-point wires in the design to represent bond-wires.

Calibre[calibre]

Physical Verification

Mentor's Calibre tool is used for layout verification and

design rule checking.

Calibre[calibre]

sta check_setup

sta check_hold

sta typical

Timing Analysis

Research centre identities

Centre for Intelligent Systems& their Applications

Institute for Adaptive& Neural Computation

Institute for Communicating& Collaborative Systems

Institute for ComputingSystems Architecture

Institute of Perception,Action and Behaviour

e-Science Institute

Laboratory for Foundationsof Computer Science

Informatics Life-Sciences Institute

Performs initial virtual flat placement and then further refines and legalises the

floorplan. Power planning, virtual power network analysis, and global routing is also

performed.

Processor Automated Synthesis by iTerative Analysis Projecthttp://groups.inf.ed.ac.uk/pasta/

Tape-out

EDA Database[Synopsis Milkyway DB]

Floorplanning

GDS II OUT

RTL to Gates

Synthesis

RTL to Placed

Gates Synthesis

IC Layout

Parasitic

Extraction

Timing

Analysis

IP Libraries

VendorLibraries

RTLDatabase

Configuration

GDS II

Design Rule

Checking

Layout

vs.

Schematic

Start

EnCore - Calton Chip Layout

Tape-out

What next?

Experience of doing a PhD in Informatics

Innovative Learning Week 2013

Tobias Edler von Koch

1

Identity development

Physical Layout

Gate-Level Netlist

RTL-DescriptionRTL Description

rtl_config config

Logic Synthesis

rtl2gates synth

floorplan floorplan

rtl2pg synth

rcxt spef

final_chip final_design

Pre-processing/Compiling of micro-code definitions and of Verilog files.

RTL-to-Gates synthesis flow takes a RTL HW description and a standard cell

library as input, and produces a gate-level netlist as output. The resulting gate-level

netlist is a completely structural description with only standard cells at the leaves of

the design. This step also creates a SAIF (Switching Activity Interchange Format)

forward-annotation file starting from the top level of the design.

Creates floorplan information including core size, placement sites, port locations,

RAM locations, as well as routing and placement obstructions.

RTL-to-placed-gates synthesis step capable of driving Design Compiler in

topographical mode to perform physical synthesis using floorplan physical

constraints. The design hierarchy is flattened partly to improve timing, but also to

ensure that the path to RAMs and pads is fixed to allow floorplanning scripts to

access them. At this step clock gating is applied and Power Compiler is enabled

(i.e. the max. dynamic and leakage power is set). Finally SDC (Synopsis Design

Constraint) files are post-processed for use with JupiterXT and Astro.

Astro Place&Route flow performs placement, clock tree synthesis, routing,

postrouting, and physical optimisation. Clock tree synthesis solves complicated

clock tree synthesis problems, such as blockage avoidance and the correlation

between prerouting and postrouting. Routing includes global routing, track

assignment, detail routing, and search-and-repair. After global routing, track

assignment, or detail routing, the design is optimised for timing and crosstalk.

Electric circuit extraction, also netlist extraction, is the translation of an IC layout

back into the electrical circuit (i.e. netlist) it is intended to represent. StarXtract

extracts parasitics into a centralised database so they can be used for circuit

simulation, static timing analysis, signal integrity, power analysis and optimisation,

and logic to layout comparison. Parasitic devices are devices which were not

explicitly intended by the designer but are inherent in the layout of the circuit.

SPEF: Standard Parasitic Exchange Format

Static timing analysis using PrimeTime generates static delay files for various

operating conditions. Integrated circuits exhibit different performance

characteristics for different operating conditions, fabrication process variations,

power supply voltage, and temperature.

- check_setup: gates_slow.sdf [worst op. condition]

- check_hold: gates_fast.sdf [best op. condition]

- typical: gates_typical.sdf [typical op. condition]

Defines top cell boundary, inserts all bond-pads, and inserts an instance of the final

core cell.

Design

Compiler[dc_shell-t]

JupiterXT[JupiterXT]

Astro[Astro]

StarXtract[StarXtract]

PrimeTime

STA[pt_shell]

EnCore Processor Design Flow

JupiterXT[JupiterXT]

SoC Hierarchical Design Planning

JupiterXT helps to partition the logical netlist into the best

physical hierarchy for optimised synthesis and physical

implementation.

Astro[Astro]

Physical Optimisation, Placement and Routing

Solution for SoC Designs

Numerous technology-dependent steps are required to

complete a complex, ultra-deep-submicron integrated

circuit (IC) design. Logic and interconnect delays must be

analysed and minimised. Physical effects such as signal

crosstalk, power density, and supply voltage drop must be

handled. Ideal clocks can no longer be assumed, and

clock skew must be minimized. Physical effects are

critical because changes to one may seriously impact the

optimization of others.

The Astro product is an advanced physical design system

for optimisation, placement and routing, using a

specialised architecture that concurrently accounts for

physical effects while optimizing the resulting design.

StarXtract[StarXtract]

Parasitic Extraction

With shrinking process technologies, increasing die size

and clock frequency, interconnect parasitic effects have

begun to manifest themselves in signal delay and noise.

Consequently, interconnects now play an important role in

the design flow. Today, IC design is interconnect-limited

and the design flow is interconnect-driven. Star-RCXT is a

parasitic extraction tool that models advanced process

effects and has the capacity to handle large designs with

tens of millions of transistors and cells.

PrimeTime

STA[pt_shell]

Static Timing Analysis

Timing analysis solution for gate-level designs featuring

comprehensive analysis including setup/hold/recovery,

parasitic or SDF delay annotations and many more (see

Synopsis product data sheet).

Design

Compiler[dc_shell-t]

RTL Synthesis

RTL synthesis solution that performs advanced arithmetic

optimisation, critical path synthesis, register retiming etc.

It enables a developer to optimise a design for timing,

area, power and test.

ASIC Design Flow Steps [Makefile targets] Synthesis Tool Descriptions

Floor Planning

Automatic Place & Route

init_chip chip

layout extract

layout chip

Power

Compiler

Power

Compiler

Power Optimisation & Analysis

Power Compiler performs both RTL and gate-level power

optimisation and gate-level power analysis. By applying

Power Compiler's various power reduction techniques,

including clock-gating, operand isolation, multivoltage

leakage power optimization, and gate-level power

optimization, you can achieve power savings, and area

and timing optimisation in the front-end synthesis domain.

Synthesis Tools

gdsii stream_out

Physical Verification

drc all

lvs all

package stream_out

Configures GDSII (Graphic Data System II) stream-out flow for design rule

checking and layout versus schematic verification.

Design Rule Checking determines whether a particular chip layout satisfies a

series of recommended parameters called design rules. Design rule checking is a

major step during physical verification of the design. Design Rules are a series of

parameters provided by semiconductor manufacturers that enable the designer to

verify the correctness of the mask set. Design rules are specific to a particular

semiconductor manufacturing process specifying certain geometric and

connectivity restrictions to ensure sufficient margins to account for variability in

semiconductor manufacturing processes, so as to ensure that most of the parts

work correctly.

Layout vs. Schematic is the class of electronic design automation verification

software that determines whether a particular integrated circuit layout corresponds

to the original schematic or circuit diagram of the design. LVS checking software

recognizes the drawn shapes of the layout that represent the electrical

components of the circuit, as well as the connections between them. The software

then compares them with the schematic or circuit diagram. Typical errors

encountered during LVS include: shorts, opens, component mismatches, missing

components, property errors.

Instantiates top-level package, inserts an instance of the final core cell into the

package, places point-to-point wires in the design to represent bond-wires.

Calibre[calibre]

Physical Verification

Mentor's Calibre tool is used for layout verification and

design rule checking.

Calibre[calibre]

sta check_setup

sta check_hold

sta typical

Timing Analysis

Research centre identities

Centre for Intelligent Systems& their Applications

Institute for Adaptive& Neural Computation

Institute for Communicating& Collaborative Systems

Institute for ComputingSystems Architecture

Institute of Perception,Action and Behaviour

e-Science Institute

Laboratory for Foundationsof Computer Science

Informatics Life-Sciences Institute

Performs initial virtual flat placement and then further refines and legalises the

floorplan. Power planning, virtual power network analysis, and global routing is also

performed.

Processor Automated Synthesis by iTerative Analysis Projecthttp://groups.inf.ed.ac.uk/pasta/

Tape-out

EDA Database[Synopsis Milkyway DB]

Floorplanning

GDS II OUT

RTL to Gates

Synthesis

RTL to Placed

Gates Synthesis

IC Layout

Parasitic

Extraction

Timing

Analysis

IP Libraries

VendorLibraries

RTLDatabase

Configuration

GDS II

Design Rule

Checking

Layout

vs.

Schematic

Start

EnCore - Calton Chip Layout

Tape-out

Comic

2

2

Identity development

Physical Layout

Gate-Level Netlist

RTL-DescriptionRTL Description

rtl_config config

Logic Synthesis

rtl2gates synth

floorplan floorplan

rtl2pg synth

rcxt spef

final_chip final_design

Pre-processing/Compiling of micro-code definitions and of Verilog files.

RTL-to-Gates synthesis flow takes a RTL HW description and a standard cell

library as input, and produces a gate-level netlist as output. The resulting gate-level

netlist is a completely structural description with only standard cells at the leaves of

the design. This step also creates a SAIF (Switching Activity Interchange Format)

forward-annotation file starting from the top level of the design.

Creates floorplan information including core size, placement sites, port locations,

RAM locations, as well as routing and placement obstructions.

RTL-to-placed-gates synthesis step capable of driving Design Compiler in

topographical mode to perform physical synthesis using floorplan physical

constraints. The design hierarchy is flattened partly to improve timing, but also to

ensure that the path to RAMs and pads is fixed to allow floorplanning scripts to

access them. At this step clock gating is applied and Power Compiler is enabled

(i.e. the max. dynamic and leakage power is set). Finally SDC (Synopsis Design

Constraint) files are post-processed for use with JupiterXT and Astro.

Astro Place&Route flow performs placement, clock tree synthesis, routing,

postrouting, and physical optimisation. Clock tree synthesis solves complicated

clock tree synthesis problems, such as blockage avoidance and the correlation

between prerouting and postrouting. Routing includes global routing, track

assignment, detail routing, and search-and-repair. After global routing, track

assignment, or detail routing, the design is optimised for timing and crosstalk.

Electric circuit extraction, also netlist extraction, is the translation of an IC layout

back into the electrical circuit (i.e. netlist) it is intended to represent. StarXtract

extracts parasitics into a centralised database so they can be used for circuit

simulation, static timing analysis, signal integrity, power analysis and optimisation,

and logic to layout comparison. Parasitic devices are devices which were not

explicitly intended by the designer but are inherent in the layout of the circuit.

SPEF: Standard Parasitic Exchange Format

Static timing analysis using PrimeTime generates static delay files for various

operating conditions. Integrated circuits exhibit different performance

characteristics for different operating conditions, fabrication process variations,

power supply voltage, and temperature.

- check_setup: gates_slow.sdf [worst op. condition]

- check_hold: gates_fast.sdf [best op. condition]

- typical: gates_typical.sdf [typical op. condition]

Defines top cell boundary, inserts all bond-pads, and inserts an instance of the final

core cell.

Design

Compiler[dc_shell-t]

JupiterXT[JupiterXT]

Astro[Astro]

StarXtract[StarXtract]

PrimeTime

STA[pt_shell]

EnCore Processor Design Flow

JupiterXT[JupiterXT]

SoC Hierarchical Design Planning

JupiterXT helps to partition the logical netlist into the best

physical hierarchy for optimised synthesis and physical

implementation.

Astro[Astro]

Physical Optimisation, Placement and Routing

Solution for SoC Designs

Numerous technology-dependent steps are required to

complete a complex, ultra-deep-submicron integrated

circuit (IC) design. Logic and interconnect delays must be

analysed and minimised. Physical effects such as signal

crosstalk, power density, and supply voltage drop must be

handled. Ideal clocks can no longer be assumed, and

clock skew must be minimized. Physical effects are

critical because changes to one may seriously impact the

optimization of others.

The Astro product is an advanced physical design system

for optimisation, placement and routing, using a

specialised architecture that concurrently accounts for

physical effects while optimizing the resulting design.

StarXtract[StarXtract]

Parasitic Extraction

With shrinking process technologies, increasing die size

and clock frequency, interconnect parasitic effects have

begun to manifest themselves in signal delay and noise.

Consequently, interconnects now play an important role in

the design flow. Today, IC design is interconnect-limited

and the design flow is interconnect-driven. Star-RCXT is a

parasitic extraction tool that models advanced process

effects and has the capacity to handle large designs with

tens of millions of transistors and cells.

PrimeTime

STA[pt_shell]

Static Timing Analysis

Timing analysis solution for gate-level designs featuring

comprehensive analysis including setup/hold/recovery,

parasitic or SDF delay annotations and many more (see

Synopsis product data sheet).

Design

Compiler[dc_shell-t]

RTL Synthesis

RTL synthesis solution that performs advanced arithmetic

optimisation, critical path synthesis, register retiming etc.

It enables a developer to optimise a design for timing,

area, power and test.

ASIC Design Flow Steps [Makefile targets] Synthesis Tool Descriptions

Floor Planning

Automatic Place & Route

init_chip chip

layout extract

layout chip

Power

Compiler

Power

Compiler

Power Optimisation & Analysis

Power Compiler performs both RTL and gate-level power

optimisation and gate-level power analysis. By applying

Power Compiler's various power reduction techniques,

including clock-gating, operand isolation, multivoltage

leakage power optimization, and gate-level power

optimization, you can achieve power savings, and area

and timing optimisation in the front-end synthesis domain.

Synthesis Tools

gdsii stream_out

Physical Verification

drc all

lvs all

package stream_out

Configures GDSII (Graphic Data System II) stream-out flow for design rule

checking and layout versus schematic verification.

Design Rule Checking determines whether a particular chip layout satisfies a

series of recommended parameters called design rules. Design rule checking is a

major step during physical verification of the design. Design Rules are a series of

parameters provided by semiconductor manufacturers that enable the designer to

verify the correctness of the mask set. Design rules are specific to a particular

semiconductor manufacturing process specifying certain geometric and

connectivity restrictions to ensure sufficient margins to account for variability in

semiconductor manufacturing processes, so as to ensure that most of the parts

work correctly.

Layout vs. Schematic is the class of electronic design automation verification

software that determines whether a particular integrated circuit layout corresponds

to the original schematic or circuit diagram of the design. LVS checking software

recognizes the drawn shapes of the layout that represent the electrical

components of the circuit, as well as the connections between them. The software

then compares them with the schematic or circuit diagram. Typical errors

encountered during LVS include: shorts, opens, component mismatches, missing

components, property errors.

Instantiates top-level package, inserts an instance of the final core cell into the

package, places point-to-point wires in the design to represent bond-wires.

Calibre[calibre]

Physical Verification

Mentor's Calibre tool is used for layout verification and

design rule checking.

Calibre[calibre]

sta check_setup

sta check_hold

sta typical

Timing Analysis

Research centre identities

Centre for Intelligent Systems& their Applications

Institute for Adaptive& Neural Computation

Institute for Communicating& Collaborative Systems

Institute for ComputingSystems Architecture

Institute of Perception,Action and Behaviour

e-Science Institute

Laboratory for Foundationsof Computer Science

Informatics Life-Sciences Institute

Performs initial virtual flat placement and then further refines and legalises the

floorplan. Power planning, virtual power network analysis, and global routing is also

performed.

Processor Automated Synthesis by iTerative Analysis Projecthttp://groups.inf.ed.ac.uk/pasta/

Tape-out

EDA Database[Synopsis Milkyway DB]

Floorplanning

GDS II OUT

RTL to Gates

Synthesis

RTL to Placed

Gates Synthesis

IC Layout

Parasitic

Extraction

Timing

Analysis

IP Libraries

VendorLibraries

RTLDatabase

Configuration

GDS II

Design Rule

Checking

Layout

vs.

Schematic

Start

EnCore - Calton Chip Layout

Tape-out

What this talk isn’t about• This is not official advice from the

University of Edinburgh - all of this is my own opinion only, not that of the university or school. If you have any questions, contact the relevant departments!

• I’m focusing on the UK, specifically Informatics at the University of Edinburgh. Things are different in other countries and subjects (especially US).

3

3

Identity development

Physical Layout

Gate-Level Netlist

RTL-DescriptionRTL Description

rtl_config config

Logic Synthesis

rtl2gates synth

floorplan floorplan

rtl2pg synth

rcxt spef

final_chip final_design

Pre-processing/Compiling of micro-code definitions and of Verilog files.

RTL-to-Gates synthesis flow takes a RTL HW description and a standard cell

library as input, and produces a gate-level netlist as output. The resulting gate-level

netlist is a completely structural description with only standard cells at the leaves of

the design. This step also creates a SAIF (Switching Activity Interchange Format)

forward-annotation file starting from the top level of the design.

Creates floorplan information including core size, placement sites, port locations,

RAM locations, as well as routing and placement obstructions.

RTL-to-placed-gates synthesis step capable of driving Design Compiler in

topographical mode to perform physical synthesis using floorplan physical

constraints. The design hierarchy is flattened partly to improve timing, but also to

ensure that the path to RAMs and pads is fixed to allow floorplanning scripts to

access them. At this step clock gating is applied and Power Compiler is enabled

(i.e. the max. dynamic and leakage power is set). Finally SDC (Synopsis Design

Constraint) files are post-processed for use with JupiterXT and Astro.

Astro Place&Route flow performs placement, clock tree synthesis, routing,

postrouting, and physical optimisation. Clock tree synthesis solves complicated

clock tree synthesis problems, such as blockage avoidance and the correlation

between prerouting and postrouting. Routing includes global routing, track

assignment, detail routing, and search-and-repair. After global routing, track

assignment, or detail routing, the design is optimised for timing and crosstalk.

Electric circuit extraction, also netlist extraction, is the translation of an IC layout

back into the electrical circuit (i.e. netlist) it is intended to represent. StarXtract

extracts parasitics into a centralised database so they can be used for circuit

simulation, static timing analysis, signal integrity, power analysis and optimisation,

and logic to layout comparison. Parasitic devices are devices which were not

explicitly intended by the designer but are inherent in the layout of the circuit.

SPEF: Standard Parasitic Exchange Format

Static timing analysis using PrimeTime generates static delay files for various

operating conditions. Integrated circuits exhibit different performance

characteristics for different operating conditions, fabrication process variations,

power supply voltage, and temperature.

- check_setup: gates_slow.sdf [worst op. condition]

- check_hold: gates_fast.sdf [best op. condition]

- typical: gates_typical.sdf [typical op. condition]

Defines top cell boundary, inserts all bond-pads, and inserts an instance of the final

core cell.

Design

Compiler[dc_shell-t]

JupiterXT[JupiterXT]

Astro[Astro]

StarXtract[StarXtract]

PrimeTime

STA[pt_shell]

EnCore Processor Design Flow

JupiterXT[JupiterXT]

SoC Hierarchical Design Planning

JupiterXT helps to partition the logical netlist into the best

physical hierarchy for optimised synthesis and physical

implementation.

Astro[Astro]

Physical Optimisation, Placement and Routing

Solution for SoC Designs

Numerous technology-dependent steps are required to

complete a complex, ultra-deep-submicron integrated

circuit (IC) design. Logic and interconnect delays must be

analysed and minimised. Physical effects such as signal

crosstalk, power density, and supply voltage drop must be

handled. Ideal clocks can no longer be assumed, and

clock skew must be minimized. Physical effects are

critical because changes to one may seriously impact the

optimization of others.

The Astro product is an advanced physical design system

for optimisation, placement and routing, using a

specialised architecture that concurrently accounts for

physical effects while optimizing the resulting design.

StarXtract[StarXtract]

Parasitic Extraction

With shrinking process technologies, increasing die size

and clock frequency, interconnect parasitic effects have

begun to manifest themselves in signal delay and noise.

Consequently, interconnects now play an important role in

the design flow. Today, IC design is interconnect-limited

and the design flow is interconnect-driven. Star-RCXT is a

parasitic extraction tool that models advanced process

effects and has the capacity to handle large designs with

tens of millions of transistors and cells.

PrimeTime

STA[pt_shell]

Static Timing Analysis

Timing analysis solution for gate-level designs featuring

comprehensive analysis including setup/hold/recovery,

parasitic or SDF delay annotations and many more (see

Synopsis product data sheet).

Design

Compiler[dc_shell-t]

RTL Synthesis

RTL synthesis solution that performs advanced arithmetic

optimisation, critical path synthesis, register retiming etc.

It enables a developer to optimise a design for timing,

area, power and test.

ASIC Design Flow Steps [Makefile targets] Synthesis Tool Descriptions

Floor Planning

Automatic Place & Route

init_chip chip

layout extract

layout chip

Power

Compiler

Power

Compiler

Power Optimisation & Analysis

Power Compiler performs both RTL and gate-level power

optimisation and gate-level power analysis. By applying

Power Compiler's various power reduction techniques,

including clock-gating, operand isolation, multivoltage

leakage power optimization, and gate-level power

optimization, you can achieve power savings, and area

and timing optimisation in the front-end synthesis domain.

Synthesis Tools

gdsii stream_out

Physical Verification

drc all

lvs all

package stream_out

Configures GDSII (Graphic Data System II) stream-out flow for design rule

checking and layout versus schematic verification.

Design Rule Checking determines whether a particular chip layout satisfies a

series of recommended parameters called design rules. Design rule checking is a

major step during physical verification of the design. Design Rules are a series of

parameters provided by semiconductor manufacturers that enable the designer to

verify the correctness of the mask set. Design rules are specific to a particular

semiconductor manufacturing process specifying certain geometric and

connectivity restrictions to ensure sufficient margins to account for variability in

semiconductor manufacturing processes, so as to ensure that most of the parts

work correctly.

Layout vs. Schematic is the class of electronic design automation verification

software that determines whether a particular integrated circuit layout corresponds

to the original schematic or circuit diagram of the design. LVS checking software

recognizes the drawn shapes of the layout that represent the electrical

components of the circuit, as well as the connections between them. The software

then compares them with the schematic or circuit diagram. Typical errors

encountered during LVS include: shorts, opens, component mismatches, missing

components, property errors.

Instantiates top-level package, inserts an instance of the final core cell into the

package, places point-to-point wires in the design to represent bond-wires.

Calibre[calibre]

Physical Verification

Mentor's Calibre tool is used for layout verification and

design rule checking.

Calibre[calibre]

sta check_setup

sta check_hold

sta typical

Timing Analysis

Research centre identities

Centre for Intelligent Systems& their Applications

Institute for Adaptive& Neural Computation

Institute for Communicating& Collaborative Systems

Institute for ComputingSystems Architecture

Institute of Perception,Action and Behaviour

e-Science Institute

Laboratory for Foundationsof Computer Science

Informatics Life-Sciences Institute

Performs initial virtual flat placement and then further refines and legalises the

floorplan. Power planning, virtual power network analysis, and global routing is also

performed.

Processor Automated Synthesis by iTerative Analysis Projecthttp://groups.inf.ed.ac.uk/pasta/

Tape-out

EDA Database[Synopsis Milkyway DB]

Floorplanning

GDS II OUT

RTL to Gates

Synthesis

RTL to Placed

Gates Synthesis

IC Layout

Parasitic

Extraction

Timing

Analysis

IP Libraries

VendorLibraries

RTLDatabase

Configuration

GDS II

Design Rule

Checking

Layout

vs.

Schematic

Start

EnCore - Calton Chip Layout

Tape-out

What this talk is about

• Is a PhD the right thing for me?

• How do I apply?

• What do PhDs actually do?

• Career options

• A little bit about my own research

4

4

Identity development

Physical Layout

Gate-Level Netlist

RTL-DescriptionRTL Description

rtl_config config

Logic Synthesis

rtl2gates synth

floorplan floorplan

rtl2pg synth

rcxt spef

final_chip final_design

Pre-processing/Compiling of micro-code definitions and of Verilog files.

RTL-to-Gates synthesis flow takes a RTL HW description and a standard cell

library as input, and produces a gate-level netlist as output. The resulting gate-level

netlist is a completely structural description with only standard cells at the leaves of

the design. This step also creates a SAIF (Switching Activity Interchange Format)

forward-annotation file starting from the top level of the design.

Creates floorplan information including core size, placement sites, port locations,

RAM locations, as well as routing and placement obstructions.

RTL-to-placed-gates synthesis step capable of driving Design Compiler in

topographical mode to perform physical synthesis using floorplan physical

constraints. The design hierarchy is flattened partly to improve timing, but also to

ensure that the path to RAMs and pads is fixed to allow floorplanning scripts to

access them. At this step clock gating is applied and Power Compiler is enabled

(i.e. the max. dynamic and leakage power is set). Finally SDC (Synopsis Design

Constraint) files are post-processed for use with JupiterXT and Astro.

Astro Place&Route flow performs placement, clock tree synthesis, routing,

postrouting, and physical optimisation. Clock tree synthesis solves complicated

clock tree synthesis problems, such as blockage avoidance and the correlation

between prerouting and postrouting. Routing includes global routing, track

assignment, detail routing, and search-and-repair. After global routing, track

assignment, or detail routing, the design is optimised for timing and crosstalk.

Electric circuit extraction, also netlist extraction, is the translation of an IC layout

back into the electrical circuit (i.e. netlist) it is intended to represent. StarXtract

extracts parasitics into a centralised database so they can be used for circuit

simulation, static timing analysis, signal integrity, power analysis and optimisation,

and logic to layout comparison. Parasitic devices are devices which were not

explicitly intended by the designer but are inherent in the layout of the circuit.

SPEF: Standard Parasitic Exchange Format

Static timing analysis using PrimeTime generates static delay files for various

operating conditions. Integrated circuits exhibit different performance

characteristics for different operating conditions, fabrication process variations,

power supply voltage, and temperature.

- check_setup: gates_slow.sdf [worst op. condition]

- check_hold: gates_fast.sdf [best op. condition]

- typical: gates_typical.sdf [typical op. condition]

Defines top cell boundary, inserts all bond-pads, and inserts an instance of the final

core cell.

Design

Compiler[dc_shell-t]

JupiterXT[JupiterXT]

Astro[Astro]

StarXtract[StarXtract]

PrimeTime

STA[pt_shell]

EnCore Processor Design Flow

JupiterXT[JupiterXT]

SoC Hierarchical Design Planning

JupiterXT helps to partition the logical netlist into the best

physical hierarchy for optimised synthesis and physical

implementation.

Astro[Astro]

Physical Optimisation, Placement and Routing

Solution for SoC Designs

Numerous technology-dependent steps are required to

complete a complex, ultra-deep-submicron integrated

circuit (IC) design. Logic and interconnect delays must be

analysed and minimised. Physical effects such as signal

crosstalk, power density, and supply voltage drop must be

handled. Ideal clocks can no longer be assumed, and

clock skew must be minimized. Physical effects are

critical because changes to one may seriously impact the

optimization of others.

The Astro product is an advanced physical design system

for optimisation, placement and routing, using a

specialised architecture that concurrently accounts for

physical effects while optimizing the resulting design.

StarXtract[StarXtract]

Parasitic Extraction

With shrinking process technologies, increasing die size

and clock frequency, interconnect parasitic effects have

begun to manifest themselves in signal delay and noise.

Consequently, interconnects now play an important role in

the design flow. Today, IC design is interconnect-limited

and the design flow is interconnect-driven. Star-RCXT is a

parasitic extraction tool that models advanced process

effects and has the capacity to handle large designs with

tens of millions of transistors and cells.

PrimeTime

STA[pt_shell]

Static Timing Analysis

Timing analysis solution for gate-level designs featuring

comprehensive analysis including setup/hold/recovery,

parasitic or SDF delay annotations and many more (see

Synopsis product data sheet).

Design

Compiler[dc_shell-t]

RTL Synthesis

RTL synthesis solution that performs advanced arithmetic

optimisation, critical path synthesis, register retiming etc.

It enables a developer to optimise a design for timing,

area, power and test.

ASIC Design Flow Steps [Makefile targets] Synthesis Tool Descriptions

Floor Planning

Automatic Place & Route

init_chip chip

layout extract

layout chip

Power

Compiler

Power

Compiler

Power Optimisation & Analysis

Power Compiler performs both RTL and gate-level power

optimisation and gate-level power analysis. By applying

Power Compiler's various power reduction techniques,

including clock-gating, operand isolation, multivoltage

leakage power optimization, and gate-level power

optimization, you can achieve power savings, and area

and timing optimisation in the front-end synthesis domain.

Synthesis Tools

gdsii stream_out

Physical Verification

drc all

lvs all

package stream_out

Configures GDSII (Graphic Data System II) stream-out flow for design rule

checking and layout versus schematic verification.

Design Rule Checking determines whether a particular chip layout satisfies a

series of recommended parameters called design rules. Design rule checking is a

major step during physical verification of the design. Design Rules are a series of

parameters provided by semiconductor manufacturers that enable the designer to

verify the correctness of the mask set. Design rules are specific to a particular

semiconductor manufacturing process specifying certain geometric and

connectivity restrictions to ensure sufficient margins to account for variability in

semiconductor manufacturing processes, so as to ensure that most of the parts

work correctly.

Layout vs. Schematic is the class of electronic design automation verification

software that determines whether a particular integrated circuit layout corresponds

to the original schematic or circuit diagram of the design. LVS checking software

recognizes the drawn shapes of the layout that represent the electrical

components of the circuit, as well as the connections between them. The software

then compares them with the schematic or circuit diagram. Typical errors

encountered during LVS include: shorts, opens, component mismatches, missing

components, property errors.

Instantiates top-level package, inserts an instance of the final core cell into the

package, places point-to-point wires in the design to represent bond-wires.

Calibre[calibre]

Physical Verification

Mentor's Calibre tool is used for layout verification and

design rule checking.

Calibre[calibre]

sta check_setup

sta check_hold

sta typical

Timing Analysis

Research centre identities

Centre for Intelligent Systems& their Applications

Institute for Adaptive& Neural Computation

Institute for Communicating& Collaborative Systems

Institute for ComputingSystems Architecture

Institute of Perception,Action and Behaviour

e-Science Institute

Laboratory for Foundationsof Computer Science

Informatics Life-Sciences Institute

Performs initial virtual flat placement and then further refines and legalises the

floorplan. Power planning, virtual power network analysis, and global routing is also

performed.

Processor Automated Synthesis by iTerative Analysis Projecthttp://groups.inf.ed.ac.uk/pasta/

Tape-out

EDA Database[Synopsis Milkyway DB]

Floorplanning

GDS II OUT

RTL to Gates

Synthesis

RTL to Placed

Gates Synthesis

IC Layout

Parasitic

Extraction

Timing

Analysis

IP Libraries

VendorLibraries

RTLDatabase

Configuration

GDS II

Design Rule

Checking

Layout

vs.

Schematic

Start

EnCore - Calton Chip Layout

Tape-out

Quick show of hands

5

5

Identity development

Physical Layout

Gate-Level Netlist

RTL-DescriptionRTL Description

rtl_config config

Logic Synthesis

rtl2gates synth

floorplan floorplan

rtl2pg synth

rcxt spef

final_chip final_design

Pre-processing/Compiling of micro-code definitions and of Verilog files.

RTL-to-Gates synthesis flow takes a RTL HW description and a standard cell

library as input, and produces a gate-level netlist as output. The resulting gate-level

netlist is a completely structural description with only standard cells at the leaves of

the design. This step also creates a SAIF (Switching Activity Interchange Format)

forward-annotation file starting from the top level of the design.

Creates floorplan information including core size, placement sites, port locations,

RAM locations, as well as routing and placement obstructions.

RTL-to-placed-gates synthesis step capable of driving Design Compiler in

topographical mode to perform physical synthesis using floorplan physical

constraints. The design hierarchy is flattened partly to improve timing, but also to

ensure that the path to RAMs and pads is fixed to allow floorplanning scripts to

access them. At this step clock gating is applied and Power Compiler is enabled

(i.e. the max. dynamic and leakage power is set). Finally SDC (Synopsis Design

Constraint) files are post-processed for use with JupiterXT and Astro.

Astro Place&Route flow performs placement, clock tree synthesis, routing,

postrouting, and physical optimisation. Clock tree synthesis solves complicated

clock tree synthesis problems, such as blockage avoidance and the correlation

between prerouting and postrouting. Routing includes global routing, track

assignment, detail routing, and search-and-repair. After global routing, track

assignment, or detail routing, the design is optimised for timing and crosstalk.

Electric circuit extraction, also netlist extraction, is the translation of an IC layout

back into the electrical circuit (i.e. netlist) it is intended to represent. StarXtract

extracts parasitics into a centralised database so they can be used for circuit

simulation, static timing analysis, signal integrity, power analysis and optimisation,

and logic to layout comparison. Parasitic devices are devices which were not

explicitly intended by the designer but are inherent in the layout of the circuit.

SPEF: Standard Parasitic Exchange Format

Static timing analysis using PrimeTime generates static delay files for various

operating conditions. Integrated circuits exhibit different performance

characteristics for different operating conditions, fabrication process variations,

power supply voltage, and temperature.

- check_setup: gates_slow.sdf [worst op. condition]

- check_hold: gates_fast.sdf [best op. condition]

- typical: gates_typical.sdf [typical op. condition]

Defines top cell boundary, inserts all bond-pads, and inserts an instance of the final

core cell.

Design

Compiler[dc_shell-t]

JupiterXT[JupiterXT]

Astro[Astro]

StarXtract[StarXtract]

PrimeTime

STA[pt_shell]

EnCore Processor Design Flow

JupiterXT[JupiterXT]

SoC Hierarchical Design Planning

JupiterXT helps to partition the logical netlist into the best

physical hierarchy for optimised synthesis and physical

implementation.

Astro[Astro]

Physical Optimisation, Placement and Routing

Solution for SoC Designs

Numerous technology-dependent steps are required to

complete a complex, ultra-deep-submicron integrated

circuit (IC) design. Logic and interconnect delays must be

analysed and minimised. Physical effects such as signal

crosstalk, power density, and supply voltage drop must be

handled. Ideal clocks can no longer be assumed, and

clock skew must be minimized. Physical effects are

critical because changes to one may seriously impact the

optimization of others.

The Astro product is an advanced physical design system

for optimisation, placement and routing, using a

specialised architecture that concurrently accounts for

physical effects while optimizing the resulting design.

StarXtract[StarXtract]

Parasitic Extraction

With shrinking process technologies, increasing die size

and clock frequency, interconnect parasitic effects have

begun to manifest themselves in signal delay and noise.

Consequently, interconnects now play an important role in

the design flow. Today, IC design is interconnect-limited

and the design flow is interconnect-driven. Star-RCXT is a

parasitic extraction tool that models advanced process

effects and has the capacity to handle large designs with

tens of millions of transistors and cells.

PrimeTime

STA[pt_shell]

Static Timing Analysis

Timing analysis solution for gate-level designs featuring

comprehensive analysis including setup/hold/recovery,

parasitic or SDF delay annotations and many more (see

Synopsis product data sheet).

Design

Compiler[dc_shell-t]

RTL Synthesis

RTL synthesis solution that performs advanced arithmetic

optimisation, critical path synthesis, register retiming etc.

It enables a developer to optimise a design for timing,

area, power and test.

ASIC Design Flow Steps [Makefile targets] Synthesis Tool Descriptions

Floor Planning

Automatic Place & Route

init_chip chip

layout extract

layout chip

Power

Compiler

Power

Compiler

Power Optimisation & Analysis

Power Compiler performs both RTL and gate-level power

optimisation and gate-level power analysis. By applying

Power Compiler's various power reduction techniques,

including clock-gating, operand isolation, multivoltage

leakage power optimization, and gate-level power

optimization, you can achieve power savings, and area

and timing optimisation in the front-end synthesis domain.

Synthesis Tools

gdsii stream_out

Physical Verification

drc all

lvs all

package stream_out

Configures GDSII (Graphic Data System II) stream-out flow for design rule

checking and layout versus schematic verification.

Design Rule Checking determines whether a particular chip layout satisfies a

series of recommended parameters called design rules. Design rule checking is a

major step during physical verification of the design. Design Rules are a series of

parameters provided by semiconductor manufacturers that enable the designer to

verify the correctness of the mask set. Design rules are specific to a particular

semiconductor manufacturing process specifying certain geometric and

connectivity restrictions to ensure sufficient margins to account for variability in

semiconductor manufacturing processes, so as to ensure that most of the parts

work correctly.

Layout vs. Schematic is the class of electronic design automation verification

software that determines whether a particular integrated circuit layout corresponds

to the original schematic or circuit diagram of the design. LVS checking software

recognizes the drawn shapes of the layout that represent the electrical

components of the circuit, as well as the connections between them. The software

then compares them with the schematic or circuit diagram. Typical errors

encountered during LVS include: shorts, opens, component mismatches, missing

components, property errors.

Instantiates top-level package, inserts an instance of the final core cell into the

package, places point-to-point wires in the design to represent bond-wires.

Calibre[calibre]

Physical Verification

Mentor's Calibre tool is used for layout verification and

design rule checking.

Calibre[calibre]

sta check_setup

sta check_hold

sta typical

Timing Analysis

Research centre identities

Centre for Intelligent Systems& their Applications

Institute for Adaptive& Neural Computation

Institute for Communicating& Collaborative Systems

Institute for ComputingSystems Architecture

Institute of Perception,Action and Behaviour

e-Science Institute

Laboratory for Foundationsof Computer Science

Informatics Life-Sciences Institute

Performs initial virtual flat placement and then further refines and legalises the

floorplan. Power planning, virtual power network analysis, and global routing is also

performed.

Processor Automated Synthesis by iTerative Analysis Projecthttp://groups.inf.ed.ac.uk/pasta/

Tape-out

EDA Database[Synopsis Milkyway DB]

Floorplanning

GDS II OUT

RTL to Gates

Synthesis

RTL to Placed

Gates Synthesis

IC Layout

Parasitic

Extraction

Timing

Analysis

IP Libraries

VendorLibraries

RTLDatabase

Configuration

GDS II

Design Rule

Checking

Layout

vs.

Schematic

Start

EnCore - Calton Chip Layout

Tape-out

Quick show of hands

• Undergraduates

5

5

Identity development

Physical Layout

Gate-Level Netlist

RTL-DescriptionRTL Description

rtl_config config

Logic Synthesis

rtl2gates synth

floorplan floorplan

rtl2pg synth

rcxt spef

final_chip final_design

Pre-processing/Compiling of micro-code definitions and of Verilog files.

RTL-to-Gates synthesis flow takes a RTL HW description and a standard cell

library as input, and produces a gate-level netlist as output. The resulting gate-level

netlist is a completely structural description with only standard cells at the leaves of

the design. This step also creates a SAIF (Switching Activity Interchange Format)

forward-annotation file starting from the top level of the design.

Creates floorplan information including core size, placement sites, port locations,

RAM locations, as well as routing and placement obstructions.

RTL-to-placed-gates synthesis step capable of driving Design Compiler in

topographical mode to perform physical synthesis using floorplan physical

constraints. The design hierarchy is flattened partly to improve timing, but also to

ensure that the path to RAMs and pads is fixed to allow floorplanning scripts to

access them. At this step clock gating is applied and Power Compiler is enabled

(i.e. the max. dynamic and leakage power is set). Finally SDC (Synopsis Design

Constraint) files are post-processed for use with JupiterXT and Astro.

Astro Place&Route flow performs placement, clock tree synthesis, routing,

postrouting, and physical optimisation. Clock tree synthesis solves complicated

clock tree synthesis problems, such as blockage avoidance and the correlation

between prerouting and postrouting. Routing includes global routing, track

assignment, detail routing, and search-and-repair. After global routing, track

assignment, or detail routing, the design is optimised for timing and crosstalk.

Electric circuit extraction, also netlist extraction, is the translation of an IC layout

back into the electrical circuit (i.e. netlist) it is intended to represent. StarXtract

extracts parasitics into a centralised database so they can be used for circuit

simulation, static timing analysis, signal integrity, power analysis and optimisation,

and logic to layout comparison. Parasitic devices are devices which were not

explicitly intended by the designer but are inherent in the layout of the circuit.

SPEF: Standard Parasitic Exchange Format

Static timing analysis using PrimeTime generates static delay files for various

operating conditions. Integrated circuits exhibit different performance

characteristics for different operating conditions, fabrication process variations,

power supply voltage, and temperature.

- check_setup: gates_slow.sdf [worst op. condition]

- check_hold: gates_fast.sdf [best op. condition]

- typical: gates_typical.sdf [typical op. condition]

Defines top cell boundary, inserts all bond-pads, and inserts an instance of the final

core cell.

Design

Compiler[dc_shell-t]

JupiterXT[JupiterXT]

Astro[Astro]

StarXtract[StarXtract]

PrimeTime

STA[pt_shell]

EnCore Processor Design Flow

JupiterXT[JupiterXT]

SoC Hierarchical Design Planning

JupiterXT helps to partition the logical netlist into the best

physical hierarchy for optimised synthesis and physical

implementation.

Astro[Astro]

Physical Optimisation, Placement and Routing

Solution for SoC Designs

Numerous technology-dependent steps are required to

complete a complex, ultra-deep-submicron integrated

circuit (IC) design. Logic and interconnect delays must be

analysed and minimised. Physical effects such as signal

crosstalk, power density, and supply voltage drop must be

handled. Ideal clocks can no longer be assumed, and

clock skew must be minimized. Physical effects are

critical because changes to one may seriously impact the

optimization of others.

The Astro product is an advanced physical design system

for optimisation, placement and routing, using a

specialised architecture that concurrently accounts for

physical effects while optimizing the resulting design.

StarXtract[StarXtract]

Parasitic Extraction

With shrinking process technologies, increasing die size

and clock frequency, interconnect parasitic effects have

begun to manifest themselves in signal delay and noise.

Consequently, interconnects now play an important role in

the design flow. Today, IC design is interconnect-limited

and the design flow is interconnect-driven. Star-RCXT is a

parasitic extraction tool that models advanced process

effects and has the capacity to handle large designs with

tens of millions of transistors and cells.

PrimeTime

STA[pt_shell]

Static Timing Analysis

Timing analysis solution for gate-level designs featuring

comprehensive analysis including setup/hold/recovery,

parasitic or SDF delay annotations and many more (see

Synopsis product data sheet).

Design

Compiler[dc_shell-t]

RTL Synthesis

RTL synthesis solution that performs advanced arithmetic

optimisation, critical path synthesis, register retiming etc.

It enables a developer to optimise a design for timing,

area, power and test.

ASIC Design Flow Steps [Makefile targets] Synthesis Tool Descriptions

Floor Planning

Automatic Place & Route

init_chip chip

layout extract

layout chip

Power

Compiler

Power

Compiler

Power Optimisation & Analysis

Power Compiler performs both RTL and gate-level power

optimisation and gate-level power analysis. By applying

Power Compiler's various power reduction techniques,

including clock-gating, operand isolation, multivoltage

leakage power optimization, and gate-level power

optimization, you can achieve power savings, and area

and timing optimisation in the front-end synthesis domain.

Synthesis Tools

gdsii stream_out

Physical Verification

drc all

lvs all

package stream_out

Configures GDSII (Graphic Data System II) stream-out flow for design rule

checking and layout versus schematic verification.

Design Rule Checking determines whether a particular chip layout satisfies a

series of recommended parameters called design rules. Design rule checking is a

major step during physical verification of the design. Design Rules are a series of

parameters provided by semiconductor manufacturers that enable the designer to

verify the correctness of the mask set. Design rules are specific to a particular

semiconductor manufacturing process specifying certain geometric and

connectivity restrictions to ensure sufficient margins to account for variability in

semiconductor manufacturing processes, so as to ensure that most of the parts

work correctly.

Layout vs. Schematic is the class of electronic design automation verification

software that determines whether a particular integrated circuit layout corresponds

to the original schematic or circuit diagram of the design. LVS checking software

recognizes the drawn shapes of the layout that represent the electrical

components of the circuit, as well as the connections between them. The software

then compares them with the schematic or circuit diagram. Typical errors

encountered during LVS include: shorts, opens, component mismatches, missing

components, property errors.

Instantiates top-level package, inserts an instance of the final core cell into the

package, places point-to-point wires in the design to represent bond-wires.

Calibre[calibre]

Physical Verification

Mentor's Calibre tool is used for layout verification and

design rule checking.

Calibre[calibre]

sta check_setup

sta check_hold

sta typical

Timing Analysis

Research centre identities

Centre for Intelligent Systems& their Applications

Institute for Adaptive& Neural Computation

Institute for Communicating& Collaborative Systems

Institute for ComputingSystems Architecture

Institute of Perception,Action and Behaviour

e-Science Institute

Laboratory for Foundationsof Computer Science

Informatics Life-Sciences Institute

Performs initial virtual flat placement and then further refines and legalises the

floorplan. Power planning, virtual power network analysis, and global routing is also

performed.

Processor Automated Synthesis by iTerative Analysis Projecthttp://groups.inf.ed.ac.uk/pasta/

Tape-out

EDA Database[Synopsis Milkyway DB]

Floorplanning

GDS II OUT

RTL to Gates

Synthesis

RTL to Placed

Gates Synthesis

IC Layout

Parasitic

Extraction

Timing

Analysis

IP Libraries

VendorLibraries

RTLDatabase

Configuration

GDS II

Design Rule

Checking

Layout

vs.

Schematic

Start

EnCore - Calton Chip Layout

Tape-out

Quick show of hands

• Undergraduates

• (Taught) MSc students

5

5

Identity development

Physical Layout

Gate-Level Netlist

RTL-DescriptionRTL Description

rtl_config config

Logic Synthesis

rtl2gates synth

floorplan floorplan

rtl2pg synth

rcxt spef

final_chip final_design

Pre-processing/Compiling of micro-code definitions and of Verilog files.

RTL-to-Gates synthesis flow takes a RTL HW description and a standard cell

library as input, and produces a gate-level netlist as output. The resulting gate-level

netlist is a completely structural description with only standard cells at the leaves of

the design. This step also creates a SAIF (Switching Activity Interchange Format)

forward-annotation file starting from the top level of the design.

Creates floorplan information including core size, placement sites, port locations,

RAM locations, as well as routing and placement obstructions.

RTL-to-placed-gates synthesis step capable of driving Design Compiler in

topographical mode to perform physical synthesis using floorplan physical

constraints. The design hierarchy is flattened partly to improve timing, but also to

ensure that the path to RAMs and pads is fixed to allow floorplanning scripts to

access them. At this step clock gating is applied and Power Compiler is enabled

(i.e. the max. dynamic and leakage power is set). Finally SDC (Synopsis Design

Constraint) files are post-processed for use with JupiterXT and Astro.

Astro Place&Route flow performs placement, clock tree synthesis, routing,

postrouting, and physical optimisation. Clock tree synthesis solves complicated

clock tree synthesis problems, such as blockage avoidance and the correlation

between prerouting and postrouting. Routing includes global routing, track

assignment, detail routing, and search-and-repair. After global routing, track

assignment, or detail routing, the design is optimised for timing and crosstalk.

Electric circuit extraction, also netlist extraction, is the translation of an IC layout

back into the electrical circuit (i.e. netlist) it is intended to represent. StarXtract

extracts parasitics into a centralised database so they can be used for circuit

simulation, static timing analysis, signal integrity, power analysis and optimisation,

and logic to layout comparison. Parasitic devices are devices which were not

explicitly intended by the designer but are inherent in the layout of the circuit.

SPEF: Standard Parasitic Exchange Format

Static timing analysis using PrimeTime generates static delay files for various

operating conditions. Integrated circuits exhibit different performance

characteristics for different operating conditions, fabrication process variations,

power supply voltage, and temperature.

- check_setup: gates_slow.sdf [worst op. condition]

- check_hold: gates_fast.sdf [best op. condition]

- typical: gates_typical.sdf [typical op. condition]

Defines top cell boundary, inserts all bond-pads, and inserts an instance of the final

core cell.

Design

Compiler[dc_shell-t]

JupiterXT[JupiterXT]

Astro[Astro]

StarXtract[StarXtract]

PrimeTime

STA[pt_shell]

EnCore Processor Design Flow

JupiterXT[JupiterXT]

SoC Hierarchical Design Planning

JupiterXT helps to partition the logical netlist into the best

physical hierarchy for optimised synthesis and physical

implementation.

Astro[Astro]

Physical Optimisation, Placement and Routing

Solution for SoC Designs

Numerous technology-dependent steps are required to

complete a complex, ultra-deep-submicron integrated

circuit (IC) design. Logic and interconnect delays must be

analysed and minimised. Physical effects such as signal

crosstalk, power density, and supply voltage drop must be

handled. Ideal clocks can no longer be assumed, and

clock skew must be minimized. Physical effects are

critical because changes to one may seriously impact the

optimization of others.

The Astro product is an advanced physical design system

for optimisation, placement and routing, using a

specialised architecture that concurrently accounts for

physical effects while optimizing the resulting design.

StarXtract[StarXtract]

Parasitic Extraction

With shrinking process technologies, increasing die size

and clock frequency, interconnect parasitic effects have

begun to manifest themselves in signal delay and noise.

Consequently, interconnects now play an important role in

the design flow. Today, IC design is interconnect-limited

and the design flow is interconnect-driven. Star-RCXT is a

parasitic extraction tool that models advanced process

effects and has the capacity to handle large designs with

tens of millions of transistors and cells.

PrimeTime

STA[pt_shell]

Static Timing Analysis

Timing analysis solution for gate-level designs featuring

comprehensive analysis including setup/hold/recovery,

parasitic or SDF delay annotations and many more (see

Synopsis product data sheet).

Design

Compiler[dc_shell-t]

RTL Synthesis

RTL synthesis solution that performs advanced arithmetic

optimisation, critical path synthesis, register retiming etc.

It enables a developer to optimise a design for timing,

area, power and test.

ASIC Design Flow Steps [Makefile targets] Synthesis Tool Descriptions

Floor Planning

Automatic Place & Route

init_chip chip

layout extract

layout chip

Power

Compiler

Power

Compiler

Power Optimisation & Analysis

Power Compiler performs both RTL and gate-level power

optimisation and gate-level power analysis. By applying

Power Compiler's various power reduction techniques,

including clock-gating, operand isolation, multivoltage

leakage power optimization, and gate-level power

optimization, you can achieve power savings, and area

and timing optimisation in the front-end synthesis domain.

Synthesis Tools

gdsii stream_out

Physical Verification

drc all

lvs all

package stream_out

Configures GDSII (Graphic Data System II) stream-out flow for design rule

checking and layout versus schematic verification.

Design Rule Checking determines whether a particular chip layout satisfies a

series of recommended parameters called design rules. Design rule checking is a

major step during physical verification of the design. Design Rules are a series of

parameters provided by semiconductor manufacturers that enable the designer to

verify the correctness of the mask set. Design rules are specific to a particular

semiconductor manufacturing process specifying certain geometric and

connectivity restrictions to ensure sufficient margins to account for variability in

semiconductor manufacturing processes, so as to ensure that most of the parts

work correctly.

Layout vs. Schematic is the class of electronic design automation verification

software that determines whether a particular integrated circuit layout corresponds

to the original schematic or circuit diagram of the design. LVS checking software

recognizes the drawn shapes of the layout that represent the electrical

components of the circuit, as well as the connections between them. The software

then compares them with the schematic or circuit diagram. Typical errors

encountered during LVS include: shorts, opens, component mismatches, missing

components, property errors.

Instantiates top-level package, inserts an instance of the final core cell into the

package, places point-to-point wires in the design to represent bond-wires.

Calibre[calibre]

Physical Verification

Mentor's Calibre tool is used for layout verification and

design rule checking.

Calibre[calibre]

sta check_setup

sta check_hold

sta typical

Timing Analysis

Research centre identities

Centre for Intelligent Systems& their Applications

Institute for Adaptive& Neural Computation

Institute for Communicating& Collaborative Systems

Institute for ComputingSystems Architecture

Institute of Perception,Action and Behaviour

e-Science Institute

Laboratory for Foundationsof Computer Science

Informatics Life-Sciences Institute

Performs initial virtual flat placement and then further refines and legalises the

floorplan. Power planning, virtual power network analysis, and global routing is also

performed.

Processor Automated Synthesis by iTerative Analysis Projecthttp://groups.inf.ed.ac.uk/pasta/

Tape-out

EDA Database[Synopsis Milkyway DB]

Floorplanning

GDS II OUT

RTL to Gates

Synthesis

RTL to Placed

Gates Synthesis

IC Layout

Parasitic

Extraction

Timing

Analysis

IP Libraries

VendorLibraries

RTLDatabase

Configuration

GDS II

Design Rule

Checking

Layout

vs.

Schematic

Start

EnCore - Calton Chip Layout

Tape-out

Quick show of hands

• Undergraduates

• (Taught) MSc students

• Consider PhD as an option in the future

5

5

Identity development

Physical Layout

Gate-Level Netlist

RTL-DescriptionRTL Description

rtl_config config

Logic Synthesis

rtl2gates synth

floorplan floorplan

rtl2pg synth

rcxt spef

final_chip final_design

Pre-processing/Compiling of micro-code definitions and of Verilog files.

RTL-to-Gates synthesis flow takes a RTL HW description and a standard cell

library as input, and produces a gate-level netlist as output. The resulting gate-level

netlist is a completely structural description with only standard cells at the leaves of

the design. This step also creates a SAIF (Switching Activity Interchange Format)

forward-annotation file starting from the top level of the design.

Creates floorplan information including core size, placement sites, port locations,

RAM locations, as well as routing and placement obstructions.

RTL-to-placed-gates synthesis step capable of driving Design Compiler in

topographical mode to perform physical synthesis using floorplan physical

constraints. The design hierarchy is flattened partly to improve timing, but also to

ensure that the path to RAMs and pads is fixed to allow floorplanning scripts to

access them. At this step clock gating is applied and Power Compiler is enabled

(i.e. the max. dynamic and leakage power is set). Finally SDC (Synopsis Design

Constraint) files are post-processed for use with JupiterXT and Astro.

Astro Place&Route flow performs placement, clock tree synthesis, routing,

postrouting, and physical optimisation. Clock tree synthesis solves complicated

clock tree synthesis problems, such as blockage avoidance and the correlation

between prerouting and postrouting. Routing includes global routing, track

assignment, detail routing, and search-and-repair. After global routing, track

assignment, or detail routing, the design is optimised for timing and crosstalk.

Electric circuit extraction, also netlist extraction, is the translation of an IC layout

back into the electrical circuit (i.e. netlist) it is intended to represent. StarXtract

extracts parasitics into a centralised database so they can be used for circuit

simulation, static timing analysis, signal integrity, power analysis and optimisation,

and logic to layout comparison. Parasitic devices are devices which were not

explicitly intended by the designer but are inherent in the layout of the circuit.

SPEF: Standard Parasitic Exchange Format

Static timing analysis using PrimeTime generates static delay files for various

operating conditions. Integrated circuits exhibit different performance

characteristics for different operating conditions, fabrication process variations,

power supply voltage, and temperature.

- check_setup: gates_slow.sdf [worst op. condition]

- check_hold: gates_fast.sdf [best op. condition]

- typical: gates_typical.sdf [typical op. condition]

Defines top cell boundary, inserts all bond-pads, and inserts an instance of the final

core cell.

Design

Compiler[dc_shell-t]

JupiterXT[JupiterXT]

Astro[Astro]

StarXtract[StarXtract]

PrimeTime

STA[pt_shell]

EnCore Processor Design Flow

JupiterXT[JupiterXT]

SoC Hierarchical Design Planning

JupiterXT helps to partition the logical netlist into the best

physical hierarchy for optimised synthesis and physical

implementation.

Astro[Astro]

Physical Optimisation, Placement and Routing

Solution for SoC Designs

Numerous technology-dependent steps are required to

complete a complex, ultra-deep-submicron integrated

circuit (IC) design. Logic and interconnect delays must be

analysed and minimised. Physical effects such as signal

crosstalk, power density, and supply voltage drop must be

handled. Ideal clocks can no longer be assumed, and

clock skew must be minimized. Physical effects are

critical because changes to one may seriously impact the

optimization of others.

The Astro product is an advanced physical design system

for optimisation, placement and routing, using a

specialised architecture that concurrently accounts for

physical effects while optimizing the resulting design.

StarXtract[StarXtract]

Parasitic Extraction

With shrinking process technologies, increasing die size

and clock frequency, interconnect parasitic effects have

begun to manifest themselves in signal delay and noise.

Consequently, interconnects now play an important role in

the design flow. Today, IC design is interconnect-limited

and the design flow is interconnect-driven. Star-RCXT is a

parasitic extraction tool that models advanced process

effects and has the capacity to handle large designs with

tens of millions of transistors and cells.

PrimeTime

STA[pt_shell]

Static Timing Analysis

Timing analysis solution for gate-level designs featuring

comprehensive analysis including setup/hold/recovery,

parasitic or SDF delay annotations and many more (see

Synopsis product data sheet).

Design

Compiler[dc_shell-t]

RTL Synthesis

RTL synthesis solution that performs advanced arithmetic

optimisation, critical path synthesis, register retiming etc.

It enables a developer to optimise a design for timing,

area, power and test.

ASIC Design Flow Steps [Makefile targets] Synthesis Tool Descriptions

Floor Planning

Automatic Place & Route

init_chip chip

layout extract

layout chip

Power

Compiler

Power

Compiler

Power Optimisation & Analysis

Power Compiler performs both RTL and gate-level power

optimisation and gate-level power analysis. By applying

Power Compiler's various power reduction techniques,

including clock-gating, operand isolation, multivoltage

leakage power optimization, and gate-level power

optimization, you can achieve power savings, and area

and timing optimisation in the front-end synthesis domain.

Synthesis Tools

gdsii stream_out

Physical Verification

drc all

lvs all

package stream_out

Configures GDSII (Graphic Data System II) stream-out flow for design rule

checking and layout versus schematic verification.

Design Rule Checking determines whether a particular chip layout satisfies a

series of recommended parameters called design rules. Design rule checking is a

major step during physical verification of the design. Design Rules are a series of

parameters provided by semiconductor manufacturers that enable the designer to

verify the correctness of the mask set. Design rules are specific to a particular

semiconductor manufacturing process specifying certain geometric and

connectivity restrictions to ensure sufficient margins to account for variability in

semiconductor manufacturing processes, so as to ensure that most of the parts

work correctly.

Layout vs. Schematic is the class of electronic design automation verification

software that determines whether a particular integrated circuit layout corresponds

to the original schematic or circuit diagram of the design. LVS checking software

recognizes the drawn shapes of the layout that represent the electrical

components of the circuit, as well as the connections between them. The software

then compares them with the schematic or circuit diagram. Typical errors

encountered during LVS include: shorts, opens, component mismatches, missing

components, property errors.

Instantiates top-level package, inserts an instance of the final core cell into the

package, places point-to-point wires in the design to represent bond-wires.

Calibre[calibre]

Physical Verification

Mentor's Calibre tool is used for layout verification and

design rule checking.

Calibre[calibre]

sta check_setup

sta check_hold

sta typical

Timing Analysis

Research centre identities

Centre for Intelligent Systems& their Applications

Institute for Adaptive& Neural Computation

Institute for Communicating& Collaborative Systems

Institute for ComputingSystems Architecture

Institute of Perception,Action and Behaviour

e-Science Institute

Laboratory for Foundationsof Computer Science

Informatics Life-Sciences Institute

Performs initial virtual flat placement and then further refines and legalises the

floorplan. Power planning, virtual power network analysis, and global routing is also

performed.

Processor Automated Synthesis by iTerative Analysis Projecthttp://groups.inf.ed.ac.uk/pasta/

Tape-out

EDA Database[Synopsis Milkyway DB]

Floorplanning

GDS II OUT

RTL to Gates

Synthesis

RTL to Placed

Gates Synthesis

IC Layout

Parasitic

Extraction

Timing

Analysis

IP Libraries

VendorLibraries

RTLDatabase

Configuration

GDS II

Design Rule

Checking

Layout

vs.

Schematic

Start

EnCore - Calton Chip Layout

Tape-out

Is a PhD the right thing for me?

• Think about why you’re interested in it

6

6

Identity development

Physical Layout

Gate-Level Netlist

RTL-DescriptionRTL Description

rtl_config config

Logic Synthesis

rtl2gates synth

floorplan floorplan

rtl2pg synth

rcxt spef

final_chip final_design

Pre-processing/Compiling of micro-code definitions and of Verilog files.

RTL-to-Gates synthesis flow takes a RTL HW description and a standard cell

library as input, and produces a gate-level netlist as output. The resulting gate-level

netlist is a completely structural description with only standard cells at the leaves of

the design. This step also creates a SAIF (Switching Activity Interchange Format)

forward-annotation file starting from the top level of the design.

Creates floorplan information including core size, placement sites, port locations,

RAM locations, as well as routing and placement obstructions.

RTL-to-placed-gates synthesis step capable of driving Design Compiler in

topographical mode to perform physical synthesis using floorplan physical

constraints. The design hierarchy is flattened partly to improve timing, but also to

ensure that the path to RAMs and pads is fixed to allow floorplanning scripts to

access them. At this step clock gating is applied and Power Compiler is enabled

(i.e. the max. dynamic and leakage power is set). Finally SDC (Synopsis Design

Constraint) files are post-processed for use with JupiterXT and Astro.

Astro Place&Route flow performs placement, clock tree synthesis, routing,

postrouting, and physical optimisation. Clock tree synthesis solves complicated

clock tree synthesis problems, such as blockage avoidance and the correlation

between prerouting and postrouting. Routing includes global routing, track

assignment, detail routing, and search-and-repair. After global routing, track

assignment, or detail routing, the design is optimised for timing and crosstalk.

Electric circuit extraction, also netlist extraction, is the translation of an IC layout

back into the electrical circuit (i.e. netlist) it is intended to represent. StarXtract

extracts parasitics into a centralised database so they can be used for circuit

simulation, static timing analysis, signal integrity, power analysis and optimisation,

and logic to layout comparison. Parasitic devices are devices which were not

explicitly intended by the designer but are inherent in the layout of the circuit.

SPEF: Standard Parasitic Exchange Format

Static timing analysis using PrimeTime generates static delay files for various

operating conditions. Integrated circuits exhibit different performance

characteristics for different operating conditions, fabrication process variations,

power supply voltage, and temperature.

- check_setup: gates_slow.sdf [worst op. condition]

- check_hold: gates_fast.sdf [best op. condition]

- typical: gates_typical.sdf [typical op. condition]

Defines top cell boundary, inserts all bond-pads, and inserts an instance of the final

core cell.

Design

Compiler[dc_shell-t]

JupiterXT[JupiterXT]

Astro[Astro]

StarXtract[StarXtract]

PrimeTime

STA[pt_shell]

EnCore Processor Design Flow

JupiterXT[JupiterXT]

SoC Hierarchical Design Planning

JupiterXT helps to partition the logical netlist into the best

physical hierarchy for optimised synthesis and physical

implementation.

Astro[Astro]

Physical Optimisation, Placement and Routing

Solution for SoC Designs

Numerous technology-dependent steps are required to

complete a complex, ultra-deep-submicron integrated

circuit (IC) design. Logic and interconnect delays must be

analysed and minimised. Physical effects such as signal

crosstalk, power density, and supply voltage drop must be

handled. Ideal clocks can no longer be assumed, and

clock skew must be minimized. Physical effects are

critical because changes to one may seriously impact the

optimization of others.

The Astro product is an advanced physical design system

for optimisation, placement and routing, using a

specialised architecture that concurrently accounts for

physical effects while optimizing the resulting design.

StarXtract[StarXtract]

Parasitic Extraction

With shrinking process technologies, increasing die size

and clock frequency, interconnect parasitic effects have

begun to manifest themselves in signal delay and noise.

Consequently, interconnects now play an important role in

the design flow. Today, IC design is interconnect-limited

and the design flow is interconnect-driven. Star-RCXT is a

parasitic extraction tool that models advanced process

effects and has the capacity to handle large designs with

tens of millions of transistors and cells.

PrimeTime

STA[pt_shell]

Static Timing Analysis

Timing analysis solution for gate-level designs featuring

comprehensive analysis including setup/hold/recovery,

parasitic or SDF delay annotations and many more (see

Synopsis product data sheet).

Design

Compiler[dc_shell-t]

RTL Synthesis

RTL synthesis solution that performs advanced arithmetic

optimisation, critical path synthesis, register retiming etc.

It enables a developer to optimise a design for timing,

area, power and test.

ASIC Design Flow Steps [Makefile targets] Synthesis Tool Descriptions

Floor Planning

Automatic Place & Route

init_chip chip

layout extract

layout chip

Power

Compiler

Power

Compiler

Power Optimisation & Analysis

Power Compiler performs both RTL and gate-level power

optimisation and gate-level power analysis. By applying

Power Compiler's various power reduction techniques,

including clock-gating, operand isolation, multivoltage

leakage power optimization, and gate-level power

optimization, you can achieve power savings, and area

and timing optimisation in the front-end synthesis domain.

Synthesis Tools

gdsii stream_out

Physical Verification

drc all

lvs all

package stream_out

Configures GDSII (Graphic Data System II) stream-out flow for design rule

checking and layout versus schematic verification.

Design Rule Checking determines whether a particular chip layout satisfies a

series of recommended parameters called design rules. Design rule checking is a

major step during physical verification of the design. Design Rules are a series of

parameters provided by semiconductor manufacturers that enable the designer to

verify the correctness of the mask set. Design rules are specific to a particular

semiconductor manufacturing process specifying certain geometric and

connectivity restrictions to ensure sufficient margins to account for variability in

semiconductor manufacturing processes, so as to ensure that most of the parts

work correctly.

Layout vs. Schematic is the class of electronic design automation verification

software that determines whether a particular integrated circuit layout corresponds

to the original schematic or circuit diagram of the design. LVS checking software

recognizes the drawn shapes of the layout that represent the electrical

components of the circuit, as well as the connections between them. The software

then compares them with the schematic or circuit diagram. Typical errors

encountered during LVS include: shorts, opens, component mismatches, missing

components, property errors.

Instantiates top-level package, inserts an instance of the final core cell into the

package, places point-to-point wires in the design to represent bond-wires.

Calibre[calibre]

Physical Verification

Mentor's Calibre tool is used for layout verification and

design rule checking.

Calibre[calibre]

sta check_setup

sta check_hold

sta typical

Timing Analysis

Research centre identities

Centre for Intelligent Systems& their Applications

Institute for Adaptive& Neural Computation

Institute for Communicating& Collaborative Systems

Institute for ComputingSystems Architecture

Institute of Perception,Action and Behaviour

e-Science Institute

Laboratory for Foundationsof Computer Science

Informatics Life-Sciences Institute

Performs initial virtual flat placement and then further refines and legalises the

floorplan. Power planning, virtual power network analysis, and global routing is also

performed.

Processor Automated Synthesis by iTerative Analysis Projecthttp://groups.inf.ed.ac.uk/pasta/

Tape-out

EDA Database[Synopsis Milkyway DB]

Floorplanning

GDS II OUT

RTL to Gates

Synthesis

RTL to Placed

Gates Synthesis

IC Layout

Parasitic

Extraction

Timing

Analysis

IP Libraries

VendorLibraries

RTLDatabase

Configuration

GDS II

Design Rule

Checking

Layout

vs.

Schematic

Start

EnCore - Calton Chip Layout

Tape-out

Bad motivations

• Don’t know what to do after I graduate … go travel, volunteer, or work instead!

• Want to make lots of £££ … work, start your own business instead!

• Want to revolutionise the world … sorry, but you probably won’t!

7

7

Identity development

Physical Layout

Gate-Level Netlist

RTL-DescriptionRTL Description

rtl_config config

Logic Synthesis

rtl2gates synth

floorplan floorplan

rtl2pg synth

rcxt spef

final_chip final_design

Pre-processing/Compiling of micro-code definitions and of Verilog files.

RTL-to-Gates synthesis flow takes a RTL HW description and a standard cell

library as input, and produces a gate-level netlist as output. The resulting gate-level

netlist is a completely structural description with only standard cells at the leaves of

the design. This step also creates a SAIF (Switching Activity Interchange Format)

forward-annotation file starting from the top level of the design.

Creates floorplan information including core size, placement sites, port locations,

RAM locations, as well as routing and placement obstructions.

RTL-to-placed-gates synthesis step capable of driving Design Compiler in

topographical mode to perform physical synthesis using floorplan physical

constraints. The design hierarchy is flattened partly to improve timing, but also to

ensure that the path to RAMs and pads is fixed to allow floorplanning scripts to

access them. At this step clock gating is applied and Power Compiler is enabled

(i.e. the max. dynamic and leakage power is set). Finally SDC (Synopsis Design

Constraint) files are post-processed for use with JupiterXT and Astro.

Astro Place&Route flow performs placement, clock tree synthesis, routing,

postrouting, and physical optimisation. Clock tree synthesis solves complicated

clock tree synthesis problems, such as blockage avoidance and the correlation

between prerouting and postrouting. Routing includes global routing, track

assignment, detail routing, and search-and-repair. After global routing, track

assignment, or detail routing, the design is optimised for timing and crosstalk.

Electric circuit extraction, also netlist extraction, is the translation of an IC layout

back into the electrical circuit (i.e. netlist) it is intended to represent. StarXtract

extracts parasitics into a centralised database so they can be used for circuit

simulation, static timing analysis, signal integrity, power analysis and optimisation,

and logic to layout comparison. Parasitic devices are devices which were not

explicitly intended by the designer but are inherent in the layout of the circuit.

SPEF: Standard Parasitic Exchange Format

Static timing analysis using PrimeTime generates static delay files for various

operating conditions. Integrated circuits exhibit different performance

characteristics for different operating conditions, fabrication process variations,

power supply voltage, and temperature.

- check_setup: gates_slow.sdf [worst op. condition]

- check_hold: gates_fast.sdf [best op. condition]

- typical: gates_typical.sdf [typical op. condition]

Defines top cell boundary, inserts all bond-pads, and inserts an instance of the final

core cell.

Design

Compiler[dc_shell-t]

JupiterXT[JupiterXT]

Astro[Astro]

StarXtract[StarXtract]

PrimeTime

STA[pt_shell]

EnCore Processor Design Flow

JupiterXT[JupiterXT]

SoC Hierarchical Design Planning

JupiterXT helps to partition the logical netlist into the best

physical hierarchy for optimised synthesis and physical

implementation.

Astro[Astro]

Physical Optimisation, Placement and Routing

Solution for SoC Designs

Numerous technology-dependent steps are required to

complete a complex, ultra-deep-submicron integrated

circuit (IC) design. Logic and interconnect delays must be

analysed and minimised. Physical effects such as signal

crosstalk, power density, and supply voltage drop must be

handled. Ideal clocks can no longer be assumed, and

clock skew must be minimized. Physical effects are

critical because changes to one may seriously impact the

optimization of others.

The Astro product is an advanced physical design system

for optimisation, placement and routing, using a

specialised architecture that concurrently accounts for

physical effects while optimizing the resulting design.

StarXtract[StarXtract]

Parasitic Extraction

With shrinking process technologies, increasing die size

and clock frequency, interconnect parasitic effects have

begun to manifest themselves in signal delay and noise.

Consequently, interconnects now play an important role in

the design flow. Today, IC design is interconnect-limited

and the design flow is interconnect-driven. Star-RCXT is a

parasitic extraction tool that models advanced process

effects and has the capacity to handle large designs with

tens of millions of transistors and cells.

PrimeTime

STA[pt_shell]

Static Timing Analysis

Timing analysis solution for gate-level designs featuring

comprehensive analysis including setup/hold/recovery,

parasitic or SDF delay annotations and many more (see

Synopsis product data sheet).

Design

Compiler[dc_shell-t]

RTL Synthesis

RTL synthesis solution that performs advanced arithmetic

optimisation, critical path synthesis, register retiming etc.

It enables a developer to optimise a design for timing,

area, power and test.

ASIC Design Flow Steps [Makefile targets] Synthesis Tool Descriptions

Floor Planning

Automatic Place & Route

init_chip chip

layout extract

layout chip

Power

Compiler

Power

Compiler

Power Optimisation & Analysis

Power Compiler performs both RTL and gate-level power

optimisation and gate-level power analysis. By applying

Power Compiler's various power reduction techniques,

including clock-gating, operand isolation, multivoltage

leakage power optimization, and gate-level power

optimization, you can achieve power savings, and area

and timing optimisation in the front-end synthesis domain.

Synthesis Tools

gdsii stream_out

Physical Verification

drc all

lvs all

package stream_out

Configures GDSII (Graphic Data System II) stream-out flow for design rule

checking and layout versus schematic verification.

Design Rule Checking determines whether a particular chip layout satisfies a

series of recommended parameters called design rules. Design rule checking is a

major step during physical verification of the design. Design Rules are a series of

parameters provided by semiconductor manufacturers that enable the designer to

verify the correctness of the mask set. Design rules are specific to a particular

semiconductor manufacturing process specifying certain geometric and

connectivity restrictions to ensure sufficient margins to account for variability in

semiconductor manufacturing processes, so as to ensure that most of the parts

work correctly.

Layout vs. Schematic is the class of electronic design automation verification

software that determines whether a particular integrated circuit layout corresponds

to the original schematic or circuit diagram of the design. LVS checking software

recognizes the drawn shapes of the layout that represent the electrical

components of the circuit, as well as the connections between them. The software

then compares them with the schematic or circuit diagram. Typical errors

encountered during LVS include: shorts, opens, component mismatches, missing

components, property errors.

Instantiates top-level package, inserts an instance of the final core cell into the

package, places point-to-point wires in the design to represent bond-wires.

Calibre[calibre]

Physical Verification

Mentor's Calibre tool is used for layout verification and

design rule checking.

Calibre[calibre]

sta check_setup

sta check_hold

sta typical

Timing Analysis

Research centre identities

Centre for Intelligent Systems& their Applications

Institute for Adaptive& Neural Computation

Institute for Communicating& Collaborative Systems

Institute for ComputingSystems Architecture

Institute of Perception,Action and Behaviour

e-Science Institute

Laboratory for Foundationsof Computer Science

Informatics Life-Sciences Institute

Performs initial virtual flat placement and then further refines and legalises the

floorplan. Power planning, virtual power network analysis, and global routing is also

performed.

Processor Automated Synthesis by iTerative Analysis Projecthttp://groups.inf.ed.ac.uk/pasta/

Tape-out

EDA Database[Synopsis Milkyway DB]

Floorplanning

GDS II OUT

RTL to Gates

Synthesis

RTL to Placed

Gates Synthesis

IC Layout

Parasitic

Extraction

Timing

Analysis

IP Libraries

VendorLibraries

RTLDatabase

Configuration

GDS II

Design Rule

Checking

Layout

vs.

Schematic

Start

EnCore - Calton Chip Layout

Tape-out

Good motivations

• You want to learn lots of new stuff … even if it’s hard and nobody teaches you

• Want to collaborate with leading scientists … and don’t mind asking questions

• Work on some challenging problems in your field

8

8

Identity development

Physical Layout

Gate-Level Netlist

RTL-DescriptionRTL Description

rtl_config config

Logic Synthesis

rtl2gates synth

floorplan floorplan

rtl2pg synth

rcxt spef

final_chip final_design

Pre-processing/Compiling of micro-code definitions and of Verilog files.

RTL-to-Gates synthesis flow takes a RTL HW description and a standard cell

library as input, and produces a gate-level netlist as output. The resulting gate-level

netlist is a completely structural description with only standard cells at the leaves of

the design. This step also creates a SAIF (Switching Activity Interchange Format)

forward-annotation file starting from the top level of the design.

Creates floorplan information including core size, placement sites, port locations,

RAM locations, as well as routing and placement obstructions.

RTL-to-placed-gates synthesis step capable of driving Design Compiler in

topographical mode to perform physical synthesis using floorplan physical

constraints. The design hierarchy is flattened partly to improve timing, but also to

ensure that the path to RAMs and pads is fixed to allow floorplanning scripts to

access them. At this step clock gating is applied and Power Compiler is enabled

(i.e. the max. dynamic and leakage power is set). Finally SDC (Synopsis Design

Constraint) files are post-processed for use with JupiterXT and Astro.

Astro Place&Route flow performs placement, clock tree synthesis, routing,

postrouting, and physical optimisation. Clock tree synthesis solves complicated

clock tree synthesis problems, such as blockage avoidance and the correlation

between prerouting and postrouting. Routing includes global routing, track

assignment, detail routing, and search-and-repair. After global routing, track

assignment, or detail routing, the design is optimised for timing and crosstalk.

Electric circuit extraction, also netlist extraction, is the translation of an IC layout

back into the electrical circuit (i.e. netlist) it is intended to represent. StarXtract

extracts parasitics into a centralised database so they can be used for circuit

simulation, static timing analysis, signal integrity, power analysis and optimisation,

and logic to layout comparison. Parasitic devices are devices which were not

explicitly intended by the designer but are inherent in the layout of the circuit.

SPEF: Standard Parasitic Exchange Format

Static timing analysis using PrimeTime generates static delay files for various

operating conditions. Integrated circuits exhibit different performance

characteristics for different operating conditions, fabrication process variations,

power supply voltage, and temperature.

- check_setup: gates_slow.sdf [worst op. condition]

- check_hold: gates_fast.sdf [best op. condition]

- typical: gates_typical.sdf [typical op. condition]

Defines top cell boundary, inserts all bond-pads, and inserts an instance of the final

core cell.

Design

Compiler[dc_shell-t]

JupiterXT[JupiterXT]

Astro[Astro]

StarXtract[StarXtract]

PrimeTime

STA[pt_shell]

EnCore Processor Design Flow

JupiterXT[JupiterXT]

SoC Hierarchical Design Planning

JupiterXT helps to partition the logical netlist into the best

physical hierarchy for optimised synthesis and physical

implementation.

Astro[Astro]

Physical Optimisation, Placement and Routing

Solution for SoC Designs

Numerous technology-dependent steps are required to

complete a complex, ultra-deep-submicron integrated

circuit (IC) design. Logic and interconnect delays must be

analysed and minimised. Physical effects such as signal

crosstalk, power density, and supply voltage drop must be

handled. Ideal clocks can no longer be assumed, and

clock skew must be minimized. Physical effects are

critical because changes to one may seriously impact the

optimization of others.

The Astro product is an advanced physical design system

for optimisation, placement and routing, using a

specialised architecture that concurrently accounts for

physical effects while optimizing the resulting design.

StarXtract[StarXtract]

Parasitic Extraction

With shrinking process technologies, increasing die size

and clock frequency, interconnect parasitic effects have

begun to manifest themselves in signal delay and noise.

Consequently, interconnects now play an important role in

the design flow. Today, IC design is interconnect-limited

and the design flow is interconnect-driven. Star-RCXT is a

parasitic extraction tool that models advanced process

effects and has the capacity to handle large designs with

tens of millions of transistors and cells.

PrimeTime

STA[pt_shell]

Static Timing Analysis

Timing analysis solution for gate-level designs featuring

comprehensive analysis including setup/hold/recovery,

parasitic or SDF delay annotations and many more (see

Synopsis product data sheet).

Design

Compiler[dc_shell-t]

RTL Synthesis

RTL synthesis solution that performs advanced arithmetic

optimisation, critical path synthesis, register retiming etc.

It enables a developer to optimise a design for timing,

area, power and test.

ASIC Design Flow Steps [Makefile targets] Synthesis Tool Descriptions

Floor Planning

Automatic Place & Route

init_chip chip

layout extract

layout chip

Power

Compiler

Power

Compiler

Power Optimisation & Analysis

Power Compiler performs both RTL and gate-level power

optimisation and gate-level power analysis. By applying

Power Compiler's various power reduction techniques,

including clock-gating, operand isolation, multivoltage

leakage power optimization, and gate-level power

optimization, you can achieve power savings, and area

and timing optimisation in the front-end synthesis domain.

Synthesis Tools

gdsii stream_out

Physical Verification

drc all

lvs all

package stream_out

Configures GDSII (Graphic Data System II) stream-out flow for design rule

checking and layout versus schematic verification.

Design Rule Checking determines whether a particular chip layout satisfies a

series of recommended parameters called design rules. Design rule checking is a

major step during physical verification of the design. Design Rules are a series of

parameters provided by semiconductor manufacturers that enable the designer to

verify the correctness of the mask set. Design rules are specific to a particular

semiconductor manufacturing process specifying certain geometric and

connectivity restrictions to ensure sufficient margins to account for variability in

semiconductor manufacturing processes, so as to ensure that most of the parts

work correctly.

Layout vs. Schematic is the class of electronic design automation verification

software that determines whether a particular integrated circuit layout corresponds

to the original schematic or circuit diagram of the design. LVS checking software

recognizes the drawn shapes of the layout that represent the electrical

components of the circuit, as well as the connections between them. The software

then compares them with the schematic or circuit diagram. Typical errors

encountered during LVS include: shorts, opens, component mismatches, missing

components, property errors.

Instantiates top-level package, inserts an instance of the final core cell into the

package, places point-to-point wires in the design to represent bond-wires.

Calibre[calibre]

Physical Verification

Mentor's Calibre tool is used for layout verification and

design rule checking.

Calibre[calibre]

sta check_setup

sta check_hold

sta typical

Timing Analysis

Research centre identities

Centre for Intelligent Systems& their Applications

Institute for Adaptive& Neural Computation

Institute for Communicating& Collaborative Systems

Institute for ComputingSystems Architecture

Institute of Perception,Action and Behaviour

e-Science Institute

Laboratory for Foundationsof Computer Science

Informatics Life-Sciences Institute

Performs initial virtual flat placement and then further refines and legalises the

floorplan. Power planning, virtual power network analysis, and global routing is also

performed.

Processor Automated Synthesis by iTerative Analysis Projecthttp://groups.inf.ed.ac.uk/pasta/

Tape-out

EDA Database[Synopsis Milkyway DB]

Floorplanning

GDS II OUT

RTL to Gates

Synthesis

RTL to Placed

Gates Synthesis

IC Layout

Parasitic

Extraction

Timing

Analysis

IP Libraries

VendorLibraries

RTLDatabase

Configuration

GDS II

Design Rule

Checking

Layout

vs.

Schematic

Start

EnCore - Calton Chip Layout

Tape-out

You should be• Self-motivating

• Independent but willing to collaborate

• Patient. Very patient.

• Excited about your field

• Have a 2:1 or First class honours degree (MSc not necessary!)

• But… nobody’s perfect!

9

9

Identity development

Physical Layout

Gate-Level Netlist

RTL-DescriptionRTL Description

rtl_config config

Logic Synthesis

rtl2gates synth

floorplan floorplan

rtl2pg synth

rcxt spef

final_chip final_design

Pre-processing/Compiling of micro-code definitions and of Verilog files.

RTL-to-Gates synthesis flow takes a RTL HW description and a standard cell

library as input, and produces a gate-level netlist as output. The resulting gate-level

netlist is a completely structural description with only standard cells at the leaves of

the design. This step also creates a SAIF (Switching Activity Interchange Format)

forward-annotation file starting from the top level of the design.

Creates floorplan information including core size, placement sites, port locations,

RAM locations, as well as routing and placement obstructions.

RTL-to-placed-gates synthesis step capable of driving Design Compiler in

topographical mode to perform physical synthesis using floorplan physical

constraints. The design hierarchy is flattened partly to improve timing, but also to

ensure that the path to RAMs and pads is fixed to allow floorplanning scripts to

access them. At this step clock gating is applied and Power Compiler is enabled

(i.e. the max. dynamic and leakage power is set). Finally SDC (Synopsis Design

Constraint) files are post-processed for use with JupiterXT and Astro.

Astro Place&Route flow performs placement, clock tree synthesis, routing,

postrouting, and physical optimisation. Clock tree synthesis solves complicated

clock tree synthesis problems, such as blockage avoidance and the correlation

between prerouting and postrouting. Routing includes global routing, track

assignment, detail routing, and search-and-repair. After global routing, track

assignment, or detail routing, the design is optimised for timing and crosstalk.

Electric circuit extraction, also netlist extraction, is the translation of an IC layout

back into the electrical circuit (i.e. netlist) it is intended to represent. StarXtract

extracts parasitics into a centralised database so they can be used for circuit

simulation, static timing analysis, signal integrity, power analysis and optimisation,

and logic to layout comparison. Parasitic devices are devices which were not

explicitly intended by the designer but are inherent in the layout of the circuit.

SPEF: Standard Parasitic Exchange Format

Static timing analysis using PrimeTime generates static delay files for various

operating conditions. Integrated circuits exhibit different performance

characteristics for different operating conditions, fabrication process variations,

power supply voltage, and temperature.

- check_setup: gates_slow.sdf [worst op. condition]

- check_hold: gates_fast.sdf [best op. condition]

- typical: gates_typical.sdf [typical op. condition]

Defines top cell boundary, inserts all bond-pads, and inserts an instance of the final

core cell.

Design

Compiler[dc_shell-t]

JupiterXT[JupiterXT]

Astro[Astro]

StarXtract[StarXtract]

PrimeTime

STA[pt_shell]

EnCore Processor Design Flow

JupiterXT[JupiterXT]

SoC Hierarchical Design Planning

JupiterXT helps to partition the logical netlist into the best

physical hierarchy for optimised synthesis and physical

implementation.

Astro[Astro]

Physical Optimisation, Placement and Routing

Solution for SoC Designs

Numerous technology-dependent steps are required to

complete a complex, ultra-deep-submicron integrated

circuit (IC) design. Logic and interconnect delays must be

analysed and minimised. Physical effects such as signal

crosstalk, power density, and supply voltage drop must be

handled. Ideal clocks can no longer be assumed, and

clock skew must be minimized. Physical effects are

critical because changes to one may seriously impact the

optimization of others.

The Astro product is an advanced physical design system

for optimisation, placement and routing, using a

specialised architecture that concurrently accounts for

physical effects while optimizing the resulting design.

StarXtract[StarXtract]

Parasitic Extraction

With shrinking process technologies, increasing die size

and clock frequency, interconnect parasitic effects have

begun to manifest themselves in signal delay and noise.

Consequently, interconnects now play an important role in

the design flow. Today, IC design is interconnect-limited

and the design flow is interconnect-driven. Star-RCXT is a

parasitic extraction tool that models advanced process

effects and has the capacity to handle large designs with

tens of millions of transistors and cells.

PrimeTime

STA[pt_shell]

Static Timing Analysis

Timing analysis solution for gate-level designs featuring

comprehensive analysis including setup/hold/recovery,

parasitic or SDF delay annotations and many more (see

Synopsis product data sheet).

Design

Compiler[dc_shell-t]

RTL Synthesis

RTL synthesis solution that performs advanced arithmetic

optimisation, critical path synthesis, register retiming etc.

It enables a developer to optimise a design for timing,

area, power and test.

ASIC Design Flow Steps [Makefile targets] Synthesis Tool Descriptions

Floor Planning

Automatic Place & Route

init_chip chip

layout extract

layout chip

Power

Compiler

Power

Compiler

Power Optimisation & Analysis

Power Compiler performs both RTL and gate-level power

optimisation and gate-level power analysis. By applying

Power Compiler's various power reduction techniques,

including clock-gating, operand isolation, multivoltage

leakage power optimization, and gate-level power

optimization, you can achieve power savings, and area

and timing optimisation in the front-end synthesis domain.

Synthesis Tools

gdsii stream_out

Physical Verification

drc all

lvs all

package stream_out

Configures GDSII (Graphic Data System II) stream-out flow for design rule

checking and layout versus schematic verification.

Design Rule Checking determines whether a particular chip layout satisfies a

series of recommended parameters called design rules. Design rule checking is a

major step during physical verification of the design. Design Rules are a series of

parameters provided by semiconductor manufacturers that enable the designer to

verify the correctness of the mask set. Design rules are specific to a particular

semiconductor manufacturing process specifying certain geometric and

connectivity restrictions to ensure sufficient margins to account for variability in

semiconductor manufacturing processes, so as to ensure that most of the parts

work correctly.

Layout vs. Schematic is the class of electronic design automation verification

software that determines whether a particular integrated circuit layout corresponds

to the original schematic or circuit diagram of the design. LVS checking software

recognizes the drawn shapes of the layout that represent the electrical

components of the circuit, as well as the connections between them. The software

then compares them with the schematic or circuit diagram. Typical errors

encountered during LVS include: shorts, opens, component mismatches, missing

components, property errors.

Instantiates top-level package, inserts an instance of the final core cell into the

package, places point-to-point wires in the design to represent bond-wires.

Calibre[calibre]

Physical Verification

Mentor's Calibre tool is used for layout verification and

design rule checking.

Calibre[calibre]

sta check_setup

sta check_hold

sta typical

Timing Analysis

Research centre identities

Centre for Intelligent Systems& their Applications

Institute for Adaptive& Neural Computation

Institute for Communicating& Collaborative Systems

Institute for ComputingSystems Architecture

Institute of Perception,Action and Behaviour

e-Science Institute

Laboratory for Foundationsof Computer Science

Informatics Life-Sciences Institute

Performs initial virtual flat placement and then further refines and legalises the

floorplan. Power planning, virtual power network analysis, and global routing is also

performed.

Processor Automated Synthesis by iTerative Analysis Projecthttp://groups.inf.ed.ac.uk/pasta/

Tape-out

EDA Database[Synopsis Milkyway DB]

Floorplanning

GDS II OUT

RTL to Gates

Synthesis

RTL to Placed

Gates Synthesis

IC Layout

Parasitic

Extraction

Timing

Analysis

IP Libraries

VendorLibraries

RTLDatabase

Configuration

GDS II

Design Rule

Checking

Layout

vs.

Schematic

Start

EnCore - Calton Chip Layout

Tape-out

10

10

Identity development

Physical Layout

Gate-Level Netlist

RTL-DescriptionRTL Description

rtl_config config

Logic Synthesis

rtl2gates synth

floorplan floorplan

rtl2pg synth

rcxt spef

final_chip final_design

Pre-processing/Compiling of micro-code definitions and of Verilog files.

RTL-to-Gates synthesis flow takes a RTL HW description and a standard cell

library as input, and produces a gate-level netlist as output. The resulting gate-level

netlist is a completely structural description with only standard cells at the leaves of

the design. This step also creates a SAIF (Switching Activity Interchange Format)

forward-annotation file starting from the top level of the design.

Creates floorplan information including core size, placement sites, port locations,

RAM locations, as well as routing and placement obstructions.

RTL-to-placed-gates synthesis step capable of driving Design Compiler in

topographical mode to perform physical synthesis using floorplan physical

constraints. The design hierarchy is flattened partly to improve timing, but also to

ensure that the path to RAMs and pads is fixed to allow floorplanning scripts to

access them. At this step clock gating is applied and Power Compiler is enabled

(i.e. the max. dynamic and leakage power is set). Finally SDC (Synopsis Design

Constraint) files are post-processed for use with JupiterXT and Astro.

Astro Place&Route flow performs placement, clock tree synthesis, routing,

postrouting, and physical optimisation. Clock tree synthesis solves complicated

clock tree synthesis problems, such as blockage avoidance and the correlation

between prerouting and postrouting. Routing includes global routing, track

assignment, detail routing, and search-and-repair. After global routing, track

assignment, or detail routing, the design is optimised for timing and crosstalk.

Electric circuit extraction, also netlist extraction, is the translation of an IC layout

back into the electrical circuit (i.e. netlist) it is intended to represent. StarXtract

extracts parasitics into a centralised database so they can be used for circuit

simulation, static timing analysis, signal integrity, power analysis and optimisation,

and logic to layout comparison. Parasitic devices are devices which were not

explicitly intended by the designer but are inherent in the layout of the circuit.

SPEF: Standard Parasitic Exchange Format

Static timing analysis using PrimeTime generates static delay files for various

operating conditions. Integrated circuits exhibit different performance

characteristics for different operating conditions, fabrication process variations,

power supply voltage, and temperature.

- check_setup: gates_slow.sdf [worst op. condition]

- check_hold: gates_fast.sdf [best op. condition]

- typical: gates_typical.sdf [typical op. condition]

Defines top cell boundary, inserts all bond-pads, and inserts an instance of the final

core cell.

Design

Compiler[dc_shell-t]

JupiterXT[JupiterXT]

Astro[Astro]

StarXtract[StarXtract]

PrimeTime

STA[pt_shell]

EnCore Processor Design Flow

JupiterXT[JupiterXT]

SoC Hierarchical Design Planning

JupiterXT helps to partition the logical netlist into the best

physical hierarchy for optimised synthesis and physical

implementation.

Astro[Astro]

Physical Optimisation, Placement and Routing

Solution for SoC Designs

Numerous technology-dependent steps are required to

complete a complex, ultra-deep-submicron integrated

circuit (IC) design. Logic and interconnect delays must be

analysed and minimised. Physical effects such as signal

crosstalk, power density, and supply voltage drop must be

handled. Ideal clocks can no longer be assumed, and

clock skew must be minimized. Physical effects are

critical because changes to one may seriously impact the

optimization of others.

The Astro product is an advanced physical design system

for optimisation, placement and routing, using a

specialised architecture that concurrently accounts for

physical effects while optimizing the resulting design.

StarXtract[StarXtract]

Parasitic Extraction

With shrinking process technologies, increasing die size

and clock frequency, interconnect parasitic effects have

begun to manifest themselves in signal delay and noise.

Consequently, interconnects now play an important role in

the design flow. Today, IC design is interconnect-limited

and the design flow is interconnect-driven. Star-RCXT is a

parasitic extraction tool that models advanced process

effects and has the capacity to handle large designs with

tens of millions of transistors and cells.

PrimeTime

STA[pt_shell]

Static Timing Analysis

Timing analysis solution for gate-level designs featuring

comprehensive analysis including setup/hold/recovery,

parasitic or SDF delay annotations and many more (see

Synopsis product data sheet).

Design

Compiler[dc_shell-t]

RTL Synthesis

RTL synthesis solution that performs advanced arithmetic

optimisation, critical path synthesis, register retiming etc.

It enables a developer to optimise a design for timing,

area, power and test.

ASIC Design Flow Steps [Makefile targets] Synthesis Tool Descriptions

Floor Planning

Automatic Place & Route

init_chip chip

layout extract

layout chip

Power

Compiler

Power

Compiler

Power Optimisation & Analysis

Power Compiler performs both RTL and gate-level power

optimisation and gate-level power analysis. By applying

Power Compiler's various power reduction techniques,

including clock-gating, operand isolation, multivoltage

leakage power optimization, and gate-level power

optimization, you can achieve power savings, and area

and timing optimisation in the front-end synthesis domain.

Synthesis Tools

gdsii stream_out

Physical Verification

drc all

lvs all

package stream_out

Configures GDSII (Graphic Data System II) stream-out flow for design rule

checking and layout versus schematic verification.

Design Rule Checking determines whether a particular chip layout satisfies a

series of recommended parameters called design rules. Design rule checking is a

major step during physical verification of the design. Design Rules are a series of

parameters provided by semiconductor manufacturers that enable the designer to

verify the correctness of the mask set. Design rules are specific to a particular

semiconductor manufacturing process specifying certain geometric and

connectivity restrictions to ensure sufficient margins to account for variability in

semiconductor manufacturing processes, so as to ensure that most of the parts

work correctly.

Layout vs. Schematic is the class of electronic design automation verification

software that determines whether a particular integrated circuit layout corresponds

to the original schematic or circuit diagram of the design. LVS checking software

recognizes the drawn shapes of the layout that represent the electrical

components of the circuit, as well as the connections between them. The software

then compares them with the schematic or circuit diagram. Typical errors

encountered during LVS include: shorts, opens, component mismatches, missing

components, property errors.

Instantiates top-level package, inserts an instance of the final core cell into the

package, places point-to-point wires in the design to represent bond-wires.

Calibre[calibre]

Physical Verification

Mentor's Calibre tool is used for layout verification and

design rule checking.

Calibre[calibre]

sta check_setup

sta check_hold

sta typical

Timing Analysis

Research centre identities

Centre for Intelligent Systems& their Applications

Institute for Adaptive& Neural Computation

Institute for Communicating& Collaborative Systems

Institute for ComputingSystems Architecture

Institute of Perception,Action and Behaviour

e-Science Institute

Laboratory for Foundationsof Computer Science

Informatics Life-Sciences Institute

Performs initial virtual flat placement and then further refines and legalises the

floorplan. Power planning, virtual power network analysis, and global routing is also

performed.

Processor Automated Synthesis by iTerative Analysis Projecthttp://groups.inf.ed.ac.uk/pasta/

Tape-out

EDA Database[Synopsis Milkyway DB]

Floorplanning

GDS II OUT

RTL to Gates

Synthesis

RTL to Placed

Gates Synthesis

IC Layout

Parasitic

Extraction

Timing

Analysis

IP Libraries

VendorLibraries

RTLDatabase

Configuration

GDS II

Design Rule

Checking

Layout

vs.

Schematic

Start

EnCore - Calton Chip Layout

Tape-out

Before applying

• Seriously consider other options

‣ Working (for a few years?)

‣ Doing a taught degree (MSc elsewhere)

‣ Gap year

• Try it out first

‣ Research internships (often not advertised!)Check https://www.wiki.ed.ac.uk/display/SciEngSchol/College for college funding for this, and ask lecturers whether they want to host you!

‣ Your undergrad/MSc dissertation research11

11

Identity development

Physical Layout

Gate-Level Netlist

RTL-DescriptionRTL Description

rtl_config config

Logic Synthesis

rtl2gates synth

floorplan floorplan

rtl2pg synth

rcxt spef

final_chip final_design

Pre-processing/Compiling of micro-code definitions and of Verilog files.

RTL-to-Gates synthesis flow takes a RTL HW description and a standard cell

library as input, and produces a gate-level netlist as output. The resulting gate-level

netlist is a completely structural description with only standard cells at the leaves of

the design. This step also creates a SAIF (Switching Activity Interchange Format)

forward-annotation file starting from the top level of the design.

Creates floorplan information including core size, placement sites, port locations,

RAM locations, as well as routing and placement obstructions.

RTL-to-placed-gates synthesis step capable of driving Design Compiler in

topographical mode to perform physical synthesis using floorplan physical

constraints. The design hierarchy is flattened partly to improve timing, but also to

ensure that the path to RAMs and pads is fixed to allow floorplanning scripts to

access them. At this step clock gating is applied and Power Compiler is enabled

(i.e. the max. dynamic and leakage power is set). Finally SDC (Synopsis Design

Constraint) files are post-processed for use with JupiterXT and Astro.

Astro Place&Route flow performs placement, clock tree synthesis, routing,

postrouting, and physical optimisation. Clock tree synthesis solves complicated

clock tree synthesis problems, such as blockage avoidance and the correlation

between prerouting and postrouting. Routing includes global routing, track

assignment, detail routing, and search-and-repair. After global routing, track

assignment, or detail routing, the design is optimised for timing and crosstalk.

Electric circuit extraction, also netlist extraction, is the translation of an IC layout

back into the electrical circuit (i.e. netlist) it is intended to represent. StarXtract

extracts parasitics into a centralised database so they can be used for circuit

simulation, static timing analysis, signal integrity, power analysis and optimisation,

and logic to layout comparison. Parasitic devices are devices which were not

explicitly intended by the designer but are inherent in the layout of the circuit.

SPEF: Standard Parasitic Exchange Format

Static timing analysis using PrimeTime generates static delay files for various

operating conditions. Integrated circuits exhibit different performance

characteristics for different operating conditions, fabrication process variations,

power supply voltage, and temperature.

- check_setup: gates_slow.sdf [worst op. condition]

- check_hold: gates_fast.sdf [best op. condition]

- typical: gates_typical.sdf [typical op. condition]

Defines top cell boundary, inserts all bond-pads, and inserts an instance of the final

core cell.

Design

Compiler[dc_shell-t]

JupiterXT[JupiterXT]

Astro[Astro]

StarXtract[StarXtract]

PrimeTime

STA[pt_shell]

EnCore Processor Design Flow

JupiterXT[JupiterXT]

SoC Hierarchical Design Planning

JupiterXT helps to partition the logical netlist into the best

physical hierarchy for optimised synthesis and physical

implementation.

Astro[Astro]

Physical Optimisation, Placement and Routing

Solution for SoC Designs

Numerous technology-dependent steps are required to

complete a complex, ultra-deep-submicron integrated

circuit (IC) design. Logic and interconnect delays must be

analysed and minimised. Physical effects such as signal

crosstalk, power density, and supply voltage drop must be

handled. Ideal clocks can no longer be assumed, and

clock skew must be minimized. Physical effects are

critical because changes to one may seriously impact the

optimization of others.

The Astro product is an advanced physical design system

for optimisation, placement and routing, using a

specialised architecture that concurrently accounts for

physical effects while optimizing the resulting design.

StarXtract[StarXtract]

Parasitic Extraction

With shrinking process technologies, increasing die size

and clock frequency, interconnect parasitic effects have

begun to manifest themselves in signal delay and noise.

Consequently, interconnects now play an important role in

the design flow. Today, IC design is interconnect-limited

and the design flow is interconnect-driven. Star-RCXT is a

parasitic extraction tool that models advanced process

effects and has the capacity to handle large designs with

tens of millions of transistors and cells.

PrimeTime

STA[pt_shell]

Static Timing Analysis

Timing analysis solution for gate-level designs featuring

comprehensive analysis including setup/hold/recovery,

parasitic or SDF delay annotations and many more (see

Synopsis product data sheet).

Design

Compiler[dc_shell-t]

RTL Synthesis

RTL synthesis solution that performs advanced arithmetic

optimisation, critical path synthesis, register retiming etc.

It enables a developer to optimise a design for timing,

area, power and test.

ASIC Design Flow Steps [Makefile targets] Synthesis Tool Descriptions

Floor Planning

Automatic Place & Route

init_chip chip

layout extract

layout chip

Power

Compiler

Power

Compiler

Power Optimisation & Analysis

Power Compiler performs both RTL and gate-level power

optimisation and gate-level power analysis. By applying

Power Compiler's various power reduction techniques,

including clock-gating, operand isolation, multivoltage

leakage power optimization, and gate-level power

optimization, you can achieve power savings, and area

and timing optimisation in the front-end synthesis domain.

Synthesis Tools

gdsii stream_out

Physical Verification

drc all

lvs all

package stream_out

Configures GDSII (Graphic Data System II) stream-out flow for design rule

checking and layout versus schematic verification.

Design Rule Checking determines whether a particular chip layout satisfies a

series of recommended parameters called design rules. Design rule checking is a

major step during physical verification of the design. Design Rules are a series of

parameters provided by semiconductor manufacturers that enable the designer to

verify the correctness of the mask set. Design rules are specific to a particular

semiconductor manufacturing process specifying certain geometric and

connectivity restrictions to ensure sufficient margins to account for variability in

semiconductor manufacturing processes, so as to ensure that most of the parts

work correctly.

Layout vs. Schematic is the class of electronic design automation verification

software that determines whether a particular integrated circuit layout corresponds

to the original schematic or circuit diagram of the design. LVS checking software

recognizes the drawn shapes of the layout that represent the electrical

components of the circuit, as well as the connections between them. The software

then compares them with the schematic or circuit diagram. Typical errors

encountered during LVS include: shorts, opens, component mismatches, missing

components, property errors.

Instantiates top-level package, inserts an instance of the final core cell into the

package, places point-to-point wires in the design to represent bond-wires.

Calibre[calibre]

Physical Verification

Mentor's Calibre tool is used for layout verification and

design rule checking.

Calibre[calibre]

sta check_setup

sta check_hold

sta typical

Timing Analysis

Research centre identities

Centre for Intelligent Systems& their Applications

Institute for Adaptive& Neural Computation

Institute for Communicating& Collaborative Systems

Institute for ComputingSystems Architecture

Institute of Perception,Action and Behaviour

e-Science Institute

Laboratory for Foundationsof Computer Science

Informatics Life-Sciences Institute

Performs initial virtual flat placement and then further refines and legalises the

floorplan. Power planning, virtual power network analysis, and global routing is also

performed.

Processor Automated Synthesis by iTerative Analysis Projecthttp://groups.inf.ed.ac.uk/pasta/

Tape-out

EDA Database[Synopsis Milkyway DB]

Floorplanning

GDS II OUT

RTL to Gates

Synthesis

RTL to Placed

Gates Synthesis

IC Layout

Parasitic

Extraction

Timing

Analysis

IP Libraries

VendorLibraries

RTLDatabase

Configuration

GDS II

Design Rule

Checking

Layout

vs.

Schematic

Start

EnCore - Calton Chip Layout

Tape-out

How to apply?

• STEP 1: Do your own background research

‣ Identify area you’d like to work in

‣ Find open problems you’d like to work on

‣ Find potential supervisors you’d like to work with

‣ Be flexible, ideas can be pretty vague at this stage

12

12

Identity development

Physical Layout

Gate-Level Netlist

RTL-DescriptionRTL Description

rtl_config config

Logic Synthesis

rtl2gates synth

floorplan floorplan

rtl2pg synth

rcxt spef

final_chip final_design

Pre-processing/Compiling of micro-code definitions and of Verilog files.

RTL-to-Gates synthesis flow takes a RTL HW description and a standard cell

library as input, and produces a gate-level netlist as output. The resulting gate-level

netlist is a completely structural description with only standard cells at the leaves of

the design. This step also creates a SAIF (Switching Activity Interchange Format)

forward-annotation file starting from the top level of the design.

Creates floorplan information including core size, placement sites, port locations,

RAM locations, as well as routing and placement obstructions.

RTL-to-placed-gates synthesis step capable of driving Design Compiler in

topographical mode to perform physical synthesis using floorplan physical

constraints. The design hierarchy is flattened partly to improve timing, but also to

ensure that the path to RAMs and pads is fixed to allow floorplanning scripts to

access them. At this step clock gating is applied and Power Compiler is enabled

(i.e. the max. dynamic and leakage power is set). Finally SDC (Synopsis Design

Constraint) files are post-processed for use with JupiterXT and Astro.

Astro Place&Route flow performs placement, clock tree synthesis, routing,

postrouting, and physical optimisation. Clock tree synthesis solves complicated

clock tree synthesis problems, such as blockage avoidance and the correlation

between prerouting and postrouting. Routing includes global routing, track

assignment, detail routing, and search-and-repair. After global routing, track

assignment, or detail routing, the design is optimised for timing and crosstalk.

Electric circuit extraction, also netlist extraction, is the translation of an IC layout

back into the electrical circuit (i.e. netlist) it is intended to represent. StarXtract

extracts parasitics into a centralised database so they can be used for circuit

simulation, static timing analysis, signal integrity, power analysis and optimisation,

and logic to layout comparison. Parasitic devices are devices which were not

explicitly intended by the designer but are inherent in the layout of the circuit.

SPEF: Standard Parasitic Exchange Format

Static timing analysis using PrimeTime generates static delay files for various

operating conditions. Integrated circuits exhibit different performance

characteristics for different operating conditions, fabrication process variations,

power supply voltage, and temperature.

- check_setup: gates_slow.sdf [worst op. condition]

- check_hold: gates_fast.sdf [best op. condition]

- typical: gates_typical.sdf [typical op. condition]

Defines top cell boundary, inserts all bond-pads, and inserts an instance of the final

core cell.

Design

Compiler[dc_shell-t]

JupiterXT[JupiterXT]

Astro[Astro]

StarXtract[StarXtract]

PrimeTime

STA[pt_shell]

EnCore Processor Design Flow

JupiterXT[JupiterXT]

SoC Hierarchical Design Planning

JupiterXT helps to partition the logical netlist into the best

physical hierarchy for optimised synthesis and physical

implementation.

Astro[Astro]

Physical Optimisation, Placement and Routing

Solution for SoC Designs

Numerous technology-dependent steps are required to

complete a complex, ultra-deep-submicron integrated

circuit (IC) design. Logic and interconnect delays must be

analysed and minimised. Physical effects such as signal

crosstalk, power density, and supply voltage drop must be

handled. Ideal clocks can no longer be assumed, and

clock skew must be minimized. Physical effects are

critical because changes to one may seriously impact the

optimization of others.

The Astro product is an advanced physical design system

for optimisation, placement and routing, using a

specialised architecture that concurrently accounts for

physical effects while optimizing the resulting design.

StarXtract[StarXtract]

Parasitic Extraction

With shrinking process technologies, increasing die size

and clock frequency, interconnect parasitic effects have

begun to manifest themselves in signal delay and noise.

Consequently, interconnects now play an important role in

the design flow. Today, IC design is interconnect-limited

and the design flow is interconnect-driven. Star-RCXT is a

parasitic extraction tool that models advanced process

effects and has the capacity to handle large designs with

tens of millions of transistors and cells.

PrimeTime

STA[pt_shell]

Static Timing Analysis

Timing analysis solution for gate-level designs featuring

comprehensive analysis including setup/hold/recovery,

parasitic or SDF delay annotations and many more (see

Synopsis product data sheet).

Design

Compiler[dc_shell-t]

RTL Synthesis

RTL synthesis solution that performs advanced arithmetic

optimisation, critical path synthesis, register retiming etc.

It enables a developer to optimise a design for timing,

area, power and test.

ASIC Design Flow Steps [Makefile targets] Synthesis Tool Descriptions

Floor Planning

Automatic Place & Route

init_chip chip

layout extract

layout chip

Power

Compiler

Power

Compiler

Power Optimisation & Analysis

Power Compiler performs both RTL and gate-level power

optimisation and gate-level power analysis. By applying

Power Compiler's various power reduction techniques,

including clock-gating, operand isolation, multivoltage

leakage power optimization, and gate-level power

optimization, you can achieve power savings, and area

and timing optimisation in the front-end synthesis domain.

Synthesis Tools

gdsii stream_out

Physical Verification

drc all

lvs all

package stream_out

Configures GDSII (Graphic Data System II) stream-out flow for design rule

checking and layout versus schematic verification.

Design Rule Checking determines whether a particular chip layout satisfies a

series of recommended parameters called design rules. Design rule checking is a

major step during physical verification of the design. Design Rules are a series of

parameters provided by semiconductor manufacturers that enable the designer to

verify the correctness of the mask set. Design rules are specific to a particular

semiconductor manufacturing process specifying certain geometric and

connectivity restrictions to ensure sufficient margins to account for variability in

semiconductor manufacturing processes, so as to ensure that most of the parts

work correctly.

Layout vs. Schematic is the class of electronic design automation verification

software that determines whether a particular integrated circuit layout corresponds

to the original schematic or circuit diagram of the design. LVS checking software

recognizes the drawn shapes of the layout that represent the electrical

components of the circuit, as well as the connections between them. The software

then compares them with the schematic or circuit diagram. Typical errors

encountered during LVS include: shorts, opens, component mismatches, missing

components, property errors.

Instantiates top-level package, inserts an instance of the final core cell into the

package, places point-to-point wires in the design to represent bond-wires.

Calibre[calibre]

Physical Verification

Mentor's Calibre tool is used for layout verification and

design rule checking.

Calibre[calibre]

sta check_setup

sta check_hold

sta typical

Timing Analysis

Research centre identities

Centre for Intelligent Systems& their Applications

Institute for Adaptive& Neural Computation

Institute for Communicating& Collaborative Systems

Institute for ComputingSystems Architecture

Institute of Perception,Action and Behaviour

e-Science Institute

Laboratory for Foundationsof Computer Science

Informatics Life-Sciences Institute

Performs initial virtual flat placement and then further refines and legalises the

floorplan. Power planning, virtual power network analysis, and global routing is also

performed.

Processor Automated Synthesis by iTerative Analysis Projecthttp://groups.inf.ed.ac.uk/pasta/

Tape-out

EDA Database[Synopsis Milkyway DB]

Floorplanning

GDS II OUT

RTL to Gates

Synthesis

RTL to Placed

Gates Synthesis

IC Layout

Parasitic

Extraction

Timing

Analysis

IP Libraries

VendorLibraries

RTLDatabase

Configuration

GDS II

Design Rule

Checking

Layout

vs.

Schematic

Start

EnCore - Calton Chip Layout

Tape-out

How to apply?

• STEP 2: Contact potential supervisors

‣ Read their website and papers

‣ Contact them and ask for an informal meeting to discuss a potential PhD (this might involve some travelling around)

‣ Gauge interest, funding prospects, ongoing projects they have

13

13

Identity development

Physical Layout

Gate-Level Netlist

RTL-DescriptionRTL Description

rtl_config config

Logic Synthesis

rtl2gates synth

floorplan floorplan

rtl2pg synth

rcxt spef

final_chip final_design

Pre-processing/Compiling of micro-code definitions and of Verilog files.

RTL-to-Gates synthesis flow takes a RTL HW description and a standard cell

library as input, and produces a gate-level netlist as output. The resulting gate-level

netlist is a completely structural description with only standard cells at the leaves of

the design. This step also creates a SAIF (Switching Activity Interchange Format)

forward-annotation file starting from the top level of the design.

Creates floorplan information including core size, placement sites, port locations,

RAM locations, as well as routing and placement obstructions.

RTL-to-placed-gates synthesis step capable of driving Design Compiler in

topographical mode to perform physical synthesis using floorplan physical

constraints. The design hierarchy is flattened partly to improve timing, but also to

ensure that the path to RAMs and pads is fixed to allow floorplanning scripts to

access them. At this step clock gating is applied and Power Compiler is enabled

(i.e. the max. dynamic and leakage power is set). Finally SDC (Synopsis Design

Constraint) files are post-processed for use with JupiterXT and Astro.

Astro Place&Route flow performs placement, clock tree synthesis, routing,

postrouting, and physical optimisation. Clock tree synthesis solves complicated

clock tree synthesis problems, such as blockage avoidance and the correlation

between prerouting and postrouting. Routing includes global routing, track

assignment, detail routing, and search-and-repair. After global routing, track

assignment, or detail routing, the design is optimised for timing and crosstalk.

Electric circuit extraction, also netlist extraction, is the translation of an IC layout

back into the electrical circuit (i.e. netlist) it is intended to represent. StarXtract

extracts parasitics into a centralised database so they can be used for circuit

simulation, static timing analysis, signal integrity, power analysis and optimisation,

and logic to layout comparison. Parasitic devices are devices which were not

explicitly intended by the designer but are inherent in the layout of the circuit.

SPEF: Standard Parasitic Exchange Format

Static timing analysis using PrimeTime generates static delay files for various

operating conditions. Integrated circuits exhibit different performance

characteristics for different operating conditions, fabrication process variations,

power supply voltage, and temperature.

- check_setup: gates_slow.sdf [worst op. condition]

- check_hold: gates_fast.sdf [best op. condition]

- typical: gates_typical.sdf [typical op. condition]

Defines top cell boundary, inserts all bond-pads, and inserts an instance of the final

core cell.

Design

Compiler[dc_shell-t]

JupiterXT[JupiterXT]

Astro[Astro]

StarXtract[StarXtract]

PrimeTime

STA[pt_shell]

EnCore Processor Design Flow

JupiterXT[JupiterXT]

SoC Hierarchical Design Planning

JupiterXT helps to partition the logical netlist into the best

physical hierarchy for optimised synthesis and physical

implementation.

Astro[Astro]

Physical Optimisation, Placement and Routing

Solution for SoC Designs

Numerous technology-dependent steps are required to

complete a complex, ultra-deep-submicron integrated

circuit (IC) design. Logic and interconnect delays must be

analysed and minimised. Physical effects such as signal

crosstalk, power density, and supply voltage drop must be

handled. Ideal clocks can no longer be assumed, and

clock skew must be minimized. Physical effects are

critical because changes to one may seriously impact the

optimization of others.

The Astro product is an advanced physical design system

for optimisation, placement and routing, using a

specialised architecture that concurrently accounts for

physical effects while optimizing the resulting design.

StarXtract[StarXtract]

Parasitic Extraction

With shrinking process technologies, increasing die size

and clock frequency, interconnect parasitic effects have

begun to manifest themselves in signal delay and noise.

Consequently, interconnects now play an important role in

the design flow. Today, IC design is interconnect-limited

and the design flow is interconnect-driven. Star-RCXT is a

parasitic extraction tool that models advanced process

effects and has the capacity to handle large designs with

tens of millions of transistors and cells.

PrimeTime

STA[pt_shell]

Static Timing Analysis

Timing analysis solution for gate-level designs featuring

comprehensive analysis including setup/hold/recovery,

parasitic or SDF delay annotations and many more (see

Synopsis product data sheet).

Design

Compiler[dc_shell-t]

RTL Synthesis

RTL synthesis solution that performs advanced arithmetic

optimisation, critical path synthesis, register retiming etc.

It enables a developer to optimise a design for timing,

area, power and test.

ASIC Design Flow Steps [Makefile targets] Synthesis Tool Descriptions

Floor Planning

Automatic Place & Route

init_chip chip

layout extract

layout chip

Power

Compiler

Power

Compiler

Power Optimisation & Analysis

Power Compiler performs both RTL and gate-level power

optimisation and gate-level power analysis. By applying

Power Compiler's various power reduction techniques,

including clock-gating, operand isolation, multivoltage

leakage power optimization, and gate-level power

optimization, you can achieve power savings, and area

and timing optimisation in the front-end synthesis domain.

Synthesis Tools

gdsii stream_out

Physical Verification

drc all

lvs all

package stream_out

Configures GDSII (Graphic Data System II) stream-out flow for design rule

checking and layout versus schematic verification.

Design Rule Checking determines whether a particular chip layout satisfies a

series of recommended parameters called design rules. Design rule checking is a

major step during physical verification of the design. Design Rules are a series of

parameters provided by semiconductor manufacturers that enable the designer to

verify the correctness of the mask set. Design rules are specific to a particular

semiconductor manufacturing process specifying certain geometric and

connectivity restrictions to ensure sufficient margins to account for variability in

semiconductor manufacturing processes, so as to ensure that most of the parts

work correctly.

Layout vs. Schematic is the class of electronic design automation verification

software that determines whether a particular integrated circuit layout corresponds

to the original schematic or circuit diagram of the design. LVS checking software

recognizes the drawn shapes of the layout that represent the electrical

components of the circuit, as well as the connections between them. The software

then compares them with the schematic or circuit diagram. Typical errors

encountered during LVS include: shorts, opens, component mismatches, missing

components, property errors.

Instantiates top-level package, inserts an instance of the final core cell into the

package, places point-to-point wires in the design to represent bond-wires.

Calibre[calibre]

Physical Verification

Mentor's Calibre tool is used for layout verification and

design rule checking.

Calibre[calibre]

sta check_setup

sta check_hold

sta typical

Timing Analysis

Research centre identities

Centre for Intelligent Systems& their Applications

Institute for Adaptive& Neural Computation

Institute for Communicating& Collaborative Systems

Institute for ComputingSystems Architecture

Institute of Perception,Action and Behaviour

e-Science Institute

Laboratory for Foundationsof Computer Science

Informatics Life-Sciences Institute

Performs initial virtual flat placement and then further refines and legalises the

floorplan. Power planning, virtual power network analysis, and global routing is also

performed.

Processor Automated Synthesis by iTerative Analysis Projecthttp://groups.inf.ed.ac.uk/pasta/

Tape-out

EDA Database[Synopsis Milkyway DB]

Floorplanning

GDS II OUT

RTL to Gates

Synthesis

RTL to Placed

Gates Synthesis

IC Layout

Parasitic

Extraction

Timing

Analysis

IP Libraries

VendorLibraries

RTLDatabase

Configuration

GDS II

Design Rule

Checking

Layout

vs.

Schematic

Start

EnCore - Calton Chip Layout

Tape-out

How to apply?

• STEP 3: Select your preferred supervisor(s)

a) Tell them that you’re applying

b) Draft your research proposal(s) - they might help you with it, so don’t worry about asking for ideas and feedback!

c) Discuss funding options

d) Ask lecturers for references

14

14

Identity development

Physical Layout

Gate-Level Netlist

RTL-DescriptionRTL Description

rtl_config config

Logic Synthesis

rtl2gates synth

floorplan floorplan

rtl2pg synth

rcxt spef

final_chip final_design

Pre-processing/Compiling of micro-code definitions and of Verilog files.

RTL-to-Gates synthesis flow takes a RTL HW description and a standard cell

library as input, and produces a gate-level netlist as output. The resulting gate-level

netlist is a completely structural description with only standard cells at the leaves of

the design. This step also creates a SAIF (Switching Activity Interchange Format)

forward-annotation file starting from the top level of the design.

Creates floorplan information including core size, placement sites, port locations,

RAM locations, as well as routing and placement obstructions.

RTL-to-placed-gates synthesis step capable of driving Design Compiler in

topographical mode to perform physical synthesis using floorplan physical

constraints. The design hierarchy is flattened partly to improve timing, but also to

ensure that the path to RAMs and pads is fixed to allow floorplanning scripts to

access them. At this step clock gating is applied and Power Compiler is enabled

(i.e. the max. dynamic and leakage power is set). Finally SDC (Synopsis Design

Constraint) files are post-processed for use with JupiterXT and Astro.

Astro Place&Route flow performs placement, clock tree synthesis, routing,

postrouting, and physical optimisation. Clock tree synthesis solves complicated

clock tree synthesis problems, such as blockage avoidance and the correlation

between prerouting and postrouting. Routing includes global routing, track

assignment, detail routing, and search-and-repair. After global routing, track

assignment, or detail routing, the design is optimised for timing and crosstalk.

Electric circuit extraction, also netlist extraction, is the translation of an IC layout

back into the electrical circuit (i.e. netlist) it is intended to represent. StarXtract

extracts parasitics into a centralised database so they can be used for circuit

simulation, static timing analysis, signal integrity, power analysis and optimisation,

and logic to layout comparison. Parasitic devices are devices which were not

explicitly intended by the designer but are inherent in the layout of the circuit.

SPEF: Standard Parasitic Exchange Format

Static timing analysis using PrimeTime generates static delay files for various

operating conditions. Integrated circuits exhibit different performance

characteristics for different operating conditions, fabrication process variations,

power supply voltage, and temperature.

- check_setup: gates_slow.sdf [worst op. condition]

- check_hold: gates_fast.sdf [best op. condition]

- typical: gates_typical.sdf [typical op. condition]

Defines top cell boundary, inserts all bond-pads, and inserts an instance of the final

core cell.

Design

Compiler[dc_shell-t]

JupiterXT[JupiterXT]

Astro[Astro]

StarXtract[StarXtract]

PrimeTime

STA[pt_shell]

EnCore Processor Design Flow

JupiterXT[JupiterXT]

SoC Hierarchical Design Planning

JupiterXT helps to partition the logical netlist into the best

physical hierarchy for optimised synthesis and physical

implementation.

Astro[Astro]

Physical Optimisation, Placement and Routing

Solution for SoC Designs

Numerous technology-dependent steps are required to

complete a complex, ultra-deep-submicron integrated

circuit (IC) design. Logic and interconnect delays must be

analysed and minimised. Physical effects such as signal

crosstalk, power density, and supply voltage drop must be

handled. Ideal clocks can no longer be assumed, and

clock skew must be minimized. Physical effects are

critical because changes to one may seriously impact the

optimization of others.

The Astro product is an advanced physical design system

for optimisation, placement and routing, using a

specialised architecture that concurrently accounts for

physical effects while optimizing the resulting design.

StarXtract[StarXtract]

Parasitic Extraction

With shrinking process technologies, increasing die size

and clock frequency, interconnect parasitic effects have

begun to manifest themselves in signal delay and noise.

Consequently, interconnects now play an important role in

the design flow. Today, IC design is interconnect-limited

and the design flow is interconnect-driven. Star-RCXT is a

parasitic extraction tool that models advanced process

effects and has the capacity to handle large designs with

tens of millions of transistors and cells.

PrimeTime

STA[pt_shell]

Static Timing Analysis

Timing analysis solution for gate-level designs featuring

comprehensive analysis including setup/hold/recovery,

parasitic or SDF delay annotations and many more (see

Synopsis product data sheet).

Design

Compiler[dc_shell-t]

RTL Synthesis

RTL synthesis solution that performs advanced arithmetic

optimisation, critical path synthesis, register retiming etc.

It enables a developer to optimise a design for timing,

area, power and test.

ASIC Design Flow Steps [Makefile targets] Synthesis Tool Descriptions

Floor Planning

Automatic Place & Route

init_chip chip

layout extract

layout chip

Power

Compiler

Power

Compiler

Power Optimisation & Analysis

Power Compiler performs both RTL and gate-level power

optimisation and gate-level power analysis. By applying

Power Compiler's various power reduction techniques,

including clock-gating, operand isolation, multivoltage

leakage power optimization, and gate-level power

optimization, you can achieve power savings, and area

and timing optimisation in the front-end synthesis domain.

Synthesis Tools

gdsii stream_out

Physical Verification

drc all

lvs all

package stream_out

Configures GDSII (Graphic Data System II) stream-out flow for design rule

checking and layout versus schematic verification.

Design Rule Checking determines whether a particular chip layout satisfies a

series of recommended parameters called design rules. Design rule checking is a

major step during physical verification of the design. Design Rules are a series of

parameters provided by semiconductor manufacturers that enable the designer to

verify the correctness of the mask set. Design rules are specific to a particular

semiconductor manufacturing process specifying certain geometric and

connectivity restrictions to ensure sufficient margins to account for variability in

semiconductor manufacturing processes, so as to ensure that most of the parts

work correctly.

Layout vs. Schematic is the class of electronic design automation verification

software that determines whether a particular integrated circuit layout corresponds

to the original schematic or circuit diagram of the design. LVS checking software

recognizes the drawn shapes of the layout that represent the electrical

components of the circuit, as well as the connections between them. The software

then compares them with the schematic or circuit diagram. Typical errors

encountered during LVS include: shorts, opens, component mismatches, missing

components, property errors.

Instantiates top-level package, inserts an instance of the final core cell into the

package, places point-to-point wires in the design to represent bond-wires.

Calibre[calibre]

Physical Verification

Mentor's Calibre tool is used for layout verification and

design rule checking.

Calibre[calibre]

sta check_setup

sta check_hold

sta typical

Timing Analysis

Research centre identities

Centre for Intelligent Systems& their Applications

Institute for Adaptive& Neural Computation

Institute for Communicating& Collaborative Systems

Institute for ComputingSystems Architecture

Institute of Perception,Action and Behaviour

e-Science Institute

Laboratory for Foundationsof Computer Science

Informatics Life-Sciences Institute

Performs initial virtual flat placement and then further refines and legalises the

floorplan. Power planning, virtual power network analysis, and global routing is also

performed.

Processor Automated Synthesis by iTerative Analysis Projecthttp://groups.inf.ed.ac.uk/pasta/

Tape-out

EDA Database[Synopsis Milkyway DB]

Floorplanning

GDS II OUT

RTL to Gates

Synthesis

RTL to Placed

Gates Synthesis

IC Layout

Parasitic

Extraction

Timing

Analysis

IP Libraries

VendorLibraries

RTLDatabase

Configuration

GDS II

Design Rule

Checking

Layout

vs.

Schematic

Start

EnCore - Calton Chip Layout

Tape-out

How to apply?

• STEP 3b: Writing a research proposal

‣ Essential part of your application

‣ About 2-3 pages long, with references

‣ Goal: convince people you can do it!

15

15

Identity development

Physical Layout

Gate-Level Netlist

RTL-DescriptionRTL Description

rtl_config config

Logic Synthesis

rtl2gates synth

floorplan floorplan

rtl2pg synth

rcxt spef

final_chip final_design

Pre-processing/Compiling of micro-code definitions and of Verilog files.

RTL-to-Gates synthesis flow takes a RTL HW description and a standard cell

library as input, and produces a gate-level netlist as output. The resulting gate-level

netlist is a completely structural description with only standard cells at the leaves of

the design. This step also creates a SAIF (Switching Activity Interchange Format)

forward-annotation file starting from the top level of the design.

Creates floorplan information including core size, placement sites, port locations,

RAM locations, as well as routing and placement obstructions.

RTL-to-placed-gates synthesis step capable of driving Design Compiler in

topographical mode to perform physical synthesis using floorplan physical

constraints. The design hierarchy is flattened partly to improve timing, but also to

ensure that the path to RAMs and pads is fixed to allow floorplanning scripts to

access them. At this step clock gating is applied and Power Compiler is enabled

(i.e. the max. dynamic and leakage power is set). Finally SDC (Synopsis Design

Constraint) files are post-processed for use with JupiterXT and Astro.

Astro Place&Route flow performs placement, clock tree synthesis, routing,

postrouting, and physical optimisation. Clock tree synthesis solves complicated

clock tree synthesis problems, such as blockage avoidance and the correlation

between prerouting and postrouting. Routing includes global routing, track

assignment, detail routing, and search-and-repair. After global routing, track

assignment, or detail routing, the design is optimised for timing and crosstalk.

Electric circuit extraction, also netlist extraction, is the translation of an IC layout

back into the electrical circuit (i.e. netlist) it is intended to represent. StarXtract

extracts parasitics into a centralised database so they can be used for circuit

simulation, static timing analysis, signal integrity, power analysis and optimisation,

and logic to layout comparison. Parasitic devices are devices which were not

explicitly intended by the designer but are inherent in the layout of the circuit.

SPEF: Standard Parasitic Exchange Format

Static timing analysis using PrimeTime generates static delay files for various

operating conditions. Integrated circuits exhibit different performance

characteristics for different operating conditions, fabrication process variations,

power supply voltage, and temperature.

- check_setup: gates_slow.sdf [worst op. condition]

- check_hold: gates_fast.sdf [best op. condition]

- typical: gates_typical.sdf [typical op. condition]

Defines top cell boundary, inserts all bond-pads, and inserts an instance of the final

core cell.

Design

Compiler[dc_shell-t]

JupiterXT[JupiterXT]

Astro[Astro]

StarXtract[StarXtract]

PrimeTime

STA[pt_shell]

EnCore Processor Design Flow

JupiterXT[JupiterXT]

SoC Hierarchical Design Planning

JupiterXT helps to partition the logical netlist into the best

physical hierarchy for optimised synthesis and physical

implementation.

Astro[Astro]

Physical Optimisation, Placement and Routing

Solution for SoC Designs

Numerous technology-dependent steps are required to

complete a complex, ultra-deep-submicron integrated

circuit (IC) design. Logic and interconnect delays must be

analysed and minimised. Physical effects such as signal

crosstalk, power density, and supply voltage drop must be

handled. Ideal clocks can no longer be assumed, and

clock skew must be minimized. Physical effects are

critical because changes to one may seriously impact the

optimization of others.

The Astro product is an advanced physical design system

for optimisation, placement and routing, using a

specialised architecture that concurrently accounts for

physical effects while optimizing the resulting design.

StarXtract[StarXtract]

Parasitic Extraction

With shrinking process technologies, increasing die size

and clock frequency, interconnect parasitic effects have

begun to manifest themselves in signal delay and noise.

Consequently, interconnects now play an important role in

the design flow. Today, IC design is interconnect-limited

and the design flow is interconnect-driven. Star-RCXT is a

parasitic extraction tool that models advanced process

effects and has the capacity to handle large designs with

tens of millions of transistors and cells.

PrimeTime

STA[pt_shell]

Static Timing Analysis

Timing analysis solution for gate-level designs featuring

comprehensive analysis including setup/hold/recovery,

parasitic or SDF delay annotations and many more (see

Synopsis product data sheet).

Design

Compiler[dc_shell-t]

RTL Synthesis

RTL synthesis solution that performs advanced arithmetic

optimisation, critical path synthesis, register retiming etc.

It enables a developer to optimise a design for timing,

area, power and test.

ASIC Design Flow Steps [Makefile targets] Synthesis Tool Descriptions

Floor Planning

Automatic Place & Route

init_chip chip

layout extract

layout chip

Power

Compiler

Power

Compiler

Power Optimisation & Analysis

Power Compiler performs both RTL and gate-level power

optimisation and gate-level power analysis. By applying

Power Compiler's various power reduction techniques,

including clock-gating, operand isolation, multivoltage

leakage power optimization, and gate-level power

optimization, you can achieve power savings, and area

and timing optimisation in the front-end synthesis domain.

Synthesis Tools

gdsii stream_out

Physical Verification

drc all

lvs all

package stream_out

Configures GDSII (Graphic Data System II) stream-out flow for design rule

checking and layout versus schematic verification.

Design Rule Checking determines whether a particular chip layout satisfies a

series of recommended parameters called design rules. Design rule checking is a

major step during physical verification of the design. Design Rules are a series of

parameters provided by semiconductor manufacturers that enable the designer to

verify the correctness of the mask set. Design rules are specific to a particular

semiconductor manufacturing process specifying certain geometric and

connectivity restrictions to ensure sufficient margins to account for variability in

semiconductor manufacturing processes, so as to ensure that most of the parts

work correctly.

Layout vs. Schematic is the class of electronic design automation verification

software that determines whether a particular integrated circuit layout corresponds

to the original schematic or circuit diagram of the design. LVS checking software

recognizes the drawn shapes of the layout that represent the electrical

components of the circuit, as well as the connections between them. The software

then compares them with the schematic or circuit diagram. Typical errors

encountered during LVS include: shorts, opens, component mismatches, missing

components, property errors.

Instantiates top-level package, inserts an instance of the final core cell into the

package, places point-to-point wires in the design to represent bond-wires.

Calibre[calibre]

Physical Verification

Mentor's Calibre tool is used for layout verification and

design rule checking.

Calibre[calibre]

sta check_setup

sta check_hold

sta typical

Timing Analysis

Research centre identities

Centre for Intelligent Systems& their Applications

Institute for Adaptive& Neural Computation

Institute for Communicating& Collaborative Systems

Institute for ComputingSystems Architecture

Institute of Perception,Action and Behaviour

e-Science Institute

Laboratory for Foundationsof Computer Science

Informatics Life-Sciences Institute

Performs initial virtual flat placement and then further refines and legalises the

floorplan. Power planning, virtual power network analysis, and global routing is also

performed.

Processor Automated Synthesis by iTerative Analysis Projecthttp://groups.inf.ed.ac.uk/pasta/

Tape-out

EDA Database[Synopsis Milkyway DB]

Floorplanning

GDS II OUT

RTL to Gates

Synthesis

RTL to Placed

Gates Synthesis

IC Layout

Parasitic

Extraction

Timing

Analysis

IP Libraries

VendorLibraries

RTLDatabase

Configuration

GDS II

Design Rule

Checking

Layout

vs.

Schematic

Start

EnCore - Calton Chip Layout

Tape-out

How to apply?

• STEP 3b: Writing a research proposal

‣ Describe context of your proposed work and why it’s important (impact!!!)

‣ Identify the open problem you’ll work on

‣ Cite notable related work (your potential supervisor might be able to help)

‣ Sketch roughly how you plan to tackle it in 3 years (what you’ll do in each year)

16

16

Identity development

Physical Layout

Gate-Level Netlist

RTL-DescriptionRTL Description

rtl_config config

Logic Synthesis

rtl2gates synth

floorplan floorplan

rtl2pg synth

rcxt spef

final_chip final_design

Pre-processing/Compiling of micro-code definitions and of Verilog files.

RTL-to-Gates synthesis flow takes a RTL HW description and a standard cell

library as input, and produces a gate-level netlist as output. The resulting gate-level

netlist is a completely structural description with only standard cells at the leaves of

the design. This step also creates a SAIF (Switching Activity Interchange Format)

forward-annotation file starting from the top level of the design.

Creates floorplan information including core size, placement sites, port locations,

RAM locations, as well as routing and placement obstructions.

RTL-to-placed-gates synthesis step capable of driving Design Compiler in

topographical mode to perform physical synthesis using floorplan physical

constraints. The design hierarchy is flattened partly to improve timing, but also to

ensure that the path to RAMs and pads is fixed to allow floorplanning scripts to

access them. At this step clock gating is applied and Power Compiler is enabled

(i.e. the max. dynamic and leakage power is set). Finally SDC (Synopsis Design

Constraint) files are post-processed for use with JupiterXT and Astro.

Astro Place&Route flow performs placement, clock tree synthesis, routing,

postrouting, and physical optimisation. Clock tree synthesis solves complicated

clock tree synthesis problems, such as blockage avoidance and the correlation

between prerouting and postrouting. Routing includes global routing, track

assignment, detail routing, and search-and-repair. After global routing, track

assignment, or detail routing, the design is optimised for timing and crosstalk.

Electric circuit extraction, also netlist extraction, is the translation of an IC layout

back into the electrical circuit (i.e. netlist) it is intended to represent. StarXtract

extracts parasitics into a centralised database so they can be used for circuit

simulation, static timing analysis, signal integrity, power analysis and optimisation,

and logic to layout comparison. Parasitic devices are devices which were not

explicitly intended by the designer but are inherent in the layout of the circuit.

SPEF: Standard Parasitic Exchange Format

Static timing analysis using PrimeTime generates static delay files for various

operating conditions. Integrated circuits exhibit different performance

characteristics for different operating conditions, fabrication process variations,

power supply voltage, and temperature.

- check_setup: gates_slow.sdf [worst op. condition]

- check_hold: gates_fast.sdf [best op. condition]

- typical: gates_typical.sdf [typical op. condition]

Defines top cell boundary, inserts all bond-pads, and inserts an instance of the final

core cell.

Design

Compiler[dc_shell-t]

JupiterXT[JupiterXT]

Astro[Astro]

StarXtract[StarXtract]

PrimeTime

STA[pt_shell]

EnCore Processor Design Flow

JupiterXT[JupiterXT]

SoC Hierarchical Design Planning

JupiterXT helps to partition the logical netlist into the best

physical hierarchy for optimised synthesis and physical

implementation.

Astro[Astro]

Physical Optimisation, Placement and Routing

Solution for SoC Designs

Numerous technology-dependent steps are required to

complete a complex, ultra-deep-submicron integrated

circuit (IC) design. Logic and interconnect delays must be

analysed and minimised. Physical effects such as signal

crosstalk, power density, and supply voltage drop must be

handled. Ideal clocks can no longer be assumed, and

clock skew must be minimized. Physical effects are

critical because changes to one may seriously impact the

optimization of others.

The Astro product is an advanced physical design system

for optimisation, placement and routing, using a

specialised architecture that concurrently accounts for

physical effects while optimizing the resulting design.

StarXtract[StarXtract]

Parasitic Extraction

With shrinking process technologies, increasing die size

and clock frequency, interconnect parasitic effects have

begun to manifest themselves in signal delay and noise.

Consequently, interconnects now play an important role in

the design flow. Today, IC design is interconnect-limited

and the design flow is interconnect-driven. Star-RCXT is a

parasitic extraction tool that models advanced process

effects and has the capacity to handle large designs with

tens of millions of transistors and cells.

PrimeTime

STA[pt_shell]

Static Timing Analysis

Timing analysis solution for gate-level designs featuring

comprehensive analysis including setup/hold/recovery,

parasitic or SDF delay annotations and many more (see

Synopsis product data sheet).

Design

Compiler[dc_shell-t]

RTL Synthesis

RTL synthesis solution that performs advanced arithmetic

optimisation, critical path synthesis, register retiming etc.

It enables a developer to optimise a design for timing,

area, power and test.

ASIC Design Flow Steps [Makefile targets] Synthesis Tool Descriptions

Floor Planning

Automatic Place & Route

init_chip chip

layout extract

layout chip

Power

Compiler

Power

Compiler

Power Optimisation & Analysis

Power Compiler performs both RTL and gate-level power

optimisation and gate-level power analysis. By applying

Power Compiler's various power reduction techniques,

including clock-gating, operand isolation, multivoltage

leakage power optimization, and gate-level power

optimization, you can achieve power savings, and area

and timing optimisation in the front-end synthesis domain.

Synthesis Tools

gdsii stream_out

Physical Verification

drc all

lvs all

package stream_out

Configures GDSII (Graphic Data System II) stream-out flow for design rule

checking and layout versus schematic verification.

Design Rule Checking determines whether a particular chip layout satisfies a

series of recommended parameters called design rules. Design rule checking is a

major step during physical verification of the design. Design Rules are a series of

parameters provided by semiconductor manufacturers that enable the designer to

verify the correctness of the mask set. Design rules are specific to a particular

semiconductor manufacturing process specifying certain geometric and

connectivity restrictions to ensure sufficient margins to account for variability in

semiconductor manufacturing processes, so as to ensure that most of the parts

work correctly.

Layout vs. Schematic is the class of electronic design automation verification

software that determines whether a particular integrated circuit layout corresponds

to the original schematic or circuit diagram of the design. LVS checking software

recognizes the drawn shapes of the layout that represent the electrical

components of the circuit, as well as the connections between them. The software

then compares them with the schematic or circuit diagram. Typical errors

encountered during LVS include: shorts, opens, component mismatches, missing

components, property errors.

Instantiates top-level package, inserts an instance of the final core cell into the

package, places point-to-point wires in the design to represent bond-wires.

Calibre[calibre]

Physical Verification

Mentor's Calibre tool is used for layout verification and

design rule checking.

Calibre[calibre]

sta check_setup

sta check_hold

sta typical

Timing Analysis

Research centre identities

Centre for Intelligent Systems& their Applications

Institute for Adaptive& Neural Computation

Institute for Communicating& Collaborative Systems

Institute for ComputingSystems Architecture

Institute of Perception,Action and Behaviour

e-Science Institute

Laboratory for Foundationsof Computer Science

Informatics Life-Sciences Institute

Performs initial virtual flat placement and then further refines and legalises the

floorplan. Power planning, virtual power network analysis, and global routing is also

performed.

Processor Automated Synthesis by iTerative Analysis Projecthttp://groups.inf.ed.ac.uk/pasta/

Tape-out

EDA Database[Synopsis Milkyway DB]

Floorplanning

GDS II OUT

RTL to Gates

Synthesis

RTL to Placed

Gates Synthesis

IC Layout

Parasitic

Extraction

Timing

Analysis

IP Libraries

VendorLibraries

RTLDatabase

Configuration

GDS II

Design Rule

Checking

Layout

vs.

Schematic

Start

EnCore - Calton Chip Layout

Tape-out

How to apply?

• STEP 3b: Writing a research proposal

‣ Doesn’t do any harm to cite your potential supervisor’s work :-)

‣ Important: you don’t actually have to do what you propose! Many people change topic/project after they start.

‣ This is just to show that you’ve done your research and know the area!

17

17

Identity development

Physical Layout

Gate-Level Netlist

RTL-DescriptionRTL Description

rtl_config config

Logic Synthesis

rtl2gates synth

floorplan floorplan

rtl2pg synth

rcxt spef

final_chip final_design

Pre-processing/Compiling of micro-code definitions and of Verilog files.

RTL-to-Gates synthesis flow takes a RTL HW description and a standard cell

library as input, and produces a gate-level netlist as output. The resulting gate-level

netlist is a completely structural description with only standard cells at the leaves of

the design. This step also creates a SAIF (Switching Activity Interchange Format)

forward-annotation file starting from the top level of the design.

Creates floorplan information including core size, placement sites, port locations,

RAM locations, as well as routing and placement obstructions.

RTL-to-placed-gates synthesis step capable of driving Design Compiler in

topographical mode to perform physical synthesis using floorplan physical

constraints. The design hierarchy is flattened partly to improve timing, but also to

ensure that the path to RAMs and pads is fixed to allow floorplanning scripts to

access them. At this step clock gating is applied and Power Compiler is enabled

(i.e. the max. dynamic and leakage power is set). Finally SDC (Synopsis Design

Constraint) files are post-processed for use with JupiterXT and Astro.

Astro Place&Route flow performs placement, clock tree synthesis, routing,

postrouting, and physical optimisation. Clock tree synthesis solves complicated

clock tree synthesis problems, such as blockage avoidance and the correlation

between prerouting and postrouting. Routing includes global routing, track

assignment, detail routing, and search-and-repair. After global routing, track

assignment, or detail routing, the design is optimised for timing and crosstalk.

Electric circuit extraction, also netlist extraction, is the translation of an IC layout

back into the electrical circuit (i.e. netlist) it is intended to represent. StarXtract

extracts parasitics into a centralised database so they can be used for circuit

simulation, static timing analysis, signal integrity, power analysis and optimisation,

and logic to layout comparison. Parasitic devices are devices which were not

explicitly intended by the designer but are inherent in the layout of the circuit.

SPEF: Standard Parasitic Exchange Format

Static timing analysis using PrimeTime generates static delay files for various

operating conditions. Integrated circuits exhibit different performance

characteristics for different operating conditions, fabrication process variations,

power supply voltage, and temperature.

- check_setup: gates_slow.sdf [worst op. condition]

- check_hold: gates_fast.sdf [best op. condition]

- typical: gates_typical.sdf [typical op. condition]

Defines top cell boundary, inserts all bond-pads, and inserts an instance of the final

core cell.

Design

Compiler[dc_shell-t]

JupiterXT[JupiterXT]

Astro[Astro]

StarXtract[StarXtract]

PrimeTime

STA[pt_shell]

EnCore Processor Design Flow

JupiterXT[JupiterXT]

SoC Hierarchical Design Planning

JupiterXT helps to partition the logical netlist into the best

physical hierarchy for optimised synthesis and physical

implementation.

Astro[Astro]

Physical Optimisation, Placement and Routing

Solution for SoC Designs

Numerous technology-dependent steps are required to

complete a complex, ultra-deep-submicron integrated

circuit (IC) design. Logic and interconnect delays must be

analysed and minimised. Physical effects such as signal

crosstalk, power density, and supply voltage drop must be

handled. Ideal clocks can no longer be assumed, and

clock skew must be minimized. Physical effects are

critical because changes to one may seriously impact the

optimization of others.

The Astro product is an advanced physical design system

for optimisation, placement and routing, using a

specialised architecture that concurrently accounts for

physical effects while optimizing the resulting design.

StarXtract[StarXtract]

Parasitic Extraction

With shrinking process technologies, increasing die size

and clock frequency, interconnect parasitic effects have

begun to manifest themselves in signal delay and noise.

Consequently, interconnects now play an important role in

the design flow. Today, IC design is interconnect-limited

and the design flow is interconnect-driven. Star-RCXT is a

parasitic extraction tool that models advanced process

effects and has the capacity to handle large designs with

tens of millions of transistors and cells.

PrimeTime

STA[pt_shell]

Static Timing Analysis

Timing analysis solution for gate-level designs featuring

comprehensive analysis including setup/hold/recovery,

parasitic or SDF delay annotations and many more (see

Synopsis product data sheet).

Design

Compiler[dc_shell-t]

RTL Synthesis

RTL synthesis solution that performs advanced arithmetic

optimisation, critical path synthesis, register retiming etc.

It enables a developer to optimise a design for timing,

area, power and test.

ASIC Design Flow Steps [Makefile targets] Synthesis Tool Descriptions

Floor Planning

Automatic Place & Route

init_chip chip

layout extract

layout chip

Power

Compiler

Power

Compiler

Power Optimisation & Analysis

Power Compiler performs both RTL and gate-level power

optimisation and gate-level power analysis. By applying

Power Compiler's various power reduction techniques,

including clock-gating, operand isolation, multivoltage

leakage power optimization, and gate-level power

optimization, you can achieve power savings, and area

and timing optimisation in the front-end synthesis domain.

Synthesis Tools

gdsii stream_out

Physical Verification

drc all

lvs all

package stream_out

Configures GDSII (Graphic Data System II) stream-out flow for design rule

checking and layout versus schematic verification.

Design Rule Checking determines whether a particular chip layout satisfies a

series of recommended parameters called design rules. Design rule checking is a

major step during physical verification of the design. Design Rules are a series of

parameters provided by semiconductor manufacturers that enable the designer to

verify the correctness of the mask set. Design rules are specific to a particular

semiconductor manufacturing process specifying certain geometric and

connectivity restrictions to ensure sufficient margins to account for variability in

semiconductor manufacturing processes, so as to ensure that most of the parts

work correctly.

Layout vs. Schematic is the class of electronic design automation verification

software that determines whether a particular integrated circuit layout corresponds

to the original schematic or circuit diagram of the design. LVS checking software

recognizes the drawn shapes of the layout that represent the electrical

components of the circuit, as well as the connections between them. The software

then compares them with the schematic or circuit diagram. Typical errors

encountered during LVS include: shorts, opens, component mismatches, missing

components, property errors.

Instantiates top-level package, inserts an instance of the final core cell into the

package, places point-to-point wires in the design to represent bond-wires.

Calibre[calibre]

Physical Verification

Mentor's Calibre tool is used for layout verification and

design rule checking.

Calibre[calibre]

sta check_setup

sta check_hold

sta typical

Timing Analysis

Research centre identities

Centre for Intelligent Systems& their Applications

Institute for Adaptive& Neural Computation

Institute for Communicating& Collaborative Systems

Institute for ComputingSystems Architecture

Institute of Perception,Action and Behaviour

e-Science Institute

Laboratory for Foundationsof Computer Science

Informatics Life-Sciences Institute

Performs initial virtual flat placement and then further refines and legalises the

floorplan. Power planning, virtual power network analysis, and global routing is also

performed.

Processor Automated Synthesis by iTerative Analysis Projecthttp://groups.inf.ed.ac.uk/pasta/

Tape-out

EDA Database[Synopsis Milkyway DB]

Floorplanning

GDS II OUT

RTL to Gates

Synthesis

RTL to Placed

Gates Synthesis

IC Layout

Parasitic

Extraction

Timing

Analysis

IP Libraries

VendorLibraries

RTLDatabase

Configuration

GDS II

Design Rule

Checking

Layout

vs.

Schematic

Start

EnCore - Calton Chip Layout

Tape-out

How to apply?

• STEP 3c: Discuss funding

‣ Ask your potential supervisor about funding opportunities - they may have money to spend, or ideas of studentships you could apply for

‣ There are lots of other sources of funding: check the Informatics website (university, SICSA, studentships for certain nationalities)

‣ If they tell you it’s unlikely you’ll get funding, don’t apply. It’s not worth it.

18

18

Identity development

Physical Layout

Gate-Level Netlist

RTL-DescriptionRTL Description

rtl_config config

Logic Synthesis

rtl2gates synth

floorplan floorplan

rtl2pg synth

rcxt spef

final_chip final_design

Pre-processing/Compiling of micro-code definitions and of Verilog files.

RTL-to-Gates synthesis flow takes a RTL HW description and a standard cell

library as input, and produces a gate-level netlist as output. The resulting gate-level

netlist is a completely structural description with only standard cells at the leaves of

the design. This step also creates a SAIF (Switching Activity Interchange Format)

forward-annotation file starting from the top level of the design.

Creates floorplan information including core size, placement sites, port locations,

RAM locations, as well as routing and placement obstructions.

RTL-to-placed-gates synthesis step capable of driving Design Compiler in

topographical mode to perform physical synthesis using floorplan physical

constraints. The design hierarchy is flattened partly to improve timing, but also to

ensure that the path to RAMs and pads is fixed to allow floorplanning scripts to

access them. At this step clock gating is applied and Power Compiler is enabled

(i.e. the max. dynamic and leakage power is set). Finally SDC (Synopsis Design

Constraint) files are post-processed for use with JupiterXT and Astro.

Astro Place&Route flow performs placement, clock tree synthesis, routing,

postrouting, and physical optimisation. Clock tree synthesis solves complicated

clock tree synthesis problems, such as blockage avoidance and the correlation

between prerouting and postrouting. Routing includes global routing, track

assignment, detail routing, and search-and-repair. After global routing, track

assignment, or detail routing, the design is optimised for timing and crosstalk.

Electric circuit extraction, also netlist extraction, is the translation of an IC layout

back into the electrical circuit (i.e. netlist) it is intended to represent. StarXtract

extracts parasitics into a centralised database so they can be used for circuit

simulation, static timing analysis, signal integrity, power analysis and optimisation,

and logic to layout comparison. Parasitic devices are devices which were not

explicitly intended by the designer but are inherent in the layout of the circuit.

SPEF: Standard Parasitic Exchange Format

Static timing analysis using PrimeTime generates static delay files for various

operating conditions. Integrated circuits exhibit different performance

characteristics for different operating conditions, fabrication process variations,

power supply voltage, and temperature.

- check_setup: gates_slow.sdf [worst op. condition]

- check_hold: gates_fast.sdf [best op. condition]

- typical: gates_typical.sdf [typical op. condition]

Defines top cell boundary, inserts all bond-pads, and inserts an instance of the final

core cell.

Design

Compiler[dc_shell-t]

JupiterXT[JupiterXT]

Astro[Astro]

StarXtract[StarXtract]

PrimeTime

STA[pt_shell]

EnCore Processor Design Flow

JupiterXT[JupiterXT]

SoC Hierarchical Design Planning

JupiterXT helps to partition the logical netlist into the best

physical hierarchy for optimised synthesis and physical

implementation.

Astro[Astro]

Physical Optimisation, Placement and Routing

Solution for SoC Designs

Numerous technology-dependent steps are required to

complete a complex, ultra-deep-submicron integrated

circuit (IC) design. Logic and interconnect delays must be

analysed and minimised. Physical effects such as signal

crosstalk, power density, and supply voltage drop must be

handled. Ideal clocks can no longer be assumed, and

clock skew must be minimized. Physical effects are

critical because changes to one may seriously impact the

optimization of others.

The Astro product is an advanced physical design system

for optimisation, placement and routing, using a

specialised architecture that concurrently accounts for

physical effects while optimizing the resulting design.

StarXtract[StarXtract]

Parasitic Extraction

With shrinking process technologies, increasing die size

and clock frequency, interconnect parasitic effects have

begun to manifest themselves in signal delay and noise.

Consequently, interconnects now play an important role in

the design flow. Today, IC design is interconnect-limited

and the design flow is interconnect-driven. Star-RCXT is a

parasitic extraction tool that models advanced process

effects and has the capacity to handle large designs with

tens of millions of transistors and cells.

PrimeTime

STA[pt_shell]

Static Timing Analysis

Timing analysis solution for gate-level designs featuring

comprehensive analysis including setup/hold/recovery,

parasitic or SDF delay annotations and many more (see

Synopsis product data sheet).

Design

Compiler[dc_shell-t]

RTL Synthesis

RTL synthesis solution that performs advanced arithmetic

optimisation, critical path synthesis, register retiming etc.

It enables a developer to optimise a design for timing,

area, power and test.

ASIC Design Flow Steps [Makefile targets] Synthesis Tool Descriptions

Floor Planning

Automatic Place & Route

init_chip chip

layout extract

layout chip

Power

Compiler

Power

Compiler

Power Optimisation & Analysis

Power Compiler performs both RTL and gate-level power

optimisation and gate-level power analysis. By applying

Power Compiler's various power reduction techniques,

including clock-gating, operand isolation, multivoltage

leakage power optimization, and gate-level power

optimization, you can achieve power savings, and area

and timing optimisation in the front-end synthesis domain.

Synthesis Tools

gdsii stream_out

Physical Verification

drc all

lvs all

package stream_out

Configures GDSII (Graphic Data System II) stream-out flow for design rule

checking and layout versus schematic verification.

Design Rule Checking determines whether a particular chip layout satisfies a

series of recommended parameters called design rules. Design rule checking is a

major step during physical verification of the design. Design Rules are a series of

parameters provided by semiconductor manufacturers that enable the designer to

verify the correctness of the mask set. Design rules are specific to a particular

semiconductor manufacturing process specifying certain geometric and

connectivity restrictions to ensure sufficient margins to account for variability in

semiconductor manufacturing processes, so as to ensure that most of the parts

work correctly.

Layout vs. Schematic is the class of electronic design automation verification

software that determines whether a particular integrated circuit layout corresponds

to the original schematic or circuit diagram of the design. LVS checking software

recognizes the drawn shapes of the layout that represent the electrical

components of the circuit, as well as the connections between them. The software

then compares them with the schematic or circuit diagram. Typical errors

encountered during LVS include: shorts, opens, component mismatches, missing

components, property errors.

Instantiates top-level package, inserts an instance of the final core cell into the

package, places point-to-point wires in the design to represent bond-wires.

Calibre[calibre]

Physical Verification

Mentor's Calibre tool is used for layout verification and

design rule checking.

Calibre[calibre]

sta check_setup

sta check_hold

sta typical

Timing Analysis

Research centre identities

Centre for Intelligent Systems& their Applications

Institute for Adaptive& Neural Computation

Institute for Communicating& Collaborative Systems

Institute for ComputingSystems Architecture

Institute of Perception,Action and Behaviour

e-Science Institute

Laboratory for Foundationsof Computer Science

Informatics Life-Sciences Institute

Performs initial virtual flat placement and then further refines and legalises the

floorplan. Power planning, virtual power network analysis, and global routing is also

performed.

Processor Automated Synthesis by iTerative Analysis Projecthttp://groups.inf.ed.ac.uk/pasta/

Tape-out

EDA Database[Synopsis Milkyway DB]

Floorplanning

GDS II OUT

RTL to Gates

Synthesis

RTL to Placed

Gates Synthesis

IC Layout

Parasitic

Extraction

Timing

Analysis

IP Libraries

VendorLibraries

RTLDatabase

Configuration

GDS II

Design Rule

Checking

Layout

vs.

Schematic

Start

EnCore - Calton Chip Layout

Tape-out

How to apply?

• STEP 3d: Get references

‣ Recommendation letters are a very important part of your application.

‣ You’ll need two, e.g. one from your personal tutor and one from your 4th year project supervisor.

‣ If you’ve done a research internship before, definitely get your supervisor to write a reference as they know best how you do in research.

19

19

Identity development

Physical Layout

Gate-Level Netlist

RTL-DescriptionRTL Description

rtl_config config

Logic Synthesis

rtl2gates synth

floorplan floorplan

rtl2pg synth

rcxt spef

final_chip final_design

Pre-processing/Compiling of micro-code definitions and of Verilog files.

RTL-to-Gates synthesis flow takes a RTL HW description and a standard cell

library as input, and produces a gate-level netlist as output. The resulting gate-level

netlist is a completely structural description with only standard cells at the leaves of

the design. This step also creates a SAIF (Switching Activity Interchange Format)

forward-annotation file starting from the top level of the design.

Creates floorplan information including core size, placement sites, port locations,

RAM locations, as well as routing and placement obstructions.

RTL-to-placed-gates synthesis step capable of driving Design Compiler in

topographical mode to perform physical synthesis using floorplan physical

constraints. The design hierarchy is flattened partly to improve timing, but also to

ensure that the path to RAMs and pads is fixed to allow floorplanning scripts to

access them. At this step clock gating is applied and Power Compiler is enabled

(i.e. the max. dynamic and leakage power is set). Finally SDC (Synopsis Design

Constraint) files are post-processed for use with JupiterXT and Astro.

Astro Place&Route flow performs placement, clock tree synthesis, routing,

postrouting, and physical optimisation. Clock tree synthesis solves complicated

clock tree synthesis problems, such as blockage avoidance and the correlation

between prerouting and postrouting. Routing includes global routing, track

assignment, detail routing, and search-and-repair. After global routing, track

assignment, or detail routing, the design is optimised for timing and crosstalk.

Electric circuit extraction, also netlist extraction, is the translation of an IC layout

back into the electrical circuit (i.e. netlist) it is intended to represent. StarXtract

extracts parasitics into a centralised database so they can be used for circuit

simulation, static timing analysis, signal integrity, power analysis and optimisation,

and logic to layout comparison. Parasitic devices are devices which were not

explicitly intended by the designer but are inherent in the layout of the circuit.

SPEF: Standard Parasitic Exchange Format

Static timing analysis using PrimeTime generates static delay files for various

operating conditions. Integrated circuits exhibit different performance

characteristics for different operating conditions, fabrication process variations,

power supply voltage, and temperature.

- check_setup: gates_slow.sdf [worst op. condition]

- check_hold: gates_fast.sdf [best op. condition]

- typical: gates_typical.sdf [typical op. condition]

Defines top cell boundary, inserts all bond-pads, and inserts an instance of the final

core cell.

Design

Compiler[dc_shell-t]

JupiterXT[JupiterXT]

Astro[Astro]

StarXtract[StarXtract]

PrimeTime

STA[pt_shell]

EnCore Processor Design Flow

JupiterXT[JupiterXT]

SoC Hierarchical Design Planning

JupiterXT helps to partition the logical netlist into the best

physical hierarchy for optimised synthesis and physical

implementation.

Astro[Astro]

Physical Optimisation, Placement and Routing

Solution for SoC Designs

Numerous technology-dependent steps are required to

complete a complex, ultra-deep-submicron integrated

circuit (IC) design. Logic and interconnect delays must be

analysed and minimised. Physical effects such as signal

crosstalk, power density, and supply voltage drop must be

handled. Ideal clocks can no longer be assumed, and

clock skew must be minimized. Physical effects are

critical because changes to one may seriously impact the

optimization of others.

The Astro product is an advanced physical design system

for optimisation, placement and routing, using a

specialised architecture that concurrently accounts for

physical effects while optimizing the resulting design.

StarXtract[StarXtract]

Parasitic Extraction

With shrinking process technologies, increasing die size

and clock frequency, interconnect parasitic effects have

begun to manifest themselves in signal delay and noise.

Consequently, interconnects now play an important role in

the design flow. Today, IC design is interconnect-limited

and the design flow is interconnect-driven. Star-RCXT is a

parasitic extraction tool that models advanced process

effects and has the capacity to handle large designs with

tens of millions of transistors and cells.

PrimeTime

STA[pt_shell]

Static Timing Analysis

Timing analysis solution for gate-level designs featuring

comprehensive analysis including setup/hold/recovery,

parasitic or SDF delay annotations and many more (see

Synopsis product data sheet).

Design

Compiler[dc_shell-t]

RTL Synthesis

RTL synthesis solution that performs advanced arithmetic

optimisation, critical path synthesis, register retiming etc.

It enables a developer to optimise a design for timing,

area, power and test.

ASIC Design Flow Steps [Makefile targets] Synthesis Tool Descriptions

Floor Planning

Automatic Place & Route

init_chip chip

layout extract

layout chip

Power

Compiler

Power

Compiler

Power Optimisation & Analysis

Power Compiler performs both RTL and gate-level power

optimisation and gate-level power analysis. By applying

Power Compiler's various power reduction techniques,

including clock-gating, operand isolation, multivoltage

leakage power optimization, and gate-level power

optimization, you can achieve power savings, and area

and timing optimisation in the front-end synthesis domain.

Synthesis Tools

gdsii stream_out

Physical Verification

drc all

lvs all

package stream_out

Configures GDSII (Graphic Data System II) stream-out flow for design rule

checking and layout versus schematic verification.

Design Rule Checking determines whether a particular chip layout satisfies a

series of recommended parameters called design rules. Design rule checking is a

major step during physical verification of the design. Design Rules are a series of

parameters provided by semiconductor manufacturers that enable the designer to

verify the correctness of the mask set. Design rules are specific to a particular

semiconductor manufacturing process specifying certain geometric and

connectivity restrictions to ensure sufficient margins to account for variability in

semiconductor manufacturing processes, so as to ensure that most of the parts

work correctly.

Layout vs. Schematic is the class of electronic design automation verification

software that determines whether a particular integrated circuit layout corresponds

to the original schematic or circuit diagram of the design. LVS checking software

recognizes the drawn shapes of the layout that represent the electrical

components of the circuit, as well as the connections between them. The software

then compares them with the schematic or circuit diagram. Typical errors

encountered during LVS include: shorts, opens, component mismatches, missing

components, property errors.

Instantiates top-level package, inserts an instance of the final core cell into the

package, places point-to-point wires in the design to represent bond-wires.

Calibre[calibre]

Physical Verification

Mentor's Calibre tool is used for layout verification and

design rule checking.

Calibre[calibre]

sta check_setup

sta check_hold

sta typical

Timing Analysis

Research centre identities

Centre for Intelligent Systems& their Applications

Institute for Adaptive& Neural Computation

Institute for Communicating& Collaborative Systems

Institute for ComputingSystems Architecture

Institute of Perception,Action and Behaviour

e-Science Institute

Laboratory for Foundationsof Computer Science

Informatics Life-Sciences Institute

Performs initial virtual flat placement and then further refines and legalises the

floorplan. Power planning, virtual power network analysis, and global routing is also

performed.

Processor Automated Synthesis by iTerative Analysis Projecthttp://groups.inf.ed.ac.uk/pasta/

Tape-out

EDA Database[Synopsis Milkyway DB]

Floorplanning

GDS II OUT

RTL to Gates

Synthesis

RTL to Placed

Gates Synthesis

IC Layout

Parasitic

Extraction

Timing

Analysis

IP Libraries

VendorLibraries

RTLDatabase

Configuration

GDS II

Design Rule

Checking

Layout

vs.

Schematic

Start

EnCore - Calton Chip Layout

Tape-out

How to apply?

• STEP 4: Submit your application(s)

‣ Final step - you’ve done all the hard work

‣ Try and do this by January/February for a September start

‣ Other start times possible, negotiate with potential supervisor(s)

20

20

Identity development

Physical Layout

Gate-Level Netlist

RTL-DescriptionRTL Description

rtl_config config

Logic Synthesis

rtl2gates synth

floorplan floorplan

rtl2pg synth

rcxt spef

final_chip final_design

Pre-processing/Compiling of micro-code definitions and of Verilog files.

RTL-to-Gates synthesis flow takes a RTL HW description and a standard cell

library as input, and produces a gate-level netlist as output. The resulting gate-level

netlist is a completely structural description with only standard cells at the leaves of

the design. This step also creates a SAIF (Switching Activity Interchange Format)

forward-annotation file starting from the top level of the design.

Creates floorplan information including core size, placement sites, port locations,

RAM locations, as well as routing and placement obstructions.

RTL-to-placed-gates synthesis step capable of driving Design Compiler in

topographical mode to perform physical synthesis using floorplan physical

constraints. The design hierarchy is flattened partly to improve timing, but also to

ensure that the path to RAMs and pads is fixed to allow floorplanning scripts to

access them. At this step clock gating is applied and Power Compiler is enabled

(i.e. the max. dynamic and leakage power is set). Finally SDC (Synopsis Design

Constraint) files are post-processed for use with JupiterXT and Astro.

Astro Place&Route flow performs placement, clock tree synthesis, routing,

postrouting, and physical optimisation. Clock tree synthesis solves complicated

clock tree synthesis problems, such as blockage avoidance and the correlation

between prerouting and postrouting. Routing includes global routing, track

assignment, detail routing, and search-and-repair. After global routing, track

assignment, or detail routing, the design is optimised for timing and crosstalk.

Electric circuit extraction, also netlist extraction, is the translation of an IC layout

back into the electrical circuit (i.e. netlist) it is intended to represent. StarXtract

extracts parasitics into a centralised database so they can be used for circuit

simulation, static timing analysis, signal integrity, power analysis and optimisation,

and logic to layout comparison. Parasitic devices are devices which were not

explicitly intended by the designer but are inherent in the layout of the circuit.

SPEF: Standard Parasitic Exchange Format

Static timing analysis using PrimeTime generates static delay files for various

operating conditions. Integrated circuits exhibit different performance

characteristics for different operating conditions, fabrication process variations,

power supply voltage, and temperature.

- check_setup: gates_slow.sdf [worst op. condition]

- check_hold: gates_fast.sdf [best op. condition]

- typical: gates_typical.sdf [typical op. condition]

Defines top cell boundary, inserts all bond-pads, and inserts an instance of the final

core cell.

Design

Compiler[dc_shell-t]

JupiterXT[JupiterXT]

Astro[Astro]

StarXtract[StarXtract]

PrimeTime

STA[pt_shell]

EnCore Processor Design Flow

JupiterXT[JupiterXT]

SoC Hierarchical Design Planning

JupiterXT helps to partition the logical netlist into the best

physical hierarchy for optimised synthesis and physical

implementation.

Astro[Astro]

Physical Optimisation, Placement and Routing

Solution for SoC Designs

Numerous technology-dependent steps are required to

complete a complex, ultra-deep-submicron integrated

circuit (IC) design. Logic and interconnect delays must be

analysed and minimised. Physical effects such as signal

crosstalk, power density, and supply voltage drop must be

handled. Ideal clocks can no longer be assumed, and

clock skew must be minimized. Physical effects are

critical because changes to one may seriously impact the

optimization of others.

The Astro product is an advanced physical design system

for optimisation, placement and routing, using a

specialised architecture that concurrently accounts for

physical effects while optimizing the resulting design.

StarXtract[StarXtract]

Parasitic Extraction

With shrinking process technologies, increasing die size

and clock frequency, interconnect parasitic effects have

begun to manifest themselves in signal delay and noise.

Consequently, interconnects now play an important role in

the design flow. Today, IC design is interconnect-limited

and the design flow is interconnect-driven. Star-RCXT is a

parasitic extraction tool that models advanced process

effects and has the capacity to handle large designs with

tens of millions of transistors and cells.

PrimeTime

STA[pt_shell]

Static Timing Analysis

Timing analysis solution for gate-level designs featuring

comprehensive analysis including setup/hold/recovery,

parasitic or SDF delay annotations and many more (see

Synopsis product data sheet).

Design

Compiler[dc_shell-t]

RTL Synthesis

RTL synthesis solution that performs advanced arithmetic

optimisation, critical path synthesis, register retiming etc.

It enables a developer to optimise a design for timing,

area, power and test.

ASIC Design Flow Steps [Makefile targets] Synthesis Tool Descriptions

Floor Planning

Automatic Place & Route

init_chip chip

layout extract

layout chip

Power

Compiler

Power

Compiler

Power Optimisation & Analysis

Power Compiler performs both RTL and gate-level power

optimisation and gate-level power analysis. By applying

Power Compiler's various power reduction techniques,

including clock-gating, operand isolation, multivoltage

leakage power optimization, and gate-level power

optimization, you can achieve power savings, and area

and timing optimisation in the front-end synthesis domain.

Synthesis Tools

gdsii stream_out

Physical Verification

drc all

lvs all

package stream_out

Configures GDSII (Graphic Data System II) stream-out flow for design rule

checking and layout versus schematic verification.

Design Rule Checking determines whether a particular chip layout satisfies a

series of recommended parameters called design rules. Design rule checking is a

major step during physical verification of the design. Design Rules are a series of

parameters provided by semiconductor manufacturers that enable the designer to

verify the correctness of the mask set. Design rules are specific to a particular

semiconductor manufacturing process specifying certain geometric and

connectivity restrictions to ensure sufficient margins to account for variability in

semiconductor manufacturing processes, so as to ensure that most of the parts

work correctly.

Layout vs. Schematic is the class of electronic design automation verification

software that determines whether a particular integrated circuit layout corresponds

to the original schematic or circuit diagram of the design. LVS checking software

recognizes the drawn shapes of the layout that represent the electrical

components of the circuit, as well as the connections between them. The software

then compares them with the schematic or circuit diagram. Typical errors

encountered during LVS include: shorts, opens, component mismatches, missing

components, property errors.

Instantiates top-level package, inserts an instance of the final core cell into the

package, places point-to-point wires in the design to represent bond-wires.

Calibre[calibre]

Physical Verification

Mentor's Calibre tool is used for layout verification and

design rule checking.

Calibre[calibre]

sta check_setup

sta check_hold

sta typical

Timing Analysis

Research centre identities

Centre for Intelligent Systems& their Applications

Institute for Adaptive& Neural Computation

Institute for Communicating& Collaborative Systems

Institute for ComputingSystems Architecture

Institute of Perception,Action and Behaviour

e-Science Institute

Laboratory for Foundationsof Computer Science

Informatics Life-Sciences Institute

Performs initial virtual flat placement and then further refines and legalises the

floorplan. Power planning, virtual power network analysis, and global routing is also

performed.

Processor Automated Synthesis by iTerative Analysis Projecthttp://groups.inf.ed.ac.uk/pasta/

Tape-out

EDA Database[Synopsis Milkyway DB]

Floorplanning

GDS II OUT

RTL to Gates

Synthesis

RTL to Placed

Gates Synthesis

IC Layout

Parasitic

Extraction

Timing

Analysis

IP Libraries

VendorLibraries

RTLDatabase

Configuration

GDS II

Design Rule

Checking

Layout

vs.

Schematic

Start

EnCore - Calton Chip Layout

Tape-out

How to apply?

• STEP 5: Wait for offer & funding

‣ Don’t be surprised if you get an offer for a place very quickly. Accept it. (This does not mean you actually have to come…)

‣ You’ll hear about funding by April/May. This is separate from your offer!

21

21

Identity development

Physical Layout

Gate-Level Netlist

RTL-DescriptionRTL Description

rtl_config config

Logic Synthesis

rtl2gates synth

floorplan floorplan

rtl2pg synth

rcxt spef

final_chip final_design

Pre-processing/Compiling of micro-code definitions and of Verilog files.

RTL-to-Gates synthesis flow takes a RTL HW description and a standard cell

library as input, and produces a gate-level netlist as output. The resulting gate-level

netlist is a completely structural description with only standard cells at the leaves of

the design. This step also creates a SAIF (Switching Activity Interchange Format)

forward-annotation file starting from the top level of the design.

Creates floorplan information including core size, placement sites, port locations,

RAM locations, as well as routing and placement obstructions.

RTL-to-placed-gates synthesis step capable of driving Design Compiler in

topographical mode to perform physical synthesis using floorplan physical

constraints. The design hierarchy is flattened partly to improve timing, but also to

ensure that the path to RAMs and pads is fixed to allow floorplanning scripts to

access them. At this step clock gating is applied and Power Compiler is enabled

(i.e. the max. dynamic and leakage power is set). Finally SDC (Synopsis Design

Constraint) files are post-processed for use with JupiterXT and Astro.

Astro Place&Route flow performs placement, clock tree synthesis, routing,

postrouting, and physical optimisation. Clock tree synthesis solves complicated

clock tree synthesis problems, such as blockage avoidance and the correlation

between prerouting and postrouting. Routing includes global routing, track

assignment, detail routing, and search-and-repair. After global routing, track

assignment, or detail routing, the design is optimised for timing and crosstalk.

Electric circuit extraction, also netlist extraction, is the translation of an IC layout

back into the electrical circuit (i.e. netlist) it is intended to represent. StarXtract

extracts parasitics into a centralised database so they can be used for circuit

simulation, static timing analysis, signal integrity, power analysis and optimisation,

and logic to layout comparison. Parasitic devices are devices which were not

explicitly intended by the designer but are inherent in the layout of the circuit.

SPEF: Standard Parasitic Exchange Format

Static timing analysis using PrimeTime generates static delay files for various

operating conditions. Integrated circuits exhibit different performance

characteristics for different operating conditions, fabrication process variations,

power supply voltage, and temperature.

- check_setup: gates_slow.sdf [worst op. condition]

- check_hold: gates_fast.sdf [best op. condition]

- typical: gates_typical.sdf [typical op. condition]

Defines top cell boundary, inserts all bond-pads, and inserts an instance of the final

core cell.

Design

Compiler[dc_shell-t]

JupiterXT[JupiterXT]

Astro[Astro]

StarXtract[StarXtract]

PrimeTime

STA[pt_shell]

EnCore Processor Design Flow

JupiterXT[JupiterXT]

SoC Hierarchical Design Planning

JupiterXT helps to partition the logical netlist into the best

physical hierarchy for optimised synthesis and physical

implementation.

Astro[Astro]

Physical Optimisation, Placement and Routing

Solution for SoC Designs

Numerous technology-dependent steps are required to

complete a complex, ultra-deep-submicron integrated

circuit (IC) design. Logic and interconnect delays must be

analysed and minimised. Physical effects such as signal

crosstalk, power density, and supply voltage drop must be

handled. Ideal clocks can no longer be assumed, and

clock skew must be minimized. Physical effects are

critical because changes to one may seriously impact the

optimization of others.

The Astro product is an advanced physical design system

for optimisation, placement and routing, using a

specialised architecture that concurrently accounts for

physical effects while optimizing the resulting design.

StarXtract[StarXtract]

Parasitic Extraction

With shrinking process technologies, increasing die size

and clock frequency, interconnect parasitic effects have

begun to manifest themselves in signal delay and noise.

Consequently, interconnects now play an important role in

the design flow. Today, IC design is interconnect-limited

and the design flow is interconnect-driven. Star-RCXT is a

parasitic extraction tool that models advanced process

effects and has the capacity to handle large designs with

tens of millions of transistors and cells.

PrimeTime

STA[pt_shell]

Static Timing Analysis

Timing analysis solution for gate-level designs featuring

comprehensive analysis including setup/hold/recovery,

parasitic or SDF delay annotations and many more (see

Synopsis product data sheet).

Design

Compiler[dc_shell-t]

RTL Synthesis

RTL synthesis solution that performs advanced arithmetic

optimisation, critical path synthesis, register retiming etc.

It enables a developer to optimise a design for timing,

area, power and test.

ASIC Design Flow Steps [Makefile targets] Synthesis Tool Descriptions

Floor Planning

Automatic Place & Route

init_chip chip

layout extract

layout chip

Power

Compiler

Power

Compiler

Power Optimisation & Analysis

Power Compiler performs both RTL and gate-level power

optimisation and gate-level power analysis. By applying

Power Compiler's various power reduction techniques,

including clock-gating, operand isolation, multivoltage

leakage power optimization, and gate-level power

optimization, you can achieve power savings, and area

and timing optimisation in the front-end synthesis domain.

Synthesis Tools

gdsii stream_out

Physical Verification

drc all

lvs all

package stream_out

Configures GDSII (Graphic Data System II) stream-out flow for design rule

checking and layout versus schematic verification.

Design Rule Checking determines whether a particular chip layout satisfies a

series of recommended parameters called design rules. Design rule checking is a

major step during physical verification of the design. Design Rules are a series of

parameters provided by semiconductor manufacturers that enable the designer to

verify the correctness of the mask set. Design rules are specific to a particular

semiconductor manufacturing process specifying certain geometric and

connectivity restrictions to ensure sufficient margins to account for variability in

semiconductor manufacturing processes, so as to ensure that most of the parts

work correctly.

Layout vs. Schematic is the class of electronic design automation verification

software that determines whether a particular integrated circuit layout corresponds

to the original schematic or circuit diagram of the design. LVS checking software

recognizes the drawn shapes of the layout that represent the electrical

components of the circuit, as well as the connections between them. The software

then compares them with the schematic or circuit diagram. Typical errors

encountered during LVS include: shorts, opens, component mismatches, missing

components, property errors.

Instantiates top-level package, inserts an instance of the final core cell into the

package, places point-to-point wires in the design to represent bond-wires.

Calibre[calibre]

Physical Verification

Mentor's Calibre tool is used for layout verification and

design rule checking.

Calibre[calibre]

sta check_setup

sta check_hold

sta typical

Timing Analysis

Research centre identities

Centre for Intelligent Systems& their Applications

Institute for Adaptive& Neural Computation

Institute for Communicating& Collaborative Systems

Institute for ComputingSystems Architecture

Institute of Perception,Action and Behaviour

e-Science Institute

Laboratory for Foundationsof Computer Science

Informatics Life-Sciences Institute

Performs initial virtual flat placement and then further refines and legalises the

floorplan. Power planning, virtual power network analysis, and global routing is also

performed.

Processor Automated Synthesis by iTerative Analysis Projecthttp://groups.inf.ed.ac.uk/pasta/

Tape-out

EDA Database[Synopsis Milkyway DB]

Floorplanning

GDS II OUT

RTL to Gates

Synthesis

RTL to Placed

Gates Synthesis

IC Layout

Parasitic

Extraction

Timing

Analysis

IP Libraries

VendorLibraries

RTLDatabase

Configuration

GDS II

Design Rule

Checking

Layout

vs.

Schematic

Start

EnCore - Calton Chip Layout

Tape-out

22

22

Identity development

Physical Layout

Gate-Level Netlist

RTL-DescriptionRTL Description

rtl_config config

Logic Synthesis

rtl2gates synth

floorplan floorplan

rtl2pg synth

rcxt spef

final_chip final_design

Pre-processing/Compiling of micro-code definitions and of Verilog files.

RTL-to-Gates synthesis flow takes a RTL HW description and a standard cell

library as input, and produces a gate-level netlist as output. The resulting gate-level

netlist is a completely structural description with only standard cells at the leaves of

the design. This step also creates a SAIF (Switching Activity Interchange Format)

forward-annotation file starting from the top level of the design.

Creates floorplan information including core size, placement sites, port locations,

RAM locations, as well as routing and placement obstructions.

RTL-to-placed-gates synthesis step capable of driving Design Compiler in

topographical mode to perform physical synthesis using floorplan physical

constraints. The design hierarchy is flattened partly to improve timing, but also to

ensure that the path to RAMs and pads is fixed to allow floorplanning scripts to

access them. At this step clock gating is applied and Power Compiler is enabled

(i.e. the max. dynamic and leakage power is set). Finally SDC (Synopsis Design

Constraint) files are post-processed for use with JupiterXT and Astro.

Astro Place&Route flow performs placement, clock tree synthesis, routing,

postrouting, and physical optimisation. Clock tree synthesis solves complicated

clock tree synthesis problems, such as blockage avoidance and the correlation

between prerouting and postrouting. Routing includes global routing, track

assignment, detail routing, and search-and-repair. After global routing, track

assignment, or detail routing, the design is optimised for timing and crosstalk.

Electric circuit extraction, also netlist extraction, is the translation of an IC layout

back into the electrical circuit (i.e. netlist) it is intended to represent. StarXtract

extracts parasitics into a centralised database so they can be used for circuit

simulation, static timing analysis, signal integrity, power analysis and optimisation,

and logic to layout comparison. Parasitic devices are devices which were not

explicitly intended by the designer but are inherent in the layout of the circuit.

SPEF: Standard Parasitic Exchange Format

Static timing analysis using PrimeTime generates static delay files for various

operating conditions. Integrated circuits exhibit different performance

characteristics for different operating conditions, fabrication process variations,

power supply voltage, and temperature.

- check_setup: gates_slow.sdf [worst op. condition]

- check_hold: gates_fast.sdf [best op. condition]

- typical: gates_typical.sdf [typical op. condition]

Defines top cell boundary, inserts all bond-pads, and inserts an instance of the final

core cell.

Design

Compiler[dc_shell-t]

JupiterXT[JupiterXT]

Astro[Astro]

StarXtract[StarXtract]

PrimeTime

STA[pt_shell]

EnCore Processor Design Flow

JupiterXT[JupiterXT]

SoC Hierarchical Design Planning

JupiterXT helps to partition the logical netlist into the best

physical hierarchy for optimised synthesis and physical

implementation.

Astro[Astro]

Physical Optimisation, Placement and Routing

Solution for SoC Designs

Numerous technology-dependent steps are required to

complete a complex, ultra-deep-submicron integrated

circuit (IC) design. Logic and interconnect delays must be

analysed and minimised. Physical effects such as signal

crosstalk, power density, and supply voltage drop must be

handled. Ideal clocks can no longer be assumed, and

clock skew must be minimized. Physical effects are

critical because changes to one may seriously impact the

optimization of others.

The Astro product is an advanced physical design system

for optimisation, placement and routing, using a

specialised architecture that concurrently accounts for

physical effects while optimizing the resulting design.

StarXtract[StarXtract]

Parasitic Extraction

With shrinking process technologies, increasing die size

and clock frequency, interconnect parasitic effects have

begun to manifest themselves in signal delay and noise.

Consequently, interconnects now play an important role in

the design flow. Today, IC design is interconnect-limited

and the design flow is interconnect-driven. Star-RCXT is a

parasitic extraction tool that models advanced process

effects and has the capacity to handle large designs with

tens of millions of transistors and cells.

PrimeTime

STA[pt_shell]

Static Timing Analysis

Timing analysis solution for gate-level designs featuring

comprehensive analysis including setup/hold/recovery,

parasitic or SDF delay annotations and many more (see

Synopsis product data sheet).

Design

Compiler[dc_shell-t]

RTL Synthesis

RTL synthesis solution that performs advanced arithmetic

optimisation, critical path synthesis, register retiming etc.

It enables a developer to optimise a design for timing,

area, power and test.

ASIC Design Flow Steps [Makefile targets] Synthesis Tool Descriptions

Floor Planning

Automatic Place & Route

init_chip chip

layout extract

layout chip

Power

Compiler

Power

Compiler

Power Optimisation & Analysis

Power Compiler performs both RTL and gate-level power

optimisation and gate-level power analysis. By applying

Power Compiler's various power reduction techniques,

including clock-gating, operand isolation, multivoltage

leakage power optimization, and gate-level power

optimization, you can achieve power savings, and area

and timing optimisation in the front-end synthesis domain.

Synthesis Tools

gdsii stream_out

Physical Verification

drc all

lvs all

package stream_out

Configures GDSII (Graphic Data System II) stream-out flow for design rule

checking and layout versus schematic verification.

Design Rule Checking determines whether a particular chip layout satisfies a

series of recommended parameters called design rules. Design rule checking is a

major step during physical verification of the design. Design Rules are a series of

parameters provided by semiconductor manufacturers that enable the designer to

verify the correctness of the mask set. Design rules are specific to a particular

semiconductor manufacturing process specifying certain geometric and

connectivity restrictions to ensure sufficient margins to account for variability in

semiconductor manufacturing processes, so as to ensure that most of the parts

work correctly.

Layout vs. Schematic is the class of electronic design automation verification

software that determines whether a particular integrated circuit layout corresponds

to the original schematic or circuit diagram of the design. LVS checking software

recognizes the drawn shapes of the layout that represent the electrical

components of the circuit, as well as the connections between them. The software

then compares them with the schematic or circuit diagram. Typical errors

encountered during LVS include: shorts, opens, component mismatches, missing

components, property errors.

Instantiates top-level package, inserts an instance of the final core cell into the

package, places point-to-point wires in the design to represent bond-wires.

Calibre[calibre]

Physical Verification

Mentor's Calibre tool is used for layout verification and

design rule checking.

Calibre[calibre]

sta check_setup

sta check_hold

sta typical

Timing Analysis

Research centre identities

Centre for Intelligent Systems& their Applications

Institute for Adaptive& Neural Computation

Institute for Communicating& Collaborative Systems

Institute for ComputingSystems Architecture

Institute of Perception,Action and Behaviour

e-Science Institute

Laboratory for Foundationsof Computer Science

Informatics Life-Sciences Institute

Performs initial virtual flat placement and then further refines and legalises the

floorplan. Power planning, virtual power network analysis, and global routing is also

performed.

Processor Automated Synthesis by iTerative Analysis Projecthttp://groups.inf.ed.ac.uk/pasta/

Tape-out

EDA Database[Synopsis Milkyway DB]

Floorplanning

GDS II OUT

RTL to Gates

Synthesis

RTL to Placed

Gates Synthesis

IC Layout

Parasitic

Extraction

Timing

Analysis

IP Libraries

VendorLibraries

RTLDatabase

Configuration

GDS II

Design Rule

Checking

Layout

vs.

Schematic

Start

EnCore - Calton Chip Layout

Tape-out

What do PhDs actually do?

• Goal: work towards your thesis, to be submitted within 5 years maximumFunding lasts for 3-3.5 years only!

• You get a desk and the equipment you need, with 24h access to the building

• Regular meetings with your supervisor

• But remember: you’re in charge! Nobody will check up on you, force you to do work, grade you, … This is not school!

23

23

Identity development

Physical Layout

Gate-Level Netlist

RTL-DescriptionRTL Description

rtl_config config

Logic Synthesis

rtl2gates synth

floorplan floorplan

rtl2pg synth

rcxt spef

final_chip final_design

Pre-processing/Compiling of micro-code definitions and of Verilog files.

RTL-to-Gates synthesis flow takes a RTL HW description and a standard cell

library as input, and produces a gate-level netlist as output. The resulting gate-level

netlist is a completely structural description with only standard cells at the leaves of

the design. This step also creates a SAIF (Switching Activity Interchange Format)

forward-annotation file starting from the top level of the design.

Creates floorplan information including core size, placement sites, port locations,

RAM locations, as well as routing and placement obstructions.

RTL-to-placed-gates synthesis step capable of driving Design Compiler in

topographical mode to perform physical synthesis using floorplan physical

constraints. The design hierarchy is flattened partly to improve timing, but also to

ensure that the path to RAMs and pads is fixed to allow floorplanning scripts to

access them. At this step clock gating is applied and Power Compiler is enabled

(i.e. the max. dynamic and leakage power is set). Finally SDC (Synopsis Design

Constraint) files are post-processed for use with JupiterXT and Astro.

Astro Place&Route flow performs placement, clock tree synthesis, routing,

postrouting, and physical optimisation. Clock tree synthesis solves complicated

clock tree synthesis problems, such as blockage avoidance and the correlation

between prerouting and postrouting. Routing includes global routing, track

assignment, detail routing, and search-and-repair. After global routing, track

assignment, or detail routing, the design is optimised for timing and crosstalk.

Electric circuit extraction, also netlist extraction, is the translation of an IC layout

back into the electrical circuit (i.e. netlist) it is intended to represent. StarXtract

extracts parasitics into a centralised database so they can be used for circuit

simulation, static timing analysis, signal integrity, power analysis and optimisation,

and logic to layout comparison. Parasitic devices are devices which were not

explicitly intended by the designer but are inherent in the layout of the circuit.

SPEF: Standard Parasitic Exchange Format

Static timing analysis using PrimeTime generates static delay files for various

operating conditions. Integrated circuits exhibit different performance

characteristics for different operating conditions, fabrication process variations,

power supply voltage, and temperature.

- check_setup: gates_slow.sdf [worst op. condition]

- check_hold: gates_fast.sdf [best op. condition]

- typical: gates_typical.sdf [typical op. condition]

Defines top cell boundary, inserts all bond-pads, and inserts an instance of the final

core cell.

Design

Compiler[dc_shell-t]

JupiterXT[JupiterXT]

Astro[Astro]

StarXtract[StarXtract]

PrimeTime

STA[pt_shell]

EnCore Processor Design Flow

JupiterXT[JupiterXT]

SoC Hierarchical Design Planning

JupiterXT helps to partition the logical netlist into the best

physical hierarchy for optimised synthesis and physical

implementation.

Astro[Astro]

Physical Optimisation, Placement and Routing

Solution for SoC Designs

Numerous technology-dependent steps are required to

complete a complex, ultra-deep-submicron integrated

circuit (IC) design. Logic and interconnect delays must be

analysed and minimised. Physical effects such as signal

crosstalk, power density, and supply voltage drop must be

handled. Ideal clocks can no longer be assumed, and

clock skew must be minimized. Physical effects are

critical because changes to one may seriously impact the

optimization of others.

The Astro product is an advanced physical design system

for optimisation, placement and routing, using a

specialised architecture that concurrently accounts for

physical effects while optimizing the resulting design.

StarXtract[StarXtract]

Parasitic Extraction

With shrinking process technologies, increasing die size

and clock frequency, interconnect parasitic effects have

begun to manifest themselves in signal delay and noise.

Consequently, interconnects now play an important role in

the design flow. Today, IC design is interconnect-limited

and the design flow is interconnect-driven. Star-RCXT is a

parasitic extraction tool that models advanced process

effects and has the capacity to handle large designs with

tens of millions of transistors and cells.

PrimeTime

STA[pt_shell]

Static Timing Analysis

Timing analysis solution for gate-level designs featuring

comprehensive analysis including setup/hold/recovery,

parasitic or SDF delay annotations and many more (see

Synopsis product data sheet).

Design

Compiler[dc_shell-t]

RTL Synthesis

RTL synthesis solution that performs advanced arithmetic

optimisation, critical path synthesis, register retiming etc.

It enables a developer to optimise a design for timing,

area, power and test.

ASIC Design Flow Steps [Makefile targets] Synthesis Tool Descriptions

Floor Planning

Automatic Place & Route

init_chip chip

layout extract

layout chip

Power

Compiler

Power

Compiler

Power Optimisation & Analysis

Power Compiler performs both RTL and gate-level power

optimisation and gate-level power analysis. By applying

Power Compiler's various power reduction techniques,

including clock-gating, operand isolation, multivoltage

leakage power optimization, and gate-level power

optimization, you can achieve power savings, and area

and timing optimisation in the front-end synthesis domain.

Synthesis Tools

gdsii stream_out

Physical Verification

drc all

lvs all

package stream_out

Configures GDSII (Graphic Data System II) stream-out flow for design rule

checking and layout versus schematic verification.

Design Rule Checking determines whether a particular chip layout satisfies a

series of recommended parameters called design rules. Design rule checking is a

major step during physical verification of the design. Design Rules are a series of

parameters provided by semiconductor manufacturers that enable the designer to

verify the correctness of the mask set. Design rules are specific to a particular

semiconductor manufacturing process specifying certain geometric and

connectivity restrictions to ensure sufficient margins to account for variability in

semiconductor manufacturing processes, so as to ensure that most of the parts

work correctly.

Layout vs. Schematic is the class of electronic design automation verification

software that determines whether a particular integrated circuit layout corresponds

to the original schematic or circuit diagram of the design. LVS checking software

recognizes the drawn shapes of the layout that represent the electrical

components of the circuit, as well as the connections between them. The software

then compares them with the schematic or circuit diagram. Typical errors

encountered during LVS include: shorts, opens, component mismatches, missing

components, property errors.

Instantiates top-level package, inserts an instance of the final core cell into the

package, places point-to-point wires in the design to represent bond-wires.

Calibre[calibre]

Physical Verification

Mentor's Calibre tool is used for layout verification and

design rule checking.

Calibre[calibre]

sta check_setup

sta check_hold

sta typical

Timing Analysis

Research centre identities

Centre for Intelligent Systems& their Applications

Institute for Adaptive& Neural Computation

Institute for Communicating& Collaborative Systems

Institute for ComputingSystems Architecture

Institute of Perception,Action and Behaviour

e-Science Institute

Laboratory for Foundationsof Computer Science

Informatics Life-Sciences Institute

Performs initial virtual flat placement and then further refines and legalises the

floorplan. Power planning, virtual power network analysis, and global routing is also

performed.

Processor Automated Synthesis by iTerative Analysis Projecthttp://groups.inf.ed.ac.uk/pasta/

Tape-out

EDA Database[Synopsis Milkyway DB]

Floorplanning

GDS II OUT

RTL to Gates

Synthesis

RTL to Placed

Gates Synthesis

IC Layout

Parasitic

Extraction

Timing

Analysis

IP Libraries

VendorLibraries

RTLDatabase

Configuration

GDS II

Design Rule

Checking

Layout

vs.

Schematic

Start

EnCore - Calton Chip Layout

Tape-out

What do PhDs actually do?

• You’re expected to publish a few papers during your PhD - university pays for trips to conferences to present them!

• Usually work towards milestones corresponding to papers you want to publish (conference deadlines!)

• Can do some teaching (tutorials, TAing) - it’s fun & paid extra

24

24

Identity development

Physical Layout

Gate-Level Netlist

RTL-DescriptionRTL Description

rtl_config config

Logic Synthesis

rtl2gates synth

floorplan floorplan

rtl2pg synth

rcxt spef

final_chip final_design

Pre-processing/Compiling of micro-code definitions and of Verilog files.

RTL-to-Gates synthesis flow takes a RTL HW description and a standard cell

library as input, and produces a gate-level netlist as output. The resulting gate-level

netlist is a completely structural description with only standard cells at the leaves of

the design. This step also creates a SAIF (Switching Activity Interchange Format)

forward-annotation file starting from the top level of the design.

Creates floorplan information including core size, placement sites, port locations,

RAM locations, as well as routing and placement obstructions.

RTL-to-placed-gates synthesis step capable of driving Design Compiler in

topographical mode to perform physical synthesis using floorplan physical

constraints. The design hierarchy is flattened partly to improve timing, but also to

ensure that the path to RAMs and pads is fixed to allow floorplanning scripts to

access them. At this step clock gating is applied and Power Compiler is enabled

(i.e. the max. dynamic and leakage power is set). Finally SDC (Synopsis Design

Constraint) files are post-processed for use with JupiterXT and Astro.

Astro Place&Route flow performs placement, clock tree synthesis, routing,

postrouting, and physical optimisation. Clock tree synthesis solves complicated

clock tree synthesis problems, such as blockage avoidance and the correlation

between prerouting and postrouting. Routing includes global routing, track

assignment, detail routing, and search-and-repair. After global routing, track

assignment, or detail routing, the design is optimised for timing and crosstalk.

Electric circuit extraction, also netlist extraction, is the translation of an IC layout

back into the electrical circuit (i.e. netlist) it is intended to represent. StarXtract

extracts parasitics into a centralised database so they can be used for circuit

simulation, static timing analysis, signal integrity, power analysis and optimisation,

and logic to layout comparison. Parasitic devices are devices which were not

explicitly intended by the designer but are inherent in the layout of the circuit.

SPEF: Standard Parasitic Exchange Format

Static timing analysis using PrimeTime generates static delay files for various

operating conditions. Integrated circuits exhibit different performance

characteristics for different operating conditions, fabrication process variations,

power supply voltage, and temperature.

- check_setup: gates_slow.sdf [worst op. condition]

- check_hold: gates_fast.sdf [best op. condition]

- typical: gates_typical.sdf [typical op. condition]

Defines top cell boundary, inserts all bond-pads, and inserts an instance of the final

core cell.

Design

Compiler[dc_shell-t]

JupiterXT[JupiterXT]

Astro[Astro]

StarXtract[StarXtract]

PrimeTime

STA[pt_shell]

EnCore Processor Design Flow

JupiterXT[JupiterXT]

SoC Hierarchical Design Planning

JupiterXT helps to partition the logical netlist into the best

physical hierarchy for optimised synthesis and physical

implementation.

Astro[Astro]

Physical Optimisation, Placement and Routing

Solution for SoC Designs

Numerous technology-dependent steps are required to

complete a complex, ultra-deep-submicron integrated

circuit (IC) design. Logic and interconnect delays must be

analysed and minimised. Physical effects such as signal

crosstalk, power density, and supply voltage drop must be

handled. Ideal clocks can no longer be assumed, and

clock skew must be minimized. Physical effects are

critical because changes to one may seriously impact the

optimization of others.

The Astro product is an advanced physical design system

for optimisation, placement and routing, using a

specialised architecture that concurrently accounts for

physical effects while optimizing the resulting design.

StarXtract[StarXtract]

Parasitic Extraction

With shrinking process technologies, increasing die size

and clock frequency, interconnect parasitic effects have

begun to manifest themselves in signal delay and noise.

Consequently, interconnects now play an important role in

the design flow. Today, IC design is interconnect-limited

and the design flow is interconnect-driven. Star-RCXT is a

parasitic extraction tool that models advanced process

effects and has the capacity to handle large designs with

tens of millions of transistors and cells.

PrimeTime

STA[pt_shell]

Static Timing Analysis

Timing analysis solution for gate-level designs featuring

comprehensive analysis including setup/hold/recovery,

parasitic or SDF delay annotations and many more (see

Synopsis product data sheet).

Design

Compiler[dc_shell-t]

RTL Synthesis

RTL synthesis solution that performs advanced arithmetic

optimisation, critical path synthesis, register retiming etc.

It enables a developer to optimise a design for timing,

area, power and test.

ASIC Design Flow Steps [Makefile targets] Synthesis Tool Descriptions

Floor Planning

Automatic Place & Route

init_chip chip

layout extract

layout chip

Power

Compiler

Power

Compiler

Power Optimisation & Analysis

Power Compiler performs both RTL and gate-level power

optimisation and gate-level power analysis. By applying

Power Compiler's various power reduction techniques,

including clock-gating, operand isolation, multivoltage

leakage power optimization, and gate-level power

optimization, you can achieve power savings, and area

and timing optimisation in the front-end synthesis domain.

Synthesis Tools

gdsii stream_out

Physical Verification

drc all

lvs all

package stream_out

Configures GDSII (Graphic Data System II) stream-out flow for design rule

checking and layout versus schematic verification.

Design Rule Checking determines whether a particular chip layout satisfies a

series of recommended parameters called design rules. Design rule checking is a

major step during physical verification of the design. Design Rules are a series of

parameters provided by semiconductor manufacturers that enable the designer to

verify the correctness of the mask set. Design rules are specific to a particular

semiconductor manufacturing process specifying certain geometric and

connectivity restrictions to ensure sufficient margins to account for variability in

semiconductor manufacturing processes, so as to ensure that most of the parts

work correctly.

Layout vs. Schematic is the class of electronic design automation verification

software that determines whether a particular integrated circuit layout corresponds

to the original schematic or circuit diagram of the design. LVS checking software

recognizes the drawn shapes of the layout that represent the electrical

components of the circuit, as well as the connections between them. The software

then compares them with the schematic or circuit diagram. Typical errors

encountered during LVS include: shorts, opens, component mismatches, missing

components, property errors.

Instantiates top-level package, inserts an instance of the final core cell into the

package, places point-to-point wires in the design to represent bond-wires.

Calibre[calibre]

Physical Verification

Mentor's Calibre tool is used for layout verification and

design rule checking.

Calibre[calibre]

sta check_setup

sta check_hold

sta typical

Timing Analysis

Research centre identities

Centre for Intelligent Systems& their Applications

Institute for Adaptive& Neural Computation

Institute for Communicating& Collaborative Systems

Institute for ComputingSystems Architecture

Institute of Perception,Action and Behaviour

e-Science Institute

Laboratory for Foundationsof Computer Science

Informatics Life-Sciences Institute

Performs initial virtual flat placement and then further refines and legalises the

floorplan. Power planning, virtual power network analysis, and global routing is also

performed.

Processor Automated Synthesis by iTerative Analysis Projecthttp://groups.inf.ed.ac.uk/pasta/

Tape-out

EDA Database[Synopsis Milkyway DB]

Floorplanning

GDS II OUT

RTL to Gates

Synthesis

RTL to Placed

Gates Synthesis

IC Layout

Parasitic

Extraction

Timing

Analysis

IP Libraries

VendorLibraries

RTLDatabase

Configuration

GDS II

Design Rule

Checking

Layout

vs.

Schematic

Start

EnCore - Calton Chip Layout

Tape-out

What do PhDs actually do?

• Internships are possible too - can interrupt your degree so you don’t lose time. Done this twice.

• At the end, submit thesis (after your supervisor OKed it!) and do your viva (3-6 hours; 1 external examiner, 2 local ones)

25

25

Identity development

Physical Layout

Gate-Level Netlist

RTL-DescriptionRTL Description

rtl_config config

Logic Synthesis

rtl2gates synth

floorplan floorplan

rtl2pg synth

rcxt spef

final_chip final_design

Pre-processing/Compiling of micro-code definitions and of Verilog files.

RTL-to-Gates synthesis flow takes a RTL HW description and a standard cell

library as input, and produces a gate-level netlist as output. The resulting gate-level

netlist is a completely structural description with only standard cells at the leaves of

the design. This step also creates a SAIF (Switching Activity Interchange Format)

forward-annotation file starting from the top level of the design.

Creates floorplan information including core size, placement sites, port locations,

RAM locations, as well as routing and placement obstructions.

RTL-to-placed-gates synthesis step capable of driving Design Compiler in

topographical mode to perform physical synthesis using floorplan physical

constraints. The design hierarchy is flattened partly to improve timing, but also to

ensure that the path to RAMs and pads is fixed to allow floorplanning scripts to

access them. At this step clock gating is applied and Power Compiler is enabled

(i.e. the max. dynamic and leakage power is set). Finally SDC (Synopsis Design

Constraint) files are post-processed for use with JupiterXT and Astro.

Astro Place&Route flow performs placement, clock tree synthesis, routing,

postrouting, and physical optimisation. Clock tree synthesis solves complicated

clock tree synthesis problems, such as blockage avoidance and the correlation

between prerouting and postrouting. Routing includes global routing, track

assignment, detail routing, and search-and-repair. After global routing, track

assignment, or detail routing, the design is optimised for timing and crosstalk.

Electric circuit extraction, also netlist extraction, is the translation of an IC layout

back into the electrical circuit (i.e. netlist) it is intended to represent. StarXtract

extracts parasitics into a centralised database so they can be used for circuit

simulation, static timing analysis, signal integrity, power analysis and optimisation,

and logic to layout comparison. Parasitic devices are devices which were not

explicitly intended by the designer but are inherent in the layout of the circuit.

SPEF: Standard Parasitic Exchange Format

Static timing analysis using PrimeTime generates static delay files for various

operating conditions. Integrated circuits exhibit different performance

characteristics for different operating conditions, fabrication process variations,

power supply voltage, and temperature.

- check_setup: gates_slow.sdf [worst op. condition]

- check_hold: gates_fast.sdf [best op. condition]

- typical: gates_typical.sdf [typical op. condition]

Defines top cell boundary, inserts all bond-pads, and inserts an instance of the final

core cell.

Design

Compiler[dc_shell-t]

JupiterXT[JupiterXT]

Astro[Astro]

StarXtract[StarXtract]

PrimeTime

STA[pt_shell]

EnCore Processor Design Flow

JupiterXT[JupiterXT]

SoC Hierarchical Design Planning

JupiterXT helps to partition the logical netlist into the best

physical hierarchy for optimised synthesis and physical

implementation.

Astro[Astro]

Physical Optimisation, Placement and Routing

Solution for SoC Designs

Numerous technology-dependent steps are required to

complete a complex, ultra-deep-submicron integrated

circuit (IC) design. Logic and interconnect delays must be

analysed and minimised. Physical effects such as signal

crosstalk, power density, and supply voltage drop must be

handled. Ideal clocks can no longer be assumed, and

clock skew must be minimized. Physical effects are

critical because changes to one may seriously impact the

optimization of others.

The Astro product is an advanced physical design system

for optimisation, placement and routing, using a

specialised architecture that concurrently accounts for

physical effects while optimizing the resulting design.

StarXtract[StarXtract]

Parasitic Extraction

With shrinking process technologies, increasing die size

and clock frequency, interconnect parasitic effects have

begun to manifest themselves in signal delay and noise.

Consequently, interconnects now play an important role in

the design flow. Today, IC design is interconnect-limited

and the design flow is interconnect-driven. Star-RCXT is a

parasitic extraction tool that models advanced process

effects and has the capacity to handle large designs with

tens of millions of transistors and cells.

PrimeTime

STA[pt_shell]

Static Timing Analysis

Timing analysis solution for gate-level designs featuring

comprehensive analysis including setup/hold/recovery,

parasitic or SDF delay annotations and many more (see

Synopsis product data sheet).

Design

Compiler[dc_shell-t]

RTL Synthesis

RTL synthesis solution that performs advanced arithmetic

optimisation, critical path synthesis, register retiming etc.

It enables a developer to optimise a design for timing,

area, power and test.

ASIC Design Flow Steps [Makefile targets] Synthesis Tool Descriptions

Floor Planning

Automatic Place & Route

init_chip chip

layout extract

layout chip

Power

Compiler

Power

Compiler

Power Optimisation & Analysis

Power Compiler performs both RTL and gate-level power

optimisation and gate-level power analysis. By applying

Power Compiler's various power reduction techniques,

including clock-gating, operand isolation, multivoltage

leakage power optimization, and gate-level power

optimization, you can achieve power savings, and area

and timing optimisation in the front-end synthesis domain.

Synthesis Tools

gdsii stream_out

Physical Verification

drc all

lvs all

package stream_out

Configures GDSII (Graphic Data System II) stream-out flow for design rule

checking and layout versus schematic verification.

Design Rule Checking determines whether a particular chip layout satisfies a

series of recommended parameters called design rules. Design rule checking is a

major step during physical verification of the design. Design Rules are a series of

parameters provided by semiconductor manufacturers that enable the designer to

verify the correctness of the mask set. Design rules are specific to a particular

semiconductor manufacturing process specifying certain geometric and

connectivity restrictions to ensure sufficient margins to account for variability in

semiconductor manufacturing processes, so as to ensure that most of the parts

work correctly.

Layout vs. Schematic is the class of electronic design automation verification

software that determines whether a particular integrated circuit layout corresponds

to the original schematic or circuit diagram of the design. LVS checking software

recognizes the drawn shapes of the layout that represent the electrical

components of the circuit, as well as the connections between them. The software

then compares them with the schematic or circuit diagram. Typical errors

encountered during LVS include: shorts, opens, component mismatches, missing

components, property errors.

Instantiates top-level package, inserts an instance of the final core cell into the

package, places point-to-point wires in the design to represent bond-wires.

Calibre[calibre]

Physical Verification

Mentor's Calibre tool is used for layout verification and

design rule checking.

Calibre[calibre]

sta check_setup

sta check_hold

sta typical

Timing Analysis

Research centre identities

Centre for Intelligent Systems& their Applications

Institute for Adaptive& Neural Computation

Institute for Communicating& Collaborative Systems

Institute for ComputingSystems Architecture

Institute of Perception,Action and Behaviour

e-Science Institute

Laboratory for Foundationsof Computer Science

Informatics Life-Sciences Institute

Performs initial virtual flat placement and then further refines and legalises the

floorplan. Power planning, virtual power network analysis, and global routing is also

performed.

Processor Automated Synthesis by iTerative Analysis Projecthttp://groups.inf.ed.ac.uk/pasta/

Tape-out

EDA Database[Synopsis Milkyway DB]

Floorplanning

GDS II OUT

RTL to Gates

Synthesis

RTL to Placed

Gates Synthesis

IC Layout

Parasitic

Extraction

Timing

Analysis

IP Libraries

VendorLibraries

RTLDatabase

Configuration

GDS II

Design Rule

Checking

Layout

vs.

Schematic

Start

EnCore - Calton Chip Layout

Tape-out

Career options

• Work in academia (end goal: lectureship)

‣ Do PostDoc(s) after your PhD. Apply for fellowships and grants…

• Work in industry

‣ Often start at more senior level and get paid better

‣ But beware: a PhD on its own might not improve your job prospects much…

26

26

Identity development

Physical Layout

Gate-Level Netlist

RTL-DescriptionRTL Description

rtl_config config

Logic Synthesis

rtl2gates synth

floorplan floorplan

rtl2pg synth

rcxt spef

final_chip final_design

Pre-processing/Compiling of micro-code definitions and of Verilog files.

RTL-to-Gates synthesis flow takes a RTL HW description and a standard cell

library as input, and produces a gate-level netlist as output. The resulting gate-level

netlist is a completely structural description with only standard cells at the leaves of

the design. This step also creates a SAIF (Switching Activity Interchange Format)

forward-annotation file starting from the top level of the design.

Creates floorplan information including core size, placement sites, port locations,

RAM locations, as well as routing and placement obstructions.

RTL-to-placed-gates synthesis step capable of driving Design Compiler in

topographical mode to perform physical synthesis using floorplan physical

constraints. The design hierarchy is flattened partly to improve timing, but also to

ensure that the path to RAMs and pads is fixed to allow floorplanning scripts to

access them. At this step clock gating is applied and Power Compiler is enabled

(i.e. the max. dynamic and leakage power is set). Finally SDC (Synopsis Design

Constraint) files are post-processed for use with JupiterXT and Astro.

Astro Place&Route flow performs placement, clock tree synthesis, routing,

postrouting, and physical optimisation. Clock tree synthesis solves complicated

clock tree synthesis problems, such as blockage avoidance and the correlation

between prerouting and postrouting. Routing includes global routing, track

assignment, detail routing, and search-and-repair. After global routing, track

assignment, or detail routing, the design is optimised for timing and crosstalk.

Electric circuit extraction, also netlist extraction, is the translation of an IC layout

back into the electrical circuit (i.e. netlist) it is intended to represent. StarXtract

extracts parasitics into a centralised database so they can be used for circuit

simulation, static timing analysis, signal integrity, power analysis and optimisation,

and logic to layout comparison. Parasitic devices are devices which were not

explicitly intended by the designer but are inherent in the layout of the circuit.

SPEF: Standard Parasitic Exchange Format

Static timing analysis using PrimeTime generates static delay files for various

operating conditions. Integrated circuits exhibit different performance

characteristics for different operating conditions, fabrication process variations,

power supply voltage, and temperature.

- check_setup: gates_slow.sdf [worst op. condition]

- check_hold: gates_fast.sdf [best op. condition]

- typical: gates_typical.sdf [typical op. condition]

Defines top cell boundary, inserts all bond-pads, and inserts an instance of the final

core cell.

Design

Compiler[dc_shell-t]

JupiterXT[JupiterXT]

Astro[Astro]

StarXtract[StarXtract]

PrimeTime

STA[pt_shell]

EnCore Processor Design Flow

JupiterXT[JupiterXT]

SoC Hierarchical Design Planning

JupiterXT helps to partition the logical netlist into the best

physical hierarchy for optimised synthesis and physical

implementation.

Astro[Astro]

Physical Optimisation, Placement and Routing

Solution for SoC Designs

Numerous technology-dependent steps are required to

complete a complex, ultra-deep-submicron integrated

circuit (IC) design. Logic and interconnect delays must be

analysed and minimised. Physical effects such as signal

crosstalk, power density, and supply voltage drop must be

handled. Ideal clocks can no longer be assumed, and

clock skew must be minimized. Physical effects are

critical because changes to one may seriously impact the

optimization of others.

The Astro product is an advanced physical design system

for optimisation, placement and routing, using a

specialised architecture that concurrently accounts for

physical effects while optimizing the resulting design.

StarXtract[StarXtract]

Parasitic Extraction

With shrinking process technologies, increasing die size

and clock frequency, interconnect parasitic effects have

begun to manifest themselves in signal delay and noise.

Consequently, interconnects now play an important role in

the design flow. Today, IC design is interconnect-limited

and the design flow is interconnect-driven. Star-RCXT is a

parasitic extraction tool that models advanced process

effects and has the capacity to handle large designs with

tens of millions of transistors and cells.

PrimeTime

STA[pt_shell]

Static Timing Analysis

Timing analysis solution for gate-level designs featuring

comprehensive analysis including setup/hold/recovery,

parasitic or SDF delay annotations and many more (see

Synopsis product data sheet).

Design

Compiler[dc_shell-t]

RTL Synthesis

RTL synthesis solution that performs advanced arithmetic

optimisation, critical path synthesis, register retiming etc.

It enables a developer to optimise a design for timing,

area, power and test.

ASIC Design Flow Steps [Makefile targets] Synthesis Tool Descriptions

Floor Planning

Automatic Place & Route

init_chip chip

layout extract

layout chip

Power

Compiler

Power

Compiler

Power Optimisation & Analysis

Power Compiler performs both RTL and gate-level power

optimisation and gate-level power analysis. By applying

Power Compiler's various power reduction techniques,

including clock-gating, operand isolation, multivoltage

leakage power optimization, and gate-level power

optimization, you can achieve power savings, and area

and timing optimisation in the front-end synthesis domain.

Synthesis Tools

gdsii stream_out

Physical Verification

drc all

lvs all

package stream_out

Configures GDSII (Graphic Data System II) stream-out flow for design rule

checking and layout versus schematic verification.

Design Rule Checking determines whether a particular chip layout satisfies a

series of recommended parameters called design rules. Design rule checking is a

major step during physical verification of the design. Design Rules are a series of

parameters provided by semiconductor manufacturers that enable the designer to

verify the correctness of the mask set. Design rules are specific to a particular

semiconductor manufacturing process specifying certain geometric and

connectivity restrictions to ensure sufficient margins to account for variability in

semiconductor manufacturing processes, so as to ensure that most of the parts

work correctly.

Layout vs. Schematic is the class of electronic design automation verification

software that determines whether a particular integrated circuit layout corresponds

to the original schematic or circuit diagram of the design. LVS checking software

recognizes the drawn shapes of the layout that represent the electrical

components of the circuit, as well as the connections between them. The software

then compares them with the schematic or circuit diagram. Typical errors

encountered during LVS include: shorts, opens, component mismatches, missing

components, property errors.

Instantiates top-level package, inserts an instance of the final core cell into the

package, places point-to-point wires in the design to represent bond-wires.

Calibre[calibre]

Physical Verification

Mentor's Calibre tool is used for layout verification and

design rule checking.

Calibre[calibre]

sta check_setup

sta check_hold

sta typical

Timing Analysis

Research centre identities

Centre for Intelligent Systems& their Applications

Institute for Adaptive& Neural Computation

Institute for Communicating& Collaborative Systems

Institute for ComputingSystems Architecture

Institute of Perception,Action and Behaviour

e-Science Institute

Laboratory for Foundationsof Computer Science

Informatics Life-Sciences Institute

Performs initial virtual flat placement and then further refines and legalises the

floorplan. Power planning, virtual power network analysis, and global routing is also

performed.

Processor Automated Synthesis by iTerative Analysis Projecthttp://groups.inf.ed.ac.uk/pasta/

Tape-out

EDA Database[Synopsis Milkyway DB]

Floorplanning

GDS II OUT

RTL to Gates

Synthesis

RTL to Placed

Gates Synthesis

IC Layout

Parasitic

Extraction

Timing

Analysis

IP Libraries

VendorLibraries

RTLDatabase

Configuration

GDS II

Design Rule

Checking

Layout

vs.

Schematic

Start

EnCore - Calton Chip Layout

Tape-out

Why Edinburgh?

• One of the largest parallel computing research groups in the UK and Europe

• Track record of ground-breaking work published at major international conferences (PLDI, ISCA, PACT, MICRO)

• SICSA provides network for collaboration with researchers across Scotland

27

27

Identity development

Physical Layout

Gate-Level Netlist

RTL-DescriptionRTL Description

rtl_config config

Logic Synthesis

rtl2gates synth

floorplan floorplan

rtl2pg synth

rcxt spef

final_chip final_design

Pre-processing/Compiling of micro-code definitions and of Verilog files.

RTL-to-Gates synthesis flow takes a RTL HW description and a standard cell

library as input, and produces a gate-level netlist as output. The resulting gate-level

netlist is a completely structural description with only standard cells at the leaves of

the design. This step also creates a SAIF (Switching Activity Interchange Format)

forward-annotation file starting from the top level of the design.

Creates floorplan information including core size, placement sites, port locations,

RAM locations, as well as routing and placement obstructions.

RTL-to-placed-gates synthesis step capable of driving Design Compiler in

topographical mode to perform physical synthesis using floorplan physical

constraints. The design hierarchy is flattened partly to improve timing, but also to

ensure that the path to RAMs and pads is fixed to allow floorplanning scripts to

access them. At this step clock gating is applied and Power Compiler is enabled

(i.e. the max. dynamic and leakage power is set). Finally SDC (Synopsis Design

Constraint) files are post-processed for use with JupiterXT and Astro.

Astro Place&Route flow performs placement, clock tree synthesis, routing,

postrouting, and physical optimisation. Clock tree synthesis solves complicated

clock tree synthesis problems, such as blockage avoidance and the correlation

between prerouting and postrouting. Routing includes global routing, track

assignment, detail routing, and search-and-repair. After global routing, track

assignment, or detail routing, the design is optimised for timing and crosstalk.

Electric circuit extraction, also netlist extraction, is the translation of an IC layout

back into the electrical circuit (i.e. netlist) it is intended to represent. StarXtract

extracts parasitics into a centralised database so they can be used for circuit

simulation, static timing analysis, signal integrity, power analysis and optimisation,

and logic to layout comparison. Parasitic devices are devices which were not

explicitly intended by the designer but are inherent in the layout of the circuit.

SPEF: Standard Parasitic Exchange Format

Static timing analysis using PrimeTime generates static delay files for various

operating conditions. Integrated circuits exhibit different performance

characteristics for different operating conditions, fabrication process variations,

power supply voltage, and temperature.

- check_setup: gates_slow.sdf [worst op. condition]

- check_hold: gates_fast.sdf [best op. condition]

- typical: gates_typical.sdf [typical op. condition]

Defines top cell boundary, inserts all bond-pads, and inserts an instance of the final

core cell.

Design

Compiler[dc_shell-t]

JupiterXT[JupiterXT]

Astro[Astro]

StarXtract[StarXtract]

PrimeTime

STA[pt_shell]

EnCore Processor Design Flow

JupiterXT[JupiterXT]

SoC Hierarchical Design Planning

JupiterXT helps to partition the logical netlist into the best

physical hierarchy for optimised synthesis and physical

implementation.

Astro[Astro]

Physical Optimisation, Placement and Routing

Solution for SoC Designs

Numerous technology-dependent steps are required to

complete a complex, ultra-deep-submicron integrated

circuit (IC) design. Logic and interconnect delays must be

analysed and minimised. Physical effects such as signal

crosstalk, power density, and supply voltage drop must be

handled. Ideal clocks can no longer be assumed, and

clock skew must be minimized. Physical effects are

critical because changes to one may seriously impact the

optimization of others.

The Astro product is an advanced physical design system

for optimisation, placement and routing, using a

specialised architecture that concurrently accounts for

physical effects while optimizing the resulting design.

StarXtract[StarXtract]

Parasitic Extraction

With shrinking process technologies, increasing die size

and clock frequency, interconnect parasitic effects have

begun to manifest themselves in signal delay and noise.

Consequently, interconnects now play an important role in

the design flow. Today, IC design is interconnect-limited

and the design flow is interconnect-driven. Star-RCXT is a

parasitic extraction tool that models advanced process

effects and has the capacity to handle large designs with

tens of millions of transistors and cells.

PrimeTime

STA[pt_shell]

Static Timing Analysis

Timing analysis solution for gate-level designs featuring

comprehensive analysis including setup/hold/recovery,

parasitic or SDF delay annotations and many more (see

Synopsis product data sheet).

Design

Compiler[dc_shell-t]

RTL Synthesis

RTL synthesis solution that performs advanced arithmetic

optimisation, critical path synthesis, register retiming etc.

It enables a developer to optimise a design for timing,

area, power and test.

ASIC Design Flow Steps [Makefile targets] Synthesis Tool Descriptions

Floor Planning

Automatic Place & Route

init_chip chip

layout extract

layout chip

Power

Compiler

Power

Compiler

Power Optimisation & Analysis

Power Compiler performs both RTL and gate-level power

optimisation and gate-level power analysis. By applying

Power Compiler's various power reduction techniques,

including clock-gating, operand isolation, multivoltage

leakage power optimization, and gate-level power

optimization, you can achieve power savings, and area

and timing optimisation in the front-end synthesis domain.

Synthesis Tools

gdsii stream_out

Physical Verification

drc all

lvs all

package stream_out

Configures GDSII (Graphic Data System II) stream-out flow for design rule

checking and layout versus schematic verification.

Design Rule Checking determines whether a particular chip layout satisfies a

series of recommended parameters called design rules. Design rule checking is a

major step during physical verification of the design. Design Rules are a series of

parameters provided by semiconductor manufacturers that enable the designer to

verify the correctness of the mask set. Design rules are specific to a particular

semiconductor manufacturing process specifying certain geometric and

connectivity restrictions to ensure sufficient margins to account for variability in

semiconductor manufacturing processes, so as to ensure that most of the parts

work correctly.

Layout vs. Schematic is the class of electronic design automation verification

software that determines whether a particular integrated circuit layout corresponds

to the original schematic or circuit diagram of the design. LVS checking software

recognizes the drawn shapes of the layout that represent the electrical

components of the circuit, as well as the connections between them. The software

then compares them with the schematic or circuit diagram. Typical errors

encountered during LVS include: shorts, opens, component mismatches, missing

components, property errors.

Instantiates top-level package, inserts an instance of the final core cell into the

package, places point-to-point wires in the design to represent bond-wires.

Calibre[calibre]

Physical Verification

Mentor's Calibre tool is used for layout verification and

design rule checking.

Calibre[calibre]

sta check_setup

sta check_hold

sta typical

Timing Analysis

Research centre identities

Centre for Intelligent Systems& their Applications

Institute for Adaptive& Neural Computation

Institute for Communicating& Collaborative Systems

Institute for ComputingSystems Architecture

Institute of Perception,Action and Behaviour

e-Science Institute

Laboratory for Foundationsof Computer Science

Informatics Life-Sciences Institute

Performs initial virtual flat placement and then further refines and legalises the

floorplan. Power planning, virtual power network analysis, and global routing is also

performed.

Processor Automated Synthesis by iTerative Analysis Projecthttp://groups.inf.ed.ac.uk/pasta/

Tape-out

EDA Database[Synopsis Milkyway DB]

Floorplanning

GDS II OUT

RTL to Gates

Synthesis

RTL to Placed

Gates Synthesis

IC Layout

Parasitic

Extraction

Timing

Analysis

IP Libraries

VendorLibraries

RTLDatabase

Configuration

GDS II

Design Rule

Checking

Layout

vs.

Schematic

Start

EnCore - Calton Chip Layout

Tape-out

Please fill in the feedback forms!

Questions?Contact me:

t.v.koch@ed.ac.uk

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Find out more:

www.icsa.inf.ed.ac.uk/compilers

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