ti jtag seminar

Topic 8 - JTAG Boundary Scan

JTAG (IEEE 1149.1/P1149.4) Tutorial - Introductory


Agenda

JTAG(IEEE 1149.1/P1149.4)

Tutorial IntroductoryAL 10Sept.-97 1149.1(JTAG)-Tut.I-1

What Is JTAG? The Increasing Problem of Test Conventional Methods of Test The Boundary-Scan Idea The Boundary-Scan Architecture Typical Applications

(5 minutes) (5 minutes) (10 minutes) (15 minutes) (15 minutes) (15 minutes)

Interconnect Testing Logic Cluster Testing Memory Testing System-Level Test

Real JTAG Applications For More Information Q&A

(10 minutes) (5 minutes) (10 minutes)1997 TI Test SymposiumJTAG (IEEE 1149.1/P1149.4) Tutorial - Introductory

1997 TI Test SymposiumJTAG (IEEE 1149.1/P1149.4) Tutorial - Introductory

AL 10Sept.-97 1149.1(JTAG)-Tut.I-2

Standard Approach To Test

What Is JTAG?

JTAG / IEEE 1149.1

Developed by Joint Test Action Group (over 200 SC, test, and system vendors) starting in mid '80's Sanctioned by IEEE as Std 1149.1 Test Access Port and Boundary-Scan Architecture in 1990 Solution: Build test facilities/test points into chips Focus: Ensure compatibility between all compliant ICs1997 TI Test SymposiumJTAG (IEEE 1149.1/P1149.4) Tutorial - Introductory




Standard Test Access Port ...User Register TDI Bypass Register TMS TCK TAP Controller DR IR Decode Logic Instruction Register TDO

and Boundary-Scan Architecture

CORE

Scan effectively partitions digital logic to facilitate control and observation of its function Chip-Internal Scan: Partitions chips at storage cells (latches/ flipflops) to effectively partition sequential logic into clusters of combinational logic Boundary-Scan: Partitions boards at chip I/Os for control and observation of board-level nodes

TRST*

4/5-Wire Interface at Chip-Level Serial Instruction/Serial Data Port Extensible to Include user-defined instructions user-defined data registers1997 TI Test SymposiumAL 10Sept.-97 1149.1(JTAG)-Tut.I-6


1997 TI Test Symposium



The Incredible Shrinking Board

Miniaturization results in loss of test access

The Increasing Problem of TestYest day erAL 10Sept.-97 1149.1(JTAG)-Tut.I-7

Today

Tom or ow ? r1997 TI Test Symposium




The Ever-Expanding Chip

Cant Afford Not To TestCost will increase by a factor of ten as fault finding moves from one level of complexity to the next. The result:

Increasing integration at chip level complicates controllability

Reduced Profit Margins Delayed Product Introduction Dissatisfied Customers

1

0

1C1 1D C1 1D

?

Yest day erAL 10Sept.-97 1149.1(JTAG)-Tut.I-9

Today1997 TI Test SymposiumJTAG (IEEE 1149.1/P1149.4) Tutorial - IntroductoryAL 10Sept.-97 1149.1(JTAG)-Tut.I-10

1. 2. 3. 4.

Device level Board level System level Field level

1 unit of cost 10 units of cost 100 units of cost 1,000 units of cost1997 TI Test SymposiumJTAG (IEEE 1149.1/P1149.4) Tutorial - Introductory

Conventional Methods of Board Test

Conventional Methods of TestAL 10Sept.-97 1149.1(JTAG)-Tut.I-11

Functional Test (Edge-Connector Test)

Based on board function, rather than structure Test generation primarily manual Test access limited to primary I/O only






Conventional Methods of Board TestIn-Circuit Test (Bed-of-Nails Test)

Conventional Methods of Board TestIn-Circuit Test (Bed-of-Nails Test)

Based on board structure, but limited by chip complexity Expensive testers and fixtures required Test access limited by: Fine pitch packages Double-sided boards Conformal coating MCMs

Chip function can be ignored for shorts testing Chip function must be considered for continuity test Test generation, though automated, requires ICT models





The Boundary Scan Idea

The Boundary-Scan IdeaAL 10Sept.-97 1149.1(JTAG)-Tut.I-15

In-Circuit test points moved onto the silicon, creating Virtual Nails Boundary scan cells bound each net, providing for continuity testing Observe/Control cells provide for test and normal function

CORE

CORE




The Boundary Scan IdeaCORE CORE

Boundary Scan Method of Board TestCORE CORE

Scan provides a means to arbitrarily observe test results and source test stimulus Scan method requires minimal on chip/board resources (pins/nets)

Based on board structure; Not limited by chip function/ complexity Test access is not limited by board physical factors

CORE

CORE

CORE

CORE

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Boundary Scan Method of Board Test

The Boundary Scan CellNI (Normal Input) SO (Serial Output)OBSERVE CONTROLTEST/DATA MUX

Chip function need not be considered for board test (shorted/open nets) Test generation is highly automated; Simple In-Circuit Library models (BSDL) are vendorsupplied or EDA-generatedCORE

NO (Normal Output)

CAPTURE/SCAN MUX

SCAN LATCH/FLOP

UPDATE LATCH/FLOP

SI (Serial Input)





The Control Architecture

The Test Access Port Controller1 Test Logic Reset 0 1 0 Run Test/IdleSelect DR-Scan

Boundary scan and other test data registers operate under control of instruction register Data is scanned from TDI to TDO through selected test data register or instruction register under control of Test Access Port (TAP) controller TAP operates synchronously to TCK using TMS for state selection

1

Select IR-Scan

1

0Capture DR

0 1 1Capture-IR

0 state transitions occur on rising edge of TCK based on the current state and the TMS input value ONLY 0 1Shift-DR

0Shift-IR

CORE

0 1

1Exit 1-DR

1Exit 1-IR

16-state TAP provides 4 major operations: RESET RUN-TEST SCAN-DR SCAN-IR Scans consist of 3 primary steps: CAPTURE SHIFT UPDATE

0 0Pause-DR

0Pause-IR

ID Register TDI Bypass Register TMS TCK TAP Controller DR IR Decode Logic Instruction Register

TDO

0

1Exit 2-DR

1 0 0Exit 2-IR

1Update-DR

1Update-IR

1

0

1

0





The Extest Instruction(REQUIRED)

The Sample/Preload Instruction(REQUIRED)

Provides for test external to chip, such as interconnect test Output pins operate in test mode, driven from contents of BSC update latch

Provides means to preload boundary before entry to test mode Output and input pins operate in normal mode Input pin data and core logic output data captured in BSC scan latches

COREID Register TDI Bypass Register TMS TCK TAP Controller DR IR Decode Logic Instruction Register TDO

Input data captured in BSC scan latches prior to shift operation Shift operation allows test response to be observed at TDO while next test stimulus inserted at TDI Following shift operation, new test stimulus transferred to BSC update latches

CORE

ID Register TDI Bypass Register TMS TCK TAP Controller DR IR Decode Logic Instruction Register TDO

Shift operation allows test response to be observed while next test stimulus inserted at TDI Following shift operation, new stimulus transferred to BSC update latches







The Bypass Instruction(REQUIRED)

Provides for abbreviated scan path through chip Output and input pins operate in normal mode The one-bit bypass register is selected for scans Mandatory that an all-ones value updated into the IR decodes to Bypass, as well as any opcodes which are otherwise undefined1997 TI Test Symposium

CORE

ID Register TDI Bypass Register TMS TCK DR TAP IR Controller Decode Logic Instruction Register TDO

Typical JTAG Applications





Interconnect TestFull B/S Board

Interconnect TestPartial B/S Board

All nets bound by BSC's and/or primary I/O requiring no physical access Parallel access reduced to card edge only Test generation and application fast and easyJ T A G

Not all nets are bound by boundary scan and/or primary I/O, perhaps requiring some ICT access Expense and complexity reduced for test generation and test application for chips/nets with B/S access Cluster testing may be used to access non-scan nets1997 TI Test Symposium

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Logic Cluster Test

Logic Cluster TestBuffer Latch

LVT18502

Random-logic cluster is bound by boundaryscannable chipsMicroprocessor

ABT18502

Address Memory Array Control

LOGIC "CLUSTER"

Test response can be captured at B/S inputs BIST methods (PRPG/PSA) can be used for increased test throughput and near "At-speed" performanceBuffer

LVT18502

Deterministic test stimulus (ATPG-generated) can be driven to cluster from B/S outputs

Buffer

Control Logic (Non-Scan)

Buffer

Registered Transceiver

ABT18502

LVT18504

LVT18502 Scan Path IEEE 1149.1 Parallel Data InTCK TDO TDI TMS

Data







Memory TestLatch

Memory TestSN74BCT8245 1A1 1B1 1B2 1A2 1B3 1A3 1B4 1A4 2A1 2B1 2B2 2A2 2B3 2A3 2B4 2A4 DIR G TDO TMS TDI TCK 256 x 8 RAM Array D0 A0 D1 A1 D2 A2 D3 A3 D4 A4 D5 A5 D6 A6 D7 A7 WE CS TDO TMS SN74BCT8244 1Y1 1A1 1Y2 1A2 1Y3 1A3 1Y4 1A4 2Y1 2A1 2Y2 2A2 2Y3 2A3 2Y4 2A4 G2 G1 TDI TCK

ABT18502

Address

Memory array bound by boundary scan chips Automatic test patterns can be generated and driven from B/S outputs Test response can be captured at B/S inputs Transceivers can test for net shorts w/o memory R/W BIST methods (PRPG/PSA) can be used for increased test throughput

Buffer

Memory Array

ABT18502

Control

Registered Transceiver

LVT18504

Data

SN74BCT8244 1A1 1Y1 1Y2 1A2 1Y3 1A3 1Y4 1A4 2Y1 2A1 2Y2 2A2 2Y3 2A3 2Y4 2A4 G2 G1 TDO TMS TDI TCK

MODE IEEE 1149.1 EXTEST & SAMPLE) IEEE 1149.1 (with BIST capability) Time To Apply Scans Patterns Time To Apply Scans Patterns

256 ACCESSES 5.625000 Seconds 512 512 0.000041 Seconds 7 512

1,000,000 ACCESSES 375.00 Minutes 2,000,000 2,000,000 < 0.01 Minutes 28,000 2,000,000





System-Level Test

TAP-addressable interface unit extends JTAG access beyond board-level System-level test System design verification Sys integration (Mfg test) Sys self-test (Field Svc) Supports in place board test and board-to-board test Allows reuse of device/ board test data

A S P A S P A S P

TDO TDI TMS TCK

Real JTAG Applications

ASP-Addressable Scan Port DeviceAL 10Sept.-97 1149.1(JTAG)-Tut.I-33




Real Applications of the TAPI N S T C E A T R N E S T N A L

Design Verification/Debug

COREBIST Emulation Programming TAP TDI TCK TMS TDO

Scan access to chips, boards, systems for: Design verification/debug Manufacturing test Hardware/software integration Field test/diagnostics Access built-in self-test (BIST) Access on-chip/in-circuit emulation (ONCE/ICE) Access in-system programming (ISP) of PLDs/EEPROMs Let your imagination run wild!!!

Provides control and observation of system under test without need for physical access Ease of set-up for test

Can be used in standard system configuration (no need for card extenders, etc.) Can be used in environmental chambers Can access on-chip emulation for software/debug Can access ISP for code download/offload/ changes1997 TI Test Symposium

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Manufacturing Test

System Configuration Maintenance

ICT

Provides test and diagnostic capabilities of in-circuit test without need/expense of physical access Improved fault coverage/diagnostic without large capital expense Highly automated test generation reduces test development time

J T A G

Provides low-level test access within configured systems for: In-house system integration Fielded-system test and diagnostics Built-in self-test In-field upgradability via ISP, etc. Remote field test, diagnostic and upgrade

J T A G





TIs JTAG Educational ProductsCall (214)-638-0333 to ORDER

IEEE StandardsCall (800) 678-IEEE to ORDER

Scan Educator PC-based tutorial with interactive boundary-scan simulation. FREE download at http://www.ti.com/sc/data/jtag/scanedu.exe IEEE 1149.1 Testability videotapes Two-part video presenting an overview and instructions for boundary scan. Item No. SATV001 (NTSC VHS) and SATV002 (PAL VHS), $149 each. In process of converting to MPEG on CD-ROM

IEEE Std 1149.1-1990 (Includes IEEE Std 1149.1a-1993), IEEE Standard Test Access Port and Boundary-Scan Architecture, ISBN 1-55937-350-4, IEEE order number SH16626.

The official document which specifies the international standard for a test access port and boundary-scan architecture. Informally known as the JTAG standard, it was officially ratified by the IEEE in February 1990. Since, it has been supplemented twice. The first supplement, ratified in June 1993, is included in the referenced document. The second supplement is currently a separate document, as referenced below.

IEEE 1149.1 Boundary-Scan

IEEE Std 1149.1b-1994, Supplement to IEEE Std 1149.1-1990, ISBN 155937-497-7, IEEE order number SH94256.

The official document which specifies the international standard for a boundary-scan description language. This supplement to IEEE Std 1149.1-1990 was ratified in September 1994.





Tutorials/Handbooks

Abbreviations/AcronymsASIC ASP ATE ATPG BIST B/S BSC BSDL BSR BST CAE DFT DR DSP EDA eTBC FPGA HSDL ICE ICT Application-Specific Integrated Circuit Addressable Scan Port Automatic Test Equipment Automatic Test Pattern Generation Built-In Self-Test Boundary-Scan Boundary-Scan Cell Boundary-Scan Description Language Boundary-Scan Register Boundary-Scan Test Computer-Aided Engineering Design-for-Test Data Register Digital Signal Processing/Processor Electronic Design Automation Embedded Test Bus Controller Field-Programmable Gate Array Hierarchical Scan Description Language In-Circuit Emulation In-Circuit Test IEEE ISP JTAG MCM Mfg PCB PLD PRPG PSA PWB SPL SVF TAP TBC TCK TDI TDO TMS TRST UUT Institute of Electrical & Electronics Engineers IR Instruction Register In-System Programming Joint Test Action Group Multi-Chip Module Manufacturing Printed Circuit Board Programmable Logic Device Pseudo-Random Pattern Generation Parallel Signature Analysis Printed Wiring Board Scan Path Linker Serial Vector Format Test Access Port Test Bus Controller Test Clock Test Data Input Test Data Output Test Mode Select Test Reset Unit Under Test

The Test Access Port and Boundary-Scan Architecture, Colin M. Maunder, Rodham E. Tulloss, ed., IEEE CS Press, ISBN 0-8186-9070-4. Edited by two principal chairs of the IEEE 1149.1 working group, this Computer Society tutorial compiles several of the seminal papers on boundaryscan along with several invited papers on various topics including applications, implementation, and others. It will primarily be of interest to the design and/or test engineer. The Boundary-Scan Handbook, Kenneth P. Parker, Kluwer Academic Publishers, ISBN 0-7923-9270-1. Authored by the principal force behind the Boundary-Scan Description Language (BSDL) and an IEEE 1149.1 working group principal as well as a long time manufacturing and design-for-test expert, this is truly considered THE indispensable handbook on boundary scan for the design and/or test engineer. Boundary-Scan Test - A Practical Approach, Harry Bleeker, Peter van den Eijnden, Frans de Jong, Kluwer Academic Publishers, ISBN 0-792-9296-5. Authored by several JTAG and IEEE 1149.1 working group principals, this book is a ready reference to boundary-scan technology, its benefits, and considerations for design and test managers and engineers. 1997 TI Test Symposium




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