TI Enables Beyond3G CellularInfrastructure With New ProductsEmbargo Date – February 4, 2008Ramesh KumarMarketing Director, Communications Infrastructure Group

Data-Intensive Applications DriveInfrastructure Complexity

• Deployment of3G worldwideis the primarydriving force

• Operators seesource of newrevenue andincreased ARPUaroundbroadband-speeddata services

• Quality, capacityand latencyissues remain

0.001

0.01

0.1

1

10

100

GSM

GPRS, cdma2000

EDGE, CDMA2000-1x

CDMA2000 1x-EV-DO

CDMA2000 1x-EVDV

W-CDMA

HSDPA, HSUPACDMA2000 1x-EV-DO R. A

“4G”

SMS,IMS

Text E-mailingRing Tones

Simple games

Multimedia messagingVideo clips, Web browsing

Games

Streaming audioStreaming video clips

Enterprise Apps (Word,Excel, Outlook)Complex games

Robust Web Browsing

Video conferencing, VoDInteractive gaming

Wireless VPNs,Streaming video

Source : iSuppli

MULTIMEDIA

STREAMING

E-MAIL

INTERACTIVITY

Peak Data

Transmission

(Mbps)

Standards Migration + Lack of Convergence =Challenging Landscape for Base Station OEMs

20082006 20102007 2009 2011

1H11 -CommercialServ ice Availability

4Q08 –LTE Trials Begin

2H10 -1st NetworkDeployments begin

4Q07 –1st LTE PrototypesSystems Available 4Q09 –

1st LTEproductionsystemsavailable

3Q06 –Early LTEdevelopment begins

2H05 –HSDPA deploymentbegins

1H08 –HSUPA deploymentbegins

2H08 –HSPA+ Phase 1deployment begins

2H09 –HSPA+ Phase 2deployment begins

4Q05802.16e Phystandardratificationexpected

2H06 -802.16ecertification begins 2Q2007

802.16e (WiMAXMobility) certifiedproduction shipments

2H2008 Integratedchipsets forPCs expected(Intel)

4Q07 -Sprint beginsWiMAXdeployment

2H2008Evolved EDGETrials Begin

2H2009EvolvedEDGEDeploymentsBegin

TCI6484: The Hardest Working DSP Available

Key Features:• Support for MAC and PHY layers on a

single platform eliminates the need for aRISC co-processor

• Enhanced memory and cacheperformance for efficient MAC-layerprocessing:

-- Increased L2 cache size to 1 megagbyte(MB); total L2 memory of 2 MB-- Increased 32-bit double data rate (DDR)memory speed to 667 MHz

• Increased symbol rate processing withup to 34 megabits per second (Mbps) ofperformance via dual Turbo Co-Processors(TCP2) Programmable platform supportsmultiple standards: GSM-EDGE, EDGEEvolution, ,TD-SCDMA, WCDMA, HSPA,HSPA+, LTE, WiMAX

• Scalable across multiple form-factors:macro, micro and pico base stations

• Full selection of peripherals: Serial RapidIO, sGMII for 10/100/1000 Ethernet, HPI,I2C, two McBSP ports, UTOPIA

TimersPLL

Boot ROM

VCP2TCP2

TCP2

L2 MEM

E n h a n c e d D M

C64x+™

Core

RSA

L1 P MEM

L1 D MEM

McB

SP

SG

MII

UT

OP

IA

HP

I

SR

IO

DD

R-2

GP

IO

I2 C

EDMA 3.0 with Switch Fabric

EM

IF 6

4

Optimized Single Core Partitioning DeliversMore Performance

Maximized Throughput• Two independent Turbo

coprocessors (TCP2),separately connected toswitch fabric

• Provides ~34Mbps ULthroughput

• Multiple 11.2 MbpsHSUPA+ sectors on asingle device

• 10MHz LTE without MIMO• Sufficient TCP decoding for

early LTE Symbol rate

Memory systemimprovements

• 400% larger cachememory

• Max L2 Cache sizeincreased by 4x - 1024Mvs 256K for TCI6482

2MB L2 M

emory 256K Cache

1792K Himalaya256K Cache “New” Cache Memory

1024K Cache

1024K Curie1024K Cache

Speed Enhancements• Speed increased

from 533 to 667Mhzfor DDR2

• Overall improvementin DDR2 access,latency and speed

• Support faster accessto off chip memory

• Improves overallperformance andaccess for off chipmemory

Scheduler Benchmark Data ProvesPerformance Enhancements

• Scheduler test– Cycle count to send/receive 1M

packets– Tested at various cache sizes

from 32k to 1024k• TCI6482 has 256K Cache• TCI6484 will have 1024K Cache

– Data collected from both actualSi and simulation

– Two test cases studies. 10% and90% cache pre-loaded

• Results– TCI6484 offers up to 19%

improvement overTCI6482 on schedulerfunctions

* TCI6484 Silicon estimate based upon a historical 4% improvement fromsimulator to actual silicon device.

TCI6484Simulator

Est.TCI6484Silicon *

TCI6482 Silicon Silicon Diff

32k 2.80E+09 2.69E+09 2.95E+09 8.88%64k 2.69E+09 2.58E+09 2.90E+09 10.95%128k 2.55E+09 2.45E+09 2.79E+09 12.26%256k 2.43E+09 2.33E+09 2.75E+09 15.17%512k 2.36E+09 2.27E+09 17.61%1024k 2.31E+09 2.22E+09 19.36%

10% Cache Pre-Loading

Total cycles for sending/receiv ing 1M packets

TCI6484Simulator

Est.TCI6484 Silicon *

TCI6482Silicon Silicon Diff

32k 2.92E+09 2.80E+09 3.10E+09 9.57%64k 2.83E+09 2.72E+09 3.05E+09 10.92%128k 2.68E+09 2.57E+09 2.96E+09 13.08%256k 2.57E+09 2.47E+09 2.83E+09 12.82%512k 2.50E+09 2.40E+09 15.19%1024k 2.38E+09 2.28E+09 19.27%

90% Cache Pre-Loading

Total cycles for sending/receiv ing 1M packets

TCP/VCP Enhancements Support MoreChannels/Carriers Per Device

Pause after each slidingwindow

NoneDebug Features

CPU/3CPU/4Clock Frequency

10.8 Mbps4.1 MbpsData Rate

4682103G Voice Users

TCI6482/84TCI6482/84(VCP2)(VCP2)

C6416 (VCP)C6416 (VCP)VCPVCP

CPU/3 MHzCPU/2 MHzClock Frequency

3/4, 1/2, 1/3, 1/4, and 1/51/2, 1/3 and 1/4Code rates

207305114Stand alone block size support

20.4 Mbps11.3 MbpsData rate

5328384 Kbps Data channels

TCI6482/84TCI6482/84(TCP2)(TCP2)

C6416 C6416 (TCP)(TCP)TCPTCP

Interface-Specific Software Libraries ReduceCustomers’ Development Time by 50%

GSM-EDGE SoftwareLibraries

WCDMA-HSPAHSPA+ Software

Libraries

DEVELOPMENTENVIRONMENT

LTE SoftwareLibraries

WiMAX SoftwareLibraries

TCI6482

DSP

TCI6484

DSP

TCI6487

DSP

TCI6488

DSP

Single Core

Multicore Solution Analysis&

System Partition