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1Theory and Applications

(Chapters 1 thru 9)

2Selector Guide

3Data Sheets

4Surface Mount

Package Information andTape and Reel Specifications

5Outline Dimensions

and Leadform Options

6Index and

Cross Reference

Thyristor Data

This edition of the Thyristor Data Manual has been revised extensively to reflect ourcurrent product portfolio and to incorporate new products and corrections to existing datasheets. An expanded index is intended to help the reader find information about a varietyof subject material in the sections on Theory and Applications.

Although information in this book has been carefully checked, no responsibility forinaccuracies can be assumed by Motorola. Please consult your nearest MotorolaSemiconductor sales office for further assistance regarding any aspect of MotorolaThyristor products.

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes nowarranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor doesMotorola assume any liability arising out of the application or use of any product or circuit, and specifically dis-claims any and all liability, including without limitation consequential or incidental damages. “Typical” parameterscan and do vary in different applications. All operating parameters, including “Typicals” must be validated foreach customer application by customer’s technical experts. Motorola does not convey any license under its pat-ent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as compo-nents in systems intended for surgical implant into the body, or other applications intended to support or sustainlife, or for any other application in which the failure of the Motorola product could create a situation where person-al injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unau-thorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates,and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees aris-ing out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unautho-rized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/AffirmativeAction Employer.

Motorola, Inc. 1995Previous Edition 1993“All Rights Reserved” Printed in U.S.A.

MOTOROLA DEVICE CLASSIFICATIONS

In an effort to provide up–to–date information to the customer regarding the status of any given device, Motorolahas classified all devices into three categories: Preferred devices, Current products and Not Recommended forNew Design products.

A Preferred type is a device which is recommended as a first choice for future use. These devices are “preferred”by virtue of their performance, price, functionality, or combination of attributes which offer the overall “best” value tothe customer. This category contains both advanced and mature devices which will remain available for theforeseeable future.

“Preferred devices” are listed in bold, italic in the Selector Guide section and are markedwith an asterisk in the Data Sheet sections.

Device types identified as “current” may not be a first choice for new designs, but will continue to be availablebecause of the popularity and/or standardization or volume usage in current production designs. These productscan be acceptable for new designs but the preferred types are considered better alternatives for long term usage.

Any device that has not been identified as a “preferred device” is a “current” device.

This data book does not contain any “Not Recommended for New Design” devices.

Cho-Therm is a registered trademark of Chromerics, Inc.Grafoil is a registered trademark of Union CarbideRubber-Duc is a trademark of AAVID EngineeringSil Pad and Thermal Clad are trademarks of the Bergquist Company.Sync-Nut is a trademark of ITW ShakeproofThermasil is a registered trademark and Thermafilm is a trademark of Thermalloy, Inc.ICePAK, POWERTAP and Thermopad are trademarks of Motorola, Inc.Designer’s, Thermopad, Thermowatt and Unibloc are trademarks of Motorola, Inc.Kapton and Teflon are registered trademarks of du Pont de Nemours & Co., Inc.

i

Introduction ii. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 1: Symbols and Terminology 1.1–1. . . . . . . . . . . Chapter 2: Theory of Thyristor Operation 1.2–1. . . . . . . .

Basic Behavior 1.2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switching Characteristics 1.2–3. . . . . . . . . . . . . . . . . . . . . False Triggering 1.2–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Theory of SCR Power Control 1.2–7. . . . . . . . . . . . . . . . . Triac Theory 1.2–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Methods of Control 1.2–15. . . . . . . . . . . . . . . . . . . . . . . . . . Zero Point Switching Techniques 1.2–16. . . . . . . . . . . . . .

Chapter 3: Thyristor Drivers and Triggering 1.3–1. . . . . Pulse Triggering of SCRs 1.3–1. . . . . . . . . . . . . . . . . . . . . Effect of Temperature, Voltage and Loads 1.3–5. . . . . . . Using Negative Bias and Shunting 1.3–7. . . . . . . . . . . . . Snubbing Thyristors 1.3–9. . . . . . . . . . . . . . . . . . . . . . . . . . Using Sensitive Gate SCRs 1.3–11. . . . . . . . . . . . . . . . . . Drivers: Programmable UnijunctionTransistors 1.3–15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Silicon Bilateral Switch 1.3–18. . . . . . . . . . . . . . . . . . . . . . Chapter 4: The SIDAC A New High VoltageBilateral Trigger 1.4-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Chapter 5: SCR Characteristics 1.5–1. . . . . . . . . . . . . . . . . SCR Turn–Off Characteristics 1.5–1. . . . . . . . . . . . . . . . . SCR Turn–Off Mechanism 1.5–1. . . . . . . . . . . . . . . . . . . . SCR Turn–Off Time tq 1.5–1. . . . . . . . . . . . . . . . . . . . . . . . Parameters Affecting tq 1.5–6. . . . . . . . . . . . . . . . . . . . . . . Characterizing SCRs for Crowbar Applications 1.5–10. . Switches as Line–Type Modulators 1.5–18. . . . . . . . . . . . Parallel Connected SCRs 1.5–23. . . . . . . . . . . . . . . . . . . . RFI Suppression in Thyristor Circuits 1.5–27. . . . . . . . . .

Theory and Applications(Chapters 1 thru 9)

PageChapter 6: Applications 1.6–1. . . . . . . . . . . . . . . . . . . . . . . .

Phase Control with Thyristors 1.6–1. . . . . . . . . . . . . . . . . Motor Control 1.6–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Phase Control with Trigger Devices 1.6–9. . . . . . . . . . . . Cycle Control with Optically IsolatedTriac Drivers 1.6–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

AC Power Control with Solid–State Relays 1.6–17. . . . . Triacs and Inductive Loads 1.6–21. . . . . . . . . . . . . . . . . . . Inverse Parallel SCRs for Power Control 1.6–23. . . . . . . Interfacing Digital Circuits to ThyristorControlled AC Loads 1.6–25. . . . . . . . . . . . . . . . . . . . . . .

DC Motor Control with Thyristors 1.6–33. . . . . . . . . . . . . . Programmable Unijunction Transistor (PUT)Applications 1.6–37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Silicon Bilateral Switch (SBS) Applications 1.6–41. . . . . Triac Zero–Point Switch Applications 1.6–44. . . . . . . . . . AN982 — Applications of Zero Voltage CrossingOptically Isolated Triac Drivers 1.6–49. . . . . . . . . . . . . . .

AN1045 — Series Triacs in AC High VoltageSwitching Circuits 1.6–59. . . . . . . . . . . . . . . . . . . . . . . . . .

AN1048 — RC Snubber Networks for ThyristorPower Control and Transient Suppression 1.6–68. . . . .

Chapter 7: Mounting Techniques for Thyristors 1.7–1. . Mounting Surface Considerations 1.7–2. . . . . . . . . . . . . . Thermal Interface 1.7–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . Insulation Considerations 1.7–4. . . . . . . . . . . . . . . . . . . . . Fastening Techniques 1.7–8. . . . . . . . . . . . . . . . . . . . . . . . Insulated Packages 1.7–12. . . . . . . . . . . . . . . . . . . . . . . . . Surface Mount Devices 1.7–13. . . . . . . . . . . . . . . . . . . . . . Thermal System Evaluation 1.7–16. . . . . . . . . . . . . . . . . .

Chapter 8: Reliability and Quality 1.8–1. . . . . . . . . . . . . . . Using Transient Thermal Resistance Data inHigh Power Pulsed Thyristor Applications 1.8–1. . . . . .

Thyristor Construction 1.8–15. . . . . . . . . . . . . . . . . . . . . . . In–Process Controls and Inspections 1.8–15. . . . . . . . . . Reliability Tests 1.8–16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stress Testing 1.8–17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Environmental Testing 1.8–18. . . . . . . . . . . . . . . . . . . . . . .

Chapter 9: Appendices NO TAG. . . . . . . . . . . . . . . . . . . . . .

ii

INTRODUCTION

Thyristors can take many forms, but they have certainthings in common. All of them are solid state switches whichact as open circuits capable of withstanding the rated voltageuntil triggered. When they are triggered, thyristors becomelow–impedance current paths and remain in that conditionuntil the current either stops or drops below a minimum valuecalled the holding level. Once a thyristor has been triggered,the trigger current can be removed without turning off thedevice.

Silicon controlled rectifiers (SCRs) and triacs are bothmembers of the thyristor family. SCRs are unidirectionaldevices where triacs are bidirectional. An SCR is designed toswitch load current in one direction, while a triac is designedto conduct load current in either direction.

Structurally, all thyristors consist of several alternatinglayers of opposite P and N silicon, with the exact structurevarying with the particular kind of device. The load is appliedacross the multiple junctions and the trigger current isinjected at one of them. The trigger current allows the loadcurrent to flow through the device, setting up a regenerativeaction which keeps the current flowing even after the triggeris removed.

These characteristics make thyristors extremely useful incontrol applications. Compared to a mechanical switch, a

thyristor has a very long service life and very fast turn on andturn off times. Because of their fast reaction times,regenerative action and low resistance once triggered,thyristors are useful as power controllers and transientovervoltage protectors, as well as simply turning devices onand off. Thyristors are used to control motors, incandescentlights and many other kinds of equipment.

Although thyristors of all sorts are generally rugged, thereare several points to keep in mind when designing circuitsusing them. One of the most important is to respect thedevices’ rated limits on rate of change of voltage and current(dv/dt and di/dt). If these are exceeded, the thyristor may bedamaged or destroyed. On the other hand, it is important toprovide a trigger pulse large enough and fast enough to turnthe gate on quickly and completely. Usually the gate triggercurrent should be at least three times the rated gate triggercurrent with a pulse rise time of less than 1 microsecond anda pulse width greater than 10 microseconds. Thyristors maybe driven in many different ways, including directly fromtransistors or logic families, power control integrated circuits,by optoisolated triac drivers, programmable unijunctiontransistors (PUTs), silicon bilateral switches (SBSs), andSIDACs. These and other design considerations are coveredin this manual.

1.1–1Theory and ApplicationsMotorola Thyristor Device Data

CHAPTER 1SYMBOLS AND TERMINOLOGY

SYMBOLSThe following are the most commonly used schematicsymbols for thyristors:

name of device symbol

Silicon controlledrectifier (SCR)

Triac

Programmable unijunctiontransistor (PUT)

Silicon bilateralswitch (SBS)

Sidac

G

KA

A K

MT2 MT1

G

G

MT1

MT1

MT2

MT2

G

Theory and Applications1.1–2

Motorola Thyristor Device Data

THYRISTOR TERMINOLOGY

The following terms are used in SCR and TRIAC specifications:

RATINGS

These ratings are defined as maximum values. Exceeding these values can result in permanent damage or device failure.

Terminology Symbol Definition

di/dt The maximum rate of change of current the devicewill withstand.

FORWARD CURRENT RMS IT(RMS) The maximum value of on–state rms current thedevice may conduct.

FORWARD PEAK GATE CURRENT IGM, IGFM The maximum gate current which may be applied tothe device to cause conduction.

PEAK FORWARD SURGE CURRENT ITSM The maximum allowable non–repetitive surge cur-rent the device will withstand at a specified pulsewidth.

AVERAGE ON–STATE CURRENT IT(AV) The maximum average on–state current the devicemay conduct under stated conditions.

PEAK GATE POWER PGM The maximum instantaneous value of gate powerdissipation between gate and cathode terminal.

FORWARD AVERAGE GATE POWER PG(AV) The maximum allowable value of gate power,averaged over a full cycle, that may be dissipatedbetween the gate and cathode terminal.

CIRCUIT FUSING CONSIDERATIONS I2t The maximum forward non–repetitive overcurrentcapability. Usually specified for one–half cycle of 60Hz operation.

PEAK GATE VOLTAGE VGM The maximum peak value of voltage allowed be-tween the gate and cathode terminal for any biascondition.

PEAK GATE VOLTAGE FORWARD VFGM, VGFM The maximum peak value of voltage allowed be-tween the gate and cathode terminals with theseterminals forward biased.

PEAK GATE VOLTAGE REVERSE VRGM,VGRM

The maximum peak value of voltage allowed be-tween the gate and cathode with these terminalsreverse biased.

PEAK REPETITIVE FORWARD BLOCKINGVOLTAGE (SCR)

VDRM The maximum allowed value of repetitive forwardvoltage which may be applied and not switch theSCR on.

PEAK REPETITIVE REVERSE BLOCKINGVOLTAGE (SCR)

VRRM The maximum allowed value of repetitive reversevoltage which may be applied to the anode terminal.

PEAK REPETITIVE OFF–STATE VOLTAGE(TRIAC)

VDRM The maximum allowed value of repetitive off–statevoltage which may be applied and not switch on thetriac.


CHARACTERISTICS


PEAK FORWARD BLOCKING CURRENT (SCR) IDRM The maximum value of current which will flow atVDRM and specified temperature.

PEAK REVERSE BLOCKING CURRENT (SCR) IRRM The maximum value of current which will flow atVRRM and specified temperature.

PEAK BLOCKING CURRENT (TRIAC) IDRM The maximum value of current which will flow foreither polarity of VDRM and at specified temperature.

PEAK ON–STATE VOLTAGE VTM The maximum voltage drop across the terminals atstated conditions.

GATE TRIGGER CURRENT IGT The maximum value of gate current required toswitch the device from the off state to the on stateunder specified conditions.

GATE TRIGGER VOLTAGE VGT The gate dc voltage required to produce the gatetrigger current.

HOLDING CURRENT IH The value of forward anode current which allows thedevice to remain in conduction. Below this value thedevice will return to a forward blocking state atprescribed gate conditions.

CRITICAL RISE OF OFF–STATE VOLTAGE dv/dt The minimum value of the rate of rise of forwardvoltage which will cause switching from the off stateto the on state.

TURN–ON TIME (SCR) tgt The time interval between a specified point at thebeginning of the gate pulse and the instant when thedevice voltage (current) has dropped to a specifiedlow value during the switching of an SCR from the offstate to the on state by a gate pulse.

TURN–OFF TIME (SCR) tq The time interval between the instant when the SCRcurrent has decreased to zero after external switch-ing of the SCR voltage circuit and the instant whenthe thyristor is capable of supporting a specifiedwave form without turning on.

OPERATING JUNCTION TEMPERATURE TJ The junction temperature of the device as a result ofambient and load conditions.

STORAGE TEMPERATURE Tstg The temperature at which the device may be storedwithout harm.

CASE TEMPERATURE TC The temperature of the device case under specifiedconditions.

AMBIENT TEMPERATURE TA The air temperature measured below a device in anenvironment of substantially uniform temperature,cooled only by natural air currents and not materiallyaffected by radiant and reflective surfaces.



CHARACTERISTICS


THERMAL RESISTANCE, CASE–TO–AMBIENT RθCA The thermal resistance (steady–state) from thedevice case to the ambient.

THERMAL RESISTANCE, JUNCTION–TO–AMBIENT

RθJA The thermal resistance (steady–state) from thesemiconductor junction(s) to the ambient.

THERMAL RESISTANCE, JUNCTION–TO–CASE RθJC The thermal resistance (steady–state) from thesemiconductor junction(s) to a stated location on thecase.

THERMAL RESISTANCE, JUNCTION–TO–MOUNTING SURFACE

RθJM The thermal resistance (steady–state) from thesemiconductor junction(s) to a stated location on themounting surface.

TRANSIENT THERMAL IMPEDANCE,JUNCTION–TO–AMBIENT

ZθJA(t) The transient thermal impedance from the semicon-ductor junction(s) to the ambient.

TRANSIENT THERMAL IMPEDANCE,JUNCTION–TO–CASE

ZθJC(t) The transient thermal impedance from the semicon-ductor junction(s) to a stated location on the case.


CHAPTER 2THEORY OF THYRISTOR OPERATION

To successfully apply thyristors, an understanding of theircharacteristics, ratings, and limitations is imperative. In thischapter, significant thyristor characteristics, the basis of theirratings, and their relationship to circuit design are discussed.

Several different kinds of thyristors are shown in Table 2.1.Silicon Controlled Rectifiers (SCRs) are the most widely usedas power control elements; triacs are quite popular in lowercurrent (under 40 A) ac power applications. Diacs, SUSs andSBSs are most commonly used as gate trigger devices forthe power control elements.

Table 2.1. Thyristor Types

*JEDEC Titles Popular Names, Types

Reverse Blocking DiodeThyristor

Four Layer Diode, SiliconUnilateral Switch (SUS)

Reverse Blocking TriodeThyristor

Silicon Controlled Rectifier (SCR)

Reverse Conducting DiodeThyristor

Reverse Conducting FourLayer Diode

Reverse Conducting TriodeThyristor

Reverse Conducting SCR

Bidirectional Triode Thyristor Triac

* JEDEC is an acronym for the Joint Electron Device EngineeringCouncils, an industry standardization activity co–sponsored by theElectronic Industries Association (EIA) and the National ElectricalManufacturers Association (NEMA).

Not generally available.

Before considering thyristor characteristics in detail, a briefreview of their operation based upon the common two–tran-sistor analogy of an SCR is in order.

BASIC BEHAVIOR

The bistable action of thyristors is readily explained byanalysis of the structure of an SCR. This analysis isessentially the same for any operating quadrant of triac

because a triac may be considered as two parallel SCRsoriented in opposite directions. Figure 2.1(a) shows theschematic symbol for an SCR, and Figure 2.1(b) shows theP–N–P–N structure the symbol represents. In the two–tran-sistor model for the SCR shown in Figure 2.1(c), theinterconnections of the two transistors are such that regen-erative action occurs. Observe that if current is injected intoany leg of the model, the gain of the transistors (if sufficientlyhigh) causes this current to be amplified in another leg. Inorder for regeneration to occur, it is necessary for the sum ofthe common base current gains (α) of the two transistors toexceed unity. Therefore, because the junction leakagecurrents are relatively small and current gain is designed tobe low at the leakage current level, the PNPN device remainsoff unless external current is applied. When sufficient triggercurrent is applied (to the gate, for example, in the case of anSCR) to raise the loop gain to unity, regeneration occurs andthe on–state principal current is limited primarily by externalcircuit impedance. If the initiating trigger current is removed,the thyristor remains in the on state, providing the currentlevel is high enough to meet the unity gain criteria. Thiscritical current is called latching current.

In order to turn off a thyristor, some change in current mustoccur to reduce the loop gain below unity. From the model, itappears that shorting the gate to cathode would accomplishthis. However in an actual SCR structure, the gate area isonly a fraction of the cathode area and very little current isdiverted by the short. In practice, the principal current mustbe reduced below a certain level, called holding current,before gain falls below unity and turn–off may commence.

In fabricating practical SCRs and Triacs, a “shortedemitter” design is generally used in which, schematically, aresistor is added from gate to cathode or gate to MT1.Because current is diverted from the N–base through theresistor, the gate trigger current, latching current and holdingcurrent all increase. One of the principal reasons for theshunt resistance is to improve dynamic performance at hightemperatures. Without the shunt, leakage current on mosthigh current thyristors could initiate turn–on at high tempera-tures.



Sensitive gate thyristors employ a high resistance shunt ornone at all; consequently, their characteristics can be altereddramatically by use of an external resistance. An externalresistance has a minor effect on most shorted emitterdesigns.

Figure 2.1. Two–transistor analogy of an SCR:(a) schematic symbol of SCR; (b) P–N–P–N structurerepresented by schematic symbol; (c) two–transistor

model of SCR.

P

ANODE

GATE

CATHODE(b)

N

P

NGATE

ANODE

CATHODE(a)

ANODE

GATE

CATHODE

IB1IC2

(c)

IC1IB2

IK

P

N NP P

N

Junction temperature is the primary variable affectingthyristor characteristics. Increased temperatures make thethyristor easier to turn on and keep on. Consequently, circuitconditions which determine turn–on must be designed tooperate at the lowest anticipated junction temperatures,while circuit conditions which are to turn off the thyristor orprevent false triggering must be designed to operate at themaximum junction temperature.

Thyristor specifications are usually written with casetemperatures specified and with electrical conditions suchthat the power dissipation is low enough that the junctiontemperature essentially equals the case temperature. It isincumbent upon the user to properly account for changes incharacteristics caused by the circuit operating conditionsdifferent from the test conditions.

TRIGGERING CHARACTERISTICSTurn–on of a thyristor requires injection of current to raise

the loop gain to unity. The current can take the form of currentapplied to the gate, an anode current resulting from leakage,or avalanche breakdown of a blocking junction. As a result,the breakover voltage of a thyristor can be varied orcontrolled by injection of a current at the gate terminal. Figure2.2 shows the interaction of gate current and voltage for anSCR.

When the gate current Ig is zero, the applied voltage mustreach the breakover voltage of the SCR before switchingoccurs. As the value of gate current is increased, however,

the ability of a thyristor to support applied voltage is reducedand there is a certain value of gate current at which thebehavior of the thyristor closely resembles that of a rectifier.Because thyristor turn–on, as a result of exceeding thebreakover voltage, can produce high instantaneous powerdissipation non–uniformly distributed over the die area duringthe switching transition, extreme temperatures resulting indie failure may occur unless the magnitude and rate of rise ofprincipal current (di/dt) is restricted to tolerable levels. Fornormal operation, therefore, SCRs and triacs are operated atapplied voltages lower than the breakover voltage, and aremade to switch to the on state by gate signals high enough toassure complete turn–on independent of the applied voltage.

Figure 2.2. Thyristor Characteristics IllustratingBreakover as a Function of Gate Current

Ig4 Ig3 Ig2 Ig1 = 0

V

–

On the other hand, diacs and other thyristor trigger devicesare designed to be triggered by anode breakover. Neverthe-less they also have di/dt and peak current limits which mustbe adhered to.

A triac works the same general way for both positive andnegative voltage. However since a triac can be switched onby either polarity of the gate signal regardless of the voltagepolarity across the main terminals, the situation is somewhatmore complex than for an SCR.

The various combinations of gate and main terminalpolarities are shown in Figure 2.3. The relative sensitivitydepends on the physical structure of a particular triac, but asa rule, sensitivity is highest in quadrant I and quadrant IV isgenerally considerably less sensitive than the others.

Figure 2.3. Quadrant Definitions for a Triac

MT2(+)

MT2(–)

G(–) G(+)

QUADRANT II QUADRANT I

MT2(+), G(–) MT2(+), G(+)

QUADRANT III QUADRANT IV

MT2(–), G(–) MT2(–), G(+)


Gate sensitivity of a triac as a function of temperature isshown in Figure 2.4.

Figure 2.4. Typical Triac Triggering Sensitivity in theFour Trigger Quadrants

I GT,

GAT

E TR

IGG

ER C

UR

REN

T (m

A)

30

20

10

7

3

5

120– 80 – 60 – 40 – 20 0 20 40 60 80 100

TJ, JUNCTION TEMPERATURE (°C)

34

QUADRANT1234

OFF–STATE VOLTAGE = 12 VdcALL QUADRANTS

Since both the junction leakage currents and the currentgain of the “transistor” elements increase with temperature,the magnitude of the required gate trigger current decreasesas temperature increases. The gate — which can beregarded as a diode — exhibits a decreasing voltage drop astemperature increases. Thus it is important that the gatetrigger circuit be designed to deliver sufficient current to thegate at the lowest anticipated temperature.

It is also advisable to observe the maximum gate current,as well as peak and average power dissipation ratings. Alsoin the negative direction, the maximum gate ratings shouldbe observed. Both positive and negative gate limits are oftengiven on the data sheets and they may indicate thatprotective devices such as voltage clamps and currentlimiters may be required in some applications. It is generallyinadvisable to dissipate power in the reverse direction.

Although the criteria for turn–on have been described interms of current, it is more basic to consider the thyristor asbeing charge controlled. Accordingly, as the duration of thetrigger pulse is reduced, its amplitude must be correspond-ingly increased. Figure 2.5 shows typical behavior at variouspulse widths and temperatures.

The gate pulse width required to trigger a thyristor alsodepends upon the time required for the anode current toreach the latching value. It may be necessary to maintain agate signal throughout the conduction period in applicationswhere the load is highly inductive or where the anode currentmay swing below the holding value within the conductionperiod.

When triggering an SCR with a dc current, excess leakagein the reverse direction normally occurs if the trigger signal ismaintained during the reverse blocking phase of the anodevoltage. This happens because the SCR operates like aremote base transistor having a gain which is generally about0.5. When high gate drive currents are used, substantialdissipation could occur in the SCR or a significant current

could flow in the load; therefore, some means usually mustbe provided to remove the gate signal during the reverseblocking phase.

Figure 2.5. Typical Behavior of Gate Trigger Current asPulse Width and Temperature Are Varied

I GTM

, PEA

K G

ATE

CU

RR

ENT

(mA)

300

30

107

3

5

0.2

PULSE WIDTH (µs)

5070

100

0.5 1 2 5 10 20 50 100 200

OFF–STATE VOLTAGE = 12 V

TJ = – 55°C

25°C

100°C

LATCH AND HOLD CHARACTERISTICSIn order for the thyristor to remain in the on state when the

trigger signal is removed, it is necessary to have sufficientprincipal current flowing to raise the loop gain to unity. Theprincipal current level required is the latching current, IL.Although triacs show some dependency on the gate currentin quadrant II, the latching current is primarily affected by thetemperature on shorted emitter structures.

In order to allow turn off, the principal current must bereduced below the level of the latching current. The currentlevel where turn off occurs is called the holding current, IH.Like the latching current, the holding current is affected bytemperature and also depends on the gate impedance.

Reverse voltage on the gate of an SCR markedlyincreases the latch and hold levels. Forward bias on thyristorgates may significantly lower the values shown in the datasheets since those values are normally given with the gateopen. Failure to take this into account can cause latch or holdproblems when thyristors are being driven from transistorswhose saturation voltages are a few tenths of a volt.

Thyristors made with shorted emitter gates are obviouslynot as sensitive to the gate circuit conditions as deviceswhich have no built–in shunt.

SWITCHING CHARACTERISTICSWhen triacs or SCRs are triggered by a gate signal, the

turn–on time consists of two stages: a delay time, td, and arise time, tr, as shown in Figure 2.6. The total gate controlledturn–on time, tgt, is usually defined as the time intervalbetween the 50 percent point of the leading edge of the gatetrigger voltage and 90 percent point of the principal current.The rise time tr is the time interval required for the principalcurrent to rise from 10 to 90 percent of its maximum value. Aresistive load is usually specified.



Figure 2.6. Waveshapes Illustrating Thyristor Turn–OnTime For A Resistive Load

PRINCIPALVOLTAGE

PRINCIPALCURRENT

90% POINT

10% POINT

90% POINT

10% POINT

0

0

trtd

ton

GATECURRENT

IGTIGT50%

50% POINT

(WAVESHAPES FOR A SENSITIVE LOAD)0

Delay time decreases slightly as the peak off–state voltageincreases. It is primarily related to the magnitude of thegate–trigger current and shows a relationship which isroughly inversely proportional.

The rise time is influenced primarily by the off–statevoltage, as high voltage causes an increase in regenerativegain. Of major importance in the rise time interval is therelationship between principal voltage and current flowthrough the thyristor di/dt. During this time the dynamicvoltage drop is high and the current density due to thepossible rapid rate of change can produce localized hotspots in the die. This may permanently degrade the blockingcharacteristics. Therefore, it is important that power dissipa-tion during turn–on be restricted to safe levels.

Turn–off time is a property associated only with SCRs andother unidirectional devices. (In triacs of bidirectional devicesa reverse voltage cannot be used to provide circuit–commu-tated turn–off voltage because a reverse voltage applied toone half of the structure would be a forward–bias voltage tothe other half.) For turn–off times in SCRs, the recoveryperiod consists of two stages, a reverse recovery time and agate or forward blocking recovery time, as shown in Figure2.7.

When the forward current of an SCR is reduced to zero atthe end of a conduction period, application of reverse voltagebetween the anode and cathode terminals causes reversecurrent flow in the SCR. The current persists until the timethat the reverse current decreases to the leakage level.Reverse recovery time (trr) is usually measured from the

point where the principal current changes polarity to aspecified point on the reverse current waveform as indicatedin Figure 2.7. During this period the anode and cathodejunctions are being swept free of charge so that they maysupport reverse voltage. A second recovery period, calledthe gate recovery time, tgr, must elapse for the charge storedin the forward–blocking junction to recombine so thatforward–blocking voltage can be reapplied and successfullyblocked by the SCR. The gate recovery time of an SCR isusually much longer than the reverse recovery time. The totaltime from the instant reverse recovery current begins to flowto the start of the forward–blocking voltage is referred to ascircuit–commutated turn–off time tq.

Turn–off time depends upon a number of circuit conditionsincluding on–state current prior to turn–off, rate of change ofcurrent during the forward–to–reverse transition, reverse–blocking voltage, rate of change of reapplied forward voltage,the gate bias, and junction temperature. Increasing junctiontemperature and on–state current both increase turn–off timeand have a more significant effect than any of the otherfactors. Negative gate bias will decrease the turn–off time.

Figure 2.7. Waveshapes Illustrating ThyristorTurn–Off Time

PRINCIPALVOLTAGE

PRINCIPALCURRENT

REAPPLIEDdv/dt

FORWARD

0

REVERSE

di/dt

FORWARD

REVERSE

0

trr tgr

tq


For applications in which an SCR is used to control acpower, during the entire negative half of the sine wave areverse voltage is applied. Turn off is easily accomplished formost devices at frequencies up to a few kilohertz. Forapplications in which the SCR is used to control the output ofa full–wave rectifier bridge, however, there is no reversevoltage available for turn–off, and complete turn–off can beaccomplished only if the bridge output is reduced close tozero such that the principal current is reduced to a valuelower than the device holding current for a sufficiently longtime. Turn–off problems may occur even at a frequency of 60Hz particularly if an inductive load is being controlled.

In triacs, rapid application of a reverse polarity voltagedoes not cause turn–off because the main blocking junctionsare common to both halves of the device. When the first triacstructure (SCR–1) is in the conducting state, a quantity ofcharge accumulates in the N–type region as a result of theprincipal current flow. As the principal current crosses thezero reference point, a reverse current is established as aresult of the charge remaining in the N–type region, which iscommon to both halves of the device. Consequently, thereverse recovery current becomes a forward current to thesecond half of the triac. The current resulting from storedcharge causes the second half of the triac to go into theconducting state in the absence of a gate signal. Oncecurrent conduction has been established by application of agate signal, therefore, complete loss in power control canoccur as a result of interaction within the N–type base regionof the triac unless sufficient time elapses or the rate ofapplication of the reverse polarity voltage is slow enough toallow nearly all the charge to recombine in the commonN–type region. Therefore, triacs are generally limited tolow–frequency –60 Hz applications. Turn–off or commutationof triacs is more severe with inductive loads than withresistive loads because of the phase lag between voltageand current associated with inductive loads. Figure 2.8shows the waveforms for an inductive load with laggingcurrent power factor. At the time the current reaches zerocrossover (Point A), the half of the triac in conduction beginsto commutate when the principal current falls below theholding current. At the instant the conducting half of the triacturns off, an applied voltage opposite the current polarity isapplied across the triac terminals (Point B). Because thisvoltage is a forward bias to the second half of the triac, thesuddenly reapplied voltage in conjunction with the remainingstored charge in the high–voltage junction reduces the

Figure 2.8. Inductive Load Waveforms

IH

V I

B

A drdt

c

over–all device capability to support voltage. The result is aloss of power control to the load, and the device remains inthe conducting state in absence of a gate signal. Themeasure of triac turn–off ability is the rate of rise of theopposite polarity voltage it can handle without remaining on.It is called commutating dv/dt (dv/dt[c]). Circuit conditions andtemperature affect dv/dt(c) in a manner similar to the way tq isaffected in an SCR.

It is imperative that some means be provided to restrict therate of rise of reapplied voltage to a value which will permittriac turn–off under the conditions of inductive load. Acommonly accepted method for keeping the commutatingdv/dt within tolerable levels is to use an RC snubber networkin parallel with the main terminals of the triac. Because therate of rise of applied voltage at the triac terminals is afunction of the load impedance and the RC snubber network,the circuit can be evaluated under worst–case conditions ofoperating case temperature and maximum principal current.The values of resistance and capacitance in the snubberarea then adjusted so that the rate of rise of commutatingdv/dt stress is within the specified minimum limit under any ofthe conditions mentioned above. The value of snubberresistance should be high enough to limit the snubbercapacitance discharge currents during turn–on and dampenthe LC oscillation during commutation. The combination ofsnubber values having highest resistance and lowest capaci-tance that provides satisfactory operation is generally pre-ferred.

FALSE TRIGGERINGCircuit conditions can cause thyristors to turn on in the

absence of the trigger signal. False triggering may resultfrom:

1) A high rate of rise of anode voltage, (the dv/dt effect).2) Transient voltages causing anode breakover.3) Spurious gate signals.

Static dv/dt effect: When a source voltage is suddenlyapplied to a thyristor which is in the off state, it may switchfrom the off state to the conducting state. If the thyristor iscontrolling alternating voltage, false turn–on resulting from atransient imposed voltage is limited to no more than one–halfcycle of the applied voltage because turn–off occurs duringthe zero current crossing. However, if the principal voltage isdc voltage, the transient may cause switching to the on stateand turn–off could then be achieved only by a circuitinterruption.

The switching from the off state caused by a rapid rate ofrise of anode voltage is the result of the internal capacitanceof the thyristor. A voltage wavefront impressed across theterminals of a thyristor causes a capacitance–chargingcurrent to flow through the device which is a function of therate of rise of applied off–state voltage (i = C dv/dt). If the rateof rise of voltage exceeds a critical value, the capacitancecharging current exceeds the gate triggering current andcauses device turn–on. Operation at elevated junctiontemperatures reduces the thyristor ability to support a steeprising voltage dv/dt because of increased sensitivity.



dv/dt ability can be improved quite markedly in sensitivegate devices and to some extent in shorted emitter designsby a resistance from gate to cathode (or MT1) howeverreverse bias voltage is even more effective in an SCR. Morecommonly, a snubber network is used to keep the dv/dt withinthe limits of the thyristor when the gate is open.

TRANSIENT VOLTAGES: — Voltage transients whichoccur in electrical systems as a result of disturbance on theac line caused by various sources such as energizingtransformers, load switching, solenoid closure, contractorsand the like may generate voltages which are above theratings of thyristors. Thyristors, in general, switch from the offstate to the on state whenever the breakover voltage of thedevice is exceeded, and energy is then transferred to theload. However, unless a thyristor is specified for use in abreakover mode, care should be exercised to ensure thatbreakover does not occur, as some devices may incursurface damage with a resultant degradation of blockingcharacteristics. It is good practice when thyristors areexposed to a heavy transient environment to provide someform of transient suppression.

For applications in which low–energy, long–duration tran-sients may be encountered, it is advisable to use thyristorsthat have voltage ratings greater than the highest voltagetransient expected in the system. The use of voltage clippingcells (MOV or Zener) is also an effective method to holdtransient below thyristor ratings. The use of an RC “snubber”circuit is effective in reducing the effects of the high–energyshort–duration transients more frequently encountered. Thesnubber is commonly required to prevent the static dv/dtlimits from being exceeded, and often may be satisfactory inlimiting the amplitude of the voltage transients as well.

For all applications, the dv/dt limits may not be exceeded.This is the minimum value of the rate of rise off–state voltageapplied immediately to the MT1–MT2 terminals after theprincipal current of the opposing polarity has decreased tozero.

SPURIOUS GATE SIGNALS: In noisy electrical environ-ments, it is possible for enough energy to cause gatetriggering to be coupled into the gate wiring by straycapacitance or electromagnetic induction. It is thereforeadvisable to keep the gate lead short and have the commonreturn directly to the cathode or MT1. In extreme cases,shielded wire may be required. Another aid commonly usedis to connect a capacitance on the order of 0.01 to 0.1 µFacross the gate and cathode terminals. This has the addedadvantage of increasing the thyristor dv/dt capability, since itforms a capacitance divider with the anode to gate capaci-tance. The gate capacitor also reduces the rate of applicationof gate trigger current which may cause di/dt failures if a highinrush load is present.

THYRISTOR RATINGSTo insure long life and proper operation, it is important that

operating conditions be restrained from exceeding thyristorratings. The most important and fundamental ratings aretemperature and voltage which are interrelated to someextent. The voltage ratings are applicable only up to the

maximum temperature ratings of a particular part number.The temperature rating may be chosen by the manufacturerto insure satisfactory voltage ratings, switching speeds, ordv/dt ability.

OPERATING CURRENT RATINGSCurrent ratings are not independently established as a

rule. The values are chosen such that at a practical casetemperature the power dissipation will not cause the junctiontemperature rating to be exceeded.

Various manufacturers may chose different criteria toestablish ratings. At Motorola, use is made of the thermalresponse of the semiconductor and worst case values ofon–state voltage and thermal resistance, to guarantee thejunction temperature is at or below its rated value. Valuesshown on data sheets consequently differ somewhat fromthose computed from the standard formula:

TC(max) = T (rated) – RθJC PD(AV)

whereTC (max) = Maximum allowable case temperatureT (rated) = Rated junction temperature or maximum

rated case temperature with zero principalcurrent and rated ac blocking voltageapplied.

RθJC = Junction to case thermal resistancePD(AV) = Average power dissipation

The above formula is generally suitable for estimating casetemperature in situations not covered by data sheet informa-tion. Worst case values should be used for thermal resis-tance and power dissipation.

OVERLOAD CURRENT RATINGSOverload current ratings may be divided into two types:

non–repetitive and repetitive.Non–repetitive overloads are those which are not a part of

the normal application of the device. Examples of suchoverloads are faults in the equipment in which the devicesare used and accidental shorting of the load. Non–repetitiveoverload ratings permit the device to exceed its maximumoperating junction temperature for short periods of timebecause this overload rating applies following any rated loadcondition. In the case of a reverse blocking thyristor or SCR,the device must block rated voltage in the reverse directionduring the current overload. However, no type of thyristor isrequired to block off–stage voltage at any time during orimmediately following the overload. Thus, in the case of atriac, the device need not block in either direction during orimmediately following the overload. Usually only approxi-mately one hundred such current overloads are permittedover the life of the device. These non–repetitive overloadratings just described may be divided into two types:multicycle (which include single cycle) and subcycle. For anSCR, the multicycle overload current rating, or surge currentrating as it is commonly called, is generally presented as acurve giving the maximum peak values of half sine waveon–state current as a function of overload duration measuredin number of cycles for a 60 Hz frequency.


For a triac, the current waveform used in the rating is a fullsine wave. Multicycle surge curves are used to select propercircuit breakers and series line impedances to preventdamage to the thyristor in the event of an equipment fault.

The subcycle overload or subcycle surge rating curve is socalled because the time duration of the rating is usually fromabout one to eight milliseconds which is less than the time ofone cycle of a 60 Hz power source. Overload peak current isoften given in curve form as a function of overload duration.This rating also applies following any rated load conditionand neither off–state nor reverse blocking capability isrequired on the part of the thyristor immediately following theoverload current. The subcycle surge current rating may beused to select the proper current–limiting fuse for protectionof the thyristor in the event of an equipment fault. Since thisuse of the rating is so common, manufacturers simply publishthe i2t rating in place of the subcycle current overload curvebecause fuses are commonly rated in terms of i2t. The i2trating can be approximated from the single cycle surge rating(ITSM) by using:

i2t = I2TSM t/2

where the time t is the time base of the overload, i.e., 8.33 msfor a 60 Hz frequency.

Repetitive overloads are those which are an intended partof the application such as a motor drive application. Sincethis type of overload may occur a large number of timesduring the life of the thyristor, its rated maximum operatingjunction temperature must not be exceeded during theoverload if long thyristor life is required. Since this type ofoverload may have a complex current waveform andduty–cycle, a current rating analysis involving the use of thetransient thermal impedance characteristics is often the onlypractical approach. In this type of analysis, the thyristorjunction–to–case transient thermal impedance characteristicis added to the user’s heat dissipator transient thermalimpedance characteristic. Then by the superposition ofpower waveforms in conjunction with the composite thermalimpedance curve, the overload current rating can beobtained. The exact calculation procedure is found in thepower semiconductor literature.

THEORY OF SCR POWER CONTROL

The most common form of SCR power control is phasecontrol. In this mode of operation, the SCR is held in an offcondition for a portion of the positive half cycle and then istriggered into an on condition at a time in the half cycledetermined by the control circuitry (in which the circuit currentis limited only by the load — the entire line voltage except fora nominal one volt drop across the SCR is applied to theload).

One SCR alone can control only one half cycle of thewaveform. For full wave ac control, two SCRs are connectedin inverse parallel (the anode of each connected to thecathode of the other, see Figure 2.9a). For full wave dccontrol, two methods are possible. Two SCRs may be usedin a bridge rectifier (see Figure 2.9b) or one SCR may beplaced in series with a diode bridge (see Figure 2.9c).

Figure 2.10 shows the voltage waveform along with somecommon terms used in describing SCR operation. Delay

angle is the time, measured in electrical degrees, duringwhich the SCR is blocking the line voltage. The period duringwhich the SCR is on is called the conduction angle.

It is important to note that the SCR is a voltage controllingdevice. The load and power source determine the circuitcurrent.

Now we arrive at a problem. Different loads respond todifferent characteristics of the ac waveform. Some loads aresensitive to peak voltage, some to average voltage andsome to rms voltage. Figures 2.11(b) and 2.12(b) show thevarious characteristic voltages plotted against the conductionangle for half wave and full wave circuits. These voltageshave been normalized to the rms of the applied voltage. Todetermine the actual peak, average or rms voltage for anyconduction angle, we simply multiply the normalized voltageby the rms value of the applied line voltage. (Thesenormalized curves also apply to current in a resistive circuit.)Since the greatest majority of circuits are either 115 or 230volt power, the curves have been redrawn for these voltagesin Figures 2.11(a) and 2.12(a).

A relative power curve has been added to Figure 2.12 forconstant impedance loads such as heaters. (Incandescentlamps and motors do not follow this curve precisely sincetheir relative impedance changes with applied voltage.) Touse the curves, we find the full wave rated power of the load,then multiply by the fraction associated with the phase anglein question. For example, a 180° conduction angle in a halfwave circuit provides 0.5 x full wave full–conduction power.

An interesting point is illustrated by the power curves. Aconduction angle of 30° provides only three per cent of fullpower in a full wave circuit, and a conduction angle of 150°provides 97 per cent of full power. Thus, the control circuitcan provide 94 per cent of full power control with a pulsephase variation of only 120°. Thus, it becomes pointless inmany cases to try to obtain conduction angles less than 30°or greater than 150°.

CONTROL CHARACTERISTICS

The simplest and most common control circuit for phasecontrol is a relaxation oscillator. This circuit is showndiagrammatically as it would be used with an SCR in Figure2.13. The capacitor is charged through the resistor from avoltage or current source until the breakover voltage of thetrigger device is reached. At that time, the trigger devicechanges to its on state, and the capacitor is dischargedthrough the gate of the SCR. Turn–on of the SCR is thusaccomplished with a short, high current pulse. Commonlyused trigger devices are programmable unijunction transis-tors, silicon bilateral switches, SIDACs, optically coupledthyristors, and power control integrated circuits. Phasecontrol can be obtained by varying the RC time constant of acharging circuit so that trigger device turn–on occurs atvarying phase angles within the controlled half cycle.

If the relaxation oscillator is to be operated from a pure dcsource, the capacitor voltage–time characteristic is shown inFigure 2.14. This shows the capacitor voltage as it rises allthe way to the supply voltage through several time constants.Figure 2.14(b) shows the charge characteristic in the firsttime constant greatly expanded. It is this portion of thecapacitor charge characteristic which is most often used inSCR and Triac control circuits.



Generally, a design starting point is selection of acapacitance value which will reliably trigger the thyristorwhen the capacitor is discharged. Gate characteristics andratings, trigger device properties, and the load impedanceplay a part in the selection. Since not all of the importantparameters for this selection are completely specified,experimental determination is often the best method.

Low–current loads and strongly inductive circuits some-times cause triggering difficulty because the gate currentpulse goes away before the principal thyristor currentachieves the latching value. A series gate resistor can beused to introduce a RC discharge time constant in the gatecircuit and lengthen trigger pulse duration allowing more timefor the main terminal current to rise to the latching value.Small thyristors will require a series gate resistance to avoidexceeding the gate ratings. The discharge time constant of asnubber, if used, can also aid latching. The duration of thesecapacitor discharge duration currents can be estimated by

tw10 = 2.3 RC where tw10 = time for current to decay to 10%of the peak.

For example, when an 8 volt SBS is used to discharge a0.5 µF capacitor through a 15 ohm resistor into the gate of anSCR

tw10 = (2.3) (15) (0.5) = 17.3 µs.

Because of internal voltage drops in the SBS and SCRgates, the peak current will be somewhat less than

Ipk = 8/15 = 0.53 amp.

All trigger devices require some drive current to fire. Highlysensitive devices appear to be voltage operated when thecurrent required to fire them is insignificant. The MBS4991SBS requires that the switching current be taken intoconsideration. For a given RC time constant, larger capaci-tors allow the use of lower value timing resistors and lesssensitive trigger components.

An example will demonstrate the procedure. Assume thatwe wish to trigger a 2N6397 SCR with an 8 volt MBS4991.We have determined that a 1 µF capacitor will supply thenecessary SCR gate current magnitude and duration whilenot exceeding the gate ratings. Assume a 16 volt 60 Hz dcgate power supply, 30° minimum conduction angle and 150°maximum conduction angle with a 60 Hz anode powersource. The capacitor must charge to 8/16 or 0.5 of theavailable charging voltage in the desired time. Referring toFigure 2.14(b), we see that 0.5 of the charging voltagerepresents 0.693 time constant. The 30° conduction anglerequires that the firing pulse be delayed 150° or 6.94milliseconds (8.33 milliseconds is the period of 1/2 cycle at60 Hz). To obtain this delay,

6.49 ms 0.693 RCRC 10.01 ms.

If C 1 F,

R 10 10–3

1 10–6 10 k ohms.

(a)ac Control

CONTROLCIRCUIT

LINE LOAD

(b)Two SCR dc Control

(c)One SCR dc Control

CONTROLCIRCUIT

CONTROLCIRCUIT

LINE

LINE

LOAD

LOAD

Figure 2.9. SCR Connections For Various MethodsOf Phase Control

Figure 2.10. Sine Wave Showing PrinciplesOf Phase Control

FULL WAVE RECTIFIED OPERATION

VOLTAGE APPLIED TO LOAD

DELAY ANGLE

CONDUCTION ANGLE


Figure 2.11. Half–Wave Characteristics Of Thyristor Power Control

Figure 2.12. Full–Wave Characteristics Of Thyristor Power Control

1.8

1.6

1.4

1.2

1

0.8

0.6

0.4

0.2

0180160140120100806040200

CONDUCTION ANGLE(a)

NO

RM

ALIZ

ED S

INE

WAV

E rm

s VO

LTAG

EPO

WER

AS

FRAC

TIO

N O

F FU

LL C

ON

DU

CTI

ON

NO

RM

ALIZ

ED S

INE

WAV

E rm

s VO

LTAG

EPO

WER

AS

FRAC

TIO

N O

F FU

LL C

ON

DU

CTI

ON

VOLT

AGE

VOLT

AGE

1.8

1.6

1.4

1.2

1

0.8

0.6

0.4

0.2

0180160140120100806040200

CONDUCTION ANGLE(a)

HALF WAVE

FULL WAVE

PEAK VOLTAGE

rms

POWER

AVG

PEAK VOLTAGE

rms

AVG

POWER

APPLIEDVOLTAGE

230 V 115 V360 180

320 160

280 140

240 120

200 100

160 80

120 60

80 40

40 20

0 0180160140120100806040200

CONDUCTION ANGLE(b)

APPLIEDVOLTAGE

230 V 115 V360 180

320 160

280 140

240 120

200 100

160 80

120 60

80 40

40 20

0 0180160140120100806040200

CONDUCTION ANGLE(b)

HALF WAVE

FULL WAVE

PEAK VOLTAGE

PEAK VOLTAGE

rms

rms

AVG

AVG



Figure 2.13. SCR Trigger Circuit

16 V 4 mA 60 HzVoltage Source

+160

10 k 2 k 151 µF

100

8 VMBS4991

2N6397SCR

The timing resistor must be capable of supplying at leastthe worst case maximum SBS switching current at the peakpoint voltage. The available current is

16 V–8 V104 ohms

800 A.

This is more than the 500 µA needed by the MBS4991 at25°C. If it were not, the design procedure would need to berepeated using larger C and smaller R. Alternatively, a moresensitive MBS4992 could be used.

To obtain minimum R, 150° conduction angle, the delay is30° or

30180x8.33 1.39 ms

RC 2.01 ms

R 2.01 10–3

1 10–6 2000 ohms.

1.39 ms 0.693 RC

A 10 k potentiometer with a 2 k series resistor will serve thispurpose.

In this application, the trigger circuit is reset by linecrossing each half cycle. Consequently, SBS latching afterfiring is permissible. If the device were used as a free runningoscillator, it would be necessary for the peak point current tobe less than the minimum holding current specification of theSBS at maximum operating temperature. Timing accuracyrequires the 16 V source to be capable of supplying the worstcase required current. In the example, the initial instanta-neous capacitor charging current will be 16 V/2 k = 8 mA. Thegate load line must also enclose the peak point voltage. TheSBS clamps the capacitor voltage when it breaks overcausing little or no further change in the voltage across thecapacitor. Consequently, all of the available current at thattime (16 V–8 V)/2 k = 4 mA) diverts through the SBS causingit to fire.

In many of the recently proposed circuits for low costoperation, the timing capacitor of the relaxation oscillator ischarged through a rectifier and resistor using the ac powerline as a source. Calculations of charging time with this circuitbecome exceedingly difficult, although they are still neces-sary for circuit design. The curves of Figure 2.15 simplify thedesign immensely. These curves show the voltage–time

Figure 2.14(a). Capacitor Charging From dc Source

Figure 2.14(b). Expanded Scale

0.9

1

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

00 1 2 3 4 5 6

TIME CONSTANTS

CAP

ACIT

OR

VO

LTAG

E AS

FRAC

TIO

N O

F SU

PPLY

VO

LTAG

E

0.7

0.6

0.5

0.4

0.3

0.2

0.1

00 0.2 0.4 0.6 0.8 1 1.2

TIME CONSTANTS

CAP

ACIT

OR

VO

LTAG

E AS

FRAC

TIO

N O

F SU

PPLY

VO

LTAG

E

characteristic of the capacitor charged from one half cycle ofa sine wave. Voltage is normalized to the rms value of thesine wave for convenience of use. The parameter of thecurves is a new term, the ratio of the RC time constant to theperiod of one half cycle, and is denoted by the Greek letter τ.It may most easily be calculated from the equation

τ = 2RCf. Where: R = resistance in OhmsC = capacitance in Faradsf = frequency in Hertz.


Figure 2.15(a). Capacitor Voltage When Charged

Figure 2.15(b). Expansion of Figure 2.15(a).

1.80

1.40

1.20

1

0.80

0.707

0.60

0.40

0.20

00

18020160

40140

60120

80100

10080

12060

14040 30

16020

1800

DELAY ANGLE IN DEG.CONDUCTION ANGLE IN DEG.

0180

20160

40140

60120

80100

10080

12060

14040

16020

1800

DELAY ANGLE IN DEG.CONDUCTION ANGLE IN DEG.

NO

RM

ALIZ

ED V

OLT

AGE

AS A

FR

ACTI

ON

OF

rms

CH

ARG

ING

SO

UR

CE

VOLT

AGE

NO

RM

ALIZ

ED V

OLT

AGE

AS A

FR

ACTI

ON

OF

rms

CH

ARG

ING

SO

UR

CE

VOLT

AGE

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0

R

CVVC

CAPACITORVOLTAGE, VC

APPLIED VOLTAGE, V

τ = 0.1

0.2

0.3

0.4

0.5

0.7

1

1.5

235

τ = 0.1 0.2 0.3 0.5 0.7 1 1.5 22.5

3

4

5

7

10

15

2050



Figure 2.15(c). Expansion of Figure 2.15(b)

0.1

0.09

0.08

0.07

0.06

0.05

0.04

0.03

0.02

0.01

0NO

RM

ALIZ

ED V

OLT

AGE

AS A

FR

ACTI

ON

OF

rms

CH

ARG

ING

SO

UR

CE

VOLT

AGE

0.0696

0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 DELAY ANGLE IN DEG.

180 170 160 150 140 130 120 110 100 90 80 70 60 50 40 30 20 10 0 CONDUCTIONANGLE IN DEG.rms CHARGING SOURCE VOLTAGE

τ = 0.1 0.2 0.3

0.510.7 1.5 2 2.5 3 4 5 7 8.5

10

12.5

15

20

35

50

To use the curves when starting the capacitor charge fromzero each half cycle, a line is drawn horizontally across thecurves at the relative voltage level of the trigger breakdowncompared to the rms sine wave voltage. The τ is determinedfor maximum and minimum conduction angles and the limitsof R may be found from the equation for τ.

An example will again clarify the picture. Consider thesame problem as the previous example, except that thecapacitor charging source is the 115 Vac, 60 Hz power line.

The ratio of the trigger diode breakover voltage to the RMScharging voltage is then

8/115 = 69.6 10–3.

A line drawn at 0.0696 on the ordinate of Figure 2.15(c)shows that for a conduction angle of 30°, τ = 12, and for aconduction angle of 150°, τ = 0.8. Therefore, sinceR = τ/(2CF)

Rmax12

2(1.0 10–6)60100 k ohms,

Rmin0.8

2(1 10–6 )606667 ohms.

These values would require a potentiometer of 100 k inseries with a 6.2 k minimum fixed resistance.

The timing resistor must be capable of supplying thehighest switching current allowed by the SBS specification atthe switching voltage.

When the conduction angle is less than 90°, triggeringtakes place along the back of the power line sine wave andmaximum firing current thru the SBS is at the start of SBSbreakover. If this current does not equal or exceed “ls” theSBS will fail to trigger and phase control will be lost. This canbe prevented by selecting a lower value resistor and largercapacitor. The available current can be determined fromFigure 2.15(a). The vertical line drawn from the conductionangle of 30° intersects the applied voltage curve at 0.707.The instantaneous current at breakover is then

I = (0.707 115–8)/110 k = 733 µA.

When the conduction angle is greater than 90°, triggeringtakes place before the peak of the sine wave. If the currentthru the SBS does not exceed the switching current at themoment of breakover, triggering may still take place but not atthe predicted time because of the additional delay for therising line voltage to drive the SBS current up to the switchinglevel. Usually long conduction angles are associated with lowvalue timing resistors making this problem less likely. TheSBS current at the moment of breakover can be determinedby the same method described for the trailing edge.

It is advisable to use a shunt gate–cathode resistor acrosssensitive gate SCR’s to provide a path for leakage currentsand to insure that firing of the SCR causes turn–on of thetrigger device and discharge of the gate circuit capacitor.


Figure 2.16(a) shows a simple dc full wave control circuit.RGK is optional on non–sensitive gate parts. Figure 2.16(b)shows an ac control derived from that of Figure 2.16(a).Figure 2.16(c) is a double time constant circuit featuring lowhysteresis.

TRIAC THEORY

The triac is a three–terminal ac semiconductor switchwhich is triggered into conduction when a low–energy signalis applied to its gate. Unlike the silicon controlled rectifier orSCR, the triac will conduct current in either direction whenturned on. The triac also differs from the SCR in that either apositive or negative gate signal will trigger the triac intoconduction. The triac may be thought of as two complemen-tary SCRs in parallel.

The triac offers the circuit designer an economical andversatile means of accurately controlling ac power. It hasseveral advantages over conventional mechanical switches.Since the triac has a positive “on” and a zero current “off”characteristic, it does not suffer from the contact bounce orarcing inherent in mechanical switches. The switching actionof the triac is very fast compared to conventional relays,giving more accurate control. A triac can be triggered by dc,ac, rectified ac or pulses. Because of the low energy requiredfor triggering a triac, the control circuit can use any of manylow–cost solid–state devices such as transistors, bilateralswitches, sensitive–gate SCRs and triacs, optically coupleddrivers and integrated circuits.

CHARACTERISTICS OF THE TRIACFigure 2.17(a) shows the triac symbol and its relationship

to a typical package. Since the triac is a bilateral device, theterms “anode” and “cathode” used for unilateral devices haveno meaning. Therefore, the terminals are simply designatedby MT1, MT2, and G, where MT1 and MT2 are thecurrent–carrying terminals, and G, is the gate terminal usedfor triggering the triac. To avoid confusion, it has becomestandard practice to specify all currents and voltages usingMT1 as the reference point.

The basic structure of a triac is shown in Figure 2.17(b).This drawing shows why the symbol adopted for the triacconsists of two complementary SCRs with a common gate.The triac is a five–layer device with the region between MT1and MT2 being P–N–P–N switch (SCR) in parallel with aN–P–N–P switch (complementary SCR). Also, the structuregives some insight into the triac’s ability to be triggered witheither a positive or negative gate signal. The region betweenMT1 and G consists of two complementary diodes. A positiveor negative gate signal will forward–bias one of these diodescausing the same transistor action found in the SCR. Thisaction breaks down the blocking junction regardless of thepolarity of MT1. Current flow between MT2 and MT1 thencauses the device to provide gate current internally. It willremain on until this current flow is interrupted.

Figure 2.16(a). Simple dc Power Control Circuit

Figure 2.16(b). Simple Full–Wave Power Control

Figure 2.16(c). Full Range ac Power Control

LINE2N6397

MBS4991100RGK

1 µF

15

6.2 k

LOAD

100 kG

LINE

MAC210–4

RGK

1001 µF

G

156.2 k

100 k

MBS4991

LOAD

LINE

MAC210–4

RGK

100

G

15

100 k

MBS4991

LOAD

27 k 0.1 µF

0.22 µF



The voltage–current characteristic of the triac is shown inFigure 2.18 where, as previously stated, MT1 is used as thereference point. The first quadrant, Q–I, is the region whereMT2 is positive with respect to MT1 and quadrant III is theopposite case. Several of the terms used in characterizingthe triac are shown on the figure. VDRM is the breakovervoltage of the device and is the highest voltage the triac maybe allowed to block in either direction. If this voltage isexceeded, even transiently, the triac may go into conductionwithout a gate signal. Although the triac is not damaged bythis action if the current is limited, this situation should beavoided because control of the triac is lost. A triac for aparticular application should have VDRM at least as high asthe peak of the ac waveform to be applied so reliable controlcan be maintained. The holding current (IH) is the minimumvalue of current necessary to maintain conduction. When thecurrent goes below IH, the triac ceases to conduct andreverse to the blocking state. IDRM is the leakage current ofthe triac with VDRM applied from MT2 to MT1 and is severalorders of magnitude smaller than the current rating of thedevice. The figure shows the characteristic of the triacwithout a gate signal applied but it should be noted that thetriac can be triggered into the on state at any value of voltageup to VDRM by the application of a gate signal. This importantcharacteristic makes the triac very useful.

Since the triac will conduct in either direction and can betriggered with either a positive or negative gate signal thereare four possible triggering modes (Figure 2.3):

Quadrant I; MT2(+), G(+), positive voltage and positivegate current. Quadrant II; MT2(+), G(–), positive voltageand negative gate current. Quadrant III; MT2(–), G(–),negative voltage and negative gate current. Quadrant IV;MT2(–), G(+), negative voltage and positive gate current.

Present triacs are most sensitive in quadrants I and III,slightly less so in quadrant II, and much less sensitive inquadrant IV. Therefore it is not recommended to usequadrant IV unless special circumstances dictate it.

An important fact to remember is that since a triac canconduct current in both directions, it has only a brief intervalduring which the sine wave current is passing through zero torecover and revert to its blocking state. For this reason,reliable operation of present triacs is limited to 60 Hz linefrequency and lower frequencies.

For inductive loads, the phase–shift between the currentand voltage means that at the time the current falls below IHand the triac ceases to conduct, there exists a certain voltagewhich must appear across the triac. If this voltage appearstoo rapidly, the triac will resume conduction and control is

MT2

GATE

MT1

MT2

MT1 G

N N

NP

P

N

(a)

(b)

Figure 2.18. Triac Voltage–Current Characteristic

IDRMVDRM

BLOCKING STATEQIII

MT2—ON–STATE

IH

I IH

V

VDRM

Q1MT2+

BLOCKINGSTATE

IDRM

ON–STATE

Figure 2.17. Triac Structure and Symbol

lost. In order to achieve control with certain inductive loads,the rate of rise in voltage (dv/dt) must be limited by a seriesRC network across the triac. The capacitor will then limit thedv/dt across the triac. The resistor is necessary to limit thesurge of current from the capacitor when the triac fires, and todamp the ringing of the capacitance with the load inductance.


METHODS OF CONTROL

AC SWITCHA useful application of triac is as a direct replacement for

an ac mechanical relay. In this application, the triac furnisheson–off control and the power–regulating ability of the triac isnot utilized. The control circuitry for this application is usuallyvery simple, consisting of a source for the gate signal andsome type of small current switch, either mechanical orelectrical. The gate signal can be obtained from a separatesource or directly from the line voltage at terminal MT2 of thetriac.

PHASE CONTROLAn effective and widely–used method of controlling the

average power to a load through the triac is by phase control.Phase control is a method of utilizing the triac to apply the acsupply to the load for a controlled fraction of each cycle. Inthis mode of operation, the triac is held in an off or opencondition for a portion of each positive and negative cycle,and then is triggered into an on condition at a time in the halfcycle determined by the control circuitry. In the on condition,the circuit current is limited only by the load — i.e., the entireline voltage (less the forward drop of the triac) is applied tothe load.

Figure 2.19 shows the voltage waveform along with somecommon terms used in describing triac operation. Delayangle is the angle, measured in electrical degrees, duringwhich the triac is blocking the line voltage. The period duringwhich the triac is on is called the conduction angle.

It is important to note that the triac is either off (blockingvoltage) or fully on (conducting). When it is in the oncondition, the circuit current is determined only by the loadand the power source.

As one might expect, in spite of its usefulness, phasecontrol is not without disadvantages. The main disadvantageof using phase control in triac applications is the generationof electro–magnetic interference (EMI). Each time the triac isfired the load current rises from zero to the load–limitedcurrent value in a very short time. The resulting di/dtgenerates a wide spectrum of noise which may interfere withthe operation of nearby electronic equipment unless properfiltering is used.

ZERO POINT SWITCHINGIn addition to filtering, EMI can be minimized by zero–point

switching, which is often preferable. Zero–point switching is atechnique whereby the control element (in this case the triac)is gated on at the instant the sine wave voltage goes throughzero. This reduces, or eliminates, turn–on transients and theEMI. Power to the load is controlled by providing bursts ofcomplete sine waves to the load as shown in Figure 2.20.Modulation can be on a random basis with an on–off control,or a proportioning basis with the proper type of proportionalcontrol.

In order for zero–point switching to be effective, it mustindeed be zero point switching. If a triac is turned on with aslittle as 10 volts across it into a load of a few–hundred watts,sufficient EMI will result to nullify the advantages of adoptingzero–point switching in the first place.

BASIC TRIAC AC SWITCHESFigure 2.21 shows methods of using the triac as an on–off

switch. These circuits are useful in applications wheresimplicity and reliability are important. As previously stated,there is no arcing with the triac, which can be very importantin some applications. The circuits are for resistive loads asshown and require the addition of a dv/dt network across thetriac for inductive loads. Figure 2.21(a) shows low–voltagecontrol of the triac. When switch S1 is closed, gate current issupplied to the triac from the 10 volt battery. In order toreduce surge current failures during turn on (ton), this currentshould be 5 to 10 times the maximum gate current (IGT)required to trigger the triac.

The triac turns on and remains on until S1 is opened. Thiscircuit switches at zero current except for initial turn on. S1can be a very–low–current switch because it carries only thetriac gate current.

Figure 2.21(b) shows a triac switch with the samecharacteristics as the circuit in Figure 2.21(a) except theneed for a battery has been eliminated. The gate signal isobtained from the voltage at MT2 of the triac prior to turn on.

The circuit shown in Figure 2.21(c) is a modification ofFigure 2.21(b). When switch S1 is in position one, the triacreceives no gate current and is non–conducting. With S1 inposition two, circuit operation is the same as that for Figure2.21(b). In position three, the triac receives gate current onlyon positive half cycles. Therefore, the triac conducts only onpositive half cycles and the power to the load is half wave.

Figure 2.21(d) shows ac control of the triac. The pulse canbe transformer coupled to isolate power and control circuits.Peak current should be 10 times IGT(max) and the RC timeconstant should be 5 times ton(max). A high frequency pulse(1 to 5 kHz) is often used to obtain zero point switching.

Figure 2.19. Sine Wave Showing Principlesof Phase Control

VOLTAGE APPLIED TO LOAD

CONDUCTION ANGLE

DELAY ANGLE



ZERO POINT SWITCHING TECHNIQUES

Zero–point switches are highly desirable in many applica-tions because they do not generate electro–magnetic inter-ference (EMI). A zero–point switch controls sine–wave powerin such a way that either complete cycles or half cycles of thepower supply voltage are applied to the load as shown inFigure 2.22. This type of switching is primarily used to controlpower to resistive loads such as heaters. It can also be usedfor controlling the speed of motors if the duty cycle ismodulated by having short bursts of power applied to theload and the load characteristic is primarily inertial rather thanfrictional. Modulation can be on a random basis with anon–off control, or on a proportioning basis with the propertype of proportioning control.

In order for zero–point switching to be effective, it must betrue zero–point switching. If an SCR is turned on with ananode voltage as low as 10 volts and a load of just a fewhundred watts, sufficient EMI will result to nullify theadvantages of going to zero–point switching in the first place.The thyristor to be turned on must receive gate drive exactlyat the zero crossing of the applied voltage.

The most successful method of zero–point thyristor controlis therefore, to have the gate signal applied before the zerocrossing. As soon as the zero crossing occurs, anodevoltage will be supplied and the thyristor will come on. This iseffectively accomplished by using a capacitor to derive a 90°leading gate signal from the power line source. However,only one thyristor can be controlled from this phase–shiftedsignal, and a slaving circuit is necessary to control the otherSCR to get full–wave power control. These basic ideas areillustrated in Figure 2.23. The slaving circuit fires only on thehalf cycle after the firing of the master SCR. This guaranteesthat only complete cycles of power will be applied to the load.The gate signal to the master SCR receives all the control; aconvenient control method is to replace the switch with alow–power transistor, which can be controlled by bridge–sensing circuits, manually controlled potentiometers, orvarious other techniques.

Figure 2.20. Sine Wave Showing Principles ofZero–Point Switching

LOADVOLTAGE

LINEVOLTAGE

HALF POWER TO LOAD

FULL POWER TO LOAD

(a): Low Voltage Controlled Triac Switch

(b): Triac ac Static Contactor

(c): 3 Position Static Switch

(d): AC Controlled Triac Switch

Figure 2.21. Triac Switches

15 ΩLOAD

15 ΩLOAD

15 ΩLOAD

15 ΩLOAD

2N6346

2N6342

2N6342

2N6346

115 VAC60 Hz

115 VAC60 Hz

115 VAC60 Hz

R147 Ω

R1100 Ω

R1100 Ω

R1

S1

32 1

+

10 V

S1

S1


Figure 2.22. Load Voltage and Line Voltage for25% Duty Cycle

LOAD VOLTAGE

LINE VOLTAGE

A basic SCR is very effective and trouble free. However, itcan dissipate considerable power. This must be taken intoaccount in designing the circuit and its packaging.

In the case of triacs, a slaving circuit is also usuallyrequired to furnish the gate signal for the negative half cycle.However, triacs can use slave circuits requiring less powerthan do SCRs as shown in Figure 2.23. Other considerationsbeing equal, the easier slaving will sometimes make the triaccircuit more desirable than the SCR circuit.

Besides slaving circuit power dissipation, there is anotherconsideration which should be carefully checked when usinghigh–power zero–point switching. Since this is on–off switch-ing, it abruptly applies the full load to the power line everytime the circuit turns on. This may cause a temporary drop involtage which can lead to erratic operation of other electricalequipment on the line (light dimming, TV picture shrinkage,etc.). For this reason, loads with high cycling rates should notbe powered from the same supply lines as lights and othervoltage–sensitive devices. On the other hand, if the loadcycling rate is slow, say once per half minute, the loadingflicker may not be objectionable on lighting circuits.

A note of caution is in order here. The full–wave zero–pointswitching control illustrated in Figure 2.23 should not be usedas a half–wave control by removing the slave SCR. When theslave SCR in Figure 2.23 is removed, the master SCR haspositive gate current flowing over approximately 1/4 of acycle while the SCR itself is in the reverse–blocking state.This occurs during the negative half cycle of the line voltage.When this condition exists, Q1 will have a high leakagecurrent with full voltage applied and will therefore bedissipating high power. This will cause excessive heating ofthe SCR and may lead to its failure. If it is desirable to usesuch a circuit as a half–wave control, then some means ofclamping the gate signal during the negative half cycle mustbe devised to inhibit gate current while the SCR is reverseblocking. The circuits shown in Figures 2.25 and 2.26 do nothave this disadvantage and may be used as half–wavecontrols.

Figure 2.23. Slave and Master SCRs forZero–Point Switching

Figure 2.24. Triac Zero–Point Switch

Figure 2.25. Sensitive–Gate Switch

Figure 2.26. Zero–Point Switch

AC LINE 1501 W

2 µF200 V

LOAD

Q2(SLAVE)

Q1(MASTER)

AC LINE

2 µF200 V

1.2 k7 W

1501 W

MAC210–4

LOADON–OFFCONTROL

LOAD

Q12N4216

D41N5760

C10.25 µF

D21N4004

D31N4004

D11N4004AC

LINE R13.8 k

R28.2 k1 W

R31 k

S1

ACLINE

D11N4004

S1

C210 nF200 V

R13.8 k

R28.2 k1 W

C10.25 µF200 V

D31N4004

D21N4004

D41N5760

R3100

Q1MCR218–4

LOAD



OPERATION

The zero–point switches shown in Figure 2.25 and 2.26are used to insure that the control SCR turns on at the start ofeach positive alternation. In Figure 2.25 a pulse is generatedbefore the zero crossing and provides a small amount of gatecurrent when line voltage starts to go positive. This circuit isprimarily for sensitive–gate SCRs. Less–sensitive SCRs,with their higher gate currents, normally require smallervalues for R1 and R2 and the result can be high powerdissipation in these resistors. The circuit of Figure 2.26 usesa capacitor, C2, to provide a low–impedance path aroundresistors R1 and R2 and can be used with less–sensitive,higher–current SCRs without increasing the dissipation. Thiscircuit actually oscillates near the zero crossing point andprovides a series of pulses to assure zero–point switching.

The basic circuit is that shown in Figure 2.25. Operationbegins when switch S1 is closed. If the positive alternation ispresent, nothing will happen since diode D1 is reversebiased. When the negative alternation begins, capacitor C1will charge through resistor R2 toward the limit of voltage setby the voltage divider consisting of resistors R1 and R2. Asthe negative alternation reaches its peak, C1 will havecharged to about 40 volts. Line voltage will decrease but C1cannot discharge because diode D2 will be reverse biased. Itcan be seen that C1 and three–layer diode D4 are effectivelyin series with the line. When the line drops to 10 volts, C1 willstill be 40 volts positive with respect to the gate of Q1. At thistime D4 will see about 30 volts and will trigger. This allows C1to discharge through D3, D4, the gate of Q1, R2, and R1.This discharge current will continue to flow as the line voltagecrosses zero and will insure that Q1 turns on at the start ofthe positive alternation. Diode D3 prevents reverse gate–cur-rent flow and resistor R3 prevents false triggering.

The circuit in Figure 2.26 operates in a similar manner upto the point where C1 starts to discharge into the gate. Thedischarge path will now be from C1 through D3, D4, R3, thegate of Q1, and capacitor C2. C2 will quickly charge from thishigh pulse of current. This reduces the voltage across D4causing it to turn off and again revert to its blocking state.Now C2 will discharge through R1 and R2 until the voltage onD4 again becomes sufficient to cause it to break back. Thisrepetitive exchange of charge from C1 to C2 causes a seriesof gate–current pulses to flow as the line voltage crosseszero. This means that Q1 will again be turned on at the startof each positive alternation as desired. Resistor R3 has beenadded to limit the peak gate current.

AN SCR SLAVING CIRCUIT

An SCR slaving circuit will provide full–wave control of anac load when the control signal is available to only one of apair of SCRs. An SCR slaving circuit is commonly usedwhere the master SCR is controlled by zero–point switching.Zero–point switching causes the load to receive a full cycle ofline voltage whenever the control signal is applied. The dutycycle of the control signal therefore determines the averageamount of power supplied to the load. Zero–point switching isnecessary for large loads such as electric heaters becauseconventional phase–shift techniques would generate anexcessive amount of electro–magnetic interference (EMI).

This particular slaving circuit has two important advan-tages over standard RC discharge slaving circuits. It derivesthese advantages with practically no increase in price byusing a low–cost transistor in place of the current–limitingresistor normally used for slaving. The first advantage is thata large pulse of gate current is available at the zero–crossingpoint. This means that it is not necessary to select sensitive–gate SCRs for controlling power. The second advantage isthat this current pulse is reduced to zero within onealternation. This has a couple of good effects on theoperation of the slaving SCR. It prevents gate drive fromappearing while the SCR is reverse–biased, which wouldproduce high power dissipation within the device. It alsoprevents the slaved SCR from being turned on for additionalhalf cycles after the drive is removed from the control SCR.

OPERATIONThe SCR slaving circuit shown in Figure 2.27 provides a

single power pulse to the gate of SCR Q2 each time SCR Q1turns on, thus turning Q2 on for the half cycle following theone during which Q1 was on. Q2 is therefore turned on onlywhen Q1 is turned on, and the load can be controlled by asignal connected to the gate of Q1 as shown in theschematic. The control signal an be either dc or a powerpulse. If the control signal is synchronized with the powerline, this circuit will make an excellent zero–point switch.During the time that Q1 is on, capacitor C1 is chargedthrough R1, D1 and Q1. While C1 is being charged, D1reverse–biases the base–emitter junction of Q3, therebyholding it off. The charging time constant, R1, C1, is set longenough that C1 charges for practically the entire half cycle.The charging rate of C1 follows an “S” shaped curve,charging slowly at first, then faster as the supply voltagepeaks, and finally slowly again as the supply voltagedecreases. When the supply voltage falls below the voltageacross C1, diode D1 becomes reverse biased and thebase–emitter of Q3 becomes forward biased. For the valuesshown, this occurs approximately 6° before the end of thehalf cycle conduction of Q1. The base current is derived fromthe energy stored in C1. This turns on Q3, discharging C1through Q3 and into the gate of Q2. As the voltage across C1decreases, the base drive of Q3 decreases and somewhatlimits the collector current. The current pulse must last untilthe line voltage reaches a magnitude such that latchingcurrent will exist in Q2. The values shown will deliver a

R1

1N4004

Q3MPS3638

Q22N6397

Q12N6397

INPUT SIGNAL

1000 W MAX10 k2 W

5 µF50 V

+C1

120 VAC60 Hz

Figure 2.27. SCR Slave Circuit

*1000 WATT LOAD. SEE TEXT.

CONTROLSCR


current pulse which peaks at 100 mA and has a magnitudegreater than 50 mA when the anode–cathode voltage of Q2reaches plus 10 volts. This circuit completely discharges C1during the half cycle that Q2 is on. This eliminates thepossibility of Q2 being slaved for additional half cycles afterthe drive is removed from Q1. The peak current and the

current duration are controlled by the values of R1 and C1.The values chosen provide sufficient drive for “shortedemitter” SCRs which typically require 10 to 20 mA to fire. Theparticular SCR used must be capable of handling themaximum current requirements of the load to be driven; the 8ampere, 200 V SCRs shown will handle a 1000 watt load.


CHAPTER 3THYRISTOR DRIVERS AND TRIGGERING

Triggering a thyristor requires meeting its gate energyspecifications and there are many ways of doing this. Ingeneral, the gate should be driven hard and fast to ensurecomplete gate turn on and thus minimize di/dt effects. Usuallythis means a gate current of at least three times the gate turnon current with a pulse rise of less than one microsecond anda pulse width greater than 10 microseconds. The gate canalso be driven by a dc source as long as the average gatepower limits are met.

Some of the methods of driving the gate include:1) Direct drive from logic families of transistors2) Opto triac drivers3) Programmable unijunction transistors (PUTs)4) Silicon bilateral switches (SBSs)5) SIDACs

In this chapter we will discuss all of these, as well as someof the important design and application considerations intriggering thyristors in general. In the chapter on applications,we will also discuss some additional considerations relatingto drivers and triggers in specific applications.

PULSE TRIGGERING OF SCRs

GATE TURN–ON MECHANISM

The turn–on of PNPN devices has been discussed in manypapers where it has been shown that the condition of

switching is given by dvdi

= 0 (i.e., α1 + α2 = 1, where α1 and

α2 are the current amplification factors of the two “transis-tors.’’ However, in the case of an SCR connected to a reversegate bias, the device can have α1 + α2 = 1 and still stay in theblocking state. The condition of turn–on is actually α1 + α2 1.

The current amplification factor, α, increases with emittercurrent; some typical curves are shown in Figure 3.1. Themonotonical increase of α with IE of the device in the blockingstate makes the regeneration of current (i.e., turn–on)possible.

Using the two transistor analysis, the anode current, IA,can be expressed as a function of gate current, IG, as:

EMITTER CURRENT DENSITY (A/mm2)

1010–3

0.8

0.4

0.2

0

1.010–2 10–1

0.6

1.0

102

, CO

MM

ON

BAS

E C

UR

REN

T G

AIN

W ≥ BASE WIDTHL ≥ DIFFUSION LENGTH

WL 0.1

WL 0.5

WL 1.0

Figure 3.1. Typical Variation of Transistor α withEmitter Current Density

IA2 IG ICS1 ICS2

1 1 2(1)

Definitions and derivations are given in Appendix I. Note thatthe anode current, IA, will increase to infinity as α1 + α2 = 1. Thisanalysis is based upon the assumption that no majoritycarrier current flows out of the gate circuit. When no suchassumption is made, the condition for turn–on is given by:

IKIA

1 12

(2)

which corresponds to α1 + α2 1 (see Appendix I).



P1 N1 P2 N2

J1 J2 J3

IG

GATE (G)

ANODE(A)

CATHODE(K)

IA IK

Figure 3.2. Schematic Structure of an SCR, PositiveCurrents Are Defined as Shown by the Arrows

Current regeneration starts when charge or current isintroduced through the gate (Figure 3.2). Electrons areinjected from the cathode across J3; they travel across theP2 “base’’ region to be swept out by the collector junction,J2, and thrown into the N1 base. The increase of majoritycarrier electrons in region N1 decreases the potential inregion N1, so that holes from P1 are injected across thejunction J1, into the N1 “base’’ region to be swept across J2,and thrown into the P2 “base’’ region. The increase in thepotential of region P2 causes more electrons to be injectedinto P2, thereby repeating the cycle. Since α increases withthe emitter current, an increase of regeneration takes placeuntil α1 + α2 1. Meanwhile, more carriers are collected thanemitted from either of the emitters. The continuity of chargeflow is violated and there is an electron build–up on the N1side of J2, and a hole build–up on the P2 side. When theinert impurity charges are compensated for by injectedmajority carriers, the junction J2 becomes forward biased.

The collector emits holes back to J1 and electrons to J3 untila steady state continuity of charge is established.

During the regeneration process, the time it takes for aminority carrier to travel across a base region is the transittime, t, which is given approximately as:

where Wi base width(3)t1

W2i2Di Di diffusion length

(The subscript “i’’ can be either 1 or 2 to indicate theappropriate base.) The time taken from the start of the gatetrigger to the turn–on of the device will be equal to somemultiple of the transit time.

CURRENT PULSE TRIGGERINGCurrent pulse triggering is defined as supplying current

through the gate to compensate for the carriers lost byrecombination in order to provide enough current to sustainincreasing regeneration. If the gate is triggered with a currentpulse, shorter pulse widths require higher currents as shownby Figure 3.3(a). Figure 3.3(a) seems to indicate there is aconstant amount of charge required to trigger on the devicewhen IG is above a threshold level. When the chargerequired for turn–on plotted versus pulse current or pulsewidth, there is an optimum range of current levels or pulsewidths for which the charge is minimum, as shown in region Aof Figure 3.3(b) and (c). Region C shows that for lowercurrent levels (i.e., longer minimum pulse widths) morecharge is required to trigger on the device. Region B showsincreasing charge required as the current gets higher and thepulse width smaller.

, PULSE WIDTH (s)

1.00.05

80

40

20

00.50.1 0.2

60

100

2.0

i

VAK = 10 VTA = 25°C

5.0 10

IG THRESHOLD

HIGH UNIT

LOWUNIT

, MIN

IMU

M G

ATE

TRIG

GER

CU

RR

ENT

(mA)

G

iG, GATE CURRENT (mA)

2.0

20

5.0

2.0

1.05.0 10

10

100

20

Q

VAK = 10 VTA = 25°C

50 100

HIGH UNITLOWUNIT

, MIN

IMU

M T

RIG

GER

CH

ARG

E (n

c)in

50

A

ITH

RES

HO

LDG

ITH

RES

HO

LDG

C B

C BA

Figure 3.3(a). Typical Variation of Minimum GateCurrent Required to Trigger

Figure 3.3(b). Variation of Charge versus Gate Current


t, MINIMUM PULSE WIDTH (s)

1.00.05

20

5.0

2.0

1.00.50.1 0.2

10

100

2.0

QVAK = 10 VT = 25°C

5.0 10

HIGH UNIT

LOWUNIT

, MIN

IMU

M T

RIG

GER

CH

ARG

E (n

c)in

50

(Q = it)

CB A

Figure 3.3(c). Variation of Charge versus MinimumPulse Width

The charge characteristic curves can be explainedqualitatively by the variation of current amplification (αT)with respect to emitter current. A typical variation of α1 andα2 for a thyristor is shown in Figure 3.4(a). From Figure

3.4(a), it can be deduced that the total current amplificationfactor, αT = α1 + α2, has a characteristic curve as shown inFigure 3.4(b). (The data does not correspond to the data ofFigure 3.3 — they are taken for different types of devices.)

The gate current levels in region A of Figure 3.3 corre-spond to the emitter (or anode) currents for which the slope ofthe αT curve is steepest (Figure 3.4(b)). In region A the ratethat αT builds up with respect to changes of IE (or IA) is high,little charge is lost by recombination, and therefore, aminimum charge is required for turn–on.

In region C of Figure 3.3, lower gate current corresponds tosmall IE (or IA) for which the slope of αT, as well as αT itself, issmall. It takes a large change in IE (or IA) in order to build upαT. In this region, a lot of the charge supplied through the gateis lost by recombination. The charge required for turn–onincreases markedly as the gate current is decreased to thethreshold level. Below this threshold, the device will not turnon regardless of how long the pulse width becomes. At thispoint, the slope of αT is equal to zero; all of the chargesupplied is lost completely in recombination or drained outthrough gate–cathode shunt resistance. A qualitative analysis of variation of charge with pulse width at region A and C isdiscussed in Appendix II.

In region B, as the gate current level gets higher and thepulse width smaller, there are two effects that contribute to anincreasing charge requirement to trigger–on the device: (1)the decreasing slope of αT and, (2) the transit time effect. Asmentioned previously, it takes some multiple of the transittime for turn–on. As the gate pulse width decreases to N (tN1+ tP2) or less, (where N is a positive real number, tN1 = transittime of base N1, and tP2 = transit time of base P2) the amount

IE, EMITTER CURRENT (mA)

3000.1

0.8

0.4

0.2

0

1001.0 10

0.6

1.0

, CU

RR

ENT

AMPL

IFIC

ATIO

N F

ACTO

R

N–P–N SECTION 2

P–N–P SECTION 1

IE, EMITTER CURRENT (mA)

3000.1

0.8

0.4

0.2

0

1001.0 10

0.6

1.4

, CU

RR

ENT

AMPL

IFIC

ATIO

N F

ACTO

R

1.0

1.2

A

B

C

Figure 3.4(a). The Variation of α1 and α2 with EmitterCurrent for the Two Sections of Two Typical

Silicon Controlled Rectifiers

Figure 3.4(b). Typical Variation of αT versus EmitterCurrent



of current required to turn–on the device should be largeenough to flood the gate to cathode junction nearly instanta-neously with a charge which corresponds to IE (or IA) highenough to give αT 1.

CAPACITANCE CHARGE TRIGGERING

Using a gate trigger circuit as shown in Figure 3.5, thecharge required for turn–on increases with the value ofcapacitance used as shown in Figure 3.7. Two reasons mayaccount for the increasing charge characteristics:

1) An effect due to threshold current.2) An effect due to variation of gate spreading resistance.

0

TOCOMMUTATING

CIRCUIT

SCR

CRS

V1

Figure 3.5. Gate Circuit of Capacitance ChargeTriggering

Figure 3.6. Gate Current Waveform in CapacitanceCharge Triggering

ÇÇÇÇÇÇÇÇÉÉÉÉÉÉ

V1rG1 RS

V2rG2 RS

e t(rG2 RS)C2

et(rG1 RS)C1

V2rG2 RS

V1rG1 RS

C1 C2V1C1 V2C2

10%

90%

|(r′G1 + RS)(C1)|(Ithr) < |(r′G2 + RS)(C2) |(Ithr)

tfi = 2.2 (r′G1 + RS)C1SHADED AREA I = |(r′G1 + RS)(C1)|(Ithr)SHADED AREA II = |(r′G2 + RS)(C2)|(Ithr)

PULSE WIDTH,

tf2

tf1

Ithr

III

Consider the gate current waveform in Figure 3.6; thetriggering pulse width is made large enough such that τtfl;the threshold trigger current is shown as Ithr. All of the chargesupplied at a transient current level less than Ithr is lost byrecombination, as shown in the shaded regions.

The gate spreading resistance (r′G) of the gate junctionvaries inversely with peak current; the higher the peakcurrent, the smaller the gate spreading resistance. Variationof gate spreading resistance measured by the method ofTime Domain Reflectometry is plotted in Figure 3.8.

From the data of Figure 3.7, it is clear that for largervalues of capacitance a lower voltage level is required forturn–on. The peak current of the spike in Figure 3.6 is given

by Ipk∆V

Rs r′G; the smaller ∆V, the smaller Ipk. Smaller

Ipk in turn yields large r′G, so that r′G is dependent on thevalue of capacitance used in capacitance charge triggering.This reasoning is confirmed by measuring the fall time of thegate trigger voltage and calculating the transient gate

spreading resistance, r′G, from: Rs r′Gtf

2.2 C. Results

are plotted in Figure 3.9. As expected, r′G increases withincreasing values of capacitance used. Referring back toFigure 3.6, for the same amount of charge (C ∆V), the largerthe (Rs + r′G)C time constant of the current spike, the morecharge under the threshold level is lost in recombination.Increasing the value of C will increase the time constant morerapidly than if r′G were invariant. Therefore, increasing thevalue of C should increase the charge lost as shown inFigure 3.7. Note that a two order of magnitude increase incapacitance increased the charge by less than 3:1.

C, CAPACITANCE (pF)

2000100

7.0

3.0

2.0

1.01000200 500

5.0

10

5000

, MIN

IMU

M T

RIG

GER

CH

ARG

E, Q

(nc)

15

Qin

10,000

VAK = 10 VTA = –15°C

HIGH UNIT

LOW UNIT

PULSE WIDTH = 50 s

Figure 3.7. Variation of Trigger Charge versusCapacitance Used


GATE CURRENT (mA)

2000.1

3.0

0.5

0.3

0.210020 50

2.0

1.0

500

NO

RM

ALIZ

ED G

ATE

SPR

EAD

ING

RES

ISTA

NC

E

1000

LOW UNIT

HIGH UNITIA = 1 ATA = 25°CVAK = 10 V

Z0 = 50

0.7

Figure 3.8. Variation of Gate Spreading Resistanceversus Gate Peak Current

EFFECT OF TEMPERATURE

The higher the temperature, the less charge required toturn on the device, as shown in Figure 3.10. At the range oftemperatures where the SCR is operated the life time ofminority carriers increases with temperature; therefore lesscharge into the gate is lost in recombination.

As analyzed in Appendix II, there are three components ofcharge involved in gate triggering: (1) Qr, charge lost inrecombination, (2) Qdr, charge drained out through thebuilt–in gate–cathode shunt resistance, (3) Qtr, net charge fortriggering. All of them are temperature dependent. Since thetemperature coefficient of voltage across a p–n junction issmall, Qdr may be considered invariant of temperature. At thetemperature range of operation, the temperature is too low togive rise to significant impurity gettering, lifetime increaseswith temperature causing Qr to decrease with increasingtemperature. Also, Qtr decreases with increasing tempera-ture because at a constant current the αT of the device in theblocking state increases with temperature;7 in other words, toattain αT = 1 at an elevated temperature, less anode current,hence gate current [see equation (3) of Appendix I], isneeded; therefore, Qtr decreases. The input charge, beingequal to the sum of Qtr, Qr, and Qdr, decreases withincreasing temperature.

The minimum current trigger charge decreases roughlyexponentially with temperature. Actual data taken on anMCR729 deviate somewhat from exponential trend (Fig-ure 3.10). At higher temperatures, the rate of decrease isless; also for different pulse widths the rates of decrease ofQin are different; for large pulse widths the recombinationcharge becomes more significant than that of small pulsewidths. As the result, it is expected and Figure 3.10 showsthat Qin decreases more rapidly with temperature at high

C, CAPACITANCE (pF)

1000200

30

10

20

0300 500

40

2000

r

VAK = 10 VT = 25°C

, GAT

E SP

REA

DIN

G R

ESIS

TAN

CE

( )

G′

(RS rG )tf

2.2C

T, TEMPERATURE (°C)

+65–15

10

8.0

9.0

4.0+25

20

+105

Q

VAK = 10 Vt = GATE CURRENT PULSE WIDTH

(Q = it)

, MIN

IMU

M T

RIG

GER

CH

ARG

E (n

c)in

7.0

6.0

5.0

t = 1 s

t = 500 nst = 100 ns

t = 300 ns

Figure 3.9. Variation of Transient Base SpreadingResistance versus Capacitance

Figure 3.10. Variation of Q versus Temperature

pulse widths. These effects are analyzed in Appendix II[equation (7), page 1–9–2]. The theory and experimentagree reasonably well.



EFFECT OF BLOCKING VOLTAGE

An SCR is an avalanche mode device; the turn–on of thedevice is due to multiplication of carriers in the middlecollector junction. The multiplication factor is given by theempirical equation

M · 1

1 ( VVB

)n(6)

where

M Multiplication factor

V Voltage across the middle “collector’’ junction(voltage at which the device is blocking prior toturn–on)

VB Breakdown voltage of the middle “collector’’ junction

n Some positive number

Note as V is increased, M also increases and in turn αincreases (the current amplification factor α = γδβM whereγ Emitter efficiency, β Base transport factor, and δ Factor of recombination).

The larger the V, the larger is α T. It would be expected forthe minimum gate trigger charge to decrease with increasingV. Experimental results show this effect (see Figure 3.11). Forthe MCR729, the gate trigger charge is only slightly affected

by the voltage at which the device is blocking prior to turn–on;this reflects that the exponent, n, in equation (6) is small.

EFFECT OF GATE CIRCUIT

As mentioned earlier, to turn on the device, the totalamplification factor must be greater than unity. This meansthat if some current is being drained out of the gate whichbleeds the regeneration current, turn–on will be affected. Thehigher the gate impedance, the less the gate trigger charge.Since the regenerative current prior to turn–on is small, thegate impedance only slightly affects the required minimumtrigger charge; but in the case of over–driving the gate toachieve fast switching time, the gate circuit impedance willhave noticeable effect.

EFFECT OF INDUCTIVE LOAD

The presence of an inductive load tends to slow down thechange of anode current with time, thereby causing therequired charge for triggering to increase with the value ofinductance. For dc or long pulse width current triggering, theinductive load has little effect, but its effect increasesmarkedly at short pulse widths, as shown in Figure 3.12. Theincrease in charge occurs because at short pulse widths, thetrigger signal has decreased to a negligible value before theanode current has reached a level sufficient to sustainturn–on.

VAK, ANODE VOLTAGE (V)

3010

10

8.09.0

4.0

20 50

Q TA = 25°CPW = 500 ns

0.05 F CAP. DISCHARGE

, MIN

IMU

M T

RIG

GER

CH

ARG

E (n

c)in

7.0

6.0

5.0

2.0

3.0

1.0100 200 500 1000

#1

#2

#3

t, MINIMUM PULSE WIDTH (ns)

30

80

40

50

Q

TA = 25°CVAK = 10 V

, MIN

IMU

M T

RIG

GER

CH

ARG

E (n

c)in

60

20

0100 200 500 100070 300 700

L = 100 H

L = 10 H

L = 0 H

Figure 3.11. Variation of Current Trigger Charge versusBlocking Voltage Prior to Turn–On

Figure 3.12. Effect of Inductance Load on TriggeringCharge


USING NEGATIVE BIAS AND SHUNTING

Almost all SCR’s exhibit some degree of turn–off gain. Atnormal values of anode current, negative gate current will nothave sufficient effect upon the internal feedback loop of thedevice to cause any significant change in anode current.However, it does have a marked effect at low anode currentlevels; it can be put to advantage by using it to modify certaindevice parameters. Specifically, turn–off time may be reducedand hold current may be increased. Reduction of turn–off timeand increase of hold current are useful in such circuits asinverters or in full–wave phase control circuits in whichinductance is present.

Negative gate current may, of course, be produced by useof an external bias supply. It may also be produced by takingadvantage of the fact that during conduction the gate ispositive with respect to the cathode and providing an externalconduction path such as a gate–to–cathode resistor. AllMotorola SCR’s, with the exception of sensitive gate devices,are constructed with a built in gate–to–cathode shunt, whichproduces the same effect as negative gate current. Furtherchange in characteristics can be produced by use of anexternal shunt. Shunting does not produce as much of achange in characteristics as does negative bias, since thenegative gate current, even with an external short circuit, islimited by the lateral resistance of the base layer. When usingexternal negative bias the current must be limited, and caremust be taken to avoid driving the gate into the avalancheregion.

The effects of negative gate current are not shown on thedevice specification sheets. The curves in Figure 3.13represent measurements made on a number of SCRs, andshould therefore not be considered as spec limits. They do,however, show definite trends. For example, all of the SCRsshowed an improvement in turn–off time of about one–thirdby using negative bias up to the point where no furthersignificant improvement was obtained. The increase in hold

GATE–TO–CATHODE RESISTANCE (OHMS)

1.0

1.2

1.0

10010

1.6

1.4

5000

NO

RM

ALIZ

ED H

OLD

ING

CU

RR

ENT

1000

SPREAD OF 5 DEVICES

Figure 3.13(a). Normalized Holding Currentversus Gate–to–Cathode Resistance

current by use of an external shunt resistor ranged typicallybetween 5 and 75 percent, whereas with negative bias, therange of improvement ran typically between 2–1/2 and 7times the open gate value. Note that the holding currentcurves are normalized and are referred to the open gate value.

GATE–TO–CATHODE VOLTAGE (VOLTS)

0

2.0

–4.0–2.0

6.0

4.0

–8.0

NO

RM

ALIZ

ED H

OLD

ING

CU

RR

ENT

–6.0

SPREAD OF 5 DEVICES

–100

GATE–TO–CATHODE VOLTAGE (VOLTS)

0

2.0

–5.0

6.0

4.0

TUR

N–O

FF T

IME

( s

)

AVERAGE 10 DEVICES

–100

IF = 10 A

IF = 5 A

Figure 3.13(b). Normalized Holding Currentversus Gate–to–Cathode Voltage

Figure 3.13(c). Turn–Off Time versus Bias

REDUCING di/dt — EFFECT FAILURES

Figure 3.14 shows a typical SCR structural cross section(not to scale). Note that the collector of transistor 1 and thebase of transistor 2 are one and the same layer. This is alsotrue for the collector of transistor 2 and the base of transistor1. Although for optimum performance as an SCR the basethicknesses are great compared to a normal transistor,nevertheless, base thickness is still small compared to thelateral dimensions. When applying positive bias to the gate,the transverse base resistance, spreading resistance or rb′will cause a lateral voltage drop which will tend to forwardbias those parts of the transistor 1 emitter–junction closest tothe base contact (gate) more heavily, or sooner than theportions more remote from the contact area. Regenerative



action, consequently will start in an area near the gatecontact, and the SCR will turn on first in this area. Once on,conduction will propagate across the entire junction.

CATHODET2 T1LAYER

(C) (B)

(B) (C)

(E)

(E)

GATE

NO. 4

NO. 3

NO. 2

NO. 1

ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ

P

N

N

P

ANODE

ÉÉÉÉ

ÉÉÉÉ

TYPICAL SCRCONSTRUCTIONSHOWING THEDIE IN PROPERSCALE…

Figure 3.14(a). Construction of Typical SCR

Figure 3.14 (b)

The phenomenon of di/dt failure is related to the turn–onmechanism. Let us look at some of the external factorsinvolved and see how they contribute. Curve 3.15(a) showsthe fall of anode–to–cathode voltage with time. This fallfollows a delay time after the application of the gate bias. Thedelay time and fall time together are called turn–on time, and,depending upon the device, will take anywhere from tens ofnanoseconds up to a few microseconds. The propagation ofconduction across the entire junction requires a considerablylonger time. The time required for propagation or equalizationof conduction is represented approximately by the timerequired for the anode–to–cathode voltage to fall from the 10percent point to its steady state value for the particular valueof anode current under consideration (neglecting the changedue to temperature effects). It is during the interval of timebetween the start of the fall of anode–to–cathode voltage andthe final equalization of conduction that the SCR is mostsusceptible to damage from excessive current.

Let us superimpose a current curve (b) on the anode–to–cathode voltage versus time curve to better understand this.If we allow the current to rise rapidly to a high value we find bymultiplying current and voltage that the instantaneousdissipation curve (c) reaches a peak which may be hundredsof times the steady state dissipation level for the same valueof current.

At the same time it is important to remember that thedissipation does not take place in the entire junction, but isconfined at this time to a small volume. Since temperature isrelated to energy per unit volume, and since the energy putinto the device at high current levels may be very large whilethe volume in which it is concentrated is very small, very highspot temperatures may be achieved. Under such conditions,it is not difficult to attain temperatures which are sufficient tocause localized melting of the device.

Even if the peak energy levels are not high enough to bedestructive on a single–shot basis, it must be realized thatsince the power dissipation is confined to a small area, thepower handling capabilities of the device are lessened. Forpulse service where a significant percentage of the powerper pulse is dissipated during the fall–time interval, it is notacceptable to extrapolate the steady state power dissipationcapability on a duty cycle basis to obtain the allowable peakpulse power.

TIME (s)

0.1 1.0

100

50

PER

CEN

T O

F M

AXIM

UM

(%)

0

INSTANTANEOUSPOWERDISSIPATION (c)

ANODE TO CATHODEVOLTAGE (a)

ANODECURRENT (b)

Figure 3.15. Typical Conditions — Fast–Rise, HighCurrent Pulse

The final criterion for the limit of operation is junctiontemperature. For reliable operation the instantaneous junc-tion temperature must always be kept below the maximumjunction temperature as stated on the manufacturer’s datasheet. Some SCR data sheets at present include informationon how to determine the thermal response of the junction tocurrent pulses. This information is not useful, however, fordetermining the limitations of the device before the entirejunction is in conduction, because they are based onmeasurements made with the entire junction in conduction.


At present, there is no known technique for making areasonably accurate measurement of junction temperature inthe time domain of interest. Even if one were to devise amethod for switching a sufficiently large current in a shortenough time, one would still be faced with the problem ofcharge storage effects in the device under test masking thethermal effects. Because of these and other problems, itbecomes necessary to determine the device limitationsduring the turn–on interval by destructive testing. Theresultant information may be published in a form such as amaximum allowable current versus time, or simply as amaximum allowable rate of rise of anode current (di/dt).

Understanding the di/dt failure mechanism is part of theproblem. To the user, however, a possible cure is infinitelymore important. There are three approaches that should beconsidered.

Because of the lateral base resistance the portion of thegate closest to the gate contact is the first to be turned onbecause it is the first to be forward biased. If the minimumgate bias to cause turn–on of the device is used, the spot inwhich conduction is initiated will be smallest in size. Byincreasing the magnitude of the gate trigger pulse to severaltimes the minimum required, and applying it with a very fastrise time, one may considerably increase the size of the spotin which conduction starts. Figure 3.16(a) illustrates the effectof gate drive on voltage fall time and Figure 3.16(b) showsthe improvement in instantaneous dissipation. We mayconclude from this that overdriving the gate will improve thedi/dt capabilities of the device, and we may reduce the stresson the device by doing so.

t, TIME (s)

4.00

300

100

50

03.52.5 3.0

250

200

4.5

ANO

DE

TO C

ATH

OD

E VO

LTAG

E (V

OLT

S)

5.0

150

2.01.50.5 1.0

350

PEAK ANODE CURRENT = 500 A

IGT = 2 A

IGT = 17 mA

Figure 3.16(a). Effect of Gate Drive on Fall Time

A very straightforward approach is to simply slow down therate of rise of anode current to insure that it stays within thedevice ratings. This may be done simply by adding someseries inductance to the circuit.

t, TIME (s)

4.00

60

20

10

03.52.5 3.0

50

40

4.5

INST

ANTA

NEO

US

POW

ER D

ISSI

PATI

ON

(kW

)

5.0

30

2.01.50.5 1.0

70

PEAK ANODE CURRENT = 500 A

IGT = 2 A

IGT = 17 mA

Figure 3.16(b). Effect of Gate Drive OnTurn–On Dissipation

If the application should require a rate of current risebeyond the rated di/dt limit of the device, then anotherapproach may be taken. The device may be turned on to arelatively low current level for a sufficient time for a large partof the junction to go into conduction; then the current levelmay be allowed to rise much more rapidly to very high levels.This might be accomplished by using a delay reactor asshown in Figure 3.17. Such a reactor would be wound on asquare loop core so that it would have sharp saturationcharacteristic and allow a rapid current rise. It is also possibleto make use of a separate saturation winding. Under theseconditions, if the delay is long enough for the entire junctionto go into conduction, the power handling capabilities of thedevice may be extrapolated on a duty cycle basis.

SCR

RL

DELAYREACTOR

+

–

Figure 3.17. Typical Circuit Use of a Delay Reactor

WHY AND HOW TO SNUB THYRISTORS

Inductive loads (motors, solenoids, etc.) present a problemfor the power triac because the current is not in phase withthe voltage. An important fact to remember is that since atriac can conduct current in both directions, it has only a briefinterval during which the sine wave current is passingthrough zero to recover and revert to its blocking state. Forinductive loads, the phase shift between voltage and currentmeans that at the time the current of the power handling triacfalls below the holding current and the triac ceases toconduct, there exists a certain voltage which must appear



across the triac. If this voltage appears too rapidly, the triacwill resume conduction and control is lost. In order to achievecontrol with certain inductive loads, the rate of rise in voltage(dv/dt) must be limited by a series RC network placed inparallel with the power triac as shown in Figure 3.18. Thecapacitor CS will limit the dv/dt across the triac.

The resistor RS is necessary to limit the surge current fromCS when the triac conducts and to damp the ringing of thecapacitance with the load inductance LL. Such an RCnetwork is commonly referred to as a “snubber.’’

Figure 3.19 shows current and voltage waveforms for thepower triac. Commutating dv/dt for a resistive load is typicallyonly 0.13 V/µs for a 240 V, 50 Hz line source and 0.063 V/µsfor a 120 V, 60 Hz line source. For inductive loads the“turn–off’’ time and commutating dv/dt stress are more difficultto define and are affected by a number of variables such asback EMF of motors and the ratio of inductance to resistance(power factor). Although it may appear from the inductiveload that the rate or rise is extremely fast, closer circuitevaluation reveals that the commutating dv/dt generated isrestricted to some finite value which is a function of the loadreactance LL and the device capacitance C but still mayexceed the triac’s critical commutating dv/dt rating which isabout 50 V/µs. It is generally good practice to use an RCsnubber network across the triac to limit the rate of rise (dv/dt)to a value below the maximum allowable rating. This snubbernetwork not only limits the voltage rise during commutationbut also suppresses transient voltages that may occur as aresult of ac line disturbances.

There are no easy methods for selecting the values for RSand CS of a snubber network. The circuit of Figure 3.18 is adamped, tuned circuit comprised of RS, CS, RL and LL, and toa minor extent the junction capacitance of the triac. When thetriac ceases to conduct (this occurs every half cycle of theline voltage when the current falls below the holding current),the triac receives a step impulse of line voltage whichdepends on the power factor of the load. A given load fixesRL and LL; however, the circuit designer can vary RS and CS.Commutating dV/dt can be lowered by increasing CS whileRS can be increased to decrease resonant “over ringing’’ ofthe tuned circuit.

RS

ZEROCROSSING

CIRCUIT

AC

LOAD

CS

R

LL RL

6

5

4

1

2

3

Figure 3.18. Triac Driving Circuit — with Snubber

BASIC CIRCUIT ANALYSISFigure 3.20 shows an equivalent circuit used for analysis,

in which the triac has been replaced by an ideal switch.When the triac is in the blocking or non–conducting state,represented by the open switch, the circuit is a standard RLC

AC LINEVOLTAGE

AC CURRENT

VOLTAGEACROSSPOWER TRIAC

IF(ON)IF(OFF)

TIMEt0

COMMUTATINGdv/dt

RESISTIVE LOAD

AC LINEVOLTAGE

AC CURRENTTHROUGHPOWER TRIAC

VOLTAGEACROSSPOWER TRIAC

IF(ON)IF(OFF)

TIME

t0

COMMUTATINGdv/dt

INDUCTIVE LOAD

0

d

Figure 3.19. Current and Voltage WaveformsDuring Commutation

series network driven by an ac voltage source. The followingdifferential equation can be obtained by summing the voltagedrops around the circuit;

(RLRS) i(t) Ldi(t)dt

qc(t)CS VMsin(t ) (2)

in which i(t) is the instantaneous current after the switchopens, qc(t) is the instantaneous charge on the capacitor, VM isthe peak line voltage, and φ is the phase angle by which thevoltage leads the current prior to opening of the switch. Afterdifferentiation and rearrangement, the equation becomes astandard second–order differential equation with constantcoefficients.

With the imposition of the boundary conditions thati(o) = 0 and qc(o) = 0 and with selected values for RL, L, RSand CS, the equation can be solved, generally by the useof a computer. Having determined the magnitude and time


of occurrence of the peak voltage across the thyristor, it isthen possible to calculate the values and times of thevoltages at 10% and 63% of the peak value. This isnecessary in order to compute the dv/dt stress as defined bythe following equation:

dvdt

V2 V1t2 t1

where V1 and t1 are the voltage and time at the 10% pointand V2 and t2 are the voltage and time at the 63% point.

Solution of the differential equation for assumed loadconditions will give the circuit designer a starting point forselecting RS and CS.

Because the design of a snubber is contingent on the load,it is almost impossible to simulate and test every possiblecombination under actual operating conditions. It is advisableto measure the peak amplitude and rate of rise of voltageacross the triac by use of an oscilloscope, then make the finalselection of RS and CS experimentally. Additional commentsabout circuit values for SCRs and Triacs are made in Chapter 6.

RS

CS

RLL

LOADAC

POWERSOURCE

Figure 3.20. Equivalent Circuit used for Analysis

USING SENSITIVE GATE SCRs

In applications of sensitive gate SCRs such as theMotorola 2N6237, the gate–cathode resistor, RGK (Figure3.21) is an important factor. Its value affects, in varyingdegrees, such parameters as IGT, VDRM, dv/dt, IH, leakagecurrent, and noise immunity.

ANODE (A)

GATE (G)

CATHODE (K)

RGK

Figure 3.21. Gate–Cathode Resistor, R GK

SCR CONSTRUCTIONThe initial step in making an SCR is the creation, by

diffusion, of P–type layers is N–type silicon base material.

Prior to the advent of the all–diffused SCR, the next step wasto form the gate–cathode P–N junction by alloying in agold–antimony foil. This produced a silicon P–N junction of theregrown type over most of the junction area. However, aresistive rather than semiconductor junction would formwhere the molten alloy terminated at the surface. This formedan internal RGK, looking in at the gate–cathode terminals, thatreduced the “sensitivity’’ of the SCR.

Modern practice is to produce the gate–cathode junction bymasking and diffusing, a much more controllable process. Itproduces a very clean junction over the entire junction areawith no unwanted resistive paths. Good dv/dt performanceby larger SCRs, however, requires resistive paths distributedover the junction area. These are diffused in as emitter shortsand naturally desensitize the device. Smaller SCRs may relyon an external RGK because the lateral resistance in the gatelayer is small enough to prevent leakage and dV/dt inducedcurrents from forward biasing the cathode and triggering theSCR.

Figure 3.22(a) shows the construction of a sensitive gateSCR and the path taken by leakage current flowing outthrough RGK. Large SCRs (Figure 3.22(b)) keep the pathlength small by bringing the gate layer up to contact thecathode metal. This allows the current to siphon out all–roundthe cathode area.

When the chip dimensions are small there is little penalty inplacing the resistor outside the package. This gives thecircuit designer considerable freedom in tailoring the electri-cal properties of the SCR. This is a great advantage whenlow trigger or holding current is needed. Still, there aretrade–offs in the maximum allowable junction temperatureand dV/dt immunity that go with larger resistor values.Verifying that the design is adequate to prevent circuit upsetby heat or noise is important. The rated value for RGK isusually 1 K Ohm. Lower values improve blocking and turn–offcapability.

K

A

G

ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ

CASE

APN

P

DIFFUSEDCATHODE

+ –N

GK

ÉÉÉÉÉÉÉÉÉÉÉÉ

CASE

APNP

EMITTERSHORTS

N

GK

METAL

DIFFUSED

DIFFUSEDBASE

N N

(a). SIMPLECONSTRUCTION

(b). SHORTED EMITTERCONSTRUCTION

Figure 3.22. Sensitive Gate SCR Construction

The sensitive gate SCR, therefore, is an all–diffuseddesign with no emitter shorts. It has a very high impedancepath in parallel with the gate–cathode P–N diode; the betterthe process is the higher this impedance, until a very gooddevice cannot block voltage in the forward direction withoutan external RGK. This is so, because thermally generatedleakage currents flowing from the anode into the gate



RGK (OHMS)

0

140

120

1003 K

180

V

160

2 K1 K

200

2N6239TJ = 110°CIAK CONSTANT

(VO

LTS)

AK

Figure 3.23(a). V AK versus R GK (Typical) for ConstantLeakage Current

junction are sufficient to turn on the SCR. The value forRGK is usually one kilohm and its presence and valueaffects many other parameters.

FORWARD BLOCKING VOLTAGE AND CURRENT,VDRM AND IDRM

The 2N6237 family is specified to have an IDRM, oranode–to–cathode leakage current, of less than 200 µA atmaximum operating junction temperature and rated VDRM.This leakage current increases if RGK is omitted and, in fact,the device may well be able to regenerate and turn on. Testswere run on several 2N6239 devices to establish thedependency of the leakage current on RGK and to determineits relationship with junction temperature, TJ, and forwardvoltage VAK (Figure 3.23a).

Figure 3.23(a) is a plot of VAK, forward voltage, versus RGKtaken at the maximum rated operating junction temperatureof 110°C. With each device the leakage current, IAK, is set fora VAK of 200 V, then VAK reduced and RGK varied tore–establish the same leakage current. The plot shows thatthe leakage current is not strongly voltage dependent or,conversely, RGK may not be increased for derate.

While the leakage current is not voltage dependent, it isvery temperature dependent. The plot in Figure 3.23(b) of TJ,junction temperature, versus RGK taken at VDRM, themaximum forward blocking voltage shows this dependence.For each device (2N6329 again) the leakage current, IAK,was measured at the maximum operating junction tempera-ture of 110°C, then the junction temperature was reducedand RGK varied to re–establish that same leakage current.The plot shows that the leakage current is strongly depen-dent on junction temperature. Conversely RGK may beincreased for derated temperature.

A conservative rule of thumb is that leakage doubles every10°C. If all the current flows out through RGK, triggering willnot occur until the voltage across RGK reaches VGT. Thisimplies an allowed doubling of the resistor for every 10°reduction in maximum junction temperature. However, thisrule should be applied with caution. Static dV/dt may requirea smaller resistor than expected. Also the leakage current

does not always follow the 10° rule below 70°C because ofsurface effects.

To summarize, the leakage current in a sensitive gate SCRis much more temperature sensitive than voltage sensitive.Operation at lower junction temperatures allows an increasein the gate–cathode resistor which makes the SCR–resistorcombination more “sensitive.’’

RGK (OHMS)

1 K

80

70

6050 K

100

T

90

10 K5 K

110

2N6239VAK = VDRM = 200 VIAK CONSTANT

( C

)J

100 K

°

RGK

dv/dt

CAG

i

RGK ()

101V/s

10,0001,000100

MCR706–6TJ = 110°C400 V PEAK

dv/d

t, R

ATE

OF

RIS

E O

F AN

OD

E VO

LTAG

E (V

/ s

)

100,000

10V/s

1,000V/s

100V/sEXPONENTIAL

METHOD

IGT = 5.6 A

IGT = 27 A

Figure 3.23(b). T J versus R GK (Typical) for ConstantLeakage Current

Figure 3.23(c). dv/dt Firing of an SCR

Figure 3.23(d). Static dv/dt as a function ofGate–Cathode Resistance on two devices

with different sensitivity.


RATE–OF–RISE OF ANODE VOLTAGE, dv/dtAn SCR’s junctions exhibit capacitance due to the separa-

tion of charge when the device is in a blocking state. If anSCR is subjected to forward dv/dt, this capacitance cancouple sufficient current into the SCR’s gate to turn it on, asshown in Figure 3.23(c). RGK acts as a diversionary path forthe dv/dt current. (In larger SCRs, where the lateral gateresistance of the device limits the influence of RGK, this pathis provided by the resistive emitter shorts mentioned pre-viously.) The gate–cathode resistor, then, might be expectedto have some effect on the dv/dt performance of the SCR.Figure 3.23(d) confirms this behavior. The static dV/dt for twoMCR706 devices varies over several powers of ten withchanges in the gate–cathode resistance. Selection of theexternal resistor allows the designer to trade dynamicperformance with the amount of drive current provided to theresistor–SCR combination. The sensitive–gate device withlow RGK provides performance approaching that of anequivalent non–sensitive SCR. This strong dependence doesnot exist with conventional shorted emitter SCRs because oftheir internal resistor. The conventional SCR cannot be mademore sensitive, but the sensitive–gate device attributes canbe reliably set with the resistor to any desired point along thesensitivity range. Low values of resistance make the dV/dtperformance more uniform and predictable. The curves fortwo devices with different sensitivity diverge at high values ofresistance because the device response becomes moredependent on its sensitivity. The resistor is the mostimportant factor determining the static dV/dt capability of theproduct. Reverse biasing the gate also improves dV/dt. A2N6241 improved by a factor of 50 with a 1 volt bias.

GATE CURRENT, IGTThe total gate current that a gating circuit must supply is

the sum of the current that the device itself requires to fireand the current flowing to circuit ground through RGK, asshown in Figure 3.24. IGT, the current required by the deviceso that it may fire, is usually specified by the devicemanufacturer as a maximum at some temperature (for the2N6236 series it is 500 µA maximum at –40°C). The currentflowing through RGK is defined by the resistor value and bythe gate–to–cathode voltage that the SCR needs to fire. This is1 V maximum at –40°C for the 2N6237 series, for example.

GATE CURRENT, IGT(min)SCR manufacturers sometimes get requests for a sensi-

tive–gate SCR specified with an IGT(min), that is, the maximum

RGKVGT

ITOT IGT

IR

Figure 3.24. SCR and R GK “Gate’’ Currents

gate current that will not fire the device. This requirementconflicts with the basic function of a sensitive gate SCR,which is to fire at zero or very low gate current, IGT(max).Production of devices with a measurable IGT(min) is at bestdifficult and deliveries can be sporadic!

One reason for an IGT(min) requirement might be somemeasurable off–state gating circuit leakage current, perhapsthe collector leakage of a driving transistor. Such current canreadily be bypassed by a suitably chosen RGK. The VGT ofthe SCR at the temperature in question can be estimatedfrom Figure 3.25, an Ohm’s Law calculation made, and theresistor installed to define this “won’t fire’’ current. This is arepeatable design well in the control of the equipmentdesigner.

GATE TRIGGER VOLTAGE, V GTThe gate–cathode junction is a p–n silicon junction. So the

gate trigger voltage follows the diode law and has roughly thesame temperature coefficient as a silicon diode, –2mV/C.Figure 3.25 is a plot of VGT versus temperature for typicalsensitive gate SCRs. They are prone to triggering by noisecoupled through the gate circuit because of their low triggervoltage. The smallest noise voltage margin occurs atmaximum temperature and with the most sensitive devices.

JUNCTION TEMPERATURE (°C)

110–30

0.7

0.3

0.2

0.19050 70

0.6

0.5

V

130

0.4

30–10 10

0.8

0.9

, GAT

E TR

IGG

ER V

OLT

AGE

(VO

LTS)

GT

LOW UNIT

HIGH UNIT

IGT = 20 NA @ 300°K

IGT = 200 A @ 300°K

Figure 3.25. Typical V GT vs TJ

HOLDING CURRENT, IHThe holding current of an SCR is the minimum anode

current required to maintain the device in the on state. It isusually specified as a maximum for a series of devices (forinstance, 5 mA maximum at 25°C for the 2N6237 series). Aparticular device will turn off somewhere between thismaximum and zero anode current and there is perhaps a20–to–1 spread in each lot of devices.

Figure 3.26 shows the holding current increasing withdecreasing RGK as the resistor siphons off more and more ofthe regeneratively produced gate current when the device isin the latched condition.

Note that the gate–cathode resistor determines the holdingcurrent when it is less than 100 Ohms. SCR sensitivity is thedetermining factor when the resistor exceeds 1 meg Ohm.



RGK, GATE–CATHODE RESISTANCE, K

0.10.01

10010

1.0

I

1,000

0.1

1.0

10

, HO

LDIN

G C

UR

REN

T, m

AH

TJ = 25°C

IGT = 20 NA

IGT = 1.62 A

Figure 3.26. 2N5064 Holding Current

This allows the designer to set the holding current over awide range of possible values using the resistor. Valuestypical of those in conventional non–sensitive devices occurwhen the external resistor is similar to their internal gate–cathode shorting resistance. The holding current uniformityalso improves when the resistor is small.

NOISE IMMUNITYChanges in electromagnetic and electrostatic fields

coupled into wires or printed circuit lines can trigger thesesensitive devices, as can logic circuit glitches. The result ismore serious than with a transistor since an SCR will latchon. Careful wire harness design (twisted pairs and adequateseparation from high–power wiring) and printed circuit layout(gate and return runs adjacent to one another) can minimizepotential problems. A gate cathode network consisting of aresistor and parallel capacitor also helps. The resistorprovides a static short and is helpful with noise signals of anyfrequency. For example, with a 1,000 Ohm resistor, between100 µA to 1 mA of noise current is necessary to generateenough voltage to fire the device. Adding a capacitor sizedbetween 0.01 and 0.1 µF creates a noise filter and improvesdV/dt by shunting dV/dt displacement current out through thegate terminal. These components must be placed as closeas possible to the gate and cathode terminals to prevent leadinductance from making them ineffective. The use of the

capacitor also requires the gate drive circuit to supplyenough current to fire the SCR without excessive time delay.This is particularly important in applications with rapidly rising(di/dt50 A/µs) anode current where a fast rise highamplitude gate pulse helps to prevent di/dt damage to theSCR.

Reverse gate voltage can cause unwanted turn–off of theSCR. Then the SCR works like a gate turn–off thyristor.Turn–off by the gate signal is more probable with small SCRsbecause of the short distance between the cathode and gateregions. Whether turn–off occurs or not depends on manyvariables. Even if turn–off does not occur, the effect of highreverse gate current is to move the conduction away from thegate, reducing the effective cathode area and surge capability.Suppressing the reverse gate voltage is particularly importantwhen the gate pulse duration is less than 1 microsecond. Thenthe part triggers by charge instead of current so halving of thegate pulse width requires double the gate current. Capaci-tance coupled gate drive circuits differentiate the gate pulse(Figure 3.27) leading to a reverse gate spike. The reversegate voltage rating should not be exceeded to preventavalanche damage.

This discussion has shown that the use of RGK, thegate–cathode resistor, has many implications. Clear under-standing of its need and its influence on the performance ofthe sensitive gate SCR will enable the designer to havebetter control of his circuit designs using this versatile part.

OPTIONALREVERSE

GATESUPPRESSOR

DIODE

Figure 3.27. Capacitance Coupled Gate Drive


DRIVERS: PROGRAMMABLE UNIJUNCTIONTRANSISTORS

The programmable unijunction transistor (PUT) is a fourlayer device similar to an SCR. However, gating is withrespect to the anode instead of the cathode. An externalresistive voltage divider accurately sets the triggering voltageand allows its adjustment. The PUT finds limited applicationas a phase control element and is most often used in longduration or low battery drain timer circuits where its highsensitivity permits the use of large timing resistors and smallcapacitors. Like an SCR, the PUT is a conductivity modu-lated device capable of providing high current output pulses.

OPERATION OF THE PUTThe PUT has three terminals, an anode (A), gate (G), and

cathode (K). The symbol and a transistor equivalent circuitare shown in Figure 3.28. As can be seen from the equivalentcircuit, the device is actually an anode–gated SCR. Thismeans that if the gate is made negative with respect to theanode, the device will switch from a blocking state to its onstate.

ANODE(A)

(K)CATHODE

GATE(G)

G

K

A

Figure 3.28(a).PUT Symbol

Figure 3.28(b).Transistor Equivalent

The PUT is a complementary SCR when its anode isconnected like an SCR’s cathode and the circuit biasvoltages are reversed. Negative resistance terminologydescribes the device characteristics because of the tradition-al application circuit. An external reference voltage must bemaintained at the gate terminal. A typical relaxation typeoscillator circuit is shown in Figure 3.29(a). The voltagedivider shown is a typical way of obtaining the gate reference.In this circuit, the characteristic curve looking into theanode–cathode terminals would appear as shown in Figure3.29(b). The peak and valley points are stable operatingpoints at either end of a negative resistance region. The peakpoint voltage (VP) is essentially the same as the external gatereference, the only difference being the gate diode drop.Since the reference is circuit and not device dependent, itmay be varied, and in this way, VP is programmable.

In characterizing the PUT, it is convenient to speak of theThevenin equivalent circuit for the external gate voltage (VS)and the equivalent gate resistance (RG). The parameters aredefined in terms of the divider resistors (R1 and R2) andsupply voltage as follows:

VS R1 V1(R1R2)RG R1 R2(R1R2)

Most device parameters are sensitive to changes in VSand RG. For example, decreasing RG will cause peak andvalley currents to increase. This is easy to see since RGactually shunts the device and will cause its sensitivity todecrease.

CHARACTERISTICS OF THE PUTTable 3.1 is a list of typical characteristics of Motorola’s

2N6027/2N6028 of programmable unijunction transistors.The test circuits and test conditions shown are essentially thesame as for the data sheet characteristics. The datapresented here defines the static curve shown in Figure3.29(b) for a 10 V gate reference (VS) with various gateresistances (RG). It also indicates the leakage currents ofthese devices and describes the output pulse. Values givenare for 25°C unless otherwise noted.

VS R1

R2RT

CT

OUTPUT

R0

V1

+

–

IGAO IP IV IFIA

VF

VV

VPVS

V AK

PEAK POINT

NEGATIVE RESISTANCE REGION

VALLEY POINT

Figure 3.29(a). Typical Oscillator Circuit

Figure 3.29(b). Static Characteristics



Table 3.1. Typical PUT Characteristics

Symbol Test Circuit Figure Test Conditions 2N6027 2N6028 Unit

IP 3.64 RG = 1 mΩRG = 10 kΩ

1.254

0.080.70

µAµA

IV 3.64 RG = 1 MΩRG = 10 kΩ

18150

18150

µAµA

VAG (See Figure 3.44)

IGAO VS = 40 V (See Figure 3.45)

IGKS VS = 40 V 5 5 nA

VF Curve Tracer Used IF = 50 mA 0.8 0.8 V

VO 3.67 11 11 V

tr 3.68 40 40 ns

PEAK POINT CURRENT, (IP)The peak point is indicated graphically by the static curve.

Reverse anode current flows with anode voltages less thanthe gate voltage (VS) because of leakage from the biasnetwork to the charging network. With currents less than IP,the device is in a blocking state. With currents above IP, thedevice goes through a negative resistance region to its onstate.

The charging current, or the current through a timingresistor, must be greater than IP at VP to insure that adevice will switch from a blocking to an on state in anoscillator circuit. For this reason, maximum values of IP aregiven on the data sheet. These values are dependent onVS temperature, and RG. Typical curves on the data sheetindicate this dependence and must be consulted for mostapplications.

The test circuit in Figure 3.30 is a sawtooth oscillatorwhich uses a 0.01 µF timing capacitor, a 20 V supply, anadjustable charging current, and equal biasing resistors(R). The two biasing resistors were chosen to given anequivalent RG of 1 MΩ and 10 kΩ. The peak point currentwas measured with the device off just prior to oscillation asdetected by the absence of an output voltage pulse. The2N5270 held effect transistor circuit is used as a currentsource. A variable gate voltage supply was used to controlthis current.

VALLEY POINT CURRENT, (I V)The valley point is indicated graphically in Figure 3.28.

With currents slightly less than IV, the device is in anunstable negative resistance state. A voltage minimumoccurs at IV and with higher currents, the device is in astable on state.

When the device is used as an oscillator, the chargingcurrent or the current through a timing resistor must be lessthan IV at the valley point voltage (VV). For this reason,minimum values for IV are given on the data sheet for RG =10 kΩ. With RG = 1 MΩ, a reasonable “low’’ is 2 µA for alldevices.

When the device is used in the latching mode, the anodecurrent must be greater than IV. Maximum values for IV aregiven with RG = 1 MΩ. All devices have a reasonable “high’’of 400 µA IV with RG = 10 kΩ.

PEAK POINT VOLTAGE, (V P)The unique feature of the PUT is that the peak point

voltage can be determined externally. This programmablefeature gives this device the ability to function in voltagecontrolled oscillators or similar applications. The triggering orpeak point voltage is approximated by

VP ≈ VT VS,

where VS is the unloaded divider voltage and VT is the offsetvoltage. The actual offset voltage will always be higher thanthe anode–gate voltage VAG, because IP flows out of the gatejust prior to triggering. This makes VT = VAG + IP RG. Achange in RG will affect both VAG and IP RG but in oppositeways. First, as RG increases, IP decreases and causes VAGto decrease. Second, since IP does not decrease as fast asRG increases, the IP RG product will increase and the actualVT will increase. These second order effects are difficult topredict and measure. Allowing VT to be 0.5 V as a first orderapproximation gives sufficiently accurate results for mostapplications.

The peak point voltage was tested using the circuit inFigure 3.30 and a scope with 10 MΩ input impedance acrossthe PUT. A Tektronix, Type W plug–in was used to determinethis parameter.

FORWARD ANODE–GATE VOLTAGE, (V AG)The forward anode–to–gate voltage drop affects the peak

point voltage as was previously discussed. The drop isessentially the same as a small signal silicon diode and isplotted in Figure 3.31. The voltage decreases as currentdecreases, and the change in voltage with temperature isgreater at low currents. At 10 nA the temperature coefficientis about –2.4 V/°C and it drops to about –1.6 mV/°C at10 mA. This information is useful in applications where it isdesirable to temperature compensate the effect of this diode.

GATE–CATHODE LEAKAGE CURRENT, (I GKS)The gate–to–cathode leakage current is the current that

flows from the gate to the cathode with the anode shorted tothe cathode. It is actually the sum of the open circuitgate–anode and gate–cathode leakage currents. The shortedleakage represents current that is shunted away from thevoltage divider.


20 V

R

R

+

–

+–VG

GRS

PUTUNDERTEST

S

D2N5270

IP, IV

20

0.01 F

Vp

OUTPUT PULSE

R = 2 RGVS = 10 V

NOTES: 1) VARIOUS SENSE RESISTORS (RS) ARE USED TOKEEP THE SENSE VOLTAGE NEAR 1 Vdc.

2) THE GATE SUPPLY (VG) IS ADJUSTED FROMABOUT –0.5 V TO +20 V.

Figure 3.30. Test Circuit for I P, VP and IV

GATE–ANODE LEAKAGE CURRENT, (I GAO)The gate–to–anode leakage current is the current that

flows from the gate to the anode with the cathode open. Itis important in long duration timers since it adds to thecharging current flowing into the timing capacitor. Thetypical leakage currents measured at 40 V are shown inFigure 3.32. Leakage at 25°C is approximately 1 nA andthe current appears to double for about every 10°C rise intemperature.

FORWARD VOLTAGE, (V F)The forward voltage (VF) is the voltage drop between the

anode and cathode when the device is biased on. It is thesum of an offset voltage and the drop across some internaldynamic impedance which both tend to reduce the outputpulse. The typical data sheet curve shows this impedance tobe less than 1 ohm for up to 2 A of forward current.

PEAK OUTPUT VOLTAGE, (V O)The peak output voltage is not only a function of VP, VF

and dynamic impedance, but is also affected by switchingspeed. This is particularly true when small capacitors (lessthan 0.01 µF) are used for timing since they lose part oftheir charge during the turn on interval. The use of arelatively large capacitor (0.2 µF) in the test circuit ofFigure 3.33 tends to minimize this last effect. The outputvoltage is measured by placing a scope across the 20 ohmresistor which is in series with the cathode lead.

RISE TIME, (tr)Rise time is a useful parameter in pulse circuits that use

capacitive coupling. It can be used to predict the amount ofcurrent that will flow between these circuits. Rise time isspecified using a fast scope and measuring between 0.6 Vand 6 V on the leading edge of the output pulse.

MINIMUM AND MAXIMUM FREQUENCYIn actual tests with devices whose parameters are known,

it is possible to establish minimum and maximum values of

IAG (A)

0.010

10010

0.7

V

1 K

0.1

1.0

0.9

(VO

LTS)

AG

25°C

10 K

0.3

0.5

0.1

75°C

IGAO, GATE TO ANODE LEAKAGE CURRENT (nA)

2010

40

°

30

1.0

70

TEM

PER

ATU

RE

( C

)

60

50

Figure 3.31. Voltage Drop of 2N6027 Series Figure 3.32. Typical Leakage Current of the 2N6027,2N6028 Reverse Voltage Equals 40 V



A1 F

16 k

OUTPUT

27 k

20 V+

–

510 k

G

20

KV0

0.2 F

Figure 3.33. PUT Test Circuit for Peak Output Voltage(Vo)

timing resistors that will guarantee oscillation. The circuitunder discussion is a conventional RC relaxation typeoscillator.

To obtain maximum frequency, it is desirable to use lowvalues of capacitance (1000 pF) and to select devices andbias conditions to obtain high IV. It is possible to use straycapacitance but the results are generally unpredictable. The

A

0.001 F

16 k

V120 V

+

–

510 k

G

20

K1000 pF

TO TEKTRONICSTYPE 567 OREQUIVALENT

RG = 10 k

27 k 100

100

A 1 k

OUTPUT

12 V+

–

RT

G

75

K0.01 F

2 k

Figure 3.34. t r Test Circuit for PUTs

Figure 3.35. Uncompensated Oscillator

minimum value of timing resistance is obtained using thefollowing rule of thumb:

R(min) 2(V1 VV)IV

where the valley voltage (VV) is often negligible.To obtain minimum frequency, it is desirable to use high

values of capacitance (10 µF) and to select devices and biasconditions to obtain low IP. It is important that the capacitorleakage be quite low. Glass and mylar dielectrics are oftenused for these applications. The maximum timing resistor isas follows:

R(max) (VI VP)2IP

In a circuit with a fixed value of timing capacitance, ourmost sensitive PUT, the 2N6028, offers the largest dynamicfrequency range. Allowing for capacitance and bias changes,the approximate frequency range of a PUT is from 0.003 Hzto 2.5 kHz.

TEMPERATURE COMPENSATIONThe PUT with its external bias network exhibits a relatively

small frequency change with temperature. The uncompen-sated RC oscillator shown in Figure 3.35 was tested atvarious frequencies by changing the timing resistor RT. Atdiscrete frequencies of 100, 200, 1000 and 2000 Hz, theambient temperature was increased from 25° to 60°C. Atthese low frequencies, the negative temperature coefficientof VAG predominated and caused a consistent 2% increasein frequency. At 10 kHz, the frequency remained within 1%over the same temperature range. The storage time phenom-enon which increases the length of the output pulse astemperature increases is responsible for this result. Sincethis parameter has not been characterized, it is obvious thattemperature compensation is more practical with relativelylow frequency oscillators.

Various methods of compensation are shown in Figure3.36. In the low cost diode–resistor combination of 3.36(a),the diode current is kept small to cause its temperaturecoefficient to increase. In 3.36(b), the bias current throughthe two diodes must be large enough so that their totalcoefficient compensates for VAG. The transistor approach in3.36(c) can be the most accurate since its temperaturecoefficient can be varied independently of bias current.

THE SILICON BILATERAL SWITCHThe silicon bilateral switch (SBS) is bidirectional and

switches, breakover triggers, or gate triggers in eitherpolarity. Its characteristics are describable in terms ofnegative resistance switching theory.

These devices are not just an improved version of a PNPNdiode. They are actually fabricated as simple integratedcircuits consisting of transistors, diodes and resistors,connected as two anti–parallel, regenerative switches. Sincethe device is fabricated as an IC, the components are wellmatched resulting in an asymmetry, or difference of positiveVS and negative VS, of less than 0.5 volts.


A third lead, designated the Gate, has been brought out forincreased circuit flexibility. Since these devices are a

R

100 k < R < 1 M

(a) DIODE–RESISTOR

(b) DUAL–DIODE (c) TRANSISTOR

Figure 3.36. Temperature Compensation Techniques

regenerative switch, they may also be designed into manylow power latching circuits.

The equivalent circuit diagram of an SBS and its symbolare shown in Figure 3.37. The device is actually a simple ICand consists of two halves of a PNP and an NPN transistor, a6.8 volt zener diode and a 15 kΩ resistor, RB. Unlike existing4–layer diodes which use a stacked structure, the SBS isconstructed using annular techniques. The result is a devicewith better stability and control of its electrical parameters.

Electrical characteristics are shown in Figure 3.38 and theparameters are defined as follows: VS, the switching voltage,is the maximum forward voltage the device can sustainwithout switching to the conducting state; IS, the switchingcurrent, is the current through the device when VS is applied;VF, the forward voltage, is the voltage drop across the devicewhen it is in the conducting state and passing a specifiedcurrent; IH, the holding current, is the current necessary tosustain conduction; IB is the leakage current through thedevice with five volts bias.

Operation of the SBS can be best understood by referringto Figures 3.38 and 3.39. Consider an adjustable source ofvoltage with a current limiting resistor in series supplying avoltage to a device anode 1 that is five volts positive withrespect to anode 2. Since this voltage is less than the sum ofVBE of the PNP transistor and VZ of the 6.8 volt zener diode,only a very small leakage current will flow and the device in

the off or blocking state. As the supply voltage is increased, apoint will be reached (near VS) where a small increase involtage results in a substantial increase in current flow. ThePNP transistor purposely has high current gain and most ofthis increased current flows out of its collector and producesa voltage drop across RB.

The two transistors are connected in a positive feedbackloop similar to the equivalent circuit for an SCR where thecollector current of one is the base current for the other.When the voltage across RB is sufficient to turn the NPNtransistor on and the loop gain exceeds unity, both transistorsare driven into saturation, the voltage across the deviceabruptly drops and the current through it is limited mainly bythe external circuitry. The device has now switched to the onor conducting state.

The 6.8 volt zener diode has a positive temperaturevoltage coefficient which is opposite to that of VBE of the PNPtransistor. The net result is good temperature stability of VS,typically + 0.02%/°C.

GATE

A2

A1

G

ANODE 2

ANODE 1

6.8 V

6.8 V

RB15 k

RB15 k

+V–V

+1

–1VF2

VF1

IS1

VS1

VS2

IS1

IS2

IS1

IH1

IH2

Figure 3.37(a).SBS Equivalent Circuit

and SymbolFigure 3.37(b)

Figure 3.38. SBS Main Terminal (V–I) Characteristic



VF, the forward voltage across the device, remainsrelatively low even if the current through it is greatlyincreased, rising approximately 3 volts/ampere. The devicewill remain on until the current through it is reduced below theholding current value. One method of insuring turn–off is toapply a reverse voltage less than VR, the maximum reversevoltage. After a few microseconds (turn–off time) haveelapsed, the transistors will have recovered from saturationand the device will again block a forward voltage up to VS.

A third lead, the gate, can be used to modify thecharacteristics of the SBS. As an example, connecting a 3.9volt zener diode from gate to cathode would lower VS toapproximately 4.6 volts. Connecting a 20 kΩ resistor fromgate to anode and a similar resistor from gate to cathode willlower VS to approximately 4 volts at the expense of increasedcurrent around the device prior to switching. Also, if a voltageless than VS is applied to an SBS it can be “gated’’ on bydrawing a small current out of the gate lead.

Like other regenerative switches, the SBS has a tendencyto switch on in the presence of rapidly rising anode voltage.The dv/dt rating of the SBS is difficult to define and themethod of measurement may produce erroneous results. Atest ramp of voltage with adjustable dv/dt as shown in Figure3.39(a) may be applied to the device if not repeated morefrequently than every 10 seconds. The device may switch tothe on state when the dv/dt is in the range of 1 to 10 volts/microsecond. The repetitive waveform of (b) may be appliedmuch more frequently (convenient for an oscilloscopedisplay) providing only that the time interval between turn–off

10 sTIME (UNSCALED)

VS

0

(a)

t > 200 sTIME (UNSCALED)

VS

0

(b)

TURN–ON–PULSES

Figure 3.39. Waveforms for dv/dt Test

and the next ramp is longer than the turn–off time of thedevice. The turn–on pulse in (b) is necessary to dischargeinternal capacitance which can accumulate a charge andgive false indication of very high dv/dt capability.

Sweeping an SBS in either direction will yield similarresults. However, when an SBS has been conducting in onedirection and the anode voltage is rapidly reversed, the dv/dtmust be limited to approximately 0.1 volt/microsecond. Thisis necessary because if the transistors in the conducting halfof the device have not recovered from saturation, they willprovide a path for a current to turn the opposite side on.

1.4-1Theory and ApplicationsMotorola Thyristor Device Data

CHAPTER 4THE SIDAC, A NEW HIGH VOLTAGE BILATERAL TRIGGER

The SIDAC is a high voltage bilateral trigger device thatextends the trigger capabilities to significantly higher volt-ages and currents than have been previously obtainable,thus permitting new, cost-effective applications. Being abilateral device, it will switch from a blocking state to aconducting state when the applied voltage of either polarityexceeds the breakover voltage. As in other trigger devices,(SBS, Four Layer Diode), the SIDAC switches through anegative resistance region to the low voltage on-state (Figure4.1) and will remain on until the main terminal current isinterrupted or drops below the holding current.

SIDAC’s are available in the large MKP3V series andeconomical, easy to insert, small MKP1V series axial leadpackages. Breakdown voltages ranging from 104 to 280 V

are available. The MKP3V devices feature bigger chips andprovide much greater surge capability along with somewhathigher RMS current ratings.

The high-voltage and current ratings of SIDACs makethem ideal for high energy applications where other triggerdevices are unable to function alone without the aid ofadditional power boosting components.

The basic SIDAC circuit and waveforms, operating off of acare shown in Figure 4.2. Note that once the input voltageexceeds V(BO), the device will switch on to the forwardon-voltage VTM of typically 1.1 V and can conduct as muchas the specified repetitive peak on-state current ITRM of 20 A(10 µs pulse, 1 kHz repetition frequency).

RS (V(BO) VS)

(IS I(BO))

V(BO)VDRM

I(BO)

VS

IS

SLOPE = RS

IDRM

IH

VTMITM

Figure 4.1(a). Idealized SIDAC V-I CharacteristicsFigure 4.1(b). Actual MKP1V130 V-I Characteristic.Horizontal: 50 V /Division. Vertical: 20 mA /Division.

(0,0) at Center. R L = 14 k Ohm.

Theory and Applications1.4-2


RS (V(BO) VS)

(IS I(BO))

Figure 4.2. Basic SIDAC Circuit and Waveforms

RS = SIDAC SWITCHINGRESISTANCE

CONDUCTIONANGLE θOFFθON

IT

IHIH

V(BO)

V(BO)

VIN

VT

RL RS

V(BO)

RLVIN I

Operation from an AC line with a resistive load can beanalyzed by superimposing a line with slope = –1/RL on thedevice characteristic. When the power source is AC, the loadline can be visualized as making parallel translations in stepwith the instantaneous line voltage and frequency. This isillustrated in Figure 4.3 where v1 through v5 are theinstantaneous open circuit voltages of the AC generator andi1 through i5 are the corresponding short circuit currents thatwould result if the SIDAC was not in the circuit. When theSIDAC is inserted in the circuit, the current that flows isdetermined by the intersection of the load line with the SIDACcharacteristic. Initially the SIDAC blocks, and only a smallleakage current flows at times 1 through 4. The SIDAC doesnot turn-on until the load line supplies the breakover current(I(BO)) at the breakover voltage (V(BO)).

If the load resistance is less than the SIDAC switchingresistance, the voltage across the device will drop quickly asshown in Figure 4.2. A stable operating point (VT, IT) willresult if the load resistor and line voltage provide a currentgreater than the latching value. The SIDAC remains in an“on” condition until the generator voltage causes the currentthrough the device to drop below the holding value (IH). Atthat time, the SIDAC switches to the point (Voff, Ioff) and onceagain only a small leakage current flows through the device.

Figure 4.4 illustrates the result of operating a SIDAC witha resistive load greater than the magnitude of its switchingresistance. The behavior is similar to that described inFigures 4.2 and 4.3 except that the turn-on and turn-off ofthe SIDAC is neither fast nor complete. Stable operatingpoints on the SIDAC characteristics between (V(BO), I(BO))

RLRS

i vRL

Figure 4.3. Load Line for Figure 4.2. (1/2 Cycle Shown.)

(VOFF, IOFF)

(VT, IT)

i1

IH

i3

i5

RL

(VBO, IBO)

vv5v4v3v2v1

i

i

SLOPE IRL

v1, ..., v5 = INSTANTANEOUS OPENCIRCUIT VOLTAGESAT TIME 1, ..., 5

i1, ..., i5 = INSTANTANEOUSSHORT CIRCUITCURRENTS ATTIME 1, ..., 5


Figure 4.4. High Resistance Load Line with Incomplete Switching

RLRSRS = SIDAC SWITCHING RESISTANCE (VBO, IBO)

(VT, IT)

IH(VS, IS)

(VOFF, IOFF)

vv1

Iv RL

i1

i2i3

i4

v2 v3 v4

and (VS, IS) result as the generator voltage increases fromv2 to v4. The voltage across the SIDAC falls only partly asthe loadline sweeps through this region. Complete turn-onof the SIDAC to (VT, IT) does not occur until the load linepasses through the point (VS, IS). The load line illustratedin Figure 4.4 also results in incomplete turn-off. When thecurrent drops below IH, the operating point switches to(Voff, Ioff) as shown on the device characteristic.

The switching current and voltage can be 2 to 3 orders ofmagnitude greater than the breakover current and on-statevoltage. These parameters are not as tightly specified as VBOand IBO. Consequently operation of the SIDAC in the statebetween fully on and fully off is undesirable because ofincreased power dissipation, poor efficiency, slow switching,and tolerances in timing.

Figure 4.5 illustrates a technique which allows the use ofthe SIDAC with high impedance loads. A resistor can beplaced around the load to supply the current required tolatch the SIDAC. Highly inductive loads slow the currentrise and the turn-on of the SIDAC because of their L/R timeconstant. The use of shunt resistor around the load willimprove performance when the SIDAC is used withinductive loads such as small transformers and motors.

The SIDAC can be used in oscillator applications. If theload line intersects the device characteristic at a pointwhere the total resistance (RL + RS) is negative, anunstable operating condition with oscillation will result.The resistive load component determines steady-statebehavior. The reactive components determine transientbehavior. Figure 4.10 shows a SIDAC relaxation oscillatorapplication. The wide span between IBO and IH makes theSIDAC easy to use. Long oscillation periods can beachieved with economical capacitor sizes because of thelow device I(BO).

Z1 is typically a low impedance. Consequently theSIDAC’s switching resistance is not important in this applica-

tion. The SIDAC will switch from a blocking to full on-state inless than a fraction of a microsecond.

The timing resistor must supply sufficient current to fire theSIDAC but not enough current to hold the SIDAC in anon-state. These conditions are guaranteed when the timingresistor is selected to be between Rmax and Rmin.

For a given time delay, capacitor size and cost isminimized by selecting the largest allowable timingresistor. Rmax should be determined at the lowest tempera-ture of operation because I(BO) increases then. The loadline corresponding to Rmax passes through the point(V(BO), I(BO)) allowing the timing resistor to supply theneeded breakover current at the breakover voltage. Theload line for a typical circuit design should enclose thispoint to prevent sticking in the off state.

Requirements for higher oscillation frequencies and great-er stored energy in the capacitor result in lower values for thetiming resistor. Rmin should be determined at the highestoperating temperature because IH is lower then. The loadline determined by R and Vin should pass below IH on thedevice characteristic or the SIDAC will stick in the on-stateafter firing once. IH is typically more than 2 orders ofmagnitude greater than IBO. This makes the SIDAC wellsuited for operation over a wide temperature span.

SIDAC turn-off can be aided when the load is anunder-damped oscillatory CRL circuit. In such cases, theSIDAC current is the sum of the currents from the timingresistor and the ringing decay from the load. SIDACturn-off behavior is similar to that of a TRIAC where turn-offwill not occur if the rate of current zero crossing is high.This is a result of the stored charge within the volume of thedevice. Consequently, a SIDAC cannot be force com-muted like an SCR. The SIDAC will pass a ring wave ofsufficient amplitude and frequency. Turn-off requires thedevice current to approach the holding current gradually.This is a complex function of junction temperature, holdingcurrent magnitude, and the current wave parameters.



TYPICAL:RSL = 2.7 k OHM

10 WATTRS = 3 k OHM

RSL = TURN-ON SPEEDUP RESISTOR

RS = SIDAC SWITCHINGRESISTANCE

RSLRS

RL

RSL

L

Figure 4.5. Inductive Load Phase Control

HIGHLOWv

How can the SIDAC be used? One application is toreplace the combination of a small-signal trigger andTRIAC with the SIDAC, as shown in Figure 4.6. In thisexample, the trigger — an SBS (Silicon BidirectionalSwitch) that conducts at about 8 V — will fire the TRIAC bydumping the charge from the capacitor into the gate of theTRIAC. This circuit is amenable to phase controlling theTRIAC, if so required, as the RC time constant can bereadily varied.

The simple SIDAC circuit can also supply switchableload current. However, the conduction angle is not readilycontrollable, being a function of the peak applied voltageand the breakover voltage of the SIDAC. As an example,for peak line voltage of about 170 V, at V(BO) of 115 V anda holding current of 100 mA, the conduction angle wouldbe about 130°. With higher peak input voltages (or lowerbreakdown voltages) the conduction angle would corre-spondingly increase. For non-critical conduction angle,1 A rms switching applications, the SIDAC is a verycost-effective device.

Figure 4.7 shows an example of a SIDAC used to phasecontrol an incandescent lamp. This is done in order tolower the RMS voltage to the filament and prolong the lifeof the bulb. This is particularly useful when lamps are usedin hard to reach locations such as outdoor lighting in signswhere replacement costs are high. Bulb life span can beextended by 1.5 to 5 times depending on the type of lamp,the amount of power reduction to the filament, and thenumber of times the lamp is switched on from a coldfilament condition.

The operating cost of the lamp is also reduced becauseof the lower power to the lamp; however, a higher wattagebulb is required for the same lumen output. The maximumpossible energy reduction is 50% if the lamp wattage is notincreased. The minimum conduction angle is 90° becausethe SIDAC must switch on before the peak of the linevoltage. Line regulation and breakover voltage toleranceswill require that a conduction angle longer than 90° beused, in order to prevent lamp turn-off under low linevoltage conditions. Consequently, practical conductionangles will run between 110° and 130° with correspondingpower reductions of 10% to 30%.

In Figure 4.2 and Figure 4.7, the SIDAC switching anglesare given by:

ON SIN1 (V(BO)Vpk)

where Vpk = Maximum Instantaneous Line Voltage

OFF 180 SIN1 (IHRL) VTVpk

where θON, θOFF = Switching Angles in degreesVT = 1 V = Main Terminal Voltage at IT = IH

Generally the load current is much greater than the SIDACholding current. The conduction angle then becomes 180°minus θ(on).

Rectifiers have also been used in this application to supplyhalf wave power to the lamp. SIDAC’s prevent the flickerassociated with half-wave operation of the lamp. Also, fullwave control prevents the introduction of a DC componentinto the power line and improves the color temperature of thelight because the filament has less time to cool during the offtime.

The fast turn-on time of the SIDAC will result in thegeneration of RFI which may be noticeable on AM radiosoperated in the vicinity of the lamp. This can be prevented bythe use of an RFI filter. A possible filter design is shown inFigure 4.5. This filter causes a ring wave of current throughthe SIDAC at turn-on time. The filter inductor must beselected for resonance at a frequency above the upperfrequency limit of human hearing and as low below the startof the AM broadcast band as possible for maximumharmonic attenuation. In addition, it is important that the filterinductor be non-saturating to prevent dI/dT damage to theSIDAC. For additional information on filter design see page1-5-30 and Figure 5.34.

ZL

VIN SIDAC

Figure 4.6. Comparison of a TRIAC and SIDAC Circuits

TRIACSBS

C

R

ZL

VIN


OPTIONALRFI FILTER

100 WATT240 V

100 µHY PREM SPE304RDC = 0.04 Ω

(2)MKP1V130

400 V

0.1 µF

220 VAC

Figure 4.7. Long-Life Circuit for Incandescent Lamp

The sizing of the SIDAC must take into account the RMScurrent of the lamp, thermal properties of the SIDAC, and thecold start surge current of the lamp which is often 10 to 20times the steady state load current. When lamps burn out,at the end of their operating life, very high surge currentswhich could damage the SIDAC are possible because ofarcing within the bulb. The large MKP3V device is recom-mended if the SIDAC is not to be replaced along with thebulb.

Since the MKP3V series of SIDACs have relatively tightV(BO) tolerances (104 V to 115 V for the –115 device), otherpossible applications are over-voltage protection (OVP)and detection circuits. An example of this, as illustrated inFigure 4.8, is the SIDAC as a transient protector in thetransformer-secondary of the medium voltage power supply,replacing the two more expensive back-to-back zeners oran MOV. The device can also be used across the output ofthe regulator (100 V) as a simple OVP, but for thisapplication, the regulator must have current foldback or acircuit breaker (or fuse) to minimize the dissipation of theSIDAC.

Another example of OVP is the telephony applications asillustrated in Figure 4.9. To protect the Subscriber LoopInterface Circuit (SLIC) and its associated electronics fromvoltage surges, two SIDACs and two rectifiers are used forsecondary protection (primary protection to 1,000 V isprovided by the gas discharge tube across the lines). As anexample, if a high positive voltage transient appeared on thelines, rectifier D1 (with a P.I.V. of 1,000 V) would block it andSIDAC D4 would conduct the surge to ground. Conversely,rectifier D2 and SIDAC D3 would protect the SLIC fornegative transients. The SIDACs will not conduct whennormal signals are present.

Being a negative resistance device, the SIDAC also canbe used in a simple relaxation oscillator where thefrequency is determined primarily by the RC time constant(Figure 4.10). Once the capacitor voltage reaches theSIDAC breakover voltage, the device will fire, dumping thecharged capacitor. By placing the load in the dischargepath, power control can be obtained; a typical load could be atransformer-coupled xeon flasher, as shown in Figure 4.12.

z

VO 100 VREG.VIN

SIDAC AS ANOVP

SIDAC AS A TRANSIENTPROTECTOR

Figure 4.8. Typical Application of SIDACs as a Transient Protector and OVP in a Regulated Power Supply



RMAXVIN V(BO)

I(BO)

RMINVIN VTM

IH

t RC In

I

IVBOVIN

TIPSENSE

TIPSENSE

D2D2

90 V RMS @ – 48 VdcRING GENERATOR90 V RMS @ – 48 VdcRING GENERATOR

SECONDARYPROTECTIONSECONDARYPROTECTION

TIPDRIVE

TIPDRIVE

D1D1

1N40071N4007

SLICMC3419-1L

SLICMC3419-1L

RINGSENSE

RINGSENSE

PRIMARYPROTECTION

GAS DISCHARGETUBE

PRIMARYPROTECTION

GAS DISCHARGETUBE

1N40071N4007

MOC3030MOC3030

RG1RG1

RG2RG2

RERE

135 V135 V

RING ENABLE0 TO + 5 VRING ENABLE0 TO + 5 V

RINGDRIVERING

DRIVE

GNDGND

– 48 VBATTERY

– 48 VBATTERY

RPRRPR

RRRR

105 V105 V

RINGRING

TIPTIP RPTRPT

RTRT

Figure 4.9. SIDACs Used for OVP in Telephony ApplicationsFigure 4.9. SIDACs Used for OVP in Telephony Applications

t

t

iL

VC

Figure 4.10. Relaxation Oscillator Using a SIDAC

C

VIN V(BO)

R

VC

iLZL

t

V(BO)


SIDAC’s provide an economical means for starting highintensity high pressure gas discharge lamps. These lampsare attractive because of their long operating life and highefficiency. They are widely used in outdoor lighting for thesereasons.

Figure 4.13 illustrates how SIDAC’s can be used in sodiumvapor lamp starters. In these circuits, the SIDAC is used togenerate a short duration (1 to 20 µs) high-voltage pulse ofseveral KV or more which is timed by means of the RCnetwork across the line to occur near the peak of the AC inputline voltage. The high voltage pulse strikes the arc whichlights the lamp.

In these circuits, an inductive ballast is required to providea stable operating point for the lamp. The lamp is a negativeresistance device whose impedance changes with current,temperature, and time over the first few minutes of operation.Initially, before the lamp begins to conduct, the lampimpedance is high and the full line voltage appears across it.This allows C to charge to the breakover voltage of theSIDAC, which then turns on discharging the capacitorthrough a step-up transformer generating the high voltagepulse. When the arc strikes, the voltage across the lamp fallsreducing the available charging voltage across RC to thepoint where VC no longer exceeds V(BO) and the SIDACremains off. The low duty cycle lowers average junctiontemperature improving SIDAC reliability. Normal operationapproximates non-repetitive conditions. However, if the lampfails or is removed during replacement, operation of theSIDAC will be at the 60 Hz line frequency. The design of thecircuit should take into account the resulting steady statepower dissipation.

4 kV PULSE TRANSFORMERRS-272-1146

560 k2 W

1 µF200 V

+

VIN ≈300 V

125 V

+1 M2 W

2202 W

2 kWXEON TUBERS-272-1145

20 µF400 V

Figure 4.11. Typical Capacitor Discharge SIDAC Circuit

Figure 4.12. Xeon Flasher Using a SIDAC

HVVIN

Figure 4.13. Sodium Vapor Lamp Starter Circuits

(b). H.V. Auto-Transformer

(a). Conventional HV Transformer

C1

C

R

vac

(c). Tapped Ballast Auto Transformer

LB

vac

vac

LB

LB

C

C

R

R

Figure 4.14 illustrates a solid state fluorescent lamp starterusing the SIDAC. In this circuit the ballast is identical to thatused with the conventional glow-tube starter shown in Figure4.15.

The glow tube starter consists of a bimetallic switch placedin series with the tube filaments which closes to energize thefilaments and then opens to interrupt the current flowingthrough the ballast inductor thereby generating the high-volt-age pulse necessary for starting. The mechanical glow-tubestarter is the circuit component most likely to cause unreli-able starting.



Figure 4.14. Fluorescent Starter Using SIDAC

L

PTC

R

D2

D1

LB

115 VAC

LB UNIVERSAL MFG CORP CAT200-H214-15-20-22 WATT BALLAST325 mHY 28.9 Ω DCR

D1 1N4005 RECTIFIER

D2 (2) MKP1V130 SIDAC

C 3 VFD 400 V

R 68 k OHMS 112 WATT

PTC KEYSTONE CARBON COMPANYRL3006-50-40-25-PTO50 OHMS/25°C

L MICROTRAN QIL 50-F50 mHY 11 OHMS

SYLV

ANIA

F15T

8/C

W

The heating of the filaments causes thermonic emission ofelectrons from them. These electrons are accelerated alongthe length of the tube causing ionization of the argon gaswithin the tube. The heat generated by the starting currentflow through the tube vaporizes the mercury dropletswithin the tube which then become ionized themselvescausing the resistance and voltage across the tube to dropsignificantly. The drop in voltage across the tube is used toturn off the starting circuit and prevent filament currentafter the lamp is lit.

The SIDAC can be used to construct a reliable startercircuit providing fast, positive lamp ignition. The startershown in Figure 4.14 generates high voltage by means of aseries CRL charging circuit. The circuit is roughly analogousto a TRIAC snubber used with an inductive load, except for alower damping factor and higher Q. The size of C determinesthe amount of filament heating current by setting theimpedance in the filament circuit before ionization of the tube.

The evolution of this circuit can be understood by firstconsidering an impractical circuit (Figure 4.16).

If LB and C are adjusted for resonance near 60 Hz, theapplication of the AC line voltage will result in a chargingcurrent that heats the filaments and a voltage across thecapacitor and tube that grows with each half-cycle of the ACline until the tube ionizes. Unfortunately, C is a largecapacitor which can suddenly discharge through the tubecausing high current pulses capable of destroying the tubefilament. Also C provides a permanent path for filamentcurrent after starting. These factors cause short tubeoperating life and poor efficiency because of filament powerlosses. The impractical circuit must be modified to:

(1) Switch off the filament current after starting.(2) Limit capacitor discharge current spikes.In Figure 4.14 a parallel connected rectifier and SIDAC

have been added in series with the capacitor C. Thebreakover voltage of the SIDAC is higher than the peak of theline voltage. Diode D1 is therefore necessary to provide acurrent path for charging C.

On the first half-cycle, C resonant charges through diodeD1 to a peak voltage of about 210 V, and remains at thatvalue because of the blocking action of the rectifier andSIDAC. During this time, the bleeder resistor R has negligibleeffect on the voltage across C because the RC time constantis long in comparison to the line period. When the linereverses, the capacitor voltage boosts the voltage across theSIDAC until breakover results. This results in a sudden stepof voltage across the inductor L, causing resonant chargingof the capacitor to a higher voltage on the 2nd half-cycle.

BALLASTINDUCTOR

FLUORESCENTCOATING

NEON GAS

(ARGON GAS)

VAC

MERCURY DROPLETS

STARTER

COATEDFILAMENT

Figure 4.15. Fluorescent Lamp with Glow Tube Starter


Q XLB

RTOTAL

fo 1

2a LC 60 Hz

BALLASTCHOKE

Figure 4.16. Impractical Starter Circuit

VSTART VMAX

– VSTART

LBRB

VC

VAC

Vmax Q VAC 2

Figure 4.17. Starting Voltage Across Fluorescent Tube 100 V /DIV0 V AT CENTERVLine = 110 V

(a). 5 ms /DIVISION (b). 100 ms /DIVISION

Several cycles of operation are necessary to approachsteady state operating conditions. Figure 4.17 shows thestarting voltage waveform across the tube.

The components R, PTC, and L serve the dual role ofguarantying SIDAC turn-off and preventing capacitor dis-charge currents through the tube.

SIDAC’s can also be used with auto-transformer ballasts.The high voltage necessary for starting is generated by theleakage autotransformer. The SIDAC is used to turn-on thefilament transformer initially and turn it off after ionizationcauses the voltage across the tube to drop.

Figure 4.18 illustrates this concept. The resistor R can beadded to aid turn-off of the SIDAC by providing a small idlecurrent resulting in a voltage drop across the impedance Z.The impedance Z could be a saturable reactor and orpositive temperature coefficient thermistor. These compo-nents help to insure stability of the system comprised of thenegative resistance SIDAC and negative resistance tubeduring starting, and promote turn off of the SIDAC.

The techniques illustrated in Figure 4.13 are also possiblemethods for generation of the necessary high-voltagerequired in fluorescent starting. The circuits must be modified



VBO VSTARTVBO VOPERATING

Figure 4.18. Fluorescent Starter Using SIDAC and Autotransformer Ballast

V

Z

C

VAC

R

Table 4.1. Possible Sources for Thermistor Devices

Fenwal Electronics, 63 Fountain StreetFramingham MA 01701

Keystone Carbon Company, Thermistor DivisionSt. Marys, PA 15857

Thermometrics, 808 U.S. Highway 1Edison, N.J. 08817

Therm-O-Disc, Inc. Micro Devices Product Group1320 South Main Street, Mansfield, OH 44907

Midwest Components Inc., P.O Box 7871981 Port City Boulevard, Muskegon, MI 49443

Nichicon (America) Corp., Dept. G927 E. State Pkwy, Schaumburg, IL 60195

to allow heating of the fluorescent tube cathodes if starting isto simulate the conditions existing when a glow tube is used.

Thermistors are useful in delaying the turn-on or insuringthe turn-off of SIDAC devices. Table 4.1 shows possiblesources of thermistor devices.

Other high voltage nominal current trigger applications are:

• Gas or oil igniters• Electric fences• HV electrostatic air filters• Capacitor Discharge ignitions

Note that all these applications use similar circuits where acharged capacitor is dumped to generate a high transformersecondary voltage (Figure 4.11).

In many cases, the SIDAC current wave can be approxi-mated by an exponential or quasi-exponential current wave(such as that resulting from a critically damped or slightly

underdamped CRL discharge circuit). The question thenbecomes; how much “real world” surge current can theSIDAC sustain? The data sheet defines an ITSM of 20 A, butthis is for a 60 Hz, one cycle, peak sine wave whereas thecapacitor discharge current waveform has a fast-rise timewith an exponential fall time.

To generate the surge current curve of peak currentversus exponential discharge pulse width, the test circuitof Figure 4.19 was implemented. It simulates the topologyof many applications whereby a charged capacitor isdumped by means of a turned-on SIDAC to produce acurrent pulse. Timing for this circuit is derived from thenonsymmetrical CMOS astable multivibrator (M.V.) gatesG1 and G2. With the component values shown, anapproximate 20 second positive-going output pulse is fedto the base of the NPN small-signal high voltage transistorQ1, turning it on. The following high voltage PNP transistoris consequently turned on, allowing capacitor C1 to becharged through limiting resistor R1 in about 16 seconds.The astable M.V. then changes state for about 1.5 secondswith the positive going pulse from Gate 1 fed throughintegrator R2-C2 to Gate 3 and then Gate 4. The net resultof about a 100 µs time delay from G4 is to ensurenon-coincident timing conditions. This positive going outputis then differentiated by C3-R3 to produce an approximate 1ms, leading edge, positive going pulse which turns on NPNtransistor Q3 and the following PNP transistor Q4. Thus,an approximate 15 mA, 1 ms pulse is generated for turningon SCR Q5 about 100 µs after capacitor chargingtransistor Q2 is turned off. The SCR now fires, dischargingC1 through the current limiting resistor R4 and the SIDACDevice Under Test (D.U.T.). The peak current and itsduration is set by the voltage VC across capacitor C1 andcurrent limiting resistor R4. The circuit has about a 240 Vcapability limited by C1, Q1 and Q2 (250 V, 300 V and 300V respectively).


1N4003

Q1MPSA42

R14 k5 W

1N914

R310 k

3.3 Ω2 W

10 k

22 k

MCR6507

C30.1 µF

1 k

1 k

10 k

+15 V

2N3906Q4

Q5

LED

39 k2 W

C180 µF250 V

R4

0.47 µF

1N914

22 k

Q2MJ4646

R2100 k

10 k

VCC 240 V0.001 µF

4

6

531

2C2

MC14011

47 k1114

+15 V

+15 V

+15 V

+15 V

22 M

Q32N3904

7

22 M

G2

13

12108

9G1

Figure 4.19. SIDAC Surge Tester

2.2 M

G3G4

SIDACDUT

The SCR is required to fire the SIDAC, rather than thebreakover voltage, so that the energy to the D.U.T. can bepredictably controlled.

By varying VC, C1 and R4, the surge current curve ofFigure 15 was derived. Extensive life testing and adequatederating ensure that the SIDAC, when properly used, willreliably operate in the various applications.

I ,

SU

RG

E C

UR

REN

T (A

MPS

)pk

tw

Figure 4.20. Exponential Surge Current Capability of theMKP3V SIDAC. Pulse Width versus Peak Current

10%

Ipk

0.3

100

tw, PULSE WIDTH (ms)

3

30

10

1011

30 100 3003


CHAPTER 5SCR CHARACTERISTICS

SCR TURN–OFF CHARACTERISTICS

In addition to their traditional role of power control devices,SCRs are being used in a wide variety of other applications inwhich the SCR’s turn–off characteristics are important. As inexample — reliable high frequency inverters and converterdesigns (20 kHz) require a known and controlled circuit–commutated turn–off time (tq). Unfortunately, it is usuallydifficult to find the turn–off time of a particular SCR for a givenset of circuit conditions.

This section discusses tq in general and describes a circuitcapable of measuring tq. Moreover, it provides data andcurves that illustrate the effect on tq when other parametersare varied, to optimize circuit performance.

SCR TURN–OFF MECHANISMThe SCR, being a four layer device (P–N–P–N), is

represented by the two interconnected transistors, as shownin Figure 5.1. This regenerative configuration allows thedevice to turn on and remain on when the gate trigger isremoved, as long as the loop gain criteria is satisfied; i.e.,when the sum of the common base current gains (α) of boththe equivalent NPN transistor and PNP transistor, exceedone. To turn off the SCR, the loop gain must be brought belowunity, whereby the on–state principal current (anode currentiT) limited by the external circuit impedance, is reduced belowthe holding current (IH). For ac line applications, this occursautomatically during the negative going portion of thewaveform. However, for dc applications (inverters, as anexample), the anode current must be interrupted or diverted;(diversion of the anode current is the technique used in the tqtest fixture described later in this application note).

SCR TURN–OFF TIME tqOnce the anode current in the SCR ceases, a period of

time must elapse before the SCR can again block a forwardvoltage. This period is the SCR’s turn–off time, tq, and isdependent on temperature, forward current, and otherparameters. The turn–off time phenomenon can be under-stood by considering the three junctions that make up theSCR. When the SCR is in the conducting state, each of thethree junctions is forward biased and the N and P

Figure 5.1. Two Transistor Analogy of an SCR

TWO TRANSISTOR MODEL

IB1 = IC2Q1

GATEQ2

ITM

P

P P

N

NGATE

IC1 = IB2N

P–N–P–N STRUC-TURE

J1

P

N

N

P

GATE

CATHODE

ANODE

ANODE

GATE

CATHODE

J2

J3

CATHODECATHODE

ANODEANODE

regions (base regions) on either side of J2 are heavilysaturated with holes and electrons (stored charge). In orderto turn off the SCR in a minimum amount of time, it isnecessary to apply a negative (reverse) voltage to the deviceanode, causing the holes and electrons near the two endjunctions, J1 and J3, to diffuse to these junctions. Thiscauses a reverse current to flow through the SCR. When the



holes and electrons near junctions J1 and J3 have beenremoved, the reverse current will cease and junctions J1 andJ3 will assume a blocking state. However, this does notcomplete the recovery of the SCR since a high concentrationof holes and electrons still exist near the center junction, J2.This concentration decreases by the recombination processand is largely independent of the external circuit. When thehole and electron concentration near junction J2 hasreached some low value, junction J2 will assume its blockingcondition and a forward voltage can, after this time, beapplied without the SCR switching back to the conductionstate.

tq MEASUREMENTWhen measuring SCR turn–off time, tq, it is first

necessary to establish a forward current for a period oftime long enough to ensure carrier equilibrium. This mustbe specified, since ITM has a strong effect on the turn–offtime of the device. Then, the SCR current is reversed at aspecified di/dt rate, usually by shunting the SCR anode tosome negative voltage through an inductor. The SCR willthen display a “reverse recovery current,” which is thecharge clearing away from the junctions. A further waitingtime must then elapse while charges recombine, before aforward voltage can be applied. This forward voltage isramped up a specified dv/dt rate. The dv/dt delay time isreduced until a critical point is reached where the SCR canno longer block the forward applied voltage ramp. In effect,the SCR turns on and consequently, the ramp voltagecollapses. The elapsed time between this critical point andthe point at which the forward SCR current passes throughzero and starts to go negative (reverse recovery phase), isthe tq of the SCR. This is illustrated by the waveformsshown in Figure 5.2.

tq GENERAL TEST FIXTUREThe simplified circuit for generating these waveforms is

schematically illustrated in Figure 5.3. This circuit is imple-mented with as many as eight transformers including variacs,and in addition to being very bulky, has been known to betroublesome to operate. However, the configuration isrelevent and, in fact, is the basis for the design, as describedin the following paragraphs.

tq TEST FIXTURE BLOCK DIAGRAMS ANDWAVEFORMS

The block diagram of the tq Test Fixture, illustrated inFigure 5.4, consists of four basic blocks: A Line Synchro-nized Pulse Generator establishes system timing; a ConstantCurrent Generator (variable in amplitude) powers the DeviceUnder Test (DUT); a di/dt Circuit controls the rate of changeof the SCR turn–off current; and the dv/dt Circuit reapplies acontrolled forward blocking voltage. Note from the wave-forms illustrated that the di/dt circuit, in parallel with the DUT,diverts the constant current from the DUT to produce thedescribed anode current ITM.

tq TEST FIXTURE CHARACTERISTICSThe complete schematic of the tq Test Fixture and the

important waveforms are shown in Figures 5.5 and 5.6,respectively.

A CMOS Gate is used as the Line Synchronized PulseGenerator, configured as a wave shaping Schmitt trigger,clocking two cascaded monostable multivibrators for delayand pulse width settings (Gates 1C to 1F). The result is apulse generated every half cycle whose width and position(where on the cycle it triggers) are adjustable by means

Figure 5.2. SCR Current and Voltage WaveformsDuring Circuit–Commutated Turn–Off

VT

IDX

ITM

50% IRMIRM

di/dt

dv/dt

trr

tqVDX

50% ITM


Figure 5.3. Simplified t q Test Circuit

V2

IT

I1

V1

S2

IT

S1 dv/dt

DUT

di/dt

L1 R2S3

V3

R1

C1

D3

S4

D2

D1

of potentiometers R2 and R3, respectively. The output pulseis normally set to straddle the peak of the ac line, which notonly makes the power supplies more efficient, but also allowsa more consistent oscilloscope display. This pulse shown inwaveform A of Figure 5.6 initiates the tq test, which requiresapproximately 0.5 ms to assure the device a complete turnon. A fairly low duty cycle results, (approximately 5%) whichis important in minimizing temperature effects. The repetitivenature of this test permits easy oscilloscope viewing andallows one to readily “walk in” the dv/dt ramp. This isaccomplished by adjusting the appropriate potentiometer(R7) which, every 8.33 ms (every half cycle) will apply thedv/dt ramp at a controlled time delay

To generate the appropriate system timing delays, four RCintegrating network/comparators are used, consisting ofop–amps U2, U5 and U6.

Op–amp U2A, along with transistor Q2, opto–coupler U4and the following transistors Q6 and Q7, provide the gatedrive pulse to the DUT (see waveforms B, C and D of Figure5.6). The resulting gate current pulse is about 50 µs wide andcan be selected, by means of switch S2, for an IGT of fromabout 1 mA to 90 mA. Opto–coupler U4, as well as U1 in theConstant Current Circuit, provide electrical isolation betweenthe power circuitry and the low level circuitry.

The Constant Current Circuit consists of an NPN Darling-ton Q3, connected as a constant current source driving aPNP tri–Darlington (Darlington Q4, Bipolar Q5). By varyingthe base voltage of Q3 (with Current Control potentiometerR4), the collector current of Q3 and thus the base voltage ofQ4 will also vary. The PNP output transistor Q5 (MJ14003)(rated at 70 A), is also configured as a constant currentsource with four, parallel connected emitter resistors (approx-imately 0.04 ohms, 200 W), thus providing as much as 60 Atest current. Very briefly, the circuit operates as follows: —CMOS Gate 1E is clocked high, turning on, in order, a) NPN

transistor Q16, b) PNP transistor Q1, c) optocoupler U3, andd) transistors Q3, Q4 and Q5. The board mounted CurrentSet potentiometer R5, sets the maximum output current and R4,the Current Control, is a front panel, multiturn potentiometer.

Time delay for the di/dt Circuit is derived from cascadedop–amps U2B and U5 (waveforms F and G of Figure 5.6).The output gate, in turn, drives NPN transistor Q8, followed

Figure 5.4. Block Diagram of the t q Test Fixtureand Waveforms

0

V1dv/dt

IT

di/dt

CONSTANTCURRENT

di/dt

dv/dt

IT

D1

DUT

IGTLINE SYNC

PULSEGENERATOR

CONSTANTCURRENT

GENERATOR

dvdt

CIRCUIT didt

CIRCUIT

Theory and Applications Motorola Thyristor Device Data1.5–4

47 2 W

0.1

µF

50 µ

F20

V

LM31

7TU7

–+

25 V

16

20,0

00µF

25

V

–+

100

1 W

–V1

–18

VTY

P

Fig

ure

5.5.

tq

Tes

t Fix

ture

120

V60

Hz

POW

ER O

N2

A S.

B.

0.1

µF20

0 V

0.1

µF, 2

00 V

+ 20

V (U

NLO

ADED

)+

12 V

(LO

ADED

)

STAN

CO

RP6

337

SW S

1

1

4N35

U4

2

GAT

E C

UR

REN

TSW

S2

150

150

kI T DU

T

– 5

VSW

.53

OFF

BIAS

1 k

8.2

k

820

330

160

120

82

Q6

10 k

2N 4919 Q7 1

W20

2N39

04

1 k

1 k

41 k

1N47

4010

V, 1

W

100

µF20

V0.

1µF

+

1N47

335.

1 V,

1 W

1N 914

– 10

V

1 k

+ 10

V 5+

10 V

– V1M

PSA1

3

CU

RR

ENT

SET

R5

1 k

CU

RR

ENT

CO

NTR

OL

R4

100

1W

4

100

1/2

W

Q3

(4) 0

.15

Ω, 5

0 W

+50

,000

µF 25 V

1.2

k2

W 0.1 µF

100

1 W

2N60

42Q

4M

J14

003

Q5

L 1

D1*

(3) M

TM15

N06

E

100

k

MR

856

– V 2

1N53

70A

56 V

5 W

1N59

32A56

02

W

Q10

µF0.

001

µF

560

2 W

Q12

0.00

1µF

Q11

.001

1N59

32A

20 V

1.5

W

0.00

2µF

1N59

32A

MJE

254

Q9

470

56 2 W

10 k

0.00

1 µF

1 k

470

1N 914

SYN

CO

UT

2N44

01Q

8

10 k

+ V 1

R1

I 1

MTM

2N90

Q15

C1

+ 10

V0.

1µF1N 4747

1 k

2 W

1N47

28

100

+(1

/2)

MC

1458

U5

U56

7

4

0.1

µF

+ 10

V

8

MJE

250

Q14

5–

10 V

1 k10

k

1N47

28

0.1

µF

t q T

IME

CO

NTR

OL

R7

R6

ON

TIM

EC

ON

TRO

L

150

k, 1

0 T

10 k

0.00

2µF

1.8

k

0.1

µF3.

3 V

– 10

V39

k

76

41

kU6

23+ 10

V

(1/2

)M

C14

58–

7U2

B

+

65

0.00

1 µF

0.02 µF

0.1

µF

4.7

k50

k

V REF

+ 10

V

3.3

k

2N39

04Q22

3.3

V

4N35

U3

3.3

k1N

4728

0.1

µF

–U2A

+

23

(1/2

)M

C14

58

820

pF

+ 10

V12

k

510

k5

+ 10

V10

k43

02

W

2N39

04Q

1610

k47 k

CO

NST

ANT

CU

RR

ENT

CIR

CU

IT

4.7

k

25 k

R3

PULS

E W

IDTH

CO

NTR

OL

111F

121E

13

15 140.

001

µF

9100

k+ 10

V

R2PU

LSE

DELA

YCO

NTRO

L

1D

+ 10

V 10

150

k0.

01 µF1M

1C5

U1

MC

1457

2

7

1 k

Q1

2N 3906

+ 10

V

100

k

220

pF+

10 V

1B3

8

14

220

k

1 A

222

k

+ 10

V

1 k

10 k

+

+ 10

V

1.8

k2

240

1

+31N

4001

2000 µF

330

1 W

–5

V+

1 k

1/2

W

90 m

A

70 3050 10

U6

MC

1741

o

o

o

– V1

– 18

V

o

10 µ

F15

V

2N39

04Q

13

TRIA

DF9

3X

1N91

4

10 V

+ 10

V

1.5

k

1 m

A

VA

1000

di dtC

IRC

UIT

560

2 W

1 K

2 W

1 K

2 W

dv dtC

IRC

UIT

6

1.2

K2

W

LINE

SYN

CHRO

NIZE

D PU

LSE

GEN

ERAT

OR

120 VSWD

L 1:

0 µH

(TYP

)*D

IOD

E R

EQU

IRED

WIT

H L

1

D1:

MR

506

FOR

3 A

, HIG

H t q

DU

TSM

R85

6 FO

R 3

A, L

OW

t q D

UTS

(DIO

DE

I F S

CAL

ED T

O D

UT

I A)

I 1:

≈ 50

mA

FOR

HIG

H t q

DU

TS

V1

R1

50V

1k

(TYP

)

≈ 1

A FO

R L

OW

t q

V1

R1

50V

50(T

YP)

C1:

DET

ERM

INED

BY

SPEC

dv/

dt

– V 2

:–

12 V

(TYP

),

– 5

0 V


by PNP transistor Q9, whose output provides the gate drivefor the three parallel connected N–channel power MOSFETtransistors Q10–Q12 (waveforms H of Figure 5.6). Thesethree FETs (MTM15N06), are rated at 15 A continuous draincurrent and 40 A pulsed current and thus can readily divertthe maximum 60 A constant current that the Fixture cangenerate. The results of this diversion from the DUT isdescribed by waveforms E, H and I of Figure 5.6, with thedi/dt of of ITM dictated by the series inductance L1. For allsubsequent testing, the inductor was a shorting bar, resultingin very little inductance and consequently, the highest di/dt(limited primarily by wiring inductance). When a physicalinductor L1 is used, a clamp diode, scaled to the divertedcurrent, should be placed across L1 to limit “inductive kicks.”

dv/dt CIRCUITThe last major portion of the Fixture, the dv/dt Circuit, is

variable time delayed by the multi–turn, front panel tq TimeControl potentiometer R7, operating as part of an integratoron the input of comparator U6. Its output (waveform J ofFigure 5.6) is used to turn–off, in order, a) normally on NPNtransistor Q13, b) PNP transistor Q14 and c) N–channelpower MOSFET Q15 (waveform L of Figure 5.6). This FET isplaced across ramp generating capacitor C1, and whenunclamped (turned off), the capacitor is allowed to chargethrough resistor R1 to the supply voltage +V1. Thus, thevoltage appearing on the drain will be an exponentially risingvoltage with a dv/dt dictated by R1, C1, whose position intime can be advanced or delayed. This waveform is thenapplied through a blocking diode to the anode of the DUT forthe forward blocking voltage test.

Another blocking diode, D1, also plays an important role intq measurements and must be properly selected. Its purposeis to prevent the dv/dt ramp from feeding back into theCurrent Source and di/dt Circuit and also to momentarilyapply a reverse blocking voltage (a function of –V2 of thedi/dt circuit) to the DUT. Consequently, D1 must have areverse recovery time trr greater than the DUT, but less thanthe tq time. When measuring standard recovery SCRs, itsselection — fast recovery rectifiers or standard recovery — isnot that critical, however, for fast recovery, low tq SCRs, thediode must be tailored to the DUT to produce accurateresults. Also, the current rating of the diode must becompatible with the DUT test current. These effects areillustrated in the waveforms shown in Figure 5.7 where both afast recovery rectifier and standard recovery rectifier wereused in measuring tq of a standard 2N6058 SCR. Althoughthe di/dt’s were the same, the reverse recovery current IRMand trr were greater with the standard recovery rectifier,resulting in a somewhat shorter tq (59 µs versus 63 µs). Infact, tq is affected by the initial conditions (ITM, di/dt, IRM,dv/dt, etc.) and these conditions should be specified tomaintain measurement repeatability. This is later described inthe published curves and tables.

Finally, the resistor R1 and the resultant current I1 in thedv/dt circuit must meet certain criteria: I1 should be greaterthan the SCR holding current so that when the DUT does

indicate tq limitation, it latches up, thus suppressing the dv/dtramp voltage; and, for fast SCRs (low tq), I1 should be largeenough to ensure measurement repeatability. Typical valuesof I1 for standard and fast SCRs may be 50 mA and 500 mA,respectively. Obviously, for high forward blocking voltage+ V1 tests, the power requirements must be met.

EFFECTS OF GATE BIAS ON t qExamples of the effects of I1 on tq are listed in Table 5.III

whereby standard and fast SCRs were tested with about 50mA and 1 A, respectively. Note that the low tq SCR’s requiredfast recovery diodes and high I1 current.

TEST FIXTURE POWER SUPPLIESMost of the power supplies for the system are self

contained, including the +12 V supply for the ConstantCurrent Circuit. This simple, unregulated supply furnishes upto 60 A peak pulsed current, primarily due to the linesynchronized operation of the system. Power supplies +V1and –V2, for this exercise, were external supplies, since theyare variable, but they can be incorporated in the system. Thereverse blocking voltage to the DUT is supplied by – V2 andis typically set for about –10 V to –20 V, being limited to

Figure 5.6. t q Test Fixture System Waveforms

U6, P6dv/dtCIRCUIT

Q15GATEdv/dt

U5, P7

Q1 COL.

U2, P7

ITDUT

IGT

t, TIME (µs)

Q15DRAINdv/dtOUTPUT

U2, P1

U4, P4

Q9 COL.Q10–Q12di/dtCIRCUIT

CONSTANTCURRENTGEN.Q5 COL.

A

B

C

D

E

F

G

H

I

J

K

L8006004002000



tq = 59 µs

Figure 5.7. The Effects of Blocking Diode D1 on t q of a2N6058 SCR

D1 = MR856, FAST RECOVERY RECTIFIER

D1 = 1N5402, STANDARD RECOVERY RECTIFIER

I = 2 A/Div

0 A

V = 10 V/Div

tq = 63 µs

0 V

I = 2 A/Div

0 A

V = 10 V/Div

0 V

t = 50 µs/Div

t = 50 µs/Div

t = 1 µs/Div

t = 1 µs/Div

the breakdown voltage of the diverting power MOSFETS(VDSS = 60 V). The +12 V unregulated supply can be as highas +20 V when unloaded; therefore, –V2 (MAX), in theory,would be –40 V but should be limited to less than –36 V dueto the 56 V protective Zener across the drain–source of theFETs. Also, –V2 must be capable of handling the peak 60 A,diverting current, if so required.

The reapplied forward blocking voltage power supply +V1,may be as high as the DUT VDRM which conceivably can be600 V, 1,000 V or greater and, since this supply is on most ofthe time, must be able to supply the required I1. Due to thesometimes high power requirements, +V1 test conditionsmay have to be reduced for extremely fast SCRs.

PARAMETERS AFFECTING t qTo see how the various circuit parameters can affect tq,

one condition at a time is varied while the others are heldconstant. The parameters to be investigated are a) forward

current magnitude (ITM), b) forward current duration, c) rate ofchange of turn–off current (di/dt), d) reverse–current magni-tude (IRM), e) reverse voltage (VRM), f) rate of reappliedforward voltage (dv/dt), g) magnitude limit of reappliedvoltage, h) gate–cathode resistance and i) gate drivemagnitude (IGT).

Typical data of this kind, taken for a variety of SCRs,including standard SCRs, high speed SCRs, is condensedand shown in Table 5.1. The data consists of the differentconditions which the particular SCR types were subjected to;ten SCRs of each type were serialized and tested to eachcondition and the ten tq’s were averaged to yield a “typical tq.”

The conditions listed in Column A in Table 5.1, are typicalconditions that might be found in circuit operation. Columns Bthrough J in Table 5.1, are in order of increasing tq; theconditions listed in these columns are only the conditions thatwere modified from those in Column A and if a parameter isnot listed, it is the same as in Column A.

Theory and ApplicationsMotorola Thyristor Device Data1.5–7

Tabl

e 5.

1. P

aram

eter

s A

ffect

ing

tq

Dev

ice

AB

CD

EF

GH

I

2N65

0825

A60

0 V

RG

K =

1 k

dv

/dt =

15

V/µ

sI T

M =

25

AI R

M =

14

Adi

/dt =

–10

0 A

/µs

I TM

dur

atio

n =

275

µs

I GT

= 3

0 m

A

RG

K =

100

dv/d

t = 2

.4 V

/µs

I TM

= 1

AI R

M =

1.8

Adi

/dt =

32

A/µ

s

RG

K =

100

dv/d

t = 2

.4 V

/µs

I TM

= 2

AI R

M =

50

mA

di/d

t = 0

.5 µ

s

RG

K =

100

dv/d

t = 2

.4 V

/µs

I RM

= 5

0 m

Adi

/dt =

0.4

5 A

/µs

RG

K =

100

dv/d

t = 2

.4 V

/µs

RG

K =

dv

/dt =

2.4

V/µ

s

RG

K =

100

dv/d

t = 2

.4 V

/µs

I TM

= 3

7 A

RG

K =

100

I GT

= 9

0 m

A

typ

t q =

68

µsty

p t q

= 4

2 µs

typ

t q =

45

µsty

p t q

= 4

9 µs

typ

t q =

60

µsty

p t q

= 6

4 µs

typ

t q =

64

µsty

p t q

= 6

5 µs

typ

t q =

68

µs

2N63

9812

AR

GK

= 1

k

dv/d

t = 9

0 V

/µs

I TM

= 1

2 A

I RM

= 1

1 A

di/d

t = –

100

A/µ

sI T

M d

urat

ion

= 2

75 µ

sI G

T =

30

mA

RG

K =

100

dv/d

t = 2

.5 V

/µs

I TM

= 1

AI R

M =

50

mA

di/d

t = –

0.5

A/µ

s

RG

K =

100

dv/d

t = 2

.5 V

/µs

I TM

= 1

AI R

M =

2.7

Adi

/dt =

56

A/µ

s

RG

K =

100

dv/d

t = 2

.5 V

/µs

I RM

= 5

0 m

Adi

/dt =

32

A/µ

s

RG

K =

100

dv/d

t = 2

.5 V

/µs

I TM

= 1

8 A

I RM

= 5

0 m

Adi

/dt =

0.3

A/µ

s

RG

K =

dv

/dt =

2.5

V/µ

sI R

M =

50

mA

di/d

t = 0

.35

A/µ

sR

GK

= 1

00I G

T =

90

mA

typ

t q =

48

µsty

p t q

= 3

0 µs

typ

t q =

31

µsty

p t q

= 3

2 µs

typ

t q =

33

µsty

p t q

= 3

5.5

µsty

p t q

= 4

5 µs

typ

t q =

48

µs

Theory and Applications Motorola Thyristor Device Data1.5–8

Tabl

e 5.

1. C

ontin

ued

Dev

ice

AB

CD

EF

GH

I

C10

6F4

AI G

T =

1 m

AR

GK

= 1

kdv

/dt =

5 V

/s

I TM

= 4

AI R

M =

4A

di/d

t = 5

0 A

/s

I TM

dur

atio

n =

275

s

VD

X =

50

V

I TM

= 2

AI R

M =

2.5

Adi

/dt =

–30

A/

sV

DX

= 5

0 V

I TM

= 6

AI R

M =

–1

A/

sdi

/dt =

–1

A/

sV

DX

= 1

50 V

I TM

= 6

AI R

M =

0.1

Adi

/dt =

–1

A/

sV

DX

= 5

0 V

dv/d

t = 1

.4 V

/s

I TM

= 2

AI R

M =

0.2

Adi

/dt =

–1.

4 A

/s

–V2

= 3

5 V

I RM

= 0

.2 A

di/d

t = –

1.4

A/

s

I RM

= 0

.15

A–V

2 =

4 V

di/d

t = –

1.4

A/

s

dv/d

t = 1

.4 V

/s

I RM

= 0

.15

Adi

/dt =

1.4

A/

s

I GT

= 9

0 m

Adv

/dt =

1.4

V/

sI R

M =

2 A

di/d

t = –

1.4

A/

s

typ

t q =

28 s

typ

t q =

25 s

typ

t q =

26 s

typ

t q =

26 s

typ

t q =

26 s

typ

t q =

27 s

typ

t q =

27 s

typ

t q =

27 s

typ

t q =

27 s

2N62

404

AR

GK

= 1

kdv

/dt =

40

V/

sI T

M =

4 A

I RM

= 4

Adi

/dt =

50

A/

sI T

M d

urat

ion

= 2

75

sI G

T =

1 m

AV

DX

= 5

0 V

RG

K =

100

dv/d

t = 1

.3 V

/s

I TM

= 1

AI R

M =

50

mA

di/d

t = –

0.5

A/

sI G

T =

90

mA

VD

X =

150

V

RG

K =

100

dv/d

t = 1

.75

V/

sI T

M =

1 A

I RM

= 5

0 m

Adi

/dt =

–0.

5 A

/s

I GT

= 9

0 m

A

RG

K =

100

dv/d

t = 1

.75

V/

sI R

M =

50

mA

di/d

t = –

0.5

A/

sI G

T =

90

mA

dv/d

t = 1

.75

V/

sR

GK

= 1

00I T

M =

6 A

I RM

= 5

0 m

Adi

/dt =

–0.

5 A

/s

I GT

= 9

0 m

A

RG

K =

100

I RM

= 5

0 m

Adi

/dt =

–0.

5 A

/s

I GT

= 9

0 m

AR

GK

= 1

00I G

T =

900

mA

RG

K =

dv

/dt =

1.7

5 V

/s

I TM

= 1

AI R

M =

50

mA

di/d

t = –

0.5

A/

sI G

T =

90

mA

I GT

= 9

0 m

A

typ

t q =

44.

8 s

typ

t q =

26 s

typ

t q =

26.

2 s

typ

t q =

27.

7 s

typ

t q =

28.

6 s

typ

t q =

30 s

typ

t q =

32.

7 s

typ

t q =

37.

2 s

typ

t q =

41.

4 s

MC

R10

0–6

0.8

AR

GK

= 1

kdv

/dt =

160

V/

sI T

M =

0.8

AI R

M =

0.8

Adi

/dt =

12

A/

sV

DX

= 5

0 V

I TM

dur

atio

n =

275

s

dv/d

t = 3

0 V

/s

I TM

= 0

.25

AI R

M =

40

mA

di/d

t = –

0.6

A/

s

dv/d

t = 3

0 V

/s

Ir =

40

mA

di/d

t = –

0.8

A/

s

–V2

= 9

VI R

M =

20

mA

di/d

t = –

0.4

A/

s

–V2

= 1

VIr

= 4

0 m

Adi

/dt =

–0.

8 A

/s

dv/d

t = 3

0 V

/s

I TM

= 1

.12

AI R

M =

40

mA

di/d

t = –

0.8

A/

s

dv/d

t = 3

0 V

/s

I TM

= 1

.12

AI R

M =

40

mA

di/d

t = –

0.8

A/

sV

DX

= 1

00 V

typ

t q =

14.

4 s

typ

t q =

12.

7 s

typ

t q =

13.

5 s

typ

t q =

13.

7 s

typ

t q =

13.

9 s

typ

t q =

14.

4 s

typ

t q =

14.

4 s

2N50

630.

8 A

RG

K =

1 k

dv/d

t = 3

0 V

/s

I TM

= 0

.8 A

I RM

= 0

.8 A

di/d

t = 1

2 A

/s

I TM

dur

atio

n =

275

s

VD

X =

50

V

dv/d

t = 5

V/

sI T

M =

0.2

AI R

M =

50

mA

di/d

t = –

0.6

A/

s

dv/d

t = 5

V/

sI R

M =

50

mA

di/d

t = –

0.8

A/

s

dv/d

t = 5

V/

sI T

M =

1.1

2 A

I RM

= 5

0 m

Adi

/dt =

–0.

8 A

/s

I RM

= 4

0 m

A–V

2 =

9 V

di/d

t = –

0.45

A/

s

I RM

= 4

0 m

A–V

2 =

1 V

di/d

t = –

0.8

A/

s

VD

X =

100

Vdv

/dt =

5 V

/s

I TM

= 1

.12

AI R

M =

50

mA

di/d

t = –

0.8

A

typ

t q =

28.

9 s

typ

t q =

27/s

typ

t q =

30/s

typ

t q =

31 s

typ

t q =

31.

2 s

typ

t q =

31.

4 s

typ

t q =

31.

7 s

2N50

610.

8 A

dv/d

t = 1

0 V

/s

I TM

= 0

.8 A

I RM

= 0

.8 A

di/d

t = 1

8 A

/s

I TM

dur

atio

n =

275

s

RG

K =

1 k

VD

X =

30

V

dv/d

t = 3

.5 V

/s

I TM

= 0

.25

AI R

M =

40

mA

di/d

t = –

0.7

A/

s

dv/d

t = –

3.5

V/

sI R

M =

40

mA

di/d

t = –

0.8

A/

s

dv/d

t = 3

.5 V

/s

I TM

= 1

.12

AI R

M =

40

mA

di/d

t = –

0.8

A/

sV

DX

= 6

0 V

dv/d

t = 3

.58/s

I TM

= 1

.12

AI R

M =

40

mA

di/d

t = –

0.7

A/

s

–V2

= 4

VI R

M =

20

mA

di/d

t = –

0.2

A/

s

–V2

= 1

VI R

M =

40

mA

di/d

t = –

0.8

A/

s

typ

t q =

31.

7 s

typ

t q =

19.

1 s

typ

t q =

19/s

typ

t q =

19.

8 s

typ

t q =

20.

2 s

typ

t q =

30 s

typ

t q =

30.

2 s


Table 5.2 is a condensed summary of Table 5.1 and showswhat happens to the tq of the different devices when aparameter is varied in one direction or the other.

THE EFFECT OF CHANGING PARAMETERSON tq

From Tables 5.1 and 5.2, it is clear that some parametersaffect tq more than others. The following discussion de-scribes the effect on tq of the various parameters.

FORWARD CURRENT MAGNITUDE (ITM)Of the parameters that were investigated, forward–current

magnitude and the di/dt rate have the strongest effect on tq.Varying the ITM magnitude over a realistic range of ITMconditions can change the measured tq by about 30%. Thechange in tq is attributed to varying current densities (storedcharge) present in the SCR’s junctions as the ITM magnitudeis changed. Thus, if a large SCR must have a short tq when alow ITM is present, a large gate trigger pulse (IGT magnitude)would be advantageous. This turns on a large portion of theSCR to minimize the high current densities that exists if onlya small portion of the SCR were turned on (by a weak gatepulse) and the low ITM did not fully extend the turned onregion.

In general, the SCR will exhibit longer tq times withincreasing ITM. Increasing temperature also increases the tqtime.

di/dt RATEVarying the turn–off rate of change of anode current di/dt

does have some effect on the tq of SCRs. Although theincrease in tq versus increasing di/dt was nominal for theSCRs illustrated, the percentage change for the fast SCRswas fairly high (about 30–40%).

REVERSE CURRENT MAGNITUDE (IRM)The reverse current is actually due to the stored charge

clearing out of the SCR’s junctions when a negative voltageis applied to the SCR anode. IRM is very closely related to thedi/dt rate; an increasing di/dt rate causing an increase of IRMand a decreasing di/dt rate causing a lower IRM.

By using different series inductors and changing thenegative anode turn–off voltage, it is possible to keep thedi/dt

Parameter Changed Device Columns1st(µs)

2nd(µs)

IGT Increase 2N65082N63982N6240C106D

AIAGAIHI

684844.827

684841.427

Decrease RGK1 k to 100 ohms

2N65082N63982N6240

AHAGGI

684841.4

654532.7

Increase RGK1 k to

2N65082N63982N6240

EFDFCH

603226.2

6435.537.2

VDX C106D2N6240MCR100–62N50632N5061

DCBCFGDGDE

2626.214.43120.2

262614.431.719.8

Decrease dv/dt Rate 2N6508C106D2N6240

EHHJDF

652930

602727.7

Increase ITM 2N65082N6398C106D2N6240

MCR100–62N50632N5061

EGDEEHDCDECECFCDBE

60322626.227.726.213.530.719.1

64332727.728.628.614.431

20.7

Table 5.2. The Effects of Changing Parameters on t q

rate constant while changing IRM. It was found that IRM haslittle or no effect on tq when it is the only variable changed(see Table 5.1 C106D, Columns F and G, for example).

REVERSE ANODE VOLTAGE (V RM)Reverse anode voltage has a strong effect on the IRM

magnitude and the di/dt rate, but when VRM alone is varied,with IRM and di/dt held constant, little or no change in tq timewas noticed. VRM must always be within the reverse voltageof the device.

Gate Bias Conditions + V1 RI dv/dt (v/ µs)

Device0V – 5 V – V2 = –10 V, IF = 3 A 50 V 1 k/50 2.5/50

Device

tq1 tq2 DiodeDI

dv/dt(V/µs) Remarks

2N6508 40 µs 30 µsSlow

MR5022.5 Slow diode faster than fast diode, (lower tq)

2N6240 16 µs 9 µs Slow 2.5 Slow diode faster. 2.5 V/µs faster than 50 V/µs

2N6398 30 µs 25 µs Slow 2.5 Tested slow diode only

C106D 13 µs 8 µs Slow 2.5 Tested slow diode only

Table 5.3 The Effects of Gate Bias on t q



Figure 5.8. Standard SCR Turn–Off Time t q as aFunction of Anode Current I TM

C106 : 5 A/ µsdv/dt : 45 V/ µsRGK : 100 Ω

TA : 25°C

ITM, ANODE CURRENT (AMPS)

di/dt

C106D

STANDARD SCR25

20

15

10

5

0502010521

t , T

UR

N-O

FF T

IME

( s)

qµ

REAPPLIED dv/dt RATEVarying the reapplied dv/dt rate across the range of dv/dt’s

commonly encountered can vary the tq of a given SCR bymore than 10%. The effect of the dv/dt rate on tq is due to theAnode–Gate capacitance. The dv/dt applied at the SCRanode injects current into the gate through this capacitance(iGT = C dv/dt). As the dv/dt rate increased, the gate currentalso increases and can trigger the SCR on. To complicatematters, this injected current also adds to the current due toleakage or stored charge left in the junctions just afterturn–off.

The stored charge remaining in the center junction is themain reason for long tq times and, for the most part, thecharge is removed by the recombination process. If thereapplied dv/dt rate is high, more charge is injected into thisjunction and prevents it from returning to the blocking state,as soon as if it were a slow dv/dt rate. The higher the dv/dtrate, the longer the tq times will be.

MAGNITUDE LIMIT OF REAPPLIED dv/dt (V DX)Changing the magnitude limit of the reapplied dv/dt voltage

has little or no effect on a given SCR’s tq time when themaximum applied voltage is well below the voltage break-down of the SCR. The tq times will lengthen if the SCR isbeing used near its voltage breakdown, since the leakagepresent near breakdown is higher than at lower voltagelevels. The leakage will lengthen the time it takes for thecharge to be swept out of the SCR’s center junction, thuslengthening the time it takes for this junction to return to theblocking state.

GATE CATHODE RESISTANCE (R GK)In general, the lower the RGK is, the shorter the tq time will

be for a given SCR. This is because low RGK aids in theremoval of stored charge in the SCR’s junctions. Anapproximate 15% change in the tq time is seen by changingRGK from 100 ohms to 1000 ohms for the DUTs.

GATE DRIVE MAGNITUDE (IGT)Changing the gate drive magnitude has little effect on a

SCR’s tq time unless it is grossly overdriven or underdriven.When it is overdriven, there is an unnecessary large amountof charge in SCR’s junction. When underdriven, it is possiblethat only a small portion of the chip at the gate region turnson. If the anode current is not large enough to spread thesmall turned on region, there is a high current and chargedensity in this region that consequently lengthens the tq time.

FORWARD CURRENT DURATIONForward current duration had no measurable effect on tq

time when varied from 100 µs to 300 µs, which were the limitsof the Motorola tq Tester. Longer ITM durations heat up theSCR which causes temperature effects; very short ITMdurations affect the tq time due to the lack of time for thecharges in the SCR’s junctions to reach equilibrium, butthese effects were not seen in the range tested.

REVERSE GATE BIAS VOLTAGEAs in transistor operation, reverse biasing the gate of the

SCR decreases the turn–off time, due to the rapid “sweepingout” of the stored charge. The reduction in tq for standardSCRs is quite pronounced, approaching perhaps 50% insome cases; for fast SCRs, only nominal improvement mightresult. Table 5.3 shows this effect on six SCRs where thegate bias was set for 0 V and – 5 V, respectively (the 1 k gateresistor of the DUT was either grounded or returned to – 5 V).Due to the internal, monolithic resistor of most SCRs, theactual reverse bias voltage between the gate–cathode is lessthan the reverse bias supply.

CHARACTERIZING SCRs FOR CROWBARAPPLICATIONS

The use of a crowbar to protect sensitive loads from powersupply overvoltage is quite common and, at the first glance,the design of these crowbars seems like a straightforward,relatively simple task. The crowbar SCR is selected so as tohandle the overvoltage condition and a fuse is chosen at 125to 250% of the supply’s rated full–load line current. However,upon further investigation, other questions and problems areencountered.

How much overvoltage and for how long (energy) can theload take this overvoltage? Will the crowbar respond tooslowly and thus not protect the load or too fast resulting infalse, nuisance triggering? How much energy can thecrowbar thyristor (SCR) take and will it survive until the fuseopens or the circuit breaker opens? How fast will the fuseopen, and at what energy level? Can the fuse adequatelydifferentiate between normal current levels — including surgecurrents — and crowbar short circuit conditions?

It is the attempt of this section to answer these questions— to characterize the load, crowbar, and fuse and thus tomatch their characteristics to each other.

The type of regulator of most concern is the low voltage,series pass regulator where the filter capacitors to be


crowbarred, due to 60 Hz operation, are relatively large andthe charge and energy stored correspondingly large. On theother hand, switching regulators operating at about 20 kHzrequire smaller capacitors and thus have lower crowbarconstraints.

These regulators are quite often line–operated using ahigh voltage, two–transistor inverter, half bridge or fullbridge, driving an output step–down transformer. If atransistor were to fail, the regulator–transformed powerwould be less and the output voltage would drop, not rise,as is the case for the linear series regulator with a shortedpass transistor. Thus, the need for overvoltage protectionof these types of switching regulators is minimized.

This premise, however, does not consider the case ofthe lower power series switching regulator where ashorted transistor would cause the output voltage to rise.Nor does it take into account overvoltage due to transientson the output bus or accidental power supply hookup. Forthese types of operations, the crowbar SCR should beconsidered.

HOW MUCH OVERVOLTAGE CAN THELOAD TAKE?

Crowbar protection is most often needed when ICs areused, particularly those requiring a critical supply voltagesuch as TTL or expensive LSI memories and MPUs.

If the load is 5 V TTL, the maximum specified continuousvoltage is 7 V. (CMOS, with its wide power supply range of

20

PULSE WIDTH (ms)

VCCTJ ≈ 85°C, DUTY CYCLE = 10%

PULSE WIDTH

12

14

16

18

5003001 105 10030 5010

V

, SU

PPLY

VO

LTAG

E (V

OLT

S)C

C

Figure 5.9. Pulsed Supply Voltage versus Pulse Width

5 V

3 to 18 V, is quite immune to most overvoltage conditions.)But, can the TTL sustain 8 V or 10 V or 15 V and, if so, forhow long and for how many power cycles? Safe OperatingArea (SOA) of the TTL must be known. Unfortunately, thisinformation is not readily available and has to be generated.

Using the test circuit illustrated in Appendix III, a quasi–SOA curve for a typical TTL gate was generated (Figure 5.9).Knowing the overvoltage–time limit, the crowbar and fuseenergy ratings can be determined.

The two possible configurations are illustrated in Figure5.10, the first case shows the crowbar SCR across the

Figure 5.10. Typical Crowbar Configurations

*NEEDED IF SUPPLY NOT CURRENT LIMITED

(b). SCR Across Output of Regulator

*

vO

Vin

vOCoCin

D1F

(a). SCR Across Input of Regulator

VinSERIES

REGULATOR

REGULATOR

OVERVOLTAGESENSE

OVERVOLTAGESENSE



input of the regulator and the second, across the output. Forboth configurations, the overvoltage comparator senses theload voltage at the remote load terminals, particularly whenthe IR drop of the supply leads can be appreciable. As longas the output voltage is less than that of the comparatorreference, the crowbar SCR will be in an off state and drawno supply current. When an over–voltage condition occurs,the comparator will produce a gate trigger to the SCR, firing it,and thus clamping the regulator input, as in the first case —to the SCRs on–state drop of about 1 to 1.5 V, therebyprotecting the load.

Placing the crowbar across the input filter capacitors,although effectively clamping the output, has several disad-vantages.

1. There is a stress placed on the input rectifiers during thecrowbarring short circuit time before the line fuse opens,particularly under repeated operation.

2. Under low line conditions, the minimum short circuitcurrent can be of the same magnitude as the maximumprimary line current at high line, high load, making the properfuse selection a difficult choice.

3. The capacitive energy to be crowbarred (input andoutput capacitor through rectifier D1) can be high.

When the SCR crowbar and the fuse are placed in the dcload circuit, the above problems are minimized. If crowbar-ring occurs due to an external transient on the line and theregulator’s current limiting is working properly, the SCR onlyhas to crowbar the generally smaller output filter capacitorand sustain the limited regulator current.

If the series pass devices were to fail (short), even withcurrent limiting or foldback disabled, the crowbarred energywould generally be less than of the previous case. This is dueto the higher impedance of the shorted regulator (due toemitter sharing and current sensing resistors) relative to thatof rectifier D1.

Fuse selection is much easier as a fault will now give agreater percentage increase in dc load current than whenmeasuring transformer primary or secondary rms current.The disadvantage, however, of placing the fuse in the dc loadis that there is no protection for the input rectifier, capacitor,and transformer, if one of these components were to fail(short). Secondly, the one fuse must protect not only the loadand regulator, but also have adequate clearing time to protectthe SCR, a situation which is not always readily accom-plished. The input circuitry can be protected with the additionof a primary fuse or a circuit breaker.

HOW MUCH ENERGY HAS TO BECROWBARRED?

This is dictated by the power supply filter capacitors, whichare a function of output current. A survey of several linearpower supply manufacturers showed the output filter capaci-tor size to be from about 100 to 400 microfarads per amperewith about 200 µF/A being typical. A 30 A regulator mighttherefore have a 6000 µF output filter capacitor.

Additionally, the usually much larger input filter capacitorwill have to be dumped if the regulator were to short, althoughthat energy to be dissipated will be dependent on the totalresistance in the circuit between that capacitor and the SCRcrowbar.

The charge to be crowbarred would be

Q CV IT,

the energy,

E 12 CV2

and the peak surge current

ipkVCRT

When the SCR crowbars the capacitor, the currentwaveform will be similar to that of Figure 5.11, with the peaksurge current, ipk, being a function of the total impedance inthe circuit (Figure 5.12) and will thus be limited by theEquivalent Series Resistance (ESR) and inductance (ESL) ofthe capacitor plus the dynamic impedance of the SCR, anyexternal current limiting resistance, (and inductance) of theinterconnecting wires and circuit board conductors.

The ESR of computer grade capacitors, depending on thecapacitor size and working voltage, might vary from 10 to1000 milliohms (mΩ). Those used in this study were in the 25to 50 mΩ range.

The dynamic impedance of the SCR (the slope of theon–state voltage, on–state current curve), at high currents,might be in the 10 to 20 mΩ range. As an example, from theon–state characteristics of the MCR70, 35 A rms SCR, thedynamic impedance is

rdVFIF

(4.5 3.4)V

(300 200)A 1.1 V

100 A11 mΩ.

The interconnecting wire might offer an additional 5 mΩ(#20 solid copper wire 20 mΩ/ft) so that the total circuitresistance, without additional current limiting, might be in the40 to 70 mΩ range. The circuit inductance was consideredlow enough to ignore so far as ipk is concerned for thisexercise, being in hundreds of nanohenry range (ESL 3nH, L wire 500 nH/ft). However, di/dt will be affected by theinductance.

HOW MUCH ENERGY CAN THE CROWBAR SCRSUSTAIN?

There are several factors which contribute to possible SCRfailures or degradation — the peak surge current, di/dt, and ameasure of the device’s energy capability, I2t.

If the peak current and/or duration of the surge is large,destruction of the device due to excessive dissipation canoccur. Obviously, the ipk can be reduced by insertingadditional impedance in the crowbar path, at an increase indump time. However, this time, which is a measure of howlong the overvoltage is present, should be within the SOA ofthe load.


Figure 5.11. Typical SCR Crowbar Waveform

CROWBAR CURRENT TERMS

di/dt

I

t2.3 τ

10%

10%

50%

ipk

5 τ

tW

tW

I = 200 A/Div RS = 0MCR69 VC = 30 VC = 22,000 µF IGT = 200 mA

0

t = 0.5 ms/Div

0

t = 10 µs/Div

The energy stored in the capacitor being a constant for aparticular voltage would suggest that the I2t integral for anylimiting resistance is also a constant. In reality, this is not thecase as the thermal response of the device must be takeninto consideration. It has been shown that the dissipation

capability of a device varies as to the t for the first tens ofmilliseconds of the thermal response and, in effect, themeasure of a device’s energy capability would be closer to

i2 t . This effect is subsequently illustrated in the empiricallyderived ipk versus time derating curves being a non–linearfunction. However, for comparison with fuses, which arerated in I2t, the linear time base, “ t,” will be used.

The di/dt of the current surge pulse is also a criticalparameter and should not exceed the device’s ratings(typically about 200 A/µs for 50 A or less SCRs). Themagnitude of di/dt that the SCR can sustain is controlled bythe device construction and, to some extent, the gate driveconditions. When the SCR gate region is driven on,conduction across the junction starts in a small region andprogressively propagates across the total junction. Anodecurrent will initially be concentrated in this small conductingarea, causing high current densities which can degrade andultimately destroy the device. To minimize this di/dt effect, thegate should be turned on hard and fast such that the areaturned on is initially maximized. This can be accomplishedwith a gate current pulse approaching five times themaximum specified continuous gate current, Igt, and with a

fast rise time (< 1 µs). The gate current pulse width should begreater than the propagation time; a figure of 10 µs minimumshould satisfy most SCRs with average current ratings under50 A or so.

The wiring inductance alone is generally large enough tolimit the di/dt. Since most SCRs are good for over 100 A/µs,this effect is not too large a problem. However, if the di/dt isfound excessive, it can be reduced by placing an inductance

Figure 5.12. Circuit Elements Affecting SCRSurge Current

RW, LW: INTERCONNECTING WIRE IMPEDANCERS, LS: CURRENT LIMITING IMPEDANCE

ESL LS

RS

RW

ESR

LW



Figure 5.13

V

EXTERNALTRIGGER

5022,000 µF

100

DUT

H.P. 214APULSE

GENERATOR

in the loop; but, again, this increases the circuit’s responsetime to an overvoltage and the trade–off should be consid-ered.

Since many SCR applications are for 60 Hz line operation,the specified peak non–repetitive surge current ITSM andcircuit fusing I2t are based on 1/2 cycle (8.3 ms) conditions.For some SCRs, a derating curve based on up to 60 or 100cycles of operation is also published. This rating, however,does not relate to crowbar applications. To fully evaluate acrowbar system, the SCR must be characterized with thecapacitor dump exponential surge current pulse.

A simple test circuit for deriving this pulse is shown inFigure 5.13, whereby a capacitor is charged through alimiting resistor to the supply voltage, V, and then the chargeis dumped by the SCR device under test (DUT). The SCRgate pulse can be varied in magnitude, pulse width, and risetime to produce the various IGT conditions. An estimate of thecrowbar energy capability of the DUT is determined by firstdumping the capacitor charged to low voltage and thenprogressively increasing the voltage until the DUT fails. Thisis repeated for several devices to establish an average andminimum value of the failure points cluster.

This procedure was used to test several different SCRs ofwhich the following Table 5.4 describes several of thepertinent energy specifications and also the measuredcrowbar surge current at the point of device failure.

This one–shot destruct test was run with a gate current offive IGT(MAX) and a 22,000 µF capacitor whose ESRproduced the exponentially decaying current pulse about 1.5ms wide at its 10% point. Based on an appropriate derating,ten devices of each line where then successfully testedunder the following conditions.

Device VC ipk t

MCR68 12 V 250 A 1.5 ms

MCR69 30 V 800 A 1.5 ms

To determine the effect of gate drive on the SCRs, threedevices from each line were characterized at non–destructlevels using three different capacitors (200, 6,000, and22,000 µF), three different capacitor voltages (10, 20, and30 V), and three different gate drives (IGT(MAX), 5IGT(MAX), and a ramp IGT(MAX) with a di/dt of about 1mA/µs). Due to its energy limitations, the MCR68 was testedwith only 10 V across the larger capacitors.

The slow ramp, IGT, was used to simulate overvoltagesense applications where the gate trigger rise time can beslow such as with a coupling zener diode.

No difference in SCR current characteristics were notedwith the different gate current drive conditions; the peakcurrents were a function of capacitor voltage and circuitimpedance, the fall times related to RTC, and the rise times,tr, and di/dt, were more circuit dependent (wiring inductance)and less device dependent (SCR turn–on time, ton). Sincethe wiring inductance limits, tr, the effect of various IGTs wasmasked, resulting in virtually identical waveforms.

The derated surge current, derived from a single (or lownumber) pulse test, does not truly reflect what a power supplycrowbar SCR might have to see over the life of the supply.Life testing over many cycles have to be performed; thus, thecircuit described in Appendix IV was developed. This life test

Table 5.4. Specified and Measured Current Characteristics of Three SCRs

Device Case

Maximum Specified ValuesMeasured CrowbarSurge Current I pk

Device CaseIT(rms)

(A)IT(AV)

(A)ITSM*

(A)I2t

(A2s)IGT(Max)

(mA)Min(A)

Max(A)

Ave(A)

MCR68 TO–220 12 8 100 40 30 380 750 480

MCR69 TO–220 25 16 300 375 30 1050 1250 1100

* ITSM = Peak Non–Repetitive Surge Current, 1/2 cycle sine wave, 8.3 ms.


Figure 5.14(a). Peak Surge Current versus Pulse Width

tW, BASE PULSE WIDTH (ms)

MCR69

0.5 1000.1 5 10

100

300

1000

3000

1

30

50

MCR68

I ,

PEA

K C

UR

REN

T (A

MPS

)pk

tW5 TC

C = 8400 µF TA = 25°CESR ≈ 25 mΩ N = 2000 PULSESVC 60 V f = 3 PULSES/MIN.

Ipk

fixture can simultaneously test ten SCRs under variouscrowbar energy and gate drive conditions.

Each of the illustrated SCRs of Figure 5.14(a) were testedwith as many as four limiting resistors (0, 50, 100, and 240mΩ) and run for 1000 cycles at a nominal energy level. If nofailures occurred, the peak current was progressively in-creased until a failure(s) resulted. Then the current wasreduced by 10% and ten new devices were tested for 2000cycles (about six hours at 350 cycles/hour). If this test provedsuccessful, the data was further derated by 20% and plottedas shown on log–log paper with a slope of – 1/4. This

theoretical slope, due to the I2 t one–dimensional heat–flowrelationship (see Appendix VI), closely follows the empiricalresults. Of particular interest is that although the peak currentincreases with decreasing time, as expected, the I2t actuallydecreases.

Figure 5.14(b) shows the effect of elevated ambienttemperature on the peak current capability of the illustratedSCRs.

FUSE CHARACTERISTICSSCRs, like rectifiers, are generally rated in terms of

average forward current, IT(AV), due to their half–waveoperation. Additionally, an rms forward current, IT(rms), a peakforward surge current, ITSM, and a circuit–fusing energy limit,I2t, may be shown. However, these specifications, which arebased one–half cycle 60 Hz operation, are not related to thecrowbar current pulse and some means must be establishedto define their relationship. Also, fuses which must ultimatelymatch the SCR and the load, are rated in rms currents.

The crowbar energy curves are based on an exponentiallydecaying surge current waveform. This can be converted* toIrms by the equation.

Irms 0.316 ipk

which now allows relating the SCR to the fuse.

*See Appendix V

(b). Peak Surge Current versus Ambient Temperature

TC, AMBIENT TEMPERATURE (°C)

0.20

1

0.8

0.6

0.4

125100755025

N = 2000 PULSES

NO

RM

ALIZ

ED P

EAK

SUR

GE

CU

RR

ENT

The logic load has its own overvoltage SOA as a functionof time (Figure 5.9). The crowbar SCR must clamp theovervoltage within a specified time, and still be within its ownenergy rating; thus, the series–limiting resistance, RS, in thecrowbar path must satisfy both the load and SCR energylimitations. The overvoltage response time is set by the totallimitations. The overvoltage response time is set by the totallimiting resistance and dumped capacitor(s) time constant.Since the SOA of the TTL used in this exercise was derivedby a rectangular overvoltage pulse (in effect, over–energy),the energy equivalent of the real–world exponentially fallingvoltage waveform must be made. An approximation can bemade by using an equivalent rectangular pulse of 0.7 timesthe peak power and 0.7 times the base time.

Once an overvoltage is detected and the crowbar isenabled, in addition to sustaining the peak current, the SCRmust handle the regulator short–circuit current for the time ittakes to open the fuse.

Thus, all three elements are tied together — the load cantake just so much overvoltage (over–energy) and thecrowbar SCR must repeatedly sustain for the life of theequipment an rms equivalent current pulse that lasts forthe fuse response time.

It would seem that the matching of the fuse to the SCRwould be straightforward — simply ensure that the fuse rmscurrent rating never exceed the SCR rms current rating(Figure 5.15), but still be sufficient to handle steady–stateand normal overload currents. The more exact relationshipwould involve the energy dissipated in the system ∫ I2Rdt,which on a comparative basis, can be reduced to I2t. Thus,the “let–through” I2t of the fuse should not exceed I2tcapability of the SCR under all operating conditions. Theseconditions are many, consisting of “available fault current,”power factor of the load, supply voltage, supply frequency,ambient temperature, and various fuse factors affecting theI2t.

There has been much detailed information published onfuse characteristics and, rather than repeat the text whichwould take many pages, the reader is referred to those



sources. Instead, the fuse basics will be defined and anexample of matching the fuse to the SCR will be shown.

In addition to interrupting high current, the fuse should limitthe current, thermal energy, and overvoltage due to the highcurrent. Figure 5.16 illustrates the condition of the fuse at themoment the over–current starts. The peak let–throughcurrent can be assumed triangular in shape for a first–orderapproximation, lasting for the clearing time of the fuse. Thistime consists of the melting or pre–arcing time and the arcingtime. The melting time is an inverse function of over–currentand, at the time that the fuse element is opened, an arc willbe formed causing the peak arc voltage. This arc voltage isboth fuse and circuit dependent and under certain conditionscan exceed the peak line voltage, a condition the user shouldensure does not overstress the electronics.

The available short–circuit current is the maximum currentthe circuit is capable of delivering and is generally limited bythe input transformer copper loss and reactance when thecrowbar SCR is placed at the input to the regulator or theregulator current limiting when placed at the output. For afuse to safely protect the circuit, it should limit the peaklet–through current and clear the fault in a short time, usuallyless than 10 ms.

Fuse manufacturers publish several curves for character-izing their products. The current–time plot, which describescurrent versus melting time (minimum time being 10 ms), isused in general industrial applications, but is not adequate forprotecting semiconductors where the clearing time must bein the subcycle range. Where protection is required fornormal multicycle overloads, this curve is useful.

Two other useful curves, the total clearing I2t characteristicand the peak let–through current IPLT characteristic, areillustrated in Figures 5.17 and 5.18 respectively. Somevendors also show total clearing time curves (overlayed onFigure 5.17 as dotted lines) which then allows directcomparison with the SCR energy limits. When this clearingtime information is not shown, then the designer shoulddetermine the IPLT and I2t from the respective curves andthen solve for the clearing time from the approximateequation relating these two parameters. Assuming a

Figure 5.15. Time–Current Characteristic Curvesof a Crowbar SCR and a Fuse

TIME t (LOG)

10 ms

LIMITED BY FUSE

Irms (max)

FUSECHARACTERISTIC

SCR CHARACTERISTICS

4 HRS

CU

RR

ENT

I

(L

OG

)rm

s

Figure 5.16. Typical Fuse Timing Waveforms DuringShort Circuit

PEAK ARC VOLTAGE

INSTANT OF SHORT

SUPPLYVOLTAGE

PEAK ASYMMETRICALFAULT CURRENT

CLEARING TIME

FUSE VOLTAGE

ARCING TIMEMELTING TIME

PEAK FUSE CURRENT

IPLT

FUSE CURRENT

triangular waveform for IPLT, the total clearing time, tc, wouldthen approximately be

tc ≈ 3 I2tIPLT2

Once tc of the fuse is known, the comparison with the SCRcan readily be made. As long as the I2t of the fuse is less thanthe I2t of the SCR, the SCR is protected. It should be pointedout that these calculations are predicated on a known valueof available fault current. By inspection of Figure 5.18, it canbe seen that IPLT can vary greatly with available fault current,which could have a marked effect on the degree ofprotection. Also, the illustrated curves are for particularoperating conditions; the curves will vary somewhat withapplied voltage and frequency, initial loading, load powerfactor, and ambient temperature. Therefore, the reader isreferred to the manufacturer’s data sheet in those caseswhere extrapolation will be required for other operatingconditions. The final proof is obtained by testing the fuse inthe actual circuit under worst–case conditions.

CROWBAR EXAMPLETo illustrate the proper matching of the crowbar SCR to the

load and the fuse, consider the following example. A 50 ATTL load, powered by a 60 A current limited series regulator,has to be protected from transients on the supply bus bycrowbarring the regulator output. The output filter capacitor of10,000 µF (200 µF/A) contributes most of the energy to becrowbarred (the input capacitor is current limited by theregulator). The transients can reach 18 V for periods 100 ms.

Referring to Figure 5.9, it is seen that this transientexceeds the empirically derived SOA. To ensure safeoperation, the overvoltage transient must be crowbarredwithin 5 ms. Since the TTL SOA is based on a rectangularpower pulse even though plotted in terms of voltage, theequivalent crowbarred energy pulse should also be derived.Thus, the exponentially decaying voltage waveform shouldbe multiplied by the exponentially decaying current to result


Figure 5.17. Maximum Clearing I 2t Characteristicsfor 10 to 20 A Fuses

SF 13X SERIES130 Vrms, 60 HzTA = 25°CPOWER FACTOR 15%

4

10

4

102

2 ms 1.5 ms TOTAL CLEARING TIME

10 A

105

5 ms

4 4102 4103 104

AVAILABLE FAULT CURRENT (SYMMETRICAL rms AMPS)

15 A

10

20 A

4

4

1

LET-

THR

OU

GH

I t

(A S

)2

2

in an energy waveform proportional to e–2x. The rectangularequivalent will have to be determined and then comparedwith the TTL SOA. However, for simplicity, by using thecrowbarred exponential waveform, a conservative rating willresult.

To protect the SCR, a fuse must be chosen that will openbefore the SCR’s I2t is exceeded, the current being theregulator limiting current which will also be the available faultcurrent to the fuse.

The fuse could be eliminated by using a 60 A SCR, but thecost versus convenience trade–off of not replacing the fuse isnot warranted for this example. A second fuse or circuitbreaker will protect the rectifiers and regulator for internal

faults (shorts), but its selection, which is based on therespective energy limits of those components, is not part ofthis exercise.

If a crowbar discharge time of 3 ms were chosen, it wouldnot only be within the rectangular pulsed SOA, but also bewell within the derived equivalent rectangular model of theexponential waveform. It would also require about 1.3 timeconstants for the overvoltage to decay from 18 V to 5 V; thus,the RC time constant would be 3 ms/1.3 or 2.3 ms.

The limiting resistance, RS would simply be

RS2.3 ms

10, 000 F 0.23 0.2

Figure 5.18. Peak Let–Through Current versus FaultCurrent for 10 to 20 A Fuses

15 A

AVAILABLE FAULT CURRENT (SYMMETRICAL rms AMPS)

MAX PEAK AVAILABLE CURRENT(2.35 x SYMMETRICAL rms AMPERES)

10 A

20 A

1054 4102 4103 10410 410

4

102

4

103

INST

ANTA

NEO

US

PEAK

LET

-TH

RO

UG

H C

UR

REN

T (A

MPS

)

SF 13X SERIES130 Vrms, 60 HzPOWER FACTOR 15%



Since the capacitor quickly charges up to the over–voltagesVCC1 of 18 V, the peak capacitor discharge current would be

Ipk VCC1

RS 18 V

0.2 90 A

The rms current equivalent for this exponentially decayingpulse would be

Irms 0.316 Ipk 0.316(90) 28.4 A rms

Now referring to the SCR peak current energy curves(Figure 5.14), it is seen that the MCR68 can sustain 210 Apeak for a base time of 3 ms. This 12 A SCR must alsosustain the 60 A regulator limited current for the time requiredto open the fuse. The MCR68 has a specified peak forwardsurge current rating of 100 A (1/2 cycle, sine wave, 60 Hz,non–repetitive) and a circuit fusing rating of 40 A2s.

The non–repetitive rating implies that the device cansustain 100 occurrences of this 1/2 cycle surge over the lifeof the device; the SCR crowbar surge current curves werebased on 2000 cycles.

For the 3 ms time frame, the I12t1 for the exponentialwaveform is

I12t1 (28.4 A)2(3 ms) 2.4 A2s

Assuming that the fuse will open within 6 ms, the approxi-mate energy that the SCR must sustain would be 60 A for anadditional 3 ms. By superposition, this would amount to

I22t2 (60 A)2(6 ms) 21.6 A2s

which , when added to the exponential energy, would result in24 A2.

The MCR68 has a 40 A2s rating based on a 1/2 cycle of8.3 ms. Due to the one–dimensional heat flow in the device,the energy capability is not linearly related to time, but varies

as to the t . Therefore, with a 6 ms 1/2–cycle sine wave, the40 A2t rating would now decrease to approximately (seeAppendix VI for derivation).

I22t2 I1

2t1t2t112

40 A2s 6 ms8.3 ms

12

34 A2s

Although the 1/2 cycle extrapolated rating is greater than theactual crowbar energy, it is only characterized for 100 cyclesof operation.

To ensure 2000 cycles of operation, at a somewhat highercost, the 25 A MCR69 could be chosen. Its exponential peakcurrent capability, at 3 ms, is about 560 A and has a specifiedITSM of 300 A for 8.3 ms. The I2t rating is not specified, butcan be calculated from the equation

I2t (ITSM)2

2t

(300 A)2

2(8.3 ms) 375 A2s

Extrapolating to 6 ms results in about 318 A2s, an I2t ratingmuch greater than the circuit 24 A2s value.

The circuit designer can then make the cost/performancetrade–offs.

All of these ratings are predicated on the fuse operatingwithin 6 ms.

With an available fault current of 60 A, Figure 5.17 showsthat a 10 A (SF13X series) fuse will have a let–through I2t ofabout 10 A2s and a total clearing time of about 6 ms,satisfying the SCR requirements, that is,

I2t fuse I2t SCRtc 6 ms

Figure 5.18 illustrates that for the same conditions,instantaneous peak let–through current of about 70 A wouldresult. For fuse manufacturers that don’t show the clearingtime information, the approximate time can be calculatedfrom the triangular model, as follows

tc 3 I2t

IPLT2

3(10)

(70)2 6.1 ms

The fuse is now matched to the SCR which is matched to thelogic load. Other types of loads can be similarly matched, ifthe load energy characteristics are known.

CHARACTERIZING SWITCHES AS LINE–TYPEMODULATORS

In the past, hydrogen thyratrons have been used exten-sively as discharge switches for line type modulators. Ingeneral, such devices have been highly satisfactory from anelectrical performance standpoint, but they have some majordrawbacks including relatively large size and weight, lowefficiency (due to filament power requirements), and short lifeexpectancy compared with semiconductor devices, now canbe eliminated through the use of silicon controlled rectifiers.

A line type modulator is a modulator whose output–pulsecharacteristics are determined by a lumped–constant trans-mission line (pulse forming network) and by the proper matchof the line impedance (PFN) to the load impedance.

A switch for this type modulator should only initiateconduction and should have no effect on pulse characteris-tics. This is in contrast to a hard switch modulator whereoutput pulse characteristics are determined by the “hard”relationship of grid (base) control of conduction through avacuum tube (transistor) switch.

Referring to the schematic (Figure 5.25), when the powersupply is first turned on, no charge exists in the PFN, andenergy is transferred from the power supply to the PFN viathe resonant circuit comprising the charging choke and PFNcapacitors. At the time that the voltage across the PFNcapacitors reaches twice the power supply voltage, currentthrough the charging choke tries to reverse and the powersupply is disconnected due to the back biased impedance ofthe hold–off diode. If we assume this diode to be perfect, theenergy remains stored in the PFN until the discharge switchis triggered to its on state. When this occurs, assuming thatthe pulse transformer has been designed to match the loadimpedance to the PFN impedance, all energy stored in the


PFN reactance will be transferred to the load if we neglectswitch losses. Upon completion of the transfer of energy theswitch must return to its off condition before allowing transferof energy once again from the power supply to the PFNstorage element.

OPTIMUM SWITCH CHARACTERISTICSFORWARD BREAKOVER VOLTAGE

Device manufacturers normally apply the variable–ampli-tude output of a half–wave rectifier across the SCR. Thus,forward voltage is applied to the device for only a half cycleand the rated voltage is applied only as an ac peak. Whilethis produces a satisfactory rating for ac applications, it doesnot hold for dc.

An estimated 90% of devices tested for minimum break-over voltage (VBO) in a dc circuit will not meet the data sheetperformance specifications. A switch designed for the pulsemodulator application should therefore specify a minimumcontinuous forward breakover voltage at rated maximumleakage current for maximum device temperatures.

THE OFF SWITCHThe maximum forward leakage current of the SCR must be

limited to a low value at maximum device temperature.During the period of device nonconduction it is desired thatthe switch offer an off impedance in the range of megohms tohundreds of megohms. This is required for two reasons: (1)to prevent diminishing the efficiency of recharge by aneffective shunt path across the PFN, and (2) to prevent thebleeding off of PFN charge during the interpulse period. Thissecond factor is especially important in the design of radartansponders wherein the period between interrogations isvariable. Change of the PFN voltage during the interpulseperiod could result in frequency shift, pulse instabilities, andloss of power from the transmitter being modulated.

THE ON SWITCHAt present, SCR design is more limited in the achievable

maximum forward sustaining voltage than in the current thatthe device will conduct. For this reason modulators utilizingSCRs can be operated at lower impedance levels thancomparable thyratron circuits of yesterday. It is not uncom-mon for the characteristic impedance of the pulse formingnetwork to be in the order of 5 to 10 ohms or less. Operatingthe SCR at higher current to switch the same equivalentpulse power as a thyratron requires the SCR on impedanceto be much lower so that the I2R loss is a reasonable value, inorder to maintain circuit efficiency. Low switch loss, more-over, is mandatory because internal power dissipation can bedirectly translated into junction–temperature–rise andassociated leakage current increase which, if excessive,could result in thermal runaway.

TURN–ON TIMEIn radar circuits the pulse–power handling capability of an

SCR, rather than the normally specified average–powercapability, is of primary importance.

For short pulses at high PRFs the major portion ofsemiconductor dissipation occurs during the initial turn–onduring the time that the anode rises from its forward leakagevalue to its maximum value. It is necessary, therefore, thatturn–on time be as short as possible to prevent excessivepower dissipation.

The function of radar is to provide distance informationmeasured as a function of time. It is important, therefore, thatany delay introduced by a component be fixed in relation tosome variable parameter such as signal strength or tempera-ture. For radar pulse modulator applications, a minimal delayvariation versus temperature is required and any suchvariation must be repetitive from SCR to SCR, in productionlots, so that adequate circuit compensation may be provided.

PULSE GATE CURRENT TO FIREThe time of delay, the time of rise, and the delay variation

versus temperature associated with SCR turn–on are func-tions of the gate triggering current available and the triggerpulse duration. In order to predict pulse circuit operation ofthe SCR, the pulse gate current required to turn the device onwhen switching the low–impedance modulator should bespecified and the limits of turn–on–time variation for thespecified pulse trigger current and collector load should begiven at the high and low operating temperature extremes.

RECOVERY TIMEAfter the cessation of forward conducting current in the on

device, a time of SCR circuit isolation must be provided toallow the semiconductor to return to its off state. Recoverytime cannot be given as an independent parameter of deviceoperation, but must include factors as determined by theexternal circuit, such as: (1) pulse current and rate of decay;(2) availability of an inverse voltage immediately followingpulse–current conduction; (3) level of base bias followingpulse current conduction; (4) rate of rise of reapplied positivevoltage and its amplitude in relation to SCR breakovervoltage; and (5) maximum circuit ambient temperature.

In the reverse direction the controlled rectifier behaves likea conventional silicon diode. Under worst circuit conditions, ifan inverse voltage is generated through the existence of aload short circuit, the current available will be limited only bythe impedance of the pulse forming network and SCRinverse characteristics. The reverse current is able to sweepout some of the carriers from the SCR junctions. Intentionaldesign of the load impedance to something less than thenetwork impedance allows development of an inversevoltage across the SCR immediately after pulse conduction,



enhancing switch turn–off time. Careful use of a fast clampdiode in series with a fast zener diode, the two in shuntacross the SCR, allows application of a safe value ofcircuit–inverse–voltage without preventing the initial usefulreverse current. Availability of a negative base–bias followingpulse current conduction provides a similar enhancement ofswitch turn–off time.

If removal of carriers from the SCR junction enables afaster switch recovery time, then, conversely, operation of theSCR at high temperatures with large forward currents andwith slow rate of current decay all increase device recoverytime.

HOLDING CURRENTOne of the anomalies that exist in the design of a pulse

SCR is the requirement for a high holding current. This needcan be determined by examining the isolation componentthat disconnects the power supply from the discharge circuitduring the time that PFN energy is being transferred to thetransmitter and during the recovery time of the dischargeswitch. An inductance resonating with the PFN capacitanceat twice the time of recharge is normally used for powersupply isolation. Resonant charging restricts the initial flow ofcurrent from the power supply, thereby maximizing the timeat which power supply current flow will exceed the holdingcurrent of the SCR. If the PFN recharge current from thepower supply exceeds the holding current of the SCR beforeit has recovered, the SCR will again conduct without theapplication of a trigger pulse. As a result continuousconduction occurs from the power supply through the lowimpedance path of the charging choke and on switch. Thislock–on condition can completely disable the equipmentemploying the SCR switch.

The charging current passed by the inductance is given as(the PFN inductance is considered negligible):

ic(t) Ebb Vn(0)

LcCn

cosTr2t

2 LcCn

sinTr

2 LcCn

Where

Ebb = power supply voltageVn(0) = 0 volts if the PFN employs a clamp diode or is

matched to the load

Tr = time of resonant recharge and is usually equal to1

PRFLc = value of charging inductanceCn = value of total PFN capacity

For a given radar pulse modulator design, the values ofpower supply voltage, time of resonant recharge, chargingchoke inductance, and PFN capacitance are established. Ifthe time (t) represents the recovery time of the SCR beingused as the discharge switch, ic then represents theminimum value of holding current required by the SCR toprevent power supply lock–on. Conversely, if the modulatordesign is about an existing SCR where holding current,recovery time, and forward breakover voltage are known, thecharge parameters can be derived by rewriting the aboveformula as follows:

iH VBO Vn(0)

LcCn

cosTr2(recovery time)

2 Lc Cn

sinTr

2 Lc Cn

The designer may find that for the chosen SCR the desired

characteristics of modulator pulse width and pulse repetitionfrequency are not obtainable.

One means of increasing the effective holding current of anSCR is for the semiconductor to exhibit some turn–off gaincharacteristic for the residual current flow at the end of themodulator pulse. The circuit designer then can provideturn–off base current, making the SCR more effective as apulse circuit element.

THE SCR AS A UNIDIRECTIONAL SWITCHWhen triggered to its on state, the SCR, like the hydrogen

thyratron, is capable of conducting current in one direction. Aload short circuit could result in an inverse voltage across theSCR due to the reflection of voltage from the pulse formingnetwork. The circuit designer may wish to provide anintentional load–to–PFN mismatch such that some inversevoltage is generated across the SCR to enhance its turn–offcharacteristics. Nevertheless, since the normal circuit ap-plication is unidirectional, the semiconductor device designercould take advantage of this fact in restricting the inverse–voltage rating that the SCR must withstand. The circuitdesigner, in turn, can accommodate this lack of peak–in-verse–voltage rating by use of a suitable diode clamp acrossthe PFN or across the SCR.


SCRs TESTS FOR PULSE CIRCUIT APPLICATION

The suitability for pulse circuit applications of SCRs notspecifically characterized for such purposes can be deter-mined from measurements carried out with relatively simpletest circuits under controlled conditions. Applicable testcircuits and procedures are outlined in the following section.

FORWARD BLOCKING VOLTAGE AND LEAKAGECURRENT

Mount the SCRs to a heat sink and connect the units to betested as shown in Figure 5.21. Place the assembly in anoven and stabilize at maximum SCR rated temperature. Turnon the power supply and raise the voltage to rated VBO. Allowunits to remain with the voltage applied for minimum of fourhours. At the end of the temperature soak, determine if anyunits exhibit thermal runaway by checking for blown fuses(without removing the power). Reject any units which haveblown circuit fuses. The forward leakage current, ILF, of theremaining units may be calculated after measuring thevoltage VL, across resistor R2. Any units with a leakagecurrent greater than manufacturer’s rating should be re-jected.

Figure 5.20. Vertical Set to 4 cm, Horizontal 0.2 µs/cm.Detected RF Magnetron Pulse

TURN–ON TIME, VARIATION AND ONIMPEDANCE

This circuit assumes that the pulse gate current required toswitch a given modulator load current is specified by themanufacturer or that the designer is able to specify theoperating conditions. Typical operating values might be:

Time of trigger pulse t = 1 µsPulse gate current IG = 200 mAForward blocking voltage VBO = 400 VLoad current ILoad = 30 A

To measure turn–on time using a Tektronix 545 oscillo-scope (or equivalent) with a dual trace type CA plug–in,connect probes of Channels A and B to Test Points A and B.Place the Mode selector switch in the Added Algebraicallyposition and the Channel B Polarity switch in the Invertedposition. Adjust the HR212A pulse generator to give apositive pulse 1 µs wide (100 pps) as viewed at Test Point A.Adjust the amplitude of the “added” voltage across the100–ohm base resistor for the specified pulse gate current(200 mA in this example).

Switch the Mode selector knob to the alternate position.Connect Channel A to Test Point D. Leave the oscilloscopeprobe, Channel B, at Test Point B, thereby displaying theinput trigger waveform. Measure the time between the 50percent voltage amplitudes of the two waveforms. This is theTurn–On Time (tD + tR).

To measure turn–on time versus temperature, place thedevice to be tested on a suitable heat sink and place theassembly in a temperature chamber. Stabilize the chamberat minimum rated (cold) temperature. Repeat the abovemeasurements. Raise the chamber temperature to maximumrated (hot) temperature and stabilize. Repeat the measure-ments above.

To measure the turn–on impedance for the specifiedcurrent load, the on impedance can be measured as an SCRforward voltage drop. The point in time of measurement shall

RESISTOR R1 IS USED ONLY IF MANUFACTURER CALLS FORBIAS RESISTOR BETWEEN GATE AND CATHODE. RESISTORR2 CAN HAVE ANY SMALL VALUE WHICH, WHEN MULTIPLIED

BY MAXIMUM ALLOWABLE LEAKAGE CURRENT, WILLPROVIDE A CONVENIENT READING OF VOLTAGE VL.

Figure 5.21. Test Setup for SCR Forward BlockingVoltage and Leakage Current Measurements

ADDITIONAL UNITSMAY BE

CONNECTED INPARALLEL

R1

GATE

ANODE

–

REGULATEDPOWERSUPPLY

+

1/16 A

R2VL

CATHODE



Figure 5.22. Suggested Test Circuit for SCR “On”Measurements

VBO2

HP212A

Bt = AS SPECIFIED

VBOE = VBO

C

100k

0 V

IC = AS SPECIFIED t = AS SPECIFIED

D

WHERE ILOAD =AS SPECIFIED

zO = R100

A

1:1

51

Von

12

RVBO

2 : 1LOAD

be half the output pulse width. For a 1 µs output pulse, themeasurement procedure would be:

Connect the oscilloscope probe, Channel B, to Point Dshown in Figure 5.22. Use the oscilloscope controls Time/CMand Multiplier to a setting of 0.5 µs per centimeter or faster.With the Amplitude Control set to view 100 volts percentimeter (to prevent amplifier overloading) measure theamplitude of the voltage drop, VF, across the SCR 0.5 µs afterthe PFN voltage waveform has dropped to half amplitude. Itmay be necessary to check ground reference several timesduring this test to provide the needed accuracy of measure-ment.

HOLDING CURRENTThe SCR holding current can be measured with or without

a gate turn–off current, according to the position of switch S2.The Motorola Trigger Pulse Generator is a transistor circuitcapable of generating a 1.5 µs turn–on pulse followed by avariable–duration turn–off pulse. Measurements should be

made at the maximum expected temperature of operation.Resistor R1 should be chosen to allow an initial magnitude ofcurrent flow at the device pulse current rating.

To measure holding current, connect the SCRs under testas illustrated in Figure 5.23. Place SCRs in oven andstabilize at maximum expected operating temperature. Viewthe waveform across R1 by connecting the oscilloscopeprobe (Tektronix 2465) Channel A to Point A, and Channel Bto Point B. Place the Mode Selector switch in the AddedAlgebraically position. Place the Polarity swich of Channel Bin the Inverted position. Adjust both Volts/CM switches to thesame scale factor, making sure that each Variable knob is inits Calibrated position. Adjust pulse generator for a positivepulse, 1 µs wide, and 1,000 pps pulse repetition frequency.Adjust power supply voltage to rated VBO. Adjust input pulseamplitude until unit fully triggers. Measure amplitude ofvoltage drop across R1, V(A – B), and calculate holdingcurrent in mA from the equation

mAV(A B)

R1

VBO100 k

Any unit which turns on but does not turn off has a holdingcurrent of less than

VBO V

100 k

The approximate voltage setting to view the amplitude ofthe holding current will be 10 or 20 volts per centimeter. Theapproximate sweep speed will be 2 to 5 µs per centimeter.These settings will, of course, vary, depending upon theholding current of the unit under test.

SCR recovery time is greatly dependent upon the circuitin which the device is used. However, any test of SCRrecovery time should suffice to compare devices of variousmanufacturers, as long as the test procedure is standard-ized. Further evaluation of the selected devices could bemade in an actual modulator circuit tester whereintechniques conducive to SCR turn–off are used.

Figure 5.23. Test Setup for Measuring Holding Current

MOTOROLATRIGGER

PULSEGEN

HARRISON800 AP.S.

NOTE: ADDITIONAL UNITS MAY BE TESTED BY SWITCHING THEANODE AND GATE CONNECTIONS TO SIMILARLYMOUNTED SCRs. SHORT LEAD LENGTHS ARE DESIRABLE.

+ 12

IH

VOLTAGE LEVEL FROMWHICH TO CALCULATE

HOLDING CURRENT

TIME AT WHICH TO MEASURE IN

2 W100k

–

+

B

R1

S1A


C17500 fd.

CATHODE

GATE

ANODE

S2 S1B

R2

HP212PULSE GEN.

A

– 12R3

R451 Ω


Figure 5.24. Modulator Circuit for SCR Tests

HARRISON800 A

HOLD OFFDIODE

CATHODE

MOTOROLATRIGGER

PULSEGEN

CANODE

R

GATEHP212APULSEGEN

zO RLOAD

PFN

B


A

CHARGINGCHOKE

RLOAD

+ 12 – 12

The above circuit setup shown in Figures 5.24 and 5.25 canbe employed for such tests. A slight load to PFN mismatch iscalled for to generate an inverse voltage across the SCR atthe termination of the output pulse. An SCR gate turn–offpulse is used. The recharge component is a charging choke,providing optimized conditions of reapplied voltage to thePFN (and across the SCR). Adequate heat sinking of the

SCR should be provided.

PARALLEL CONNECTED SCRs

When an application requires current capability in excessof a single economical SCR, it can be worthwhile to considerparalleling two or more devices. To help determine if two or

Figure 5.25. Radar Modulator, Resonant Line Type

TRIGGERIN

SIMPLIFIED SCHEMATIC

SCR

LOAD

HOLD OFF DIODECHARGING CHOKE

PFN

BLOCK DIAGRAM;

DISCSWITCH

ENERGYSTORE

POWERSUPPLY

CHARGEIMPEDANCE LOAD

PULSE TRANSFORMER

Es



more SCRs in parallel are more cost effective than one highcurrent SCR, some of the advantages and disadvantagesare listed for parallel devices.

Advantages1. Less expensive to purchase2. Less expensive to mount3. Less expensive to replace, in case of failure4. Ease of mounting5. Ease of isolation from sink

Disadvantages1. Increased SCR count2. Selected or matched devices3. Increased component count4. Greater R & D effort

There are several factors to keep in mind in paralleling andmany are pertinent for single SCR operations as well.

GATE DRIVEThe required gate current (IGT) amplitude can vary greatly

and can depend upon SCR type and load being switched. Asa general rule for parallel SCRs, IGT should be at least two orthree times the IGT(MAX) specification on the data sheet andideally close to, but never exceeding, the maximum specifiedgate power dissipation or peak current. Adequate gatecurrent is necessary for rapid turn–on of all the parallel SCRsand to ensure simultaneous turn–on without excessivecurrent crowding across any of the individual die. The risetime of the gate drive pulse should be fast, ideally 100 ns.Each gate should be driven from a good current source andthrough its own resistor, even if transformer drive is used.Gate pulse width requirements vary but should be ofsufficient width to ensure simultaneous turn–on and last wellbeyond the turn–on delay of the slowest device, as well asbeyond the time required for latching of all devices. Ideally,gate current would flow for the entire conduction period toensure latching under all operating conditions.

With low voltage switching, which includes conductionangles near 180° and near zero degrees, the gate driverequirements can be more critical and special emphasis maybe required of gate pulse amplitude and width.

PARAMETER MATCHINGFor reliable current sharing with parallel SCRs, there are

certain device parameters that should be matched or heldwithin close tolerances. The degree of matching requiredvaries and can be affected by type of load (resistive,inductive, incandescent lamp or phase controlled loads)being switched.

The most common device parameters that can effectcurrent sharing are:

1. )td — turn–on delay time 2. ) tr — turn–on rise time of anode current 3. )

VA(MIN) — minimum anode voltage at which devicewill turn on 4. ) Static on–state voltage and current 5. ) IL — Latching current

The four parameters shown in Table 5.6 were measuredwith a curve tracer and are:

IL, latching current; VTM, on–state voltage; IGT and VGT, minimum gate current and voltage for turn on.

Of the four parameters, IL and VTM can greatly affect currentsharing.

The latching current of each SCR is important at turn–on toensure each device turns on and will stay on for the entireconduction period. On–state voltage determines how well theSCRs share current when cathode ballasting is not used.

Table 5.5 gives turn–on delay time (td) and turn–on risetime (tr) of the anode–cathode voltage and the minimumforward anode voltage for turn–on. These parameters weremeasured in the circuits shown in Figures 5.28 and 5.29.One SCR at a time was used in the circuit shown in Figure5.28.

Turn–on delay on twenty–five SCRs was measured (onlyten are shown in Table 5.5) and they could be from one ormore production lots. The variation in td was slight andranged from 35 to 44 ns but could vary considerably on otherproduction lots and this possible variation in td would have tobe considered in a parallel application.

Waveforms for minimum forward anode voltage for turn–onare shown in Figure 5.26. The trailing edge of the gatecurrent pulse is phase delayed (R3) so that the SCR is notturned on. The width of the gate current pulse is nowincreased (R5) until the SCR turns on and the forward anodevoltage switches to the on–state at about 0.73 V. This is theminimum voltage at which this SCR will turn on with the circuitconditions shown in Figure 5.28.

For dynamic turn–on current sharing, td, tr and VA(MIN) arevery important. As an example, with a high wattage incan-descent lamp load, it is very important that the inrush currentof the cold filament be equally shared by the parallel SCRs.The minimum anode voltage at which a device turns on isalso very important. If one of the parallel devices turns on

Table 5.5. MCR12D Turn–On Delay, Rise Time andMinimum Forward Anode Voltage For Turn–On

Device

Turn–On Delay and Rise TimeOff–State Voltage = 8 V Peak

RL = 10 Ohms, I A 6.5 A PeakIG = 100 mA (PW = 100 µs)

Conduction Angle 90 Degrees

Minimum AnodeVoltage For

Turn–On Off–StateVoltage = 4 V Peak

RL = 0.5 OhmIA = 5A

IG = 100 mA

td(ns) tr(µs) (Volts)

12345678910

35384544444338383837

0.800.95

11

0.900.851.301.25

10.82

0.700.810.750.750.750.750.750.700.750.70


Figure 5.26. Minimum Anode Voltage For Turn–OnOff–State Voltage = 4 V Peak, R L = 0.5 Ohm,

IA ≈ 5 A, IG = 75 mA

OFF–STATE

ANODE–CATHODEVOLTAGE 0.2 V/Div

ON–STATE

00

100 µs/Div

1 mA/DivIG = 50

before the other devices and its on–state voltage is lowerthan the required minimum anode voltage for turn–on of theunfired devices, they therefore cannot turn on. This wouldoverload the device which turned on, probably causingfailure from over–current and excessive junction tempera-ture.

Turn–off time — tq is important in higher frequencyapplications which require the SCR to recover from theforward conduction period and be able to block the next cycleof forward voltage. Thus, tq matching for high frequencyoperation can be as important as td, tr and VA(MIN) matchingfor equal turn–on current sharing.

Due to the variable in tq measurement, no further attemptwill be made here to discuss this parameter and the reader isreferred to Application Note AN914.

The need for on–state matching of current and voltage isimportant, especially in unforced current sharing circuits.

UNFORCED CURRENT SHARINGWhen operating parallel SCRs without forced current

sharing, such as without cathode ballasting using resistors orinductors, it is very important that the device parameters beclosely matched. This includes td, tr, minimum forward anodevoltage for turn–on and on–state voltage matching. Thedegree of matching determines the success of the circuit.

In circuits without ballasting, it is especially important thatphysical layout, mounting of devices and resistance paths beidentical for good current sharing, even with on–statematched devices.

Figure 5.27 shows how anode current can vary on devicesclosely matched for on–state voltage (1, 3 and 4) and amismatched device (2). Without resistance ballasting, thematched devices share peak current within one ampere anddevice 2 is passing only nine amps, seven amps lower thandevice 1. Table 5.6 shows the degree of match or mismatchof VTM of the four SCRs.

With unforced current sharing (RK = 0), there was a greatertendency for one device (1) to turn–on, preventing the othersfrom turning on when low anode switching voltage ( 10 V

rms) was tried. Table 5.5 shows that the minimum anodevoltage for turn–on is from 7 to 14% lower for device 1 thanon 2, 3 and 4. Also, device 1 turn–on delay is 35 ns versus38, 45 and 44 ns for devices 2, 3 and 4.

The tendency for device 1 to turn on, preventing the otherthree from turning on, is most probably due to its lowerminimum anode voltage requirement and shorter turn ondelay. The remedy would be closer matching of the minimumanode voltage for turn–on and driving the gates hard (butless than the gate power specifications) and increasing thewidth of the gate current pulse.

FORCED CURRENT SHARINGCathode ballast elements can be used to help ensure

good static on–state current sharing. Either inductors orresistors can be used and each has advantages anddisadvantages. This section discuses resistive ballasting, butit should be kept in mind that the inductor method is usuallybetter suited for the higher current levels. Although they aremore expensive and difficult to design, there is less powerloss with inductor ballasting as well as other benefits.

The degree of peak current sharing is shown in Figure 5.27for four parallel MCR12D SCRs using cathode resistorballasting with an inductive anode load. With devices 1, 3and 4, on–state voltage is matched within 10 mV at an anodecurrent of 15 A (See Table 5.6) and are within 1A of eachother in Figure 5.27, with cathode resistance (RK) equal tozero. As RK increases, the current sharing becomes evencloser. The unmatched device 2, with a VTM of 1.41 V (Table5.6), is not carrying its share of current (Figure 5.29) with RKequal zero. As RK increases, device 2 takes a greater shareof the total current and with RK around 0.25 ohm, the fourSCRs are sharing peak current quite well. The value of RKdepends on how close the on–state voltage is matched onthe SCRs and the degree of current sharing desired, as wellas the permissible power dissipation in RK.

Figure 5.27. Effects Of Cathode Resistor On AnodeCurrent Sharing

#2

#3

IG = 400 mAPW = 400 µsOFF–STATE VOLTAGE = 26 V(rms)INDUCTIVE LOADCONDUCTION ANGLE = 120°

RK, CATHODE RESISTORS (MILLIOHMS)

SCR #1

#4

7

17

15

13

50

11

2502001500

9

100

I

,

PEAK

AN

OD

E C

UR

REN

T (A

MPS

)A(

pk)



Table 5.6. MCR12D Parameters Measured On CurveTracer, T C = 25°C

Device #

IL, LatchingCurrent

VD = 12 VdcIG = 100 mA

VTM, On–StateVoltage

IA = 15 APW = 300 µs

Minimum GateCurrent & Voltage

for Turn–OnVD = 12 Vdc,RL = 140 Ω

IGT VGT

12345678910

13 mA272823232318191916

1.25 V1.411.261.261.281.261.251.251.251.25

5.6 mA8.8129.69.49.67.17

8.46.9

0.615 V0.6790.6580.6490.6590.6450.6900.6870.6940.679

LINE SYNCHRONIZED DRIVE CIRCUITGate drive for phase control of the four parallel SCRs is

accomplished with one complementary MOS hex gate,MC14572, and two bipolar transistors (Figure 5.28). Thisadjustable line–synchronized driver permits SCR conductionfrom near zero to 180 degrees. A Schmitt trigger clocks adelay monostable multivibrator that is followed by a pulse–

width monostable multivibrator.Line synchronization is achieved through the half–wave

section of the secondary winding of the full–wave, center–tapped transformer (A). This winding also supplies power tothe circuit through rectifiers D1 and D2.

The full–wave signal is clipped by diode D5, referenced toa + 15 volt supply, so that the input limit of the CMOS chip isnot exceeded. The waveform is then shaped by the Schmitttrigger, which is composed of inverters U1–a and U1–b. A fastswitching output signal B results.

The positive–going edge of this pulse is differentiated bythe capacitive–resistive network of C1 and R2 and triggersthe delay multivibrator that is composed of U1–c and U1–d.As a result, the normally high output is switched low. Thetrailing edge of this pulse (C) then triggers the followingmultivibrator, which is composed of NAND gate U1–e andinverter U1–f. The positive going output pulse (waveform D)of this multivibrator, whose width is set by potentiometer R6,turns on transistors Q1 and Q2, which drives the gates of thefour SCRs. Transistor Q2 supplies about 400 mA drivecurrent to each gate through 100 ohm resistors and has arise time of 100 ns.

PARALLEL SCR CIRCUIT

The four SCRs are MCR12Ds, housed in the TO–220package, rated at 12 A rms, 50 V and are shown schematically

B

DA

A

Figure 5.28. Line–Synchronized Gate Driver

+ 15 V

τ2

015 V

τ1

TRIADF90X

1N914

120 V60 Hz

D3

HALF–

WAVED4

S1

FULL–WAVE 0 kΩ

22 kΩ1 kΩ1N914

D1

D2

1N914D5

100 Ω,1 W

250µF 25 V 1N5352

5 V, 5 W

+ 15 V

+ 40 V

10 k

Q2MJE253

1 kTO GATES

RESISTORS0.005

TIP122

10 k

14

1315U1 ––e

R5100 kΩ

0.01µF

U1 – f8

1116

120.01 µF

10 k0.001

4.7 kΩ

R625 kΩ

U1 – a

R1220 kΩ

C10.01µF

150kΩ

4

R4

+ 15 V

R2100kΩSCHMITT TRIGGER

R31 mΩ

2

D

C

B

30 µs τ2 200 µsPULSE–WIDTHMULTIVIBRATOR

1 3

0.7 ms τ1 6 rmsDELAY MULTIVIBRATOR

79

U1 – d100.01

µF

5

U1 – b

5.30(b)

5.30(a)

U1

0

15 V

015 V

015 V

6


Figure 5.29. Parallel Thyristors

LOAD: FOUR STANCOR FILTER CHOKES (#C–2688) IN PARALLELEACH RATED AT: 10 mH @ 12.5 Adc AND 0.11 OHMS

ALL ANODES COMMON TO HEAT SINK

Q3 – Q6, MCR12D

120 V rms60 Hz

26 V rms

1 k

100 100 100

Q6

100 R7100

SNUBBER

0.25C2

Q4

RK

Q3 Q5

1 k 1 k 1 k

RK RK RK

in Figure 5.29. Due to line power limitations, it was decided touse a voltage step down transformer and not try working directlyfrom the 120 V line. Also, line isolation was desirable in anexperiment of this type.

The step down transformer ratings were 120 V rmsprimary, 26 V rms secondary, rated at 100 A, and was usedwith a variable transformer for anode voltage adjustment.The inductive load consisted of four filter chokes in parallel(Stancor #C–2688 with each rated at 10 mH, 12.5 Adc and0.11 ohm).

For good current sharing with parallel SCRs, symmetry inlayout and mounting is of primary importance. The four SCRswere mounted on a natural finish aluminum heat sink andtorqued to specification which is 8 inch pounds. Cathodeleads and wiring were identical, and when used, the cathoderesistors RK were matched within 1%. An RC snubbernetwork (R7 and C2) was connected across the anodes–cathodes to slow down the rate–of–rise of the off–statevoltage, preventing unwanted turn–on.

CHARACTERIZING RFI SUPPRESSION INTHYRISTOR CIRCUITS

In order to understand the measures for suppression of EMI,characteristics of the interference must be explored first. Tohave interference at all, we must have a transmitter, or creator ofinterference, and a receiver, a device affected by the interfer-ence. Neither the transmitter nor the receiver need be related inany way to those circuits commonly referred to as radio–fre-quency circuits. Common transmitters are opening and closingof a switch or relay contacts, electric motors with commutators,all forms of electric arcs, and electronic circuits with rapidlychanging voltages and currents. Receivers are generally elec-tronic circuits, both low and high impedance which are sensitiveto pulse or high frequency energy. Often the very circuitscreating the interference are sensitive to similar interferencefrom other circuits nearby or on the same power line.

EMI can generally be separated into two categories —radiated and conducted. Radiated interference travels byway of electro–magnetic waves just as desirable RF energydoes. Conducted interference travels on power, communica-tions, or control wires. Although this separation and nomen-clature might seem to indicate two neat little packages,independently controllable, such is not the case. The two arevery often interdependent such that in some cases control ofone form may completely eliminate the other. In any case,both interference forms must be considered when interfer-ence elimination steps are taken.

Phase control circuits using thyristors (SCRs, triacs, etc.)for controlling motor speed or resistive lighting and heatingloads are particularly offensive in creating interference. Theycan completely obliterate most stations on any AM radionearby and will play havoc with another control on the samepower line. These controls are generally connected in one ofthe two ways shown in the block diagrams of Figure 5.30.

A common example of the connection of 5.30(a) is the wallmounted light dimmer controlling a ceiling mounted lamp. Amotorized appliance with a built–in control such as a foodmixer is an example of the connection shown in 5.30(b).

Figure 5.30(a) may be re–drawn as shown in Figure 5.31,illustrating the complete circuit for RF energy.The switch inthe control box represents the thyristor, shown in its blockingstate. In phase control operation, this switch is open at thebeginning of each half cycle of the power line alternations.After a delay determined by the remainder of the controlcircuitry, the switch is closed and remains that way until theinstantaneous current drops to zero. This switch is thesource from which the RF energy flows down the power linesand through the various capacitors to ground.

If the load is passive, such as a lamp or a motor whichdoes not generate interference, it may be considered as animpedance bypassed with the wire–to–wire capacitance ofits leads. If it is another RF energy source, however, such asa motor with a commutator, it must be treated separately toreduce interference from that source. The power supply may



LINE

CONTROLLOAD

LOAD

CONTROL

LINE

(b). Control and Load in the Same Enclosure

(a). Separately Mounted Control

Figure 5.30. Block Diagram of Control Connections

be considered as dc since the interference pulse is extremelyshort (10 µs) compared to the period of the power linefrequency (16 ms for 60 Hz). The inductance associated withthe power source comes from two separate phenomena.First is the leakage impedance of the supply transformer, andsecond is the self–inductance of the wires between thepower line transformer and the load.

One of the most difficult parameters to pin down in thesystem is the effect of grounding. Most industrial andcommercial wiring and many homes use a grounded conduitsystem which provides excellent shielding of radiated energyemanating from the wiring. However, a large number ofhomes are being wired with two to three wire insulated cablewithout conduit. In three–wire systems, one wire is groundedindependently of the power system even though one of thepower lines is already grounded. The capacitances to groundshown in Figure 5.31 will be greatly affected by the type ofgrounding used. Of course, in any home appliance, filteringmust be provided suitable for all three different systems.

Before the switch in the control is closed, the system is in asteady–state condition with the upper line of the power line atthe system voltage and the bottom line and the load atground potential. When the switch is closed, the upper linepotential instantaneously falls due to the line and sourceinductance, then it rises back to its original value as the lineinductance is charged. While the upper line is rising, the linefrom the control to the load also rises in potential. The effectof both of these lines increasing in potential together causesan electro–static field change which radiates energy. Inaddition, any other loads connected across the power lines atpoint A, for example, would be affected by a temporary lossof voltage created by the closing of the switch and by the line

and source inductance. This is a form of conductedinterference.

A second form of radiated interference is inductivecoupling in which the power line and ground form a one–turnprimary of an air core transformer. In this mode, anunbalanced transient current flows down the power lines withthe difference current flowing to ground through the variouscapacitive paths available. The secondary is the radioantenna or the circuit being affected. This type of interferenceis a problem only when the receiver is within about onewavelength of the transmitter at the offending frequency.

Radiated interference from the control circuit proper is oflittle consequence due to several factors. The lead lengths ingeneral are so short compared to the wavelengths inquestion that they make extremely poor antenna. In addition,most of these control circuits are mounted in metal enclo-sures which provide shielding for radiated energy generatedwithin the control circuitry.

A steel box will absorb radiated energy at 150 kHz suchthat any signal inside the box is reduced 12.9 dB per mil ofthickness of the box. In other words, a 1/16 inch thick steelbox will attenuate radiated interference by over 800 dB! Asimilar aluminum box will attenuate 1 dB per mil or 62.5 dBtotal. Thus, even in an aluminum box, the control circuitry willradiate very little energy.

Both forms of radiated interference which are a problemare a result of conducted interference on the power lineswhich is in turn caused by a rapid rise in current. Thus, if thiscurrent rise is slowed, all forms of interference will bereduced.

RFI SOLUTIONS

Since the switch in Figure 5.31, when it closes, provides avery low impedance path, a capacitor in parallel with it willshow little benefit in slowing down the rise of current. Thecapacitor will be charged to a voltage determined by the

Figure 5.31. RF Circuit for Fi gure 5.30(a)

LOADCONTROL

A


Figure 5.32. One Possible EMI Reduction Circuit

LOAD

8A

CONTROL10 A TRIAC

100 µH0.1 µF

circuit constants and the phase angle of the line voltage justbefore the switch closes. When the switch closes, thecapacitor will discharge quickly, its current limited only by itsown resistance and the resistance of the switch. However, aseries inductor will slow down the current rise in the load andthus reduce the voltage transient on all lines. A capacitorconnected as shown in Figure 5.32 will also help slow downthe current rise since the inductor will now limit the current outof the capacitor. Thus, the capacitor voltage will drop slowlyand correspondingly the load voltage will increase slowly.

Although this circuit will be effective in many cases, thefilter is unbalanced, providing an RF current path through thecapacitances to ground. It has, therefore, been foundadvantageous to divide the inductor into two parts and to puthalf in each line to the control. Figure 5.33 illustrates thiscircuit showing the polarity marks of two coils which arewound on the same core.

A capacitor at point A will help reduce interference further.This circuit is particularly effective when used with theconnection of Figure 5.30(b) where the load is not always onthe grounded side of the power line. In this case, the twohalves of the inductor would be located in the power lineleads, between the controlled circuit and the power source.

Where the control circuit is sensitive to fast rising linetransients, a capacitor at point B will do much to eliminate thisproblem. The capacitor must charge through the impedanceof the inductor, thus limiting the rate of voltage change (dv/dt)applied to the thyristor while it is in the blocking state.

DESIGN CRITERIA

Design equations for the split inductor have been devel-oped based on parameters which should be known beforeattempting a design. The most difficult to determine is tr, theminimum allowable current rise time which will not causeobjectionable interference. The value of this parameter mustbe determined empirically in each situation if completeinterference reduction is needed. Motorola has conductedextensive tests using an AM radio as a receiver and a 600Watt thyristor lamp dimmer as a transmitter. A rate of about0.35 Amp per µs seems to be effective in eliminatingobjectionable interference as well as materially reducingfalse triggering of the thyristor due to line transients. Thevalue of tr may be calculated by dividing the peak currentanticipated by the allowable rate of current rise.

Ferrite core inductors have proved to be the most practicalphysical configuration. Most ferrites are effective; those withhighest permeability and saturation flux density are pre-ferred. Those specifically designed as high frequency typesare not necessarily desirable.

Laminated iron cores may also be used; however, theyrequire a capacitor at point A in Figure 5.33 to be at alleffective. At these switching speeds, the iron requiresconsiderable current in the windings before any flux changecan take place. We have found currents rising to half theirpeak value in less than one µs before the inductance beginsto slow down the rise. The capacitor supplies this current forthe short period without dropping in voltage, thus eliminatingthe pulse on the power line.

Once a core material has been selected, wire size is thenext decision in the design problems. Due to the smallnumber of turns involved (generally a single layer) smallersizes than normally used in transformers may be chosensafely. Generally, 500 to 800 circular mills per ampere isacceptable, depending on the enclosure of the filter and themaximum ambient temperature expected.

An idea of the size of the core needed may be determinedfrom the equation:

(1) AcAw26 Awire Erms tr

BMAXwhere:

Ac = the effective cross–sectional area of the core inin2

Aw = available core window area in in2Awire = wire cross section in circular mils

BMAX = core saturation flux density in gausstr = allowable current rise time in seconds

Erms = line voltage

(A factor of 3 has been included in this equation to allow forwinding space factor.) Once a tentative core selection hasbeen made, the number of turns required may be found fromthe equation:

(2) N11 Erms tr 106

BMAXAcwhere:

N = the total number of turns on the core

The next step is to check how well the required number ofturns will fit onto the core. If the fit is satisfactory, the coredesign is complete; if not, some trade–offs will have to bemade.

Figure 5.33. Split Inductor Circuit

LOAD

CONTROL10 A TRIAC

A120 Vac

240 µH

240 µH5A

B



In most cases, the inductor as designed at this point willhave far too much inductance. It will support the entire peakline voltage for the time selected as tr and will then saturatequickly, giving much too fast a current rise. The requiredinductance should be calculated from the allowable rise timeand load resistance, making the rise time equal to two timeconstants. Thus:

(3) 2LR tr or L

R tr2

Paper or other insulating material should be insertedbetween the core halves to obtain the required inductance bythe equation:

(4) Ig3.19 N2 Ac 108

L

Ic

where:Ig = total length of air gap in inchesµ = effective ac permeability of the core material at the

power line frequencyIc = effective magnetic path length of the core in inches

Ac = effective cross sectional area of the core in squareinches

L = inductance in henries

DESIGN EXAMPLE

Consider a 600 watt, 120 Volt lamp dimmer using a

Motorola 2N6148 triac. Line current is 600120

= 5 amperes. #16

wire will provide about 516 circular mils per ampere.For core material, type 3C5 of Ferroxcube Corporation of

America, Saugerties, New York, has a high Bmax and µ. Thecompany specifies BMAX = 3800 gauss and µ = 1900 formaterial.

As was previously mentioned, a current rise rate of about0.35 ampere per µs has been found to be acceptable forinterference problems with ac–dc radios in most wiringsituations. With 5 amperes rms, 7 amperes peak,

tr7

0.35 20 s

Then the equation (1):

AcAw26 2580 120 20 106

3800 gauss 0.044

Core part number 1F30 of the same company in a U–1configuration has an AcAw product of 0.0386, which shouldbe close enough.

N 10.93 120 20 106 106

3800 0.137 42 turns

Two coils of 21 turns each should be wound on either one ortwo legs and be connected as shown in Figure 5.35.

The required inductance of the coil is found fromequation (3).

LR tr

2

EratedIrated

tr2

1205

202106

240106

L 240 H

To obtain this inductance, the air gap should be

Ig3.19422

0.137108

240106

3.331900

0.03210.00175

Ig0.03035

Thus, 15 mils of insulating material in each leg will providethe necessary inductance.

If a problem still exists with false triggering of the thyristordue to conducted interference, a capacitor at point B inFigure 5.33 will probably remedy the situation.


CHAPTER 6APPLICATIONS

Because they are reliable solid state switches, thyristorshave many applications, especially as controls.

One of the most common uses for thyristors is to control acloads such as electric motors. This can be done either bycontrolling the part of each ac cycle when the circuit conductscurrent (phase control) or by controlling the number of cyclesper time period when current is conducted (cycle control).

In addition, thyristors can serve as the basis of relaxationoscillators for timers and other applications. Most of thedevices covered in this book have control applications.

PHASE CONTROL WITH THYRISTORSThe most common method of electronic ac power control

is called phase control. Figure 6.1 illustrates this concept.During the first portion of each half-cycle of the ac sine wave,an electronic switch is opened to prevent the current flow. Atsome specific phase angle, α, this switch is closed to allowthe full line voltage to be applied to the load for the remainderof that half-cycle. Varying α will control the portion of the totalsine wave that is applied to the load (shaded area), andthereby regulate the power flow to the load.

The simplest circuit for accomplishing phase control isshown in Figure 6.2. The electronic switch in this case is atriac (Q) which can be turned on by a small current pulse to itsgate. The TRIAC turns off automatically when the currentthrough it passes through zero. In the circuit shown,capacitor CT is charged during each half-cycle by the currentflowing through resistor RT and the load. The fact that theload is in series with RT during this portion of the cycle is oflittle consequence since the resistance of RT is many timesgreater than that of the load. When the voltage across CTreaches the breakdown voltage of the DIAC bilateral trigger(D), the energy stored in capacitor CT is released. Thisenergy produces a current pulse in the DIAC, which flowsthrough the gate of the TRIAC and turns it on. Since both theDIAC and the TRIAC are bidirectional devices, the values ofRT and CT will determine the phase angle at which the TRIACwill be triggered in both the positive and negative half-cyclesof the ac sine wave.

α = 150°

PORTION OF WAVEFORMAPPLIED TO LOAD

α

α

APPLIED SINE WAVE

AC LINEVOLTAGE

CT

LOAD

RT

D

Q

α = 90°

α = 90°

α = 150°

Figure 6.1. Phase Control of AC Waveform

Figure 6.2. Simplest Circuit for Phase Control

Figure 6.3. Waveforms of Capacitor Voltageat Two Phase Angles

The waveform of the voltage across the capacitor for twotypical control conditions (α = 90° and 150°) is shown inFigure 6.3. If a silicon controlled rectifier is used in this circuit



in place of the TRIAC, only one half-cycle of the waveformwill be controlled. The other half-cycle will be blocked,resulting in a pulsing dc output whose average value canbe varied by adjusting RT.

CONTROL OF INDUCTION MOTORSShaded-pole motors driving low-starting-torque loads

such as fans and blowers may readily be controlled usingany of the previously described full-wave circuits. Oneneeds only to substitute the winding of the shaded-polemotor for the load resistor shown in the circuit diagrams.

Constant-torque loads or high-starting-torque loads aredifficult, if not impossible, to control using the voltagecontrols described here. Figure 6.4 shows the effect ofvarying voltage on the speed-torque curve of a typicalshaded-pole motor. A typical fan-load curve and aconstant-torque-load curve have been superimposedupon this graph. It is not difficult to see that the torquedeveloped by the motor is equal to the load torque at twodifferent points on the constant-torque-load curve, givingtwo points of equilibrium and thus an ambiguity to thespeed control. The equilibrium point at the lower speed isa condition of high motor current because of low counterEMF and would result in burnout of the motor winding if themotor were left in this condition for any length of time. Bycontrast, the fan speed-torque curve crosses each of themotor speed-torque curve crosses each of the motorspeed-torque curves at only one point, therefore causingno ambiguities. In addition, the low-speed point is one oflow voltage well within the motor winding’s current-carry-ing capabilities.

Permanent-split-capacitor motors can also be controlledby any of these circuits, but more effective control isachieved if the motor is connected as shown in Figure 6.5.Here only the main winding is controlled and the capacitorwinding is continuously connected to the entire ac linevoltage. This connection maintains the phase shift be-tween the windings, which is lost if the capacitor phase isalso controlled. Figure 6.6(a) shows the effect of voltageon the speed-torque characteristics of this motor and asuperimposed fan-load curve.

3/4 VR

TORQUE

1/4 VR

CONSTANT TORQUE LOAD

1/2 VR

VR = FULL RATED VOLTAGE

TYPICAL FANLOAD

VR

SPEE

DCONTROLCIRCUIT

AC LINEVOLTAGE

MOT

Figure 6.4. Characteristics of Shaded-Pole Motorsat Several Voltages

Figure 6.5. Connection Diagram forPermanent-Split-Capacitor Motors

Not all induction motors of either the shaded-pole or thepermanent-split-capacitor types can be controlled effec-tively using these techniques, even with the proper loads.Motors designed for the highest efficiencies and, there-fore, low slip also have a very low starting torque and may,under certain conditions, have a speed-torque character-istic that could be crossed twice by a specific fan-loadspeed-torque characteristic. Figure 6.6(b) shows motor

(a). High-Starting-Torque Motor (b). High-Efficiency Motor


TORQUE

TYPICAL FANLOAD

1/4 VR

1/2 VR

3/4 VR

VR

SPEE

D

TORQUE

1/4 VR

1/2 VR

3/4 VR

VR

HIGH-STARTING-TORQUE FAN

LOAD

SPEE

D

Figure 6.6. Speed–Torque Curves for a Permanent–Split–Capacitor Motors at Various Applied Voltages


torque-speed characteristic curves upon which has beensuperimposed the curve of a fan with high starting torque. It istherefore desirable to use a motor whose squirrel-cage rotoris designed for medium-to-high impedance levels and,therefore, has a high starting torque. The slight loss inefficiency of such a motor at full rated speed and load is asmall price to pay for the advantage of speed controlprevents the TRIAC from turning on due to line transientsand inductive switching transients.

A unique circuit for use with capacitor-start motors inexplosive or highly corrosive atmospheres, in which thearcing or the corrosion of switch contacts is severe andundesirable, is shown in Figure 6.7. Resistor R1 isconnected in series with the main running winding and is ofsuch a resistance that the voltage drop under normalfull-load conditions is approximately 0.2 V peak. Sincestarting currents on these motors are quite high, this peakvoltage drop will exceed 1 V during starting conditions,triggering the TRIAC, which will cause current to flow in thecapacitor winding. When full speed is reached, the currentthrough the main winding will decrease to about 0.2 V,which is insufficient to trigger the TRIAC — thus thecapacitor winding will no longer be energized. Resistor R2and capacitor C2 form a dv/dt suppression network; thisprevents the TRIAC from turning on due to line transientsand inductive switching transients.

CONTROL OF UNIVERSAL MOTORSAny of the half-wave or full-wave controls described

previously can be used to control universal motors. Non-feedback, manual controls, such as those shown in Figure6.2, are simple and inexpensive, but they provide very littletorque at low speeds. A comparison of typical speed-torquecurves using a control of this type with those of feedbackcontrol is shown in Figure 6.8.

These motors have some unique characteristics whichallow their speed to be controlled very easily and efficientlywith a feedback circuit such as that shown in Figure 6.9. Thiscircuit provides phase-controlled half-wave power to themotor; that is, on the negative half-cycle, the SCR blockscurrent flow in the negative direction causing the motor to bedriven by a pulsating direct current whose amplitude isdependent on the phase control of the SCR.

Figure 6.7. Circuit Diagram for Capacitor-Start Motor

AC LINEVOLTAGE

R1

MOTC1

R2

C2

Figure 6.8. Comparison of Feedback Controlwith Non-Feedback Control

1/2 VR

3/4 VR

VR

TORQUE(B) FEEDBACK CONTROL

1/4 VR

1/2 VR

3/4 VR

VR


TORQUE(A) NON-FEEDBACK CONTROL

SPEE

D

SPEE

D

The theory of operation of this control circuit is not at alldifficult to understand. Assuming that the motor has beenrunning, the voltage at point A in the circuit diagram mustbe larger than the forward drop of Diode D1, thegate-to-cathode drop of the SCR, and the EMF generatedby the residual MMF in the motor, to get sufficient currentflow to trigger the SCR.

The waveform at point A (VA) for one positive half-cycleis shown in 6.9(b), along with the voltage levels of the SCRgate (VSCR), the diode drop (VD), and the motor-generatedEMF (VM). The phase angle (α) at which the SCR wouldtrigger is shown by the vertical dotted line. Should themotor for any reason speed up so that the generated motorvoltage would increase, the trigger point would moveupward and to the right along the curve so that the SCRwould trigger later in the half-cycle and thus provide lesspower to the motor, causing it to slow down again.

Similarly, if the motor speed decreased, the trigger pointwould move to the left and down the curve, causing theTRIAC to trigger earlier in the half-cycle providing morepower to the motor, thereby speeding it up.

Resistors R1, R2, and R3, along with diode D2 andcapacitor C1 form the ramp-generator section of thecircuit. Capacitor C1 is changed by the voltage divider R1,R2, and R3 during the positive half-cycle. Diode D2prevents negative current flow during the negative half-cycle, therefore C1 discharges through only R2 and R3during that half-cycle. Adjustment of R3 controls theamount by which C1 discharges during the negativehalf-cycle. Because the resistance of R1 is very muchlarger than the ac impedance of capacitor C1, the voltagewaveform on C1 approaches that of a perfect cosine wavewith a dc component. As potentiometer R2 is varied, boththe dc and the ac voltages are divided, giving a family ofcurves as shown in 6.9(c).



Figure 6.9. (a). Speed-Control Scheme forUniversal Motors

AC LINEVOLTAGE

C1 R2

D2

R3

R1

A

C2

MOT

D1

The gain of the system, that is, the ratio of the change ofeffective SCR output voltage to the change in generatorEMF, is considerably greater at low speed settings than itis at high speed settings. This high gain coupled with amotor with a very low residual EMF will cause a conditionsometimes known as cycle skipping. In this mode ofoperation, the motor speed is controlled by skipping entirecycles or groups of cycles, then triggering one or two cyclesearly in the period to compensate for the loss in speed.Loading the motor would eliminate this condition; however,the undesirable sound and vibration of the motor necessitatethat this condition be eliminated. This can be done in twoways.

The first method is used if the motor design is fixed andcannot be changed. In this case, the impedance level of thevoltage divider R1, R2 and R3 can be lowered so that C1 willcharge more rapidly, thus increasing the slope of the rampand lowering the system gain. The second method, which willprovide an overall benefit in improved circuit performance,involves a redesign of the motor so that the residual EMFbecomes greater. In general, this means using a lower gradeof magnetic steel for the laminations. As a matter of fact,some people have found that ordinary cold-rolled steel usedas rotor laminations makes a motor ideally suited for this typeof electronic control.

Another common problem encountered with this circuitis that of thermal runaway. With the speed control set atlow or medium speed, at high ambient temperatures thespeed may increase uncontrollably to its maximum value.This phenomenon is caused by an excessive impedancein the voltage-divider string for the SCR being triggered. Ifthe voltage-divider current is too low, current will flow intothe gate of the SCR without turning it on, causing thewaveform at point A to be as shown in 6.9(d). The flatportion of the waveform in the early part of the half-cycle iscaused by the SCR gate current loading the voltagedivider before the SCR is triggered. After the SCR istriggered, diode D1 is back-biased and a load is no longeron the voltage divider so that it jumps up to its unloadedvoltage. As the ambient temperature increases, the SCRbecomes more sensitive, thereby requiring less gatecurrent to trigger, and is triggered earlier in the half-cycle.This early triggering causes increased current in theSCR, thereby heating the junction still further and increas-ing still further the sensitivity of the SCR until maximumspeed has been reached.

(b). Waveform for One Positive Half-Cycle of Circuit

(c). Voltage Waveform at Point “A” for Three Settingsof Potentiometer R2

(d). Point “A” Voltage with Excessive Resistance R1

α2

α

α3α1

VM

VA

R2 (R2)″

(R2)′

VD

PHASEANGLE

VM

VSCR

VA

VA

PHASEANGLE

UNLOADEDWAVEFORM

ACTUALWAVEFORM

TRIGGERPOINT

The solutions to this problem are the use of the mostsensitive SCR practical and a voltage divider network ofsufficiently low impedance. As a rough rule of thumb, theaverage current through the voltage divider during thepositive half-cycle should be approximately three timesthe current necessary to trigger the lowest-sensitivity(highest gate current) SCR being used.


In addition to the type of steel used in the motorlaminations, consideration should also be given to the designof motors used in this half-wave speed control. Since themaximum rms voltage available to the motor under half-waveconditions is 85 V, the motor should be designed for use atthat voltage to obtain maximum speed. However, U.L.requirements state that semiconductor devices used inappliance control systems must be able to be short-circuitedwithout causing danger. Many designers have found itadvantageous, therefore, to use 115 V motors with thissystem and provide a switch to apply full-wave voltage to themotor for high-speed operation. Figure 6.10 shows theproper connection for this switch. If one were to simplyshort-circuit the SCR for full-speed operation, a problemcould arise. If the motor were operating at full speed withthe switch closed, and the switch were then opened duringthe negative half-cycle, the current flowing in the inductivefield of the motor could then break down the SCR in thenegative direction and destroy the control. With the circuitas shown, the energy stored in the field of the motor isdissipated in the arc of the switch before the SCR isconnected into the circuit.

CONTROL OF PERMANENT-MAGNET MOTORSAs a result of recent developments in ceramic perma-

nent-magnet materials that can be easily molded intocomplex shapes at low cost, the permanent-magnet motorhas become increasingly attractive as an appliancecomponent. Electronic control of this type of motor can beeasily achieved using techniques similar to those justdescribed for the universal motor. Figure 6.11 is a circuitdiagram of a control system that we have developed andtested successfully to control permanent-magnet motorspresently being used in blenders. Potentiometer R3 anddiode D1 form a dc charging path for capacitor C1; variableresistor R1 and resistor R2 form an ac charging path whichcreates the ramp voltage on the capacitor. Resistor R4 anddiode D2 serve to isolate the motor control circuit from theramp generator during the positive and negative half-cycles, respectively.

A small amount of cycle skipping can be experienced atlow speeds using this control, but not enough to necessi-tate further development work. Since the voltage gener-ated during off time is very high, the thermal runawayproblem does not appear at all. Typical speed-torquecurves for motors of this type are shown in Figure 6.12.

MOTOR SPEED CONTROL WITH FEEDBACKWhile many motor speed control circuits have used

SCRs, the TRIAC has not been very popular in this ap-plication. At first glance, it would appear that the TRIACwould be perfect for speed control because of its bilateralcharacteristics. There are a couple of reasons why this isnot true. The major difficulty is the TRIAC’s dv/dt charac-teristic. Another reason is the difficulty of obtaining a feed-back signal because of the TRIAC’s bilatera nature.

Figure 6.10. Switching Scheme forFull-Wave Operation

CONTROLCIRCUIT

MOT

AC L

INE

VOLT

AGE

While the TRIAC has its disadvantages, it does offer someadvantages. In a SCR speed control either two SCRs mustbe used, or the line voltage must be full-wave rectifiedusing relatively high current rectifiers, or the control mustbe limited to half-wave. The TRIAC eliminates all thesedifficulties. By using a TRIAC the part count, package size,and cost can be reduced. Figure 6.13 shows a TRIACmotor speed control circuit that derives its feedback fromthe load current and does not require separate connec-tions to the motor field and armature windings. Therefore,this circuit can be conveniently built into an appliance orused as a separate control.

The circuit operates as follows: When the TRIACconducts, the normal line voltage, less the drop across theTRIAC and resistor R5, is applied to the motor. By delayingthe firing of the TRIAC until a later portion of the cycle, therms voltage applied to the motor is reduced and its speedis reduced proportionally. The use of feedback maintainstorque at reduced speeds.

Figure 6.11. Circuit Diagram for ControllingPermanent-Magnet Motors

R3

D1

R4 D2

C1

R2

R1

MOT

AC L

INE

VOLT

AGE



Figure 6.12. Speed-Torque Characteristic of PermanenMagnet Motors at Various Applied Voltages

3/4 VR

1/4 VR

VR VR = FULL RATED VOLTAGE

TORQUE

1/2 VR

SPEE

D

Diodes D1 through D4 form a bridge which appliesfull-wave rectified voltage to the phase-control circuit. Phasecontrol of the TRIAC is obtained by the charging of capacitorC1 through resistors R2 and R3 from the voltage levelestablished by zener diode D5. When C1 charges to thefiring voltage of PUT Q1, the TRIAC triggers by transform-er T1. C1 discharges through the emitter of Q1. While theTRIAC is conducting, the voltage drop between points Aand B falls below the breakdown voltage of D5. Therefore,during the conduction period, the voltage on C1 is deter-mined by the voltage drop from A to B and by resistors R1,R2, and R3. Since the voltage between A and B is a functionof motor current due to resistor R5, C1 is charged during theconduction period to a value which is proportional to the

motor current. The value of R5 is chosen so that C1 cannotcharge to a high enough voltage to fire Q1 during theconduction period. However, the amount of charging re-quired to fire Q1 has been decreased by an amountproportional to the motor current. Therefore, the firing angleat which Q1 will fire has been advanced in proportion to themotor current. As the motor is loaded and draws morecurrent, the firing angle of Q1 is advanced even more,causing a proportionate increase in the rms voltage appliedto the motor, and a consequent increase in its availabletorque.

Since the firing voltage of Q1 depends on the voltage frombase one to base two, it is necessary to support the base twovoltage during the conduction portion of the cycle to preventthe feedback voltage from firing Q1. D6 and C2 perform thisfunction.

Because the motor is an inductive load, it is necessary tolimit the commutation dv/dt for reliable circuit operation. R6and C3 perform this function.

Nominal values for R5 can be obtained from the table orthey can be calculated from the equation given. Exact valuesfor R5 depend somewhat on the motor characteristics.Therefore, it is suggested that R5 be an adjustable wire-wound resistor which can be calibrated in terms of motorcurrent, and the speed control can be adapted to manydifferent motors. If the value of R5 is too high, feedback willbe excessive and surging or loss of control will result. If thevalue is too low, a loss of torque will result. The maximummotor current flows through R5, and its wattage must bedetermined accordingly.

Figure 6.13. Motor Speed Control with Feedback

BMOTOR

115 VAC60 Hz

A

IN4006(4)

D4D3

D1 D2

18 k2 W

R1

D5ZENER9.1 V

R350 k

R227 k

C10.1 µF

Q12N6027

D61N4001

T1DALE

PT-50 ORIGIN

R416 k

R727 k

C210 µF10 V

Q2MAC9D R6

100 Ω

C30.1 µF

R5SEE TABLE

6.5

3

2

Motor Rating(Amperes)

0.32

0.67

1

OHMS

15

10

5

Watts

R5

NOMINAL R5 VALUES

IM = Max. RatedMotor Current

(RMS)

R5 2IM


Figure 6.14. TDA 1185-A Universal Motor Speed Control.— Internal Block Diagram /Pin Assignment

–

+

+

+

100 µF

C88

1.0 µF

R12

SET12

120 k

MAIN LINE

VOLTAGE COMPENSATION

RCOMPENSATION

+C13SOFTSTART

PROGRAMMING PIN

13

FULL-WAVE

R10

10

C4

4

SAWTOOTHGENERATOR

FULL-WAVETRIGGER PULSE

GENERATOR

MONITORING

POSITIVE

FEEDBACK

R90.05

100

MAC8D

14

9

2

M

CURRENTSYNCHRO

820 k6

1 7

18 k

2.0 W

– VCC 820 k

VOLTAGE SYNCHRO

1N4005

This circuit has been operated successfully with 2 and 3ampere 1/4-inch drills and has satisfactorily controlled motorspeeds down to 1/3 or less of maximum speed with goodtorque characteristics. to the motor, and a consequentincrease in its available torque.

AN INTEGRATED CIRCUIT FEEDBACK CONTROLThe TDA1185A TRIAC phase angle controller (Figure

6.14) generates controlled triac triggering pulses and appliespositive current feedback to stabilize the speed of universalmotors. A ramp voltage synchronized to the ac line half cycleand compared to an external set voltage determines the firingangle. Negative gate pulses drive the triac in quadrants twoand three.

Because the speed of a universal motor decreases astorque increases, the TDA1185A lengthens the triac conduc-tion angle in proportion to the motor current, sensed throughresistor R9.

The TDA1185A is the best solution for low costapplications tolerating 5% motor speed variation. Openloop systems do not have a tachometer or negativefeedback and consequently cannot provide perfect speedcompensation.

CONSTANT SPEED MOTOR CONTROL USINGTACHOMETER FEEDBACK

Tachometer feedback sensing rotor speed providesexcellent performance with electric motors. The principal

advantages to be gained from tachometer feedback arethe ability to apply feedback control to shaded-polemotors, and better brush life in universal motors used infeedback circuits. This latter advantage results from theuse of full-wave rather than half-wave control, reducing thepeak currents for similar power levels.

THE TACHOMETERThe heart of this system is, of course, the speed-sensing

tachometer itself. Economy being one of the principal goalsof the design, it was decided to use a simple magnetictachometer incorporating the existing motor fan as anintegral part of the magnetic circuit. The generator consists ofa coil wound on a permanent magnet which is placed so thatthe moving fan blades provide a magnetic path of varyingreluctance as they move past the poles of the magnet.Several possible configurations of the magnetic system areshown in Figure 6.15.

Flux in a magnetic circuit can be found from the “magneticOhm’s law”:

φ MMFR

,

where φ = the flux,

MMF = the magnetomotive force (strength of themagnet), and

R = the reluctance of the magnetic path.

dφdt



Figure 6.15. (a). Locations for Magnetic SensingTachometer Generator Using a Horseshoe Magnet

(b). Locations for Magnetic Sensing TachometerGenerator Using an “L” or Bar Magnet

POSSIBLE MAGNET SHAPESAND LOCATIONS

FERROUSMOTOR HOUSING

FAN

MOTOR FAN

MAGNET

COIL WIRES

MOTORARMATURE

MAGNET

COILWIRES

SIDE VIEW

MOTOR FAN

TOP VIEW

MOTORARMATURE

MOTORARMATURE

Assuming the MMF of the permanent magnet to be constant,it is readily apparent that variations in reluctance will directlyaffect the flux. The steel fan blades provide a low-reluctancepath for the flux once it crosses the air gap between them andthe poles of the magnet. If the magnet used has a horseshoeor U shape, and is placed so that adjacent fan blades aredirectly opposite each pole in one position of the motorarmature, the magnetic path will be of relatively low reluc-tance; then as the motor turns the reluctance will increaseuntil one fan blade is precisely centered between the poles ofthe magnet. As rotation continues, the reluctance will thenalternately increase and decrease as the fan blades pass thepoles of the magnet. If a bar- or L-shaped magnet is used sothat one pole is close to the shaft or the frame of the motorand the other is near the fan blades, the magnetic pathreluctance will vary as each blade passes the magnet polenear the fan. In either case the varying reluctance causesvariations in the circuit flux and a voltage is generated in thecoil wound around the magnet. The voltage is given by theequation:

e –N dφdt

x10–8,

where e = the coil voltage in volts,N = the number of turns in the coil, and

= the rate of change of flux in lines persecond.

In a practical case, a typical small horseshoe magnet woundwith 1000 turns of wire generated a voltage of about 0.5volts/1000 rpm when mounted in a blender.

Since both generated voltage and frequency are directlyproportional to the motor speed, either parameter can beused as the feedback signal. However, circuits using voltagesensing are less complex and therefore less expensive. Onlythat system will be discussed here.

THE ELECTRONICSIn one basic circuit, which is shown in Figure 6.16, the

generator output is rectified by rectifier D1, then filtered andapplied between the positive supply voltage and the base ofthe detector transistor Q1. This provides a negative voltagewhich reduces the base-voltage on Q1 when the speedincreases.

The emitter of the detector transistor is connected to avoltage divider which is adjusted to the desired tachometeroutput voltage. In normal operation, if the tachometer voltageis less than desired, the detector transistor, Q1, is turned onby current through R1 into its base. Q1 then turns on Q2which causes the timing capacitor for programmable unijunc-tion transistor Q3 to charge quickly.

As the tachometer output approaches the voltage desired,the base-emitter voltage of Q1 is reduced to the point atwhich Q1 is almost cut off. Thereby, the collector current ofQ2, which charges the PUT timing capacitor, reduces,causing it to charge slowly and trigger the thyristor later in thehalf cycle. In this manner, the average power to the motor isreduced until just enough power to maintain the desiredmotor speed is allowed to flow.

Input circuit variations are used when the tachometeroutput voltage is too low to give a usable signal with a siliconrectifier. In the variation shown in Figure 6.16(b), thetachometer is connected between a voltage divider and thebase of the amplifier transistor. The voltage divider is set sothat with no tachometer output the transistor is just barely inconduction. As the tachometer output increases, QT is cut offon negative half cycles and conducts on positive half cycles.Resistors R9 and R10 provide a fixed gain for this amplifierstage, providing the hFE of QT is much greater than the ratioof R9 to R10. Thus the output of the amplifier is a fixedmultiple of the positive values of the tachometer waveform.The rectifier diode D1 prevents C1 from discharging throughR9 on negative half cycles of the tachometer. The


Figure 6.16. (a). Basic Tachometer Control Circuit

(b). Variation Used when the Tachometer Output isToo Low for Adequate Control

(c). Variation Providing Better Temperature Trackingand Easier Initial Adjustment

DETECTOR AND POWERCONTROL CIRCUIT

INPUT CIRCUIT

TACHOMETERGENERATOR

D1

C1R1 R2 R5R3

Q1

R4

C2

R6

Q2+ V2

120 VAC

LOAD

(PULSING dc)

(PURE dc)

R9 R1C1

D1QT

R10

TACH

R8

R7

D2

TACHR7

R10

D1QT

R9 C1 R1

+ V1

remainder of the filter and control circuitry is the same asthe basic circuit.

In the second variation, shown in 6.16(c), R8 has beenreplaced by a semiconductor diode, D2. Since the voltageand temperature characteristics more closely match those ofthe transistor base-to-emitter junction, this circuit is easier todesign and needs no initial adjustments as does the circuit in6.16(b). The remainder of this circuit is identical to that ofFigure 6.15.

In the second basic circuit, which is shown in Figure 6.17,the rectified and filtered tachometer voltage is added to theoutput voltage of the voltage divider formed by R1 and R2. Ifthe sum of the two voltages is less than V1 – VBE Q1 (whereVBE Q1 is the base-emitter voltage of Q1), Q1 will conduct acurrent proportional to V1 – VBE Q1, charging capacitor C. Ifthe sum of the two voltages is greater than V1 – VBE Q1, Q1will be cut off and no current will flow into the capacitor. The

operation of the remainder of the circuit is the same as thepreviously described circuits.

All of the described circuits show a PUT as the triggerdevice. An SBS may also be used as shown in Figure 6.18.The rectifier diode which is connected to the pulsing dcvoltage, V2, discharges the capacitor at the end of each halfcycle of the line voltage alternations, providing synchroniza-tion to the line voltage.

PHASE CONTROL WITH TRIGGER DEVICES

Phase control using thyristors is one of the most commonmeans of controlling the flow of power to electric motors,lamps, and heaters. With an ac voltage applied to the circuit,the gated thyristor (SCR, TRIAC, etc.) remains in its off-statefor the first portion of each half cycle of the power line, then,at a time (phase angle) determined by the control circuit, thethyristor switches on for the remainder of the half cycle. Bycontrolling the phase angle at which the thyristor is switchedon, the relative power in the load may be controlled.

PHASE CONTROL WITH PROGRAMMABLEUNIJUNCTION TRANSISTORS

PUTs provide a simple, convenient means for obtaining thethyristor trigger pulse synchronized to the ac line at acontrolled phase angle.

Figure 6.17. Another Basic Tachometer Circuit

Figure 6.18. SBS as an Alternative TriggeringDevice in Figures 6.15 and 6.16

+ V1 (PURE dc)

+ V2 PULSATING dc

LOAD

120 VAC

Q1

C

R1

TACH

R2

TOCHARGINGCIRCUIT

MBS4991

+ V2 120 VAC

LOAD

NOTE: V1 VBR OF TRIGGER



Figure 6.19. Basic Relaxation Oscillator Circuit (a)and Waveforms (b)

0

IBBRB1

VCG

RGK

Von

Voff

RB1

RB2 K

G A

CT

RT LOAD

VS

V

VC

APAC

ITO

RVO

LTAG

E

CT

VO

UTP

UT

VOLT

AGE

RB1

(a)

(b)

These circuits are all based on the simple relaxationoscillator circuit of Figure 6.19. RT and CT in the figure formthe timing network which determines the time between theapplication of voltage to the circuit (represented by theclosing of S1) and the initiation of the pulse. In the case of thecircuit shown, with Vs pure dc, the oscillator is free running,RT and CT determine the frequency of oscillation. The peakof the output pulse voltage is clipped by the forwardconduction voltage of the gate to cathode diode in thethyristor. The principal waveforms associated with the circuitare shown in Figure 6.19(b).

Operation of the circuit may best be described by referringto the capacitor voltage waveform. Following power applica-tion, CT charges at the rate determined by its own capaci-tance and the value of RT until its voltage reaches the peakpoint voltage of the PUT. Then the PUT switches intoconduction, discharging CT through RGK and the gate of thethyristor. With Vs pure dc, the cycle then repeats immediately;however, in many cases Vs is derived from the anode voltageof the thyristor so that the timing cycle cannot start again untilthe thyristor is blocking forward voltage and once againprovides Vs.

It is often necessary to synchronize the timing of the outputpulses to the power line voltage zero-crossing points. Onesimple method of accomplishing synchronization is shown inFigure 6.20. Zener diode D1 clips the rectified supply voltageresulting in a Vs as shown in 6.20(b). Since VS, and thereforethe peak point voltage of the PUT drops to zero each time theline voltage crosses zero, CT discharges at the end of everyhalf cycle and begins each half cycle in the discharged state.Thus, even if the PUT has not triggered during one half cycle,the capacitor begins the next half cycle discharged. Conse-quently, the values of RT and CT directly control the phaseangle at which the pulse occurs on each half cycle. Thezener diode also provides voltage stabilization for the timingcircuit giving the same pulse phase angle regardless ofnormal line voltage fluctuations.

APPLICATIONSThe most elementary application of the PUT trigger circuit,

shown in Figure 6.21, is a half-wave control circuit. In thiscircuit, RD is selected to limit the current through D1 so thatthe diode dissipation capability is not exceeded. Dividing the

LINE

D1

CT

R3

R2

VS

R1RT

RD

ACLINE

D1 1N5250A

CT0.1 µF

2N6027

R3 100 k

R2 10 kMCR8D

100 kRT

6.8 k2 W

R1 5.1 k

RD600 W

LOAD

RECTIFIEDSINE WAVEVS

(a)

Figure 6.20. Control Circuit (a) with ZenerClipped,Rectified Voltage (b)

(b)

Figure 6.21. Half Wave Control Circuit with TypicalValues for a 600 Watt Resistive Load


allowable diode dissipation by one-half the zener voltage willgive the allowable positive current in the diode since it isconducting in the voltage regulating mode only duringpositive half cycles. Once the positive half-cycle current isfound, the resistor value may be calculated by subtracting0.7 times the zener voltage from the rms line voltage anddividing the result by the positive current:

RDErms 0.7 Vz

Ipositive

The power rating of RD must be calculated on the basis of fullwave conduction as D1 is conducting on the negative halfcycle acting as a shunt rectifier as well as providing Vs on thepositive half cycle.

The thyristor is acting both as a power control device and arectifier, providing variable power to the load during thepositive half cycle and no power to the load during thenegative half cycle. The circuit is designed to be a twoterminal control which can be inserted in place of a switch. Iffull wave power is desired as the upper extreme of thiscontrol, a switch can be added which will short circuit theSCR when RT is turned to its maximum power position. Theswitch may be placed in parallel with the SCR if the load is

Figure 6.22. Half Wave Controls with Switching forFull Wave Operation

(a). Resistive Load

(b). Inductive Load

Figure 6.23. A Simple Full Wave Trigger Circuit withTypical Values for a 900 Watt Resistive Load

CONTROLCIRCUIT

CONTROLCIRCUIT

900 W

LOAD

LINE

MDA920A4

1N5250A

6.8 k2 W

RD

RT

D1

2N6027100 k R1 5.1 k

10 kR2

CT0.1 µF

DALEPT50

(OR EQUIVALENT)

R3100 k

MAC12D

resistive; however, if the load is inductive, the load must betransferred from the SCR to the direct line as shown in Figure6.22.

Full wave control may be realized by the addition of abridge rectifier, a pulse transformer, and by changing thethyristor from an SCR to a TRIAC, shown in Figure 6.23.

Occasionally a circuit is required which will provideconstant output voltage regardless of line voltage changes.Adding potentiometer P1, as shown in Figure 6.24, to thecircuits of Figures 6.21 and 6.23, will provide an approximatesolution to this problem. The potentiometer is adjusted toprovide reasonably constant output over the desired range ofline voltage. As the line voltage increases, so does thevoltage on the wiper of P1 increasing VS and thus the peakpoint voltage of the PUT. The increased peak point voltageresults in CT charging to a higher voltage and thus takingmore time to trigger. The additional delay reduces thethyristor conduction angle and maintains the average voltageat a reasonably constant value.

FEEDBACK CIRCUITSThe circuits described so far have been manual control

circuits; i.e., the power output is controlled by a potentiometerturned by hand. Simple feedback circuits may be constructedby replacing RT with heat or light-dependent sensingresistors; however, these circuits have no means of adjustingthe operating levels. The addition of a transistor to the circuitsof Figures 6.21 and 6.23 allows complete control.

Figure 6.25 shows a feedback control using a sensingresistor for feedback. The sensing resistor may respond toany one of many stimuli such as heat, light, moisture,pressure, or magnetic field. Rs is the sensing resistor and Rcis the control resistor that establishes the desired operatingpoint. Transistor Q1 is connected as an emitter follower suchthat an increase in the resistance of Rs decreases thevoltage on the base of Q1, causing more current to flow.

Figure 6.24. Circuit for Line Voltage Compensation

Figure 6.25. Feedback Control Circuit

Rs*

*Rs SHOULD BE SELECTED TO BE ABOUT 3 k TO 5 k OHMS AT THE DESIRED OUTPUT LEVEL

RECTIFIEDLINE(FULL ORHALF WAVE)

RD

6.8 k

Rc100 k

1N5250AD1

Q1

CT0.1 µF

2N6027MPS6512

10 k

RT(MIN)

10 k

100

5.1 k

TO THYRISTOR

GATE-CATHODE

RECTIFIEDLINE(FULL ORHALF WAVE) CT

0.1 µF

D11N5250A

6.8 k

RD

500

P1

RT

100

100 k

2N6027

RG1

RGK

RG2

5.1 k

10 k

TO THYRISTOR

GATE-CATHODE



Current through Q1 charges CT, triggering the PUT at adelayed phase angle. As Rs becomes larger, more chargingcurrent flows, causing the capacitor voltage to increase morerapidly. This triggers the PUT with less phase delay, boostingpower to the load. When Rs decreases, less power is appliedto the load. Thus, this circuit is for a sensing resistor whichdecreases in response to too much power in the load. If thesensing resistor increases with load power, then Rs and Rcshould be interchanged.

Figure 6.26. Voltage Feedback Circuit

Figure 6.27. Half Wave, Average Voltage Feedback

Figure 6.28. Full Wave, Average VoltageFeedback Control

MCR218-4(2)

RG10

es

6.8 k

AC LINE

1N4721(2)

1N4003(2)

DALE PT50(OR EQUIVALENT)

D11N5250A

T10µFC1

CT0.1 µF

2N6028

DCLOAD

R230 k

R1100 k

MPS6512

Q12 k6.8 k2 WRD

RG

T

DCLOAD600 W

R230 k

C110 µF

2N6028

CT0.1 µF

T

1N5250A

RC1 k

2 k MPS6512Q1

TDALE PT50

(OR EQUIVALENT)

MCR218-4

6.8 kRD

ACLINE

R1

MPS6512

CT 100

10 k

TOTHYRISTOR

GATE-CATHODE

5.1 k2N6027

RT(MIN)10 k

Rc100 k1N5250A

RECTIFIEDLINE

R1100 k

3.9

k

3.9

k

10

0.1 µF

If the quantity to be sensed can be fed back to the circuit inthe form of an isolated, varying dc voltage such as the outputof a tachometer, it may be inserted between the voltagedivider and the base of Q1 with the proper polarity. In thiscase, the voltage divider would be a potentiometer to adjustthe operating point. Such a circuit is shown in Figure 6.26.

In some cases, average load voltage is the desiredfeedback variable. In a half wave circuit this type of feedbackusually requires the addition of a pulse transformer, shown inFigure 6.27. The RC network, R1, R2, C1, averages loadvoltage so that it may be compared with the set point on Rsby Q1. Full wave operation of this type of circuit requires dc inthe load as well as the control circuit. Figure 6.28 is onemethod of obtaining this full wave control.

Each SCR conducts on alternate half-cycles and suppliespulsating dc to the load. The resistors (Rg) insure sharing ofthe gate current between the simultaneously driven SCRs.Each SCR is gated while blocking the line voltage everyother half cycle. This momentarily increases reverse blockingleakage and power dissipation. However, the leakage powerloss is negligible due to the low line voltage and duty cycle ofthe gate pulse.

There are, of course, many more sophisticated circuitswhich can be derived from the basic circuits discussed here.If, for example, very close temperature control is desired, thecircuit of Figure 6.25 might not have sufficient gain. To solvethis problem a dc amplifier could be inserted between thevoltage divider and the control transistor gate to provide asclose a control as desired. Other modifications to addmultiple inputs, switched gains, ramp and pedestal control,etc., are all simple additions to add sophistication.

CLOSED LOOP UNIVERSAL MOTOR SPEEDCONTROL

Figure 6.29 illustrates a typical tachometer stabilizedclosed feedback loop control using the TDA1285A integratedcircuit. This circuit operates off the ac line and generates aphase angle varied trigger pulse to control the triac. It usesinductive or hall effect speed sensors, controls motor startingacceleration and current, and provides a 1 to 2% speedvariation for temperature and load variations.

CYCLE CONTROL WITH OPTICALLYISOLATED TRIAC DRIVERS

In addition to the phase control circuits, TRIAC drivers canalso be used for ac power control by on-off or burst control, ofa number of ac cycles. This form of power control allows logiccircuits and microprocessors to easily control ac power withTRIAC drivers of both the zero-crossing and non zero-cross-ing varieties.


NOTES:Frequency to Voltage converter—Max. motor speed 30,000 rpm—Tachogenerator 4 pairs of poles: max. frequency =

—C11 = 680 pF. R4 adjusted to obtain VPin 4 = 12 V at max. speed: 68 kΩ—Power Supplywith Vmains = 120 Vac, R1 = 4.7 kΩ. Perfect operationwill occur down to 80 Vac.

30, 00060

x 4 2 kHz

TDA1285A

126

C5

10 NF

C4100 nF

R41.0 MΩ

1.5 µF220 nF

220 k

330 nF

C1447 nF

+VCC

47 µF

0.1 µF

22 k 0.1 µF

R3

2.2 k

220 nF1.0 µF

C7

C11

R1

10 k 1N4005

820 k

820 k

InductiveTACHOM

3

220 V

13

1291410

126711854

16 TDA1285A

47 k

HALL-EFFECTSENSOR

M

Figure 6.29. (a). Motor Control Circuit

(b). Circuit Modificationsto Connect a Hall-Effect Sensor

USING NON-ZERO CROSSING OPTICALLYISOLATED TRIAC DRIVERSUSING THE MOC3011 ON 240 VAC LINES

The rated voltage of a MOC3011 is not sufficiently high forit to be used directly on 240 V line; however, the designermay stack two of them in series. When used this way, tworesistors are required to equalize the voltage dropped acrossthem as shown in Figure 6.30.

REMOTE CONTROL OF AC VOLTAGELocal building codes frequently require all 115 V light

switch wiring to be enclosed in conduit. By using aMOC3011, a TRIAC, and a low voltage source, it is possibleto control a large lighting load from a long distance throughlow voltage signal wiring which is completely isolated fromthe ac line. Such wiring usually is not required to be put inconduit, so the cost savings in installing a lighting systemin commercial or residential buildings can be considerable.An example is shown in Figure 6.30. Naturally, the load couldalso be a motor, fan, pool pump, etc.

LOAD

MOC3011

MOC3011

150+ 5 V

λ

λ 1 M

1 M

1 k

240 Vac

180

Figure 6.30. Two MOC3011 TRIAC Drivers in Series to Drive 240 V TRIAC



λ

NON-CONDUIT #22 WIRE

5 V

360

MOC3011

180

115 V

2N6342A

Figure 6.31. Remote Control of AC Loads Through Low Voltage Non-Conduit Cable

SOLID STATE RELAYFigure 6.31 shows a complete general purpose, solid state

relay snubbed for inductive loads with input protection. Whenthe designer has more control of the input and outputconditions, he can eliminate those components which are notneeded for his particular application to make the circuit morecost effective.

INTERFACING MICROPROCESSORS TO 115 VACPERIPHERALS

The output of a typical microcomputer input-output (I/O)port is a TTL-compatible terminal capable of driving one ortwo TTL loads. This is not quite enough to drive theMOC3011, nor can it be connected directly to an SCR orTRIAC, because computer common is not normally refer-enced to one side of the ac supply. Standard 7400 seriesgates can provide an input compatible with the output of anMC6821, MC6846 or similar peripheral interface adaptor andcan directly drive the MOC3011. If the second input of a 2input gate is tied to a simple timing circuit, it will also provideenergization of the TRIAC only at the zero crossing of the ac

line voltage as shown in Figure 6.33. This technique extendsthe life of incandescent lamps, reduces the surge currentstrains on the TRIAC, and reduces EMI generated by loadswitching. Of course, zero crossing can be generated withinthe microcomputer itself, but this requires considerable soft-ware overhead and usually just as much hardware to gener-ate the zero-crossing timing signals

APPLICATIONS USING THE ZERO CROSSINGTRIAC DRIVER

For applications where EMI induced, non-zero crossing-load switching is a problem, the zero crossing TRIAC driver isthe answer. This TRIAC driver can greatly simplify thesuppression of EMI for only a nominal increased cost.Examples of several applications using the MOC3031, 41follows.

115 V2N6071B

10 k

0.1 µF

2.4 k180

47

MOC30112N3904

2 W1N4002

150

λ

Figure 6.32. Solid-State Relay


Figure 6.33. Interfacing an M6800 Microcomputer System to 115 Vac Loads

115 V(RESISTIVELOAD)

+ 5 V

200 W

115 V(INDUCTIVELOAD)

2N6071

2N6071B

MOTOR

0.1 µF

2.4 k

180

180

ADDRESS

DATA

MC6800OR

MC6802MPU

MC6820OR

MC6821OR

MC6846I/O

115 V6.3 V

3 k

100 k

2N3904

1 k5 V

OPTIONALZERO-CROSSINGCIRCUITRY

7400

+ 5 V

300

300

OPTO TRIACDRIVERS

MOC3011

MOC3011

MATRIX SWITCHINGMatrix, or point-to-point switching, represents a method of

controlling many loads using a minimum number of compo-nents. On the 115 V line, the MOC3031 is ideal for thisapplication; refer to Figure 6.34. The large static dv/dt ratingof the MOC3031 prevents unwanted loads from beingtriggered on. This might occur, in the case of non-zerocrossing TRIAC drivers, when a TRIAC driver on a verticalline was subjected to a large voltage ramp due to a TRIAC on

a horizontal line being switched on. Since non-zero crossingTRIAC drivers have lower static dv/dt ratings, this rampwould be sufficiently large to trigger the device on.

R is determined as before:

R(min)Vin(pk)

ITSM

170 V1.2 A

150 ohms

CONTROL BUS

150 Ω

MOC3031

LOAD

LOAD

LOAD

150 Ω

MOC3031

LOAD

LOAD

LOAD

150 Ω

MOC3031

115 V

150 Ω

MOC3031

LOAD

150 Ω

MOC3031

LOAD

150 ΩLOAD

MOC3031

Figure 6.34. Matrix Switching



POWERRELAY

(230 VAC COIL)

300 Ω

MOC3041

CONTROL

230 VAC

LOAD

LOAD

LOAD

LOAD

Figure 6.35. Power Relay Control

POWER RELAYSThe use of high-power relays to control the application of

ac power to various loads is a very widespread practice.Their low contact resistance causes very little power loss andmany options in power control are possible due to theirmultipole-multithrow capability. The MOC3041 is well suitedto the use of power relays on the 230 Vac line; refer to Figure6.35. The large static dv/dt of this device makes a snubbernetwork unnecessary, thus reducing component count andthe amount of printed circuit board space required. Anon-zero crossing TRAIC driver (MOC3021) could be used inthis application, but its lower static dv/dt rating wouldnecessitate a snubber network.

MICROCOMPUTER INTERFACEThe output of most microcomputer input/output (I/O) ports

is a TTL signal capable of driving several TTL gates. This isinsufficient to drive a zero-crossing TRIAC driver. In addition,it cannot be used to drive an SCR or TRIAC directly, becausecomputer common is not usually referenced to one side ofthe ac supply. However, standard 7400 NAND gates can beused as buffers to accept the output of the I/O port and inturn, drive the MOC3031 and/or MOC3041; refer to Figure6.36.

The zero-crossing feature of these devices extends the lifeof incandescent lamps, reduces inrush currents and mini-mizes EMI generated by load switching.

AC MOTORSThe large static dv/dt rating of the zero-crossing TRIAC

drivers make them ideal when controlling ac motors. Figure6.37 shows a circuit for reversing a two phase motor usingthe MOC3041. The higher voltage MOC3041 is required,even on the 115 Vac line, due to the mutual and self-induc-tance of each of the motor windings, which may cause avoltage much higher than 115 Vac to appear across thewinding which is not conducting current.

DETERMINING LIMITING RESISTOR R FOR AHIGH-WATTAGE INCANDESCENT LAMP

Many high-wattage incandescent lamps suffer shortenedlifetimes when switched on at ac line voltages other thanzero. This is due to a large inrush current destroying thefilament. A simple solution to this problem is the use of theMOC3041 as shown in Figure 6.38. The MOC3041 may becontrolled from a switch or some form of digital logic.

1 kΩ

MC6820ORMC6821ORMC6846I/O

+ 5 V

7400

+ 5 V

300

300

MOC3041

MOC3031

230 V(INDUCTIVELOAD)

115 V(RESISTIVELOAD)

150 Ω

300 Ω

2N6073

MOTOR

2N6071

200 W+ 5 V

MC68000MPU

DATA

ADDRESS

Figure 6.36. M68000 Microcomputer Interface


OPTIONALCURRENT LIMITING RESISTOR

MOC3041

300C

R

MOTOR

300

MOC3041

115 V

Figure 6.37. Reversing Motor Circuit

The minimum value of R is determined by the maximumsurge current rating of the MOC3041 (ITSM):

R(min)Vin(pk)

ITSM

Vin(pk)

1.2 A

(10)

On a 230 Vac Line:

R(min)340 V1.2 A

283 ohms (11)

In reality, this would be a 300 ohm resistor.

AC POWER CONTROL WITH SOLID-STATERELAYS

The Solid-State Relay (SSR) as described below, is a relayfunction with:

a. . Four Terminals (Two Input, Two Output)b. . DC or AC Input

c. . Optical Isolation Between Input and Outputd. . Thyristor (SCR or TRIAC) Outpute. . Zero Voltage Switching Output (Will Only Turn On

Close to Zero Volts)f. . AC Output (50 or 60 Hz)

Figure 6.39 shows the general format and waveforms ofthe SSR. The input on/off signal is conditioned (perhaps onlyby a resistor) and fed to the Light-Emitting-Diode (LED) of anoptoelectronic-coupler. This is ANDed with a go signal that isgenerated close to the zero-crossing of the line, typically 10 Volts. Thus, the output is not gated on via the amplifierexcept at the zero-crossing of the line voltage. The SSRoutput is then re-gated on at the beginning of every half-cycleuntil the input on signal is removed. When this happens, thethyristor output stays on until the load current reaches zero,and then turns off.

ADVANTAGES AND DISADVANTAGES OF SSRsThe SSR has several advantages that make it an attractive

choice over its progenitor, the Electromechanical Relay(EMR) although the SSR generally costs more than itselectromechanical counterpart. These advantages are:

300

R

LAMP

230 VSWITCH ORDIGITAL LOGIC

MOC3041

Figure 6.38. High-Wattage Lamp Control



LINE

LOAD

POWERSWITCH

AMPL

AND

GO/NO GO

ZERO CROSSDETECTOR

ON/OFFINPUT LED

Figure 6.39. SSR Block Diagram

NO GO

LINE 0

GO

ONOFF

OUTPUT

1. No Moving Parts — the SSR is all solid-state. Thereare no bearing surfaces to wear, springs to fatigue, as-semblies to pick up dust and rust. This leads to severalother advantages.2. No Contact Bounce — this in turn means no contactwear, arcing, or Electromagnetic Interference (EMI)associated with contact bounce.3. Fast Operation — usually less than 10 µs. Fast turn-on time allows the SSR to be easily synchronized withline zero-crossing. This also minimizes EMI and cangreatly increase the lifetime of tungsten lamps, of consid-erable value in applications such as traffic signals.4. Shock and Vibration Resistance — the solid-statecontact cannot be “shaken open” as easily as the EMRcontact.5. Absence of Audible Noise — this devolves from thelack of moving mechanical parts.6. Output Contact Latching — the thyristor is a latchingdevice, and turns off only at the load current zero-cross-ing, minimizing EMI.7. High Sensitivity — the SSR can readily be designedto interface directly with TTL and CMOS logic, simplifyingcircuit design.8. Very Low Coupling Capacitance Between Input andOutput. This is a characteristic inherent in the optoelec-tronic-coupler used in the SSR, and can be useful in

areas such as medical electronics where the reduction ofstray leakage paths is important.

This list of advantages is impressive, but of course, thedesigner has to consider the following disadvantages:

1. Voltage Transient Resistance — the ac line is notthe clean sine wave obtainable from a signal genera-tor. Superimposed on the line are voltage spikes frommotors, solenoids, EMRs (ironical), lightning, etc. Thesolid-state components in the SSR have a finite volt-age rating and must be protected from such spikes,either with RC networks (snubbing), zener diodes,MOVs or selenium voltage clippers. If not done, thethyristors will turn on for part of a half cycle, and atworst, they will be permanently damaged, and fail toblock voltage. For critical applications a safety marginon voltage of 2 to 1 or better should be sought.

The voltage transient has at least two facets — the firstis the sheer amplitude, already discussed. The secondis its frequency, or rate-of-rise of voltage (dv/dt). All thy-ristors are sensitive to dv/dt to some extent, and the tran-sient must be snubbed, or “soaked up,” to below this levelwith an RC network.(1) Typically this rating (“critical” or“static” dv/dt) is 50 to 100 V/µs at maximum temperature.Again the failure mode is to let through, to a half-cycle ofthe line, though a high energy transient can cause per-manent damage. Table 6.1 gives some starting points forsnubbing circuit values. The component values requireddepend on the characteristics of the transient, which areusually difficult to quantify. Snubbing across the line aswell as across the SSR will also help.

Table 6.1. Typical Snubbing Values

Load CurrentA rms

ResistanceΩ

CapacitanceµF

5 47 0.047

10 33 0.1

25 10 0.22

40 22 0.47

1. For a more thorough discussion of snubbers, see page 1-3.9.


Q2

INPUT AND CONTROL CIRCUIT TRIAC POWER CIRCUITLINE

R12

TR11

C11

R13

LOADR11

BR11

+

–

R4 R6

SCR1

D2

R7R5C2

Q1

R3

R2C1

OC1

–

+INPUT

D1

R1

FIRING WINDOW

FIRINGWINDOWWITHC1 AND C2

(d)

FIRINGWINDOWWITHOUTC1 AND C2

(c)

FIRINGWINDOW

“ZERO” VOLTAGEFIRING LEVEL

(b)

VSCR1

E

Figure 6.40(a). TRIAC SSR Circuit

Figure 6.40. Firing Windows

LIN

E ZE

RO

CR

OSS

ING



2. Voltage Drop — The SSR output contact has someoffset voltage — approximately 1 V, depending on cur-rent, causing dissipation. As the thyristor has an oper-ating temperature limit of +125°C, this heat must beremoved, usually by conduction to air via a heat sink orthe chassis.3. Leakage Current — When an EMR is open, no cur-rent can flow. When an SSR is open however, it doesnot have as definite an off condition. There is alwayssome current leakage through the output powerswitching thyristor, the control circuitry, and the snub-bing network. The total of this leakage is usually 1 to10 mA rms — three or four orders of magnitude lessthan the on-state current rating.4. Multiple Poles — are costly to obtain in SSRs, andthree phase applications may be difficult to implement.5. Nuclear Radiation — SSRs will be damaged by nu-clear radiation.

TRIAC SSR CIRCUIT

Many SSR circuits use a TRIAC as the output switchingdevice. Figure 6.40(a) shows a typical TRIAC SSR circuit.The control circuit is used in the SCR relay as well, and isdefined separately. The input circuit is TTL compatible.Output snubbing for inductive loads will be described later.

A sensitive-gate SCR (SCR1) is used to gate the powerTRIAC, and a transistor amplifier is used as an interfacebetween the optoelectronic-coupler and SCR1. (A sensitive-gate SCR and a diode bridge are used in preference to asensitive gate TRIAC because of the higher sensitivity of theSCR.)

CONTROL CIRCUIT OPERATIONThe operation of the control circuit is straightforward. The

AND function of Figure 6.39 is performed by the wired-NORcollector configuration of the small-signal transistors Q1 andQ2. Q1 clamps the gate of SCR1 if optoelectronic-couplerOC1 is off. Q2 clamps the gate if there is sufficient voltage at

Table 6.2. Control Circuit Parts List

Line Voltage

Part 120 V rms 240 V rms

C1 220 pF, 20%, 200 Vdc 100 pF, 20%, 400 VdcC1C2

220 F, 20%, 200 Vdc0.022 µF, 20%, 50 Vdc

100 F, 20%, 400 Vdc0.022 µF, 20%, 50 Vdc

D1µ

1N4001µ

1N4001D2

OC11N4001MOC1005

1N4001MOC1005OC1

Q1MOC1005MPS5172

MOC1005MPS5172Q1

Q2MPS5172MPS5172

MPS5172MPS5172Q2

R1MPS51721 kΩ, 10%, 1 W

MPS51721 kΩ, 10%, 1 WR1

R21 kΩ, 10%, 1 W47 kΩ, 5%, 1/2 W

1 kΩ, 10%, 1 W100 kΩ, 5%, 1 W

R3, ,

1 MΩ, 10%, 1/4 W, ,

1 MΩ, 10%, 1/4 WR4R5

110 kΩ, 5%, 1/2 W15 kΩ 5% 1/4 W

220 kΩ, 5%, 1/2 W15 kΩ 5% 1/4 WR5

R615 kΩ, 5%, 1/4 W33 kΩ 10% 1/2 W

15 kΩ, 5%, 1/4 W68 kΩ 10% 1 WR6

R733 kΩ, 10%, 1/2 W10 kΩ 10% 1/4 W

68 kΩ, 10%, 1 W10 kΩ 10% 1/4 WR7

SCR110 kΩ, 10%, 1/4 W2N5064

10 kΩ, 10%, 1/4 W2N6240SCR1 2N5064 2N6240

the junction of the potential divider R4,R5 to overcome theVBE of Q2. By judicious selection of R4 and R5, Q2 will clampSCR1’s gate if more than approximately 5 Volts appear at theanode of SCR1; i.e., Q2 is the zero-crossing detector.

If OC1 is on, Q1 is clamped off, and SCR1 can be turnedon by current flowing down R6, only if Q2 is also off —which it is only at zero crossing.

The capacitors are added to eliminate circuit raceconditions and spurious firing, time ambiguities in opera-tion. Figure 6.40(b) shows the full-wave rectified line thatappears across the control circuit. The zero voltage firinglevel is shown in 6.40(b) and 6.40(c), expanded in time andvoltage. A race condition exists on the up-slope of thesecond half-cycle in that SCR1 may be triggered via R6before Q1 has enough base current via R2 to clampSCR1’s gate. C1 provides current by virtue of the rate ofchange of the supply voltage, and Q1 is turned on firmly asthe supply voltage starts to rise, eliminating any possibilityof unwanted firing of the SSR; thus eliminating the racecondition.

This leaves the possibility of unwanted firing of the SSRon the down-slope of the first half cycle shown. C2provides a phase shift to the zero voltage potential divider,and Q2 is held on through the real zero-crossing. Theresultant window is shown in 6.40(d).

CONTROL CIRCUIT COMPONENTSThe parts list for the control circuit at two line voltages is

shown in Table 6.2.R1 limits the current in the input LED of OC1. The input

circuit will function over the range of 3 to 33 Vdc.D1 provides reverse voltage protection for the input of

OC1.D2 allows the gate of SCR1 to be reverse biased,

providing better noise immunity and dv/dt performance.R7 eliminates pickup on SCR1’s gate through the

zero-crossing interval.SCR1 is a sensitive gate SCR; the 2N5064 is a TO-92

device, the 2N6240 is a Case 77 device.Alternatives to the simple series resistor (R1) input

circuit will be described later.

POWER CIRCUIT COMPONENTSThe parts list for the TRIAC power circuit in Figure

6.40(a) is shown in Table 6.3 for several rms currentratings, and two line voltages. The metal TRIACs are in thehalf-inch pressfit package in the isolated stud configura-tion; the plastic TRIACs are in the TO-220 Thermowattpackage. R12 is chosen by calculating the peak controlcircuit off-state leakage current and ensuring that thevoltage drop across R12 is less than the VGT(MIN) of theTRIAC.

C11 must be an ac rated capacitor, and with R13provides some snubbing for the TRIAC. The values shownfor this network are intended more for inductive loadcommutating dv/dt snubbing than for voltage transientsuppression. Consult the individual data sheets for thedissipation, temperature, and surge current limits of theTRIACs.


Table 6.3. TRIAC Power Circuit Parts List

Voltage 120 V rms 240 V rms

rms Current Amperes 8 12 25 40 8 12 25 40

BR11 IN4004(4) IN4004(4) IN4004(4) IN4004(4) IN4004(4) IN4004(4) IN4004(4) IN4004(4)

C11, µF(10%, line voltage ac rated)

0.047 0.047 0.1 0.1 0.047 0.047 0.1 0.1

R11(10%, 1 W)

39 39 39 39 39 39 39 39

R12(10%, 1/2 W)

18 18 18 18 18 18 18 18

R13(10%, 1/2 W)

620 620 330 330 620 620 330 330

TR11 Plastic 2N6342 2N6342A 2N6343 2N6343ATR11 Plastic 2N6342 2N6342A — — 2N6343 2N6343A — —

TRIACs AND INDUCTIVE LOADSThe TRIAC is a single device which to some extent is the

equivalent of two SCRs inverse parallel connected; certainlythis is so for resistive loads. Inductive loads however, cancause problems for TRIACs, especially at turn-off.

A TRIAC turns off every line half-cycle when the linecurrent goes through zero. With a resistive load, thiscoincides with the line voltage also going through zero. TheTRIAC must regain blocking-state before there are more than1 or 2 Volts of the reverse polarity across it — at 120 V rms,60 Hz line this is approximately 30 µs. The TRIAC has notcompletely regained its off-state characteristics, but does soas the line voltage increases at the 60 Hz rate.

Figure 6.41 indicates what happens with an inductive orlagging load. The on signal is removed asynchronouslyand the TRIAC, a latching device, stays on until the nextcurrent zero. As the current is lagging the applied voltage,the line voltage at that instant appears across the TRIAC.It is this rate-of-rise of voltage, the commutating dv/dt, thatmust be limited in TRIAC circuits, usually to a few volts per

microsecond. This is normally done by use of a snubbernetwork RS and CS as shown in Figure 6.42.

SCRs have less trouble as each device has a fullhalf-cycle to turn off and, once off, can resist dv/dt to thecritical value of 50 to 100 V/µs.

CHOOSING THE SNUBBING COMPONENTS(1)There are no easy methods for selecting the values of RS

and CS in Figure 6.42 required to limit commutating dv/dt.The circuit is a damped tuned circuit comprised by RS, CS, RLand LL, and to a minor extent the junction capacitance of theTRIAC. At turn-off this circuit receives a step impulse of linevoltage which depends on the power factor of the load.Assuming the load is fixed, which is normally the case, thedesigner can vary RS and CS. CS can be increased todecrease the commutating dv/dt; RS can be increased todecrease the resonant over-ring of the tuned circuit — toincrease damping. This can be done empirically, beginningwith the values for C11 and R13 given in Table 6.3, and aiming

1. For a more thorough discussion of snubbers, see page 1-3-9.

TRIAC VOLTAGE

0

0

OFF

ON

dv/dtLINE VOLTAGE

LINE ANDTRIAC VOLTAGE

LOAD CURRENT

ON/OFFSIGNAL

(LAGGING LOAD)

Figure 6.41. Commutating dv/dt



Table 6.4. SCR Power Circuit Parts List

Voltage 120 V rms 240 V rms

rms Current Amperes 5 11 22 49 5 11 22 49

C21 (10%, line voltage ac rated) SEE TEXT

D21-24 1N4003 1N4003 1N4003 1N4003 1N4004 1N4004 1N4004 1N4004

R21 (10%, 1 W) 39 39 39 39 39 39 39 39

R22, 23 (10%, 1/2 W) 18 18 18 18 18 18 18 18

R24 SEE TEXT

SCR21 22 Plastic 2N6239 2N6396 2N6402 2N6240 2N6397 2N6403SCR21, 22 Plastic 2N6239 2N6396 2N6402 — 2N6240 2N6397 2N6403 —

CS

RS

RL

LOADLL

Figure 6.42. TRIAC with Snubber Networkat close to critical damping and the data sheet value forcommutating dv/dt. Reduced temperatures, voltages, andoff-going di/dt (rate-of-change of current at turn-off) will givesome safety margin.

SCR SSR CIRCUITThe inverse parallel connected Silicon Controlled Rectifier

(SCR) pair (shown in Figure 6.43) is less sensitive tocommutating dv/dt. Other advantages are the improvedthermal and surge characteristics of having two devices; thedisadvantage is increased cost.

The SCR power circuit can use the same control circuit asthe TRIAC Circuit shown in Figure 6.40(a). In Figure 6.43, forpositive load terminal and when the control circuit is gatedon, current flows through the load, D21, R21, SCR1, D22, thegate of SCR21 and back to the line, thus turning on SCR21.Operation is similar for the other line polarity. R22 and R23provide a path for the off-state leakage of the control circuitand are chosen so that the voltage dropped across them isless than the VGT(MIN) of the particular SCR. R24 and C21provide snubbing and line transient suppression, and may bechosen from Table 6.4 or from the C11, R13 rows of Table6.3. The latter values will provide less transient protection butalso less off-state current, with the capacitor being smaller.Other circuit values are shown in Table 6.46.

CONTROLCIRCUIT

(SEE FIGURE 6.39(a)AND TABLE 6.II)

R21

LINE

LOAD

SCR22

SCR21

D21

D24

D22

D23

R22

R24

C21

+ +

–

R23

–

INPUT

Figure 6.43. SCR SSR Circuit


Consult the individual data sheets for packages anddissipation, temperature, and surge current limits.

While the SCRs have much higher dv/dt commutationability, with inductive loads, attention should be paid tomaintaining the dv/dt below data sheet levels.

ALTERNATE INPUT CIRCUITSCMOS COMPATIBLE

The 1 kΩ resistor, R1, shown in Figure 6.40(a) and Table6.2, provide an input that is compatible with the current that aTTL gate output can sink. The resistor R1 must be changedfor CMOS compatibility, aiming at 2 mA in the LED foradequate performance to 100°C. At 2 mA do not use theCMOS output for any other function, as a LOGIC 0 or 1 maynot be guaranteed. Assume a forward voltage drop of 1.1 Vfor the LED, and then make the Ohm’s Law calculation for thesystem dc supply voltage, thus defining a new value for R1.

TTL/CMOS COMPATIBLETo be TTL compatible at 5 Volts and CMOS compatible

over 3 to 15 Volts, a constant current circuit is required, suchas the one in Figure 6.44. The current is set by the VBE ofQ31 and the resistance of the R32, R33, and thermistorTH31 network, and is between 1 and 2 mA, higher at hightemperatures to compensate for the reduced transmissionefficiency of optoelectronic-couplers at higher temperature.The circuit of Figure 6.44 gives an equivalent impedance ofapproximately 50 kΩ. The circuit performs adequately over 3to 33 Vdc and –40 to +100°C. Note that though the SSR isprotected against damage from improperly connected inputs,the external circuit is not, as D31 acts as a bypass for awrongly connected input driver.

AC LINE COMPATIBLETo use SSRs as logic switching elements is inefficient,

considering the availability and versatility of logic familiessuch as CMOS. When it is convenient to trigger from ac, acircuit such as shown in Figure 6.45 may be used. Thecapacitor C41 is required to provide current to the LED ofOC1 through the zero-crossing time. An in-phase inputvoltage gives the worst case condition. The circuit gives 2mA minimum LED current at 75% of nominal line voltage.

R31330 k

TH31 WESTERN THERMISTORCORP., CURVE 2,650 Ω ± 10% @ 25°CP/N2C6500 OREQUIVALENT

2N6427

R32330

OC1

Q32

Q31MPS5172

D311N4001

+

INPUT

TH31

R33180

–Figure 6.44. TTL /CMOS Compatible Input

INVERSE PARALLEL SCRs FOR POWERCONTROL

TRIACs are very useful devices. They end up in solid staterelays, lamp drivers, motor controls, sensing and detectioncircuits; just about any industrial full-wave application. But inhigh-frequency applications or those requiring high voltageor current, their role is limited by their present physicalcharacteristics, and they become very expensive at currentlevels above 40 amperes rms.

SCRs can be used in an inverse-parallel connection tobypass the limitations of a TRIAC. A simple scheme for doingthis is shown in Figure 6.46.The control device can take any

2 µF10%50 V

2 kΩ, 10%1/2 W

47 kΩ, 10%, 2 W22 kΩ, 10%, 1 W

240 V120 V

R42

R41

OC1INPUT AC

C41

BR41

R41

Figure 6.45. AC Compatible Input



ILa

FLOATINGLOAD RL

ba2V

SCR1OR

ILb

2

IG1

1IG

R

AA

CONTROL DEVICE(CLOSED RESISTANCE)

RC

IG2GROUNDEDLOAD RL

WHERE IGP ISPEAK GATECURRENTRATING OF SCR

SCR2

R 2 V

IGP (RLRC)

Figure 6.46. Use of Inverse Parallel SCRs

of many forms, shown is the reed relay (Figure 6.46). TRIACsand Opto couplers can be inserted at point A-A to replace thereed relay.

Compared to a TRIAC, an inverse-parallel configurationhas distinct advantages. Voltage and current capabilities aredependent solely on SCR characteristics with ratings todayof over a thousand volts and several hundred amps.Because each SCR operates only on a half-wave basis, thesystem’s rms current rating is 2 times the SCR’s rms currentrating (see Suggested SCR chart). The system has the samesurge current rating as the SCRs do. Operation at 400 Hz isalso no problem. While turn-off time and dv/dt limits controlTRIAC operating speed, the recovery characteristics of anSCR need only be better than the appropriate half-waveperiod.

With inductive loads you no longer need to worry aboutcommutating dv/dt, either. SCRs only need to withstandstatic dv/dt, for which they are typically rated an order ofmagnitude greater than TRIACs are for commutating dv/dt.

Better reliability can be achieved by replacing the reedrelay with a low current TRIAC to drive the SCRs, althoughsome of its limitations come with it. In the preferred circuit ofFigure 6.47(b), the main requirements of the TRIAC are that itbe able to block the peak system voltage and that it have asurge current rating compatible with the gate current require-ments of the SCRs. This is normally so small that a TO-92cased device is adequate to drive the largest SCRs.

IfIn circuits like Figure 6.46, the control devices alter-nately pass the gate currents IG1 and IG2 during the “a” and“b” half cycles, respectively. ILa and ILb are the loadcurrents during the corresponding half cycles. Each SCRthen gets the other half cycle for recovery time. Heatsinking can also be done more efficiently, since power isbeing dissipated in two packages, rather than all in one.The load can either be floated or grounded. the SCRs arenot of the shunted-gate variety, a gate-cathode resistance should be added to shunt the leakage current at higher temperatures. The diodes act as steering diodes so thegate-cathode junctions are not avalanched. The blockingcapability of the diodes need only be as high as the VGT ofthe SCRs. A snubber can also be used if conditions dictate.

A A

GATECONTROL

A AAA

GATECONTROL GATE

CONTROL(FLOATING)

Figure 6.47. Control Devices

(a). Reed Relay (b). Low-Current TRIAC (c). Optically Coupled TRIAC Driver


Table 6.6. Driver TRIACs

LineVoltage

Gate Negative OrIn Phase WithLine Voltage

GatePositive

OpticallyCoupled

120 MAC97A4 MAC97A4 MOC3030*, 3011220 MAC97A6 MAC97A6 MOC3020, MOC3021

*Includes inhibit circuit for zero crossover firing.

This circuit offers several benefits. One is a considerableincrease in gain. This permits driving the TRIAC with almostany other semiconductors such as linear ICs, photosensitivedevices and logic, including MOS. If necessary, it can use anoptically coupled TRIAC driver to isolate (up to 7500 Visolation) delicate logic circuits from the power circuit (seeFigure 6.47(c)). Table 6.6. lists suggested components.Another benefit is being able to gate the TRIAC with a supplyof either polarity. Probably the most important benefit of theTRIAC/SCR combination is its ability to handle variable-phase applications — nearly impossible for non solid-statecontrol devices.

INTERFACING DIGITAL CIRCUITS TOTHYRISTOR CONTROLLED AC LOADS

Because they are bidirectional devices, TRIACs are themost common thyristor for controlling ac loads. A TRIAC canbe triggered by either a positive or negative gate signal oneither the positive or negative half-cycle of applied MT2voltage, producing four quadrants of operation. However, theTRIAC’s trigger sensitivity varies with the quadrant, withquadrants II and III (gate signal negative and MT2 eitherpositive or negative) being the most sensitive and quadrantIV (gate positive, MT2 negative) the least sensitive.

For driving a TRIAC with IC logic, quadrants II and III areparticularly desirable, not only because less gate triggercurrent is required, but also because IC power dissipation isreduced since the TRIAC can be triggered by an “active low”output from the IC.

There are other advantages to operating in quadrants IIand III. Since the rate of rise of on-state current of a TRIAC(di/dt) is a function of how hard the TRIAC’s gate is turnedon, a given IC output in quadrants II and III will produce agreater di/dt capability than in the less sensitive quadrantIV. Moreover, harder gate turn-on could reduce di/dtfailure. One additional advantage of quadrant II and IIIoperation is that devices specified in all four quadrants aregenerally more expensive than devices specified inquadrants I, II and III, due to the additional testing involvedand the resulting lower yields.

USING TRIACsTwo important thyristor parameters are gate trigger current

(IGT) and gate trigger voltage (VGT).IGT (Gate Trigger Current) is the amount of gate trigger

current required to turn the device on. IGT has a negativetemperature coefficient — that is, the trigger current requiredto turn the device on increases with decreasing temperature.If the TRIAC must operate over a wide temperature range, itsIGT requirement could double at the low temperature extremefrom that of its 25°C rating.

It is good practice, if possible, to trigger the thyristor withthree to ten times the IGT rating for the device. This increasesits di/dt capability and ensures adequate gate trigger currentat low temperatures.

VGT (Gate Trigger Voltage) is the voltage the thyristor gateneeds to ensure triggering the device on. This voltage isneeded to overcome the input threshold voltage of thedevice. To prevent thyristor triggering, gate voltage should bekept to approximately 0.4 V or less.

Like IGT, VGT increases with decreasing temperature.

INDUCTIVE LOAD SWITCHINGSwitching of inductive loads, using TRIACs, may require

special consideration in order to avoid false triggering. Thisfalse-trigger mechanism is illustrated in Figure 6.48 whichshows an inductive circuit together with the accompanyingwaveforms.

As shown, the TRIAC is triggered on, at t1, by the positivegate current (IGT). At that point, TRIAC current flows and thevoltage across the TRIAC is quite low since the TRIACresistance, during conduction, is very low.

From point t1 to t2 the applied IGT keeps the TRIAC in aconductive condition, resulting in a continuous sinusoidalcurrent flow that leads the applied voltage by 90° for this pureinductive load.

At t2, IGT is turned off, but TRIAC current continues to flowuntil it reaches a value that is less than the sustaining current(IH), at point A. At that point, TRIAC current is cut off andTRIAC voltage is at a maximum. Some of that voltage is fedback to the gate via the internal capacitance (from MT2 togate) of the TRIAC.



TTL-TO-THYRISTOR INTERFACEThe subject of interfacing requires a knowledge of the

output characteristics of the driving stages as well as theinput requirements of the load. This section describes thedriving capabilities of some of the more popular TTL circuitsand matches these to the input demands of thyristors undervarious practical operating conditions.

CHANGE INTRIAC VOLTAGE DURING

TURN-OFF (dv)

UNDESIRED TRIGGERINGDUE TO FEEDBACK

TRIACVOLTAGEWITH SNUBBERNETWORK

toff(dt)

IGT

A

TRIACCURRENT

GATEMT1

60 Hz LINE

VOLTAGEAPPLIEDTO TERMINALS A AND B

MT2

LOAD

B

A

t2t1

TRIACVOLTAGEWITH SNUBBERNETWORK

Figure 6.48. Inductive Load TRIAC Circuit andEquivalent Waveforms

TTL CIRCUITS WITH TOTEM-POLE OUTPUTS (e.g. 5400SERIES)

The configuration of a typical totem-pole connected TTLoutput stage is illustrated in Figure 6.49(a). This stage iscapable of “sourcing” current to a load, when the load isconnected from Vout to ground, and of “sinking” current fromthe load when the latter is connected from Vout to VCC. If theload happens to be the input circuit of a TRIAC (gate to MT1),the TRIAC will be operating in quadrants I and IV (gate goespositive) when connected from Vout to ground, and of“sinking” II and III (gate goes negative) when connected fromVout to VCC.

QUADRANT I-IV OPERATIONConsidering first the gate-positive condition, Figure

6.49(b), the operation of the circuit is as follows:When Vin to the TTL output stage is low (logical “zero”),

transistors Q1 and Q3 of that stage are cut off, and Q2 isconducting. Therefore, Q2 sources current to the thyristor,and the thyristor would be triggered on during the Vin = 0condition.

When Vin goes high (logical “one”), transistors Q1 and Q3are on and Q2 is off. In this condition depicted by theequivalent circuit transistor Q3 is turned on and its collectorvoltage is, essentially, VCE(sat). As a result, the TRIAC isclamped off by the low internal resistance of Q3.

QUADRANT II-III OPERATIONWhen the TRIAC is to be operated in the more sensitive

quadrants II and III (negative-gate turn-on), the circuit inFigure 6.50(a) may be employed.

With Q3 in saturation, as shown in the equivalent circuit of6.50(b), its saturation voltage is quite small, leaving virtuallythe entire –VEE voltage available for thyristor turn-on. Thiscould result in a TRIAC gate current that exceeds the currentlimit of Q3, requiring a current-limiting series resistor, (R(Iim)).

When the Vout level goes high, Q3 is turned off and Q2becomes conductive. Under those conditions, the TRIACgate voltage is below VGT and the TRIAC is turned off.

DIRECT-DRIVE LIMITATIONSWith sensitive-gate TRIACs, the direct connection of a

TRIAC to a TTL circuit may sometimes be practical.However, the limitations of such circuits must be recognized.

For example:For TTL circuits, the “high” logic level is specified as 2.4

volts. In the circuit of Figure 6.49(a), transistor Q2 iscapable of supplying a short-circuit output current (ISC) of20 to 55 mA (depending on the tolerances of R1 and R2,and on the hFE of Q2). Although this is adequate to turn asensitive-gate TRIAC on, the specified 2.4 volt (high) logiclevel can only be maintained if the sourcing current is heldto a maximum of 0.4 mA — far less than the currentrequired to turn on any thyristor. Thus, the direct connec-tion is useful only if the driver need not activate other logiccircuits in addition to a TRIAC.


TRIACLOAD

60 HzVout

Q3

1 k

Q1

R1

MT1GATE

60 Hz

Vout

TRIACLOAD

Q2

R2

Vout

VCC

SINK CURRENT

SOURCECURRENT

R1

Vin

VinTTLGATE

1 k

LOADCONNECTION

FORCURRENTSOURCE

CONDITION

Q3

VoutQ1

R11.4 k Q2

R2100

LOADCONNECTION

FORCURRENT

SINKCONDITION

VCCVCC

SOURCECURRENT

SINKCURRENT

(a)

(b)

(c)

Figure 6.49. Totem-Pole Output Circuit TTL Logic,Together with Voltage and Current Waveforms,

(b) Equivalent Circuit for Triggering TRIAC with a PositiveVoltage — TRIAC-On Condition, (c) TRIAC-Off Condition

A similar limiting condition exists in the Logic “0” conditionof the output, when the thyristor is to be clamped off. In thiscondition, Q3 is conducting and Vout equals the saturationvoltage (VCE(sat)) of Q3. TTL specifications indicate that thelow logic level (logic “0”) may not exceed 0.4 volts, and thatthe sink current must be limited to 16 mA in order not toexceed this value. A higher value of sink current would cause(VCE(sat)) to rise, and could trigger the thyristor on.

CIRCUIT DESIGN CONSIDERATIONSWhere a 5400-type TTL circuit is used solely for controlling

a TRIAC, with positive-gate turn-on (quadrants I-IV), asensitive gate TRIAC may be directly coupled to the logicoutput, as in Figure 6.49. If the correct logic levels must bemaintained, however, a couple of resistors must be added tothe circuit, as in Figure 6.51(a). In this diagram, R1 is apull-up which allows the circuit to source more current duringa high logical output. Its value must be large enough,however, to limit the sinking current below the 16 mAmaximum when Vout goes low so that the logical zero level of0.4 volts is not exceeded.

Resistor R2, a voltage divider in conjunction with R1,insures VOH (the “high” output voltage) to be 2.4 V or greater.

60 HzLINE

LOAD

MT2

MT1R(lim)

LOGIC CIRCUIT

– 5 V

R1Isink

Vout MT1

Q1

1 k

– 5 V

Q3

R(lim)

VEE(sat)0.4 V MAX

60 HzLINE

MT2

LOAD

(a)

(b)

Figure 6.50. TTL Circuit for Quadrant II and III TRIACOperation Requiring Negative V GT, (b) Schematic

Illustrates TRIAC Turn-On Condition,Vout = Logical “0”



G = 1 V

LOGIC CIRCUIT

R2

Vout = 2.4 V

R1

60 HzLINE

MT2

MT1

R2

R1

Vout

LOAD

VCCVCC

Figure 6.51. Practical Direct-Coupled TTL TRIAC Circuit,(b) Equivalent Circuit Used for Calculation of Resistor

Values

(a) (b)

For a supply voltage of 5 V and a maximum sinking currentof 16 mA

R1 VCC16 mA 50.016 312

Thus, 330 Ω, 1/4 W resistor may be used. Assuming R1 to be330 Ω and a thyristor gate on voltage (VGT) of 1 V, the equiva-lent circuit of Figure 6.50(b) exists during the logical “1” out-put level. Since the logical “1” level must be maintaned at 2.4volts, the voltage drop across R2 must be 1.4 V. Therefore,

R2 1.4IR 1.4VR1R2 1.4(2.63.30) 175

A 180 Ω resistor may be used for R2. If the VGT is less than1 volt, R2 may need to be larger.

The MAC97A and 2N6071A TRIACs are compatibledevices for this circuit arrangement, since they are guaran-teed to be triggered on by 5 mA, whereas the current throughthe circuit of Figure 6.51(b) is approximately 8 mA,

When the TRIAC is to be turned on by a negative gatevoltage, as in Figure 6.50(b), the purpose of the limitingresistor R(Iim) is to hold the current through transistor Q3 to16 mA. With a 5 V supply, a TRIAC VGT of 1 V and amaximum sink current of 16 mA

R(lim) (VCC–VGT)Isink (5–1)(0.016250

In practice, a 270 Ω, 1/4 W resistor may be used.

OPEN COLLECTOR TTL CIRCUITThe output section of an open-collector TTL gate is shown

in Figure 6.52(a).A typical logic gate of this kind is the 5401 type Q2-input

NAND gate circuit. This logic gate also has a maximum sinkcurrent of 16 mA (VOL = 0.4 V max.) because of the Q1 (sat)limitations. If this logic gate is to source any current, apull-up-collector resistor, R1 (6.52b) is needed. When thisTTL gate is used to trigger a thyristor, R1 should be chosen tosupply the maximum trigger current available from the TTLcircuit ( 16 mA, in this case). The value of R1 is calculatedin the same way and for the same reasons as in Figure 6.51.

If a logical “1” level must be maintained at the TTL output (2.4V min.), the entire circuit of Figure 6.51 should be used.

For direct drive (logical “0”) quadrants II and III triggering,the open collector, negative supplied (–5 V) TTL circuit ofFigure 6.53 can be used. Resistor R1 can have a value of270 Ω, as in Figure 6.50. Resistor R2 ensures that the TRIACgate is referenced to MT1 when the TTL gate goes high (off),thus preventing unwanted turn-on. An R2 value of about 1 kshould be adequate for sensitive gate TRIACs and still drawminimal current.

– 5 V

LOAD

MT2

MT1G

R2

R1

LOGIC CIRCUIT

5 V

LOAD

MT2R1

Vout

LOGIC CIRCUITMT1

G

1 k

Q1

Vout

1.4 k

TTLGATE

VCC

60 HzLINE

60 HzLINE

(a)

(b)

Figure 6.52. Output Section of Open-Collector TTL,(b) For Current Sourcing, A Pull-up Resistor, R1,

Must Be Added

Figure 6.53. Negative-Supplied ( –5 V) TTL GatePermits TRIAC Operation in Quadrants II and III

(VR1R1).


LOGIC GATE

R3

Q1

R5

LOAD

G MT1

MT2 60 HzLINE

R4

R2

R1

VCC

Figure 6.54. Series Switch, High Output (Logic “1”)Circuits utilizing Schottky TTL are generally designed in

the same way as TTL circuits, although the current source/sink capabilities may be slightly different.

TRIGGERING THYRISTORS FROM LOGIC GATESUSING INTERFACE TRANSISTORS

For applications requiring thyristors that demand moregate current than a direct-coupled logic circuit can supply, aninterface device is needed. This device can be a small-signaltransistor or an opto coupler.

The transistor circuits can take several different configura-tions, depending on whether a series or shunt switch designis chosen, and whether gate-current sourcing (quadrants Iand IV) or sinking (quadrants II and III) is selected. Anexample of a series switch, high output (logic 1) activation, isshown in Figure 6.54. Any logic family can be used as longas the output characteristics are known. The NPN interfacetransistor, Q1, is configured in the common-emitter mode —the simplest approach — with the emitter connected directlyto the gate of the thyristor.

Depending on the logic family used, resistor R1 (pull-upresistor) and R3 (base-emitter leakage resistor) may or maynot be required. If, for example, the logic is a typical TTLtotem-pole output gate that must supply 5 mA to the base ofthe NPN transistor and still maintain a “high” (2.4 V) logicoutput, then R1 and R2 are required. If the “high” logic level isnot required, then the TTL circuit can directly source the basecurrent, limited by resistor R2.

To illustrate this circuit, consider the case where theselected TRIAC requires a positive-gate current of 100 mA.The interface transistor, a popular 2N4401, has a specifiedminimum hFE (at a collector current of 150 mA) of 100. Toensure that this transistor is driven hard into saturation, under“worse case” (low temperature) conditions, a forced hFE of 20is chosen — thus, 5 mA of base current. For this example,the collector supply is chosen to be the same as the logicsupply (+5 V); but for the circuit configuration, it could be a

different supply, if required. The collector-resistor, R4, issimply

R4 (VCC VCE(sat) VGT(typ))IGT

(5 1 0.9)100 mA 40

A 39 ohm, 1 W resistor is then chosen, since its actualdissipation is about 0.4 W.

If the “logic 1” output level is not important, then the baselimiting resistor R2 is required, and the pull-up resistor R1 isnot. Since the collector resistor of the TTL upper totem-poletransistor, Q2, is about 100 Ω, this resistor plus R2 shouldlimit the base current to 5 mA.

Thus R2 calculates to

R2 [(VCC VBE VGT)5 mA] 100

[(5 0.7 0.9)0.005] 100 560 (specified)

When the TTL output is low, the lower transistor of thetotem-pole, Q3, is a clamp, through the 560 Ω resistor, acrossthe 2N4401; and, since the 560 Ω resistor is relatively low, noleakage-current shunting resistor, R3, is required.

In a similar manner, if the TTL output must remain at “logic1” level, the resistor R1 can be calculated as described earlier(R3 may or may not be required).

For low-logic activation (logic “0”), the circuit of Figure 6.55can be used. In this example, the PNP-interface transistor2N4403, when turned on, will supply positive-gate current tothe thyristor. To ensure that the high logic level will keep thethyristor off, the logic gate and the transistor emitter must besupplied with the same power supply. The base resistors, asin the previous example, are dictated by the output character-istics of the logic family used. Thus if a TTL gate circuit isused, it must be able to sink the base current of the PNPtransistor (IOL(MAX) = 16 mA).

When thyristor operation in quadrants II and III is desired,the circuits of Figures 6.56 and 6.57 can be used; Figure 6.56is for high logic output activation and Figure 6.57 is for low.Both circuits are similar to those on Figures 6.54 and 6.55,but with the transistor polarity and power supplies reversed.

Figure 6.56 sinks current from the thyristor gate through a+ 5 V

LOGIC GATE

R1

R2

Q1

G

R4

R3

MT2

MT1

60 HzLINE

LOAD

Figure 6.55. Low-Logic Activation withInterface Transistor



LOGIC GATE

R3

R1

R2Q1

R4R5

LOAD

GMT1

MT260 HzLINE

– VEE

Figure 6.56. High-Logic Output Activation

– VEE

LOGIC GATE

R3LOAD

MT2

MT1G

R4

R1

R2

60 HzLINE

Figure 6.57. Low-Logic Output Activation

switched NPN transistor whose emitter is referenced to anegative supply. The logic circuit must also be referenced tothis negative supply to ensure that transistor Q1 is turned offwhen required; thus, for TTL gates, VEE would be –5 V.

In Figure 6.57, the logic-high bus, which is now ground, isthe common ground for both the logic, and the thyristor andthe load. As in the first example (Figure 6.54), the negativesupply for the logic circuit (–VEE) and the collector supply forthe PNP transistor need not be the same supply. If, forpower-supply current limitations, the collector supply ischosen to be another supply (–VCC), it must be within theVCEO ratings of the PNP transistor. Also, the power dissipa-tion of collector resistor, R3, is a function of –VCC — the lower–VCC, the lower the power rating.

The four examples shown use gate-series switching toactivate the thyristor and load (when the interface transistor isoff, the load is off). Shunt-switching can also be used if theconverse is required, as shown in Figures 6.58 and 6.59. InFigure 6.58, when the logic output is high, NPN transistor,Q1, is turned on, thus clamping the gate of the thyristor off. Toactivate the load, the logic output goes low, turning off Q1 andallowing positive gate current, as set by resistor R3, to turn onthe thyristor.

In a similar manner, quadrant’s II and III operation isderived from the shunt interface circuit of Figure 6.59.

OPTICAL ISOLATORS /COUPLERSAn Optoelectronic isolator combines a light-emitting device

and a photo detector in the same opaque package thatprovides ambient light protection. Since there is no electricalconnection between input and output, and the emitter anddetector cannot reverse their roles, a signal can pass throughthe coupler in one direction only.

Since the opto-coupler provides input circuitry protectionand isolation from output-circuit conditions, ground-loopprevention, dc level shifting, and logic control of high voltagepower circuitry are typical areas where opto-couplers areuseful.

Figure 6.60 shows a photo-TRIAC used as a driver for ahigher-power TRIAC. The photo-TRIAC is light sensitive andis turned on by a certain specified light density (H), which is afunction of the LED current. With dark conditions (LEDcurrent = 0) the photo-TRIAC is not turned on, so that theonly output current from the coupler is leakage current, calledpeak-blocking current (IDRM). The coupler is bilateral anddesigned to switch ac signals.

The photo-TRIAC output current capability is, typically, 100mA, continuous, or 1 A peak.

Any Motorola TRIAC can be used in the circuit of Figure6.60 by using Table 6.8. The value of R is based on the

+ 5 V

LOGIC GATE

R2

R1Q1

R3 LOAD

G

MT1

MT2 60 HzLINE

Figure 6.58. Shunt-Interface Circuit (High-Logic Output)

R2

R1

LOGIC GATE

R3 LOAD

G

MT2

MT1

– VEE

60 HzLINE

Figure 6.59. Shunt-Interface Circuit(Quadrants I and III Operation)


LED

OPTO COUPLER

PHOTOTRIAC

H

I

LOAD

G

R

MT2

MT160 HzLINE

Figure 6.60. Optically-Coupled TRIAC Driver is Used toDrive a Higher-Power TRIAC

photo-TRIAC’s current-handling capability. For example,when the MOC3011 operates with a 120 V line voltage(approximately 175 V peak), a peak IGT current of 175 V/180ohm (approximately 1 A) flows when the line voltage is at itsmaximum. If less than 1 A of IGT is needed, R can beincreased. Circuit operation is as follows:

Table 6.8. Specifications for Typical Optically CoupledTRIAC Drivers

DeviceType

Maximum Required LEDTrigger Current (mA)

PeakBlockingVoltage

R(Ohms)

MOC3009 30 250 180MOC3009MOC3011

3015

250250

180180MOC3011

MOC30111510

250250

180180MOC3011

MOC30201030

250400

180260MOC3020

MOC30213015

400400

260360MOC3021

MOC30301530

400250

36051MOC3030

MOC30313015

250250

5151MOC3031 15 250 51

When an op-amp, logic gate, transistor or any otherappropriate device turns on the LED, the emitted light triggersthe photo-TRIAC. Since, at this time, the main TRIAC is noton, MT2-to-gate is an open circuit. The 60 Hz line can nowcause a current flow via R, the photo-TRIAC, Gate-MT1junction and load. This Gate-MT1 current triggers the mainTRIAC, which then shorts and turns off the photo-TRIAC. Theprocess repeats itself every half cycle until the LED is turnedoff.

Triggering the main TRIAC is thus accomplished by turningon the LED with the required LED-trigger current indicated inTable 6.7.

MICROPROCESSORS

Microprocessor systems are also capable of controlling acpower loads when interfaced with thyristors. Commonly, theoutput of the MPU drives a PIA (peripheral interface adaptor)which then drives the next stage. The PIA Output Portgenerally has a TTL compatible output with significantly lesscurrent source and sink capability than standard TTL. (MPUsand PIAs are sometimes constructed together on the samechip and called microcontrollers.)

When switching ac loads from microcomputers, it isgood practice to optically isolate them from unexpectedload or ac line phenomena to protect the computer systemfrom possible damage. In addition, optical isolation willmake UL recognition possible.

A typical TTL-compatible microcontroller, such as theMC3870P offers the following specifications:

IOH 300 A (VOH 2.4 V)

IOL 1.8 mA (VOL 0.4 V)

VCC 5 V

Since this is not adequate for driving the optocouplerdirectly (10 mA for the MOC3011), an interface transistoris necessary.

The circuit of Figure 6.61 may be used for thyristortriggering from the 3870 logical “1.”

The interface transistor, again, can be the 2N4401. With 10mA of collector current (for the MOC3011) and a base currentof 0.75 mA, the VCE(sat) will be approximately 0.1 V.

R1 can be calculated as in a previous example.Specifically:

1.8 mA (maximum IOL for the 3870)

5 VR1; R1 2.77 k

R1 can be 3 k, 14 W

With a base current of 0.75 mA, R1 will drop (0.75 mA) (3 k)or 2.25 V. This causes a VOH of 2.75 V, which is within thelogical “1” range.

R2 [2.75 V–VBE(on)]IB (2.75–0.75)0.75 2.66 k

R2 can be a 2.7 k, 14 W resistor..

R3 must limit IC to 10 mA :

R3 [5 V–VCE(sat) – VF(diode)10 mA]

(5–0.1–1.2)10 mA 370

Since R3 is relatively small, no base-emitter leakageresistor is required.

Figure 6.62 shows logical “0” activation. Resistor valuesare calculated in a similar way.

MC3870

MT1

MT2

R

G

LOADQ1

R2

R1

R3

+ 5 V

Figure 6.61. Logical “1” Activation from MC3870PMicrocomputer

60 HzLINE



MC3870P

Q1

R1R2

+ 5 V

R3

G

LOAD

MT1

60 HzLINE

MT2

R

Figure 6.62. Logical “0” Activation

THE CMOS INTERFACE

Another popular logic family, CMOS, can also be used todrive thyristors.

As shown in Figure 6.63(a), the output stage of a typicalCMOS Gate consists of a P-channel MOS device connectedin series with an N-channel device (drain-to-drain), with thegates tied together and driven from a common input signal.When the input signal goes high, logical 1, the P-channeldevice is essentially off and conducts only leakage current(IDSS), on the order of pico-amps. The N-channel unit isforward-biased and, although it has a relatively high on

D

S

D

P-CHANNELrDS(on)P-CHANNEL

S

N-CHANNEL

RL

Vout

RL

VDD

Vin

VDDVDD

VoutVout

N-CHANNELrDS(on)

Figure 6.63. Output Section of a Typical CMOS Gate, (b) Equivalent Current-Sourcing Circuit is Activated when V in goes Low, Turning the P-Channel Device Fully On, (c) Equivalent Current Sinking Circuit is Activated when the Input Goes High and Turns the

N-Channel Device On

(a) (b) (c)

resistance (rDS(on)), the drain-to-source voltage of the N-channel device (VDS) is very low (essentially zero) becauseof the very low drain current (VDSS) flowing through thedevice. Conversely, when the input goes low (zero), theP-channel device is turned fully on, the N-channel device isoff and the output voltage will be very near VDD.

When interfacing with transistors or thyristors, the CMOSGate is current-limited mainly by its relatively high onresistance, the dc resistance between drain and source,when the device is turned on.

The equivalent circuits for sourcing and sinking current intoan external load is shown in Figures 6.63(b) and 6.63(c).Normally, when interfacing CMOS to CMOS, the logicoutputs will be very near their absolute maximum states (VDDor 0 V) because of the extremely small load currents. Withother types of loads (e.g. TRIACs), the current, and theresulting output voltage, is dictated by the simple voltagedivider of rDS(on) and the load resistor RL, where rDS(on) is thetotal series and/or parallel resistance of the devices compris-ing the NOR and NAND function.

Interfacing CMOS gates with thyristors requires a knowl-edge of the on resistance of the gate in the source and sinkconditions. The on-resistance of CMOS devices is notnormally specified on data sheets.

It can easily be calculated, however, from the output drivecurrents, which are specified. The drive (source/sink) cur-rents of typical CMOS gates at various supply voltages areshown in Table 6.9. From this information, the on resistancefor worst case design is calculated as follows:

For the source condition

rDS(on)(MAX) (VDD VOH)IOH(MIN)

Similarly, for the sink current condition

rDS(on)(MAX) VOLIOL(MIN)

Values of rDS(on) for the various condition shown in Table6.9 are tabulated in Table 6.10.

Table 6.9. CMOS Characteristics

Specified source/sink currents to maintain logical “1” andlogical “0” levels for various power-supply (VDD) voltages.The IOH and IOL values are used to calculate the “on”resistance of the CMOS output.

Output Drive Current

CMOS ALSeriesmA, dc

CMOSCL/CPSeriesmA, dc

Min Typ Min Typ

I(source) – IOHI(source) IOHVDD = 5 V; VOH = 2.5 V – 0.5 – 1.7 – 0.2 – 1.7DD OHVDD = 10 V; VOH = 9.5 V – 0.5 – 0.9 – 0.2 – 0.9VDD = 15 V; VOH = 13.5 V – 3.5 – 3.5

I(sink) – IOLI(sink) IOLVDD = 5 V; VOL= 0.4 V 0.4 7.8 0.2 7.8DD OLVDD = 10 V; VOL = 0.5 V 0.9 2 0.5 2VDD = 15 V; VOL = 1.5 V 7.8 7.8


Table 6.10. Calculated CMOS On Resistance Values ForCurrent Sourcing and Sinking at Various V DD Options

Operating Conditions

Output Resistance, r DS(on)Ohmsp g

Typical Maximum

Source ConditionVDD = 5 V

10 V15 V

1.7 k500430

12.5 k2.5 k

—

Sink ConditionVDD = 5 V

10 V15 V

500420190

2 k1 k—

It is apparent from this table that the on resistancedecreases with increasing supply voltage.

Although the minimum currents are now shown on the datasheet for the 15 V case, the maximum on resistance can beno greater than the 10 V example and, therefore, can beassumed for worst case approximation to be 1 and 2.5kohms for sink-and-source current cases, respectively.

The sourcing on resistance is greater than the sinkingcase because the difference in carrier mobilities of the twochannel types.

Since rDS(on) for both source and sink conditions varieswith supply voltage (VDD), there are certain drive limitations.The relative high rDS(on) of the P-channel transistor couldpossibly limit the direct thyristor drive capability; and, in a likemanner, the N-channel rDS(on) might limit its clampingcapability. With a 10 or 15 V supply, the device may becapable of supplying more than 10 mA, but should be limitedto that current, with an external limiting resistor, to avoidexceeding the reliable limits of the unit metalization.

VM = BACK EMFOF MOTOR

LM = MOTOR INDUCTANCE

RM = MOTORRESISTANCE

VM

LM

RMBATTERY–

BATTERYCURRENT

+

MOTORCURRENT

DIODECURRENT

APPLIEDBATTERYVOLTAGE

AVERAGE

–+

AVERAGE

AVERAGE

AVERAGE

Figure 6.64. Basic Pulse Width ModulatedMotor Speed Control

DC MOTOR CONTROL WITH THYRISTORSIn order to control the speed of a dc series field motor at

different required torque levels, it is necessary to adjust thevoltage applied to the motor. For any particular appliedvoltage the motor speed is determined solely by the torquerequirements and top speed is reached under minimumtorque conditions. When a series motor is used as a tractiondrive for vehicles, it is desirable to control the voltage to themotor to fit the various torque requirements of grades, speedand load. The common method of varying the speed of themotor is by inserting resistance in series with the motor toreduce the supplied voltage. This type of motor speed controlis very inefficient due to the I2R loss, especially under highcurrent and torque conditions.

A much more efficient method of controlling the voltageapplied to the motor is the pulse width modulation methodshown in Figure 6.64. In this method, a variable width pulseof voltage is applied to the motor at the same rate toproportionally vary the average voltage applied to the motor.A diode is placed in parallel with the inductive motor path toprovide a circuit for the inductive motor current and preventabrupt motor current change. Abrupt current changes wouldcause high induced voltage across the switching device.

The circulating current through the diode decreases only inresponse to motor and diode loss. With reference to Figure6.64, it can be seen that the circulating diode current causesmore average current to flow through the motor than is takenfrom the battery. However, the power taken from the battery isapproximately equal to the power delivered to the motor,indicating that energy is stored in the motor inductance at thebattery voltage level and is delivered to the motor at theapproximate current level when the battery is disconnected.

To provide smooth and quiet motor operation, the currentvariations through the motor should be kept to a minimumduring the switching cycle. There are limitations on theamount of energy that can be stored in the motor inductance,which, in turn, limits the power delivered to the motor duringthe off time; thus the off time must be short. To operate themotor at low speeds, the on time must be approximately 10percent of the off time and therefore, a rapid switching rate isrequired that is generally beyond the capabilities of mechani-cal switches. Practical solutions can be found by the use ofsemiconductor devices for fast, reliable and efficient switch-ing operations.

SCR DC MOTOR CONTROLSCRs offer several advantages over power transistors as

semiconductor switches. They require less driver power, areless susceptible to damage by overload currents and canhandle more voltage and current. Their disadvantages arethat they have a higher power dissipation due to highervoltage drops and the difficulty in commutating to the offcondition.



SCR1TRIGGERCIRCUIT

SCR2

Cc

R1

Figure 6.65. Speed Control with Resistive ChargingThe SCR must be turned off by either interrupting the

current through the anode-cathode circuit or by forcingcurrent through the SCR in the reverse direction so that thenet flow of forward current is below the holding current longenough for the SCR to recover blocking ability. Commutationof the SCR in high current motor control circuits is generallyaccomplished by discharging a capacitor through the SCR inthe reverse direction. The value of this capacitor is deter-mined approximately from the following equation:

CcTq IA

Vc

Where:Cc = value of necessary commutating capacitanceTq = turn-off time of the SCRIA = value of anode current before commutationVc = voltage of Cc before commutation

This relationship shows that to reduce the size of Cc, thecapacitor should be charged to as high a voltage as possibleand the SCR should be selected with as low a turn-off time aspossible.

If a 20 microsecond turn-off time SCR is commutated by acapacitor charged to 36 volts, it would take over 110 µF toturn off 200 amperes in the RC commutating circuit of Figure6.65. If a 50 cycle switching frequency is desired, the value ofR1 would be approximately 5 ohms to allow charging timewith an on duty cycle of 10 percent. The value of this resistorwould give approximately 260 watts dissipation in thecharging circuit with 90 percent off duty cycle.

SCR1 SCR2

Cc

Lc

SCR3

TRIGGERCIRCUIT

Figure 6.66. Speed Control with Inductive Charging

TRIGGERCIRCUIT SCR1 SCR2

D1

D2

Figure 6.67. SCR Motor Control withTransformer Charging

If the resonant charging commutating circuitry of Figure6.66 is used, the capacitor is reduced to approximately 55 µF.In this circuit, SCR3 is gated on at the same time as SCR1and allows the resonant charging of Cc through Lc to twicethe supply voltage. SCR3 is then turned off by the reversal ofvoltage in the resonant circuit before SCR2 is gated on. It isapparent that there is very little power loss in the chargecircuit depending upon the voltage drop across SCR3 andthe resistance in Lc.

If the commutating capacitor is to be reduced further, it isnecessary to use a transformer to charge the capacitor tomore than twice the supply voltage. This type of circuit isillustrated by the transformer charge circuit shown in Figure6.67. In this circuit the capacitor can be charged to severaltimes the supply voltage by transformer action through diodeD1 before commutating SCR1. The disadvantage of thiscircuit is in the high motor current that flows through thetransformer primary winding.

HEAVY DUTY MOTOR CONTROL WITH SCRsAnother advantage of SCRs is their high surge current

capabilities, demonstrated in the motor drive portion of thegolf cart controller shown in Figure 6.68. Germanium powertransistors were used because of the low saturation voltagesand resulting low static power loss. However, since switchingspeeds are slow and leakage currents are high, additionalcircuit techniques are required to ensure reliable operation:

1. The faster turn-on time of the SCR (Q9) over that of thegermanium transistors shapes the turn-on load line.2. The parallelled output transistors (Q3-Q8) require a 6V reverse bias.3. The driver transistor Q2 obtains reverse bias bymeans of diode D4.

To obtain the 6 V bias, the 36 V string of 6 V batteries are


tapped, as shown in the schematic. Thus, the motor ispowered from 30 V and the collector supply for Q2 is 24 V,minimizing the dissipation in colllector load resistor R1.

Total switching loss in switchmode applications is theresult of the static (on-state) loss, dynamic (switching) lossand leakage current (off-state) loss. The low saturationvoltage of germanium transistors produces low static loss.However, switching speeds of the germanium transistors arelow and leakage currents are high. Loss due to leakagecurrent can be reduced with off bias, and load line shapingcan minimize switching loss. The turn-off switching loss wasreduced with a standard snubber network (D5, C1, R2) seeFigure 6.68.

Turn-on loss was uniquely and substantially reduced byusing a parallel connected SCR (across the germaniumtransistors) the MCR265-4 (55 A rms, 550 A surge). Thisfaster switching device diverts the initial turn-on motor loadcurrent from the germanium output transistors, reducing bothsystem turn-on loss and transistor SOA stress.

The main point of interest is the power switching portion ofthe PWM motor controller. Most of the readily available PWMICs can be used (MC3420, MC34060, TL494, SG1525A,UA78S40, etc.), as they can source at least a 10 mA, +15 Vpulse for driving the following power MOSFET.

Due to the extremely high input impedance of the powerMOSFET, the PWM output can be directly connected to theFET gate, requiring no active interface circuitry. The positivegoing output of the PWM is power gained and inverted by theTMOS FET Q1 to supply the negative going base drive toPNP transistor Q2. Diode D1 provides off-bias to thisparaphase amplifier, the negative going pulse from theemitter furnishing base drive to the six parallel connected

output transistors and the positive going collector outputpulse supplying the SCR gate trigger coupled throughtransformer T1.

Since the faster turn-on SCR is triggered on first, it willcarry the high, initial turn-on motor current. Then the slowerturn-on germanium transistors will conduct clamping off theSCR, and carry the full motor current. For the illustrated 2HPmotor and semiconductors, a peak exponentially rising andfalling SCR current pulse of 120 A lasting for about 60 µs wasmeasured. This current is well within the rating of the SCR.Thus, the high turn-on stresses are removed from thetransistors providing a much more reliable and efficient motorcontroller while using only a few additional components.

DIRECTION AND SPEED CONTROL FOR MOTORS

For a shunt motor, a constant voltage should be applied tothe shunt field to maintain constant field flux so that thearmature reaction has negligible effect. When constant voltageis applied to the shunt field, the speed is a direct function ofthe armature voltage and the armature current. If the field isweak, then the armature reaction may counterbalance thevoltage drop due to the brushes, windings and armatureresistances, with the net result of a rising speed-loadcharacteristic.

The speed of a shunt-wound motor can be controlled witha variable resistance in series with the field or the armature.Varying the field current for small motor provides a widerange of speeds with good speed regulation. However, if thefield becomes extremely weak, a rising speed-load charac-teristic results. This method cannot provide control below the

PWM

+ 15 V

+ 10 µF25 V

0.01 µF

1 k

10 k

MTP12N10E

Q1

2050 WR1

27

0.6200 W

1N1183D4

Q21 µF

1N914D3

(2)

D2

330D1

1N914

(6) MATCHED

Q8Q3

625 W

OFF BIAS

UTCH51

SENSECURRENTTO PWM

0.001

dcMOTOR

2 HP

FORWARD

Q9MCR265-4

1N4744

D5

1N1183

1R2

700 µFC1

+ 18 V470

+ 24 V

+ 15 V

+ 30 V

+ 36 V

REVERSE

Figure 6.68. PWM DC Motor Controller Using SCRTurn-On Feature



design motor speed. Varying the resistance in series with thearmature results in speeds less than the designed motorspeed; however, this method yields poor speed regulation,especially at low speed settings. This method of control alsoincreases power dissipation and reduces efficiency and thetorque since the maximum armature current is reduced.Neither type of resistive speed control is very satisfactory.Thyristor drive controls, on the other hand, provide continu-ous control through the range of speed desired, do not havethe power losses inherent in resistive circuits, and do notcompromise the torque characteristics of motors.

Although a series-wound motor can be used with either dcor ac excitation, dc operation provides superior performance.A universal motor is a small series-wound motor designed tooperate from either a dc or an ac supply of the same voltage.In the small motors used as universal motors, the windinginductance is not large enough to produce sufficient currentthrough transformer action to create excessive commutationproblems. Also, high-resistance brushes are used to aidcommutation. The characteristics of a universal motoroperated from alternating current closely approximate thoseobtained for a dc power source up to full load; however,above full load the ac and dc characteristics differ. For aseries motor that was not designed as a universal motor, thespeed-torque characteristic with ac rather than dc is not asgood as that for the universal motor. At eight loads, the speedfor ac operation may be greater than for dc since the effectiveac field strength is smaller than that obtained on directcurrent. At any rate, a series motor should not be operated in

a no-load condition unless precaution is are taken to limit themaximum speed.

SERIES-WOUND MOTORSThe circuit shown in Figure 6.69 can be used to control the

speed and direction of rotation of a series-wound dc motor.Silicon controlled rectifiers Q1-Q4, which are connected in abridge arrangement, are triggered in diagonal pairs. Whichpair is turned on is controlled by switch S1 since it connectseither coupling transformer T1 or coupling transformer T2 toa pulsing circuit. The current in the field can be reversed byselecting either SCRs Q2 and Q3 for conduction, or SCRsQ1 and Q4 for conduction. Since the armature current isalways in the same direction, the field current reverses inrelation to the armature current, thus reversing the directionof rotation of the motor.

A pulse circuit is used to drive the SCRs through eithertransformer T1 or T2. The pulse required to fire the SCR isobtained from the energy stored in capacitor C1. Thiscapacitor charges to the breakdown voltage of zener diodeD5 through potentiometer R1 and resistor R2. As thecapacitor voltage exceeds the zener voltage, the zenerconducts, delivering current to the gate of SCR Q5. Thisturns Q5 on, which discharges C1 through either T1 or T2depending on the position of S1. This creates the desiredtriggering pulse. Once Q5 is on, it remains on for the durationof the half cycle. This clamps the voltage across C1 to theforward voltage drop of Q5. When the supply voltage drops tozero, Q5 turns off, permitting C1 to begin charging when thesupply voltage begins to increase.

R31 k

D51N5262

Q52N5062

R2, 4.7 k5 W

R120 k5 W

D3

D1

D4

D2(4) 1N4722

ORMDA2503AC

LINE

(2)SPRAGUE

11Z13

T2T1

S1C1

+

5 µF75 V

MCR12DQ3

T2

MCR12DQ1

T1

FIELD MCR12DQ4

MCR12DQ2

ARMATURE

T1

T2

Figure 6.69. Direction and Speed Control for Series-Wound or Universal Motor


Q52N5062

R31 k

D51N5262

T1

C1

acLINE

R2, 4.7 k5 W

R120 k5 W

D3

D1

D4

D2(4) 1N4722

+

5 µF75 V

T1 AND T2 ARE SPRAGUE 11Z13Q1 THRU Q4 — MCR12D

T2

FIELD

Q3

T2

T1

Q4

ARMATURE

Q2

T2

T1

Q1

Figure 6.70. Direction and Speed Control for Shunt-Wound Motor

The speed of the motor can be controlled by potentiome-ter R1. The larger the resistance in the circuit, the longerrequired to charge C1 to the breakdown voltage of zenerD5. This determines the conduction angle of either Q1 andQ4, or Q2 and Q3, thus setting the average motor voltageand thereby the speed.

SHUNT-WOUND MOTORSIf a shunt-wound motor is to be used, then the circuit in

Figure 6.70 is required. This circuit operates like the oneshown in Figure 6.69. The only differences are that the field isplaced across the rectified supply and the armature is placedin the SCR bridge. Thus the field current is unidirectional butarmature current is reversible; consequently the motor’sdirection of rotation is reversible. Potentiometer R1 controlsthe speed as explained previously.

RESULTSExcellent results were obtained when these circuits were

used to control 1/15 hp, 115 V, 5,000 r/min motors. Thiscircuit will control larger, fractional-horsepower motors pro-

R2910

C110 µF

Q12N6027

R1100 k

R31 k

R42 k

R51 k

0.01 µF

C2Q2

2N5060

R651 k

C3

0.01 µF

(SEE TEXT)

–+

C44 µF

R71 k

Q32N5060

GE NO. 14

+ 3 V

Figure 6.71. Low Voltage Lamp Flasher

vided the motor current requirements are within the semi-conductor ratings. Higher current devices will permit controlof even larger motors, but the operation of the motor underworst case must not cause anode currents to exceed theratings of the semiconductor.

PUT APPLICATIONSPUTs are negative resistance devices and are often used

in relaxation oscillator applications and as triggers forcontrolling thyristors. Due to their low leakage current, theyare useful for high-impedance circuits such as long-durationtimers and comparators.

TYPICAL CIRCUITS

The following circuits show a few of the many ways inwhich the PUT can be used. The circuits are not optimizedeven though performance data is shown.

In several of the circuit examples, the versatility of the PUThas been hidden in the design. By this it is meant that indesigning the circuit, the circuit designer was able to select aparticular intrinsic standoff ratio or he could select a particularRG (gate resistance) that would provide a maximum orminimum valley and peak current. This makes the PUT veryversatile and very easy to design with.

LOW VOLTAGE LAMP FLASHER

The PUT operates very well at low supply voltagesbecause of its low on-state voltage drop.

A circuit using the PUT in a low voltage application isshown in Figure 6.71 where a supply voltage of 3 volts isused. The circuit is a low voltage lamp flasher composed of arelaxation oscillator formed by Q1 and an SCR flip flopformed by Q2 and Q3.



2

19

876543 5

6

7

8

9

10

11

12

13

14

15

16

17

18

20

1

C = 0.0047 µF

C = 0.01 µF

DURATION TIME (ms)

V(V

OLT

S)in

(b). Voltage versus Ramp Duration Time of VCRG

5 to 20 VC1

R220 k

–40 V

+

R110 k

Q1MPS6516

R3510 k

R4100

2N6027R5

100 k

RAMP OUT

+

Figure 6.72. (a). Voltage Controlled Ramp Generator(VCRG)

With the supply voltage applied to the circuit, the timingcapacitor C1 charges to the firing point of the PUT, 2 voltsplus a diode drop. The output of the PUT is coupled throughtwo 0.01 µF capacitors to the gate of Q2 and Q3. To clarifyoperation, assume that Q3 is on and capacitor C4 is chargedplus to minus as shown in the figure. The next pulse from thePUT oscillator turns Q2 on. This places the voltage on C4across Q3 which momentarily reverse biases Q3. Thisreverse voltage turns Q3 off. After discharging, C4 thencharges with its polarity reversed to that shown. The nextpulse from Q1 turns Q3 on and Q2 off. Note that C4 is anon-polarized capacitor.

For the component values shown, the lamp is on for about1/2 second and off the same amount of time.

VOLTAGE CONTROLLED RAMP GENERATORThe PUT provides a simple approach to a voltage

controlled ramp generator, VCRG, as shown in Figure6.72(a). The current source formed by Q1 in conjuction withcapacitor C1 set the duration time of the ramp. As the positivedc voltage at the gate is changed, the peak point firingvoltage of the PUT is changed which changes the durationtime, i.e., increasing the supply voltage increases the peakpoint firing voltage causing the duration time to increase.

Figure 6.72(b) shows a plot of voltage-versus-rampduration time for a 0.0047 µF and a 0.01 µF timing capacitor.The figure indicates that it is possible to have a change infrequency of 3 ms and 5.4 ms for the 0.0047 µF and the 0.01µF capacitor respectively as the control voltage is varied from5 to 20 volts.

LOW FREQUENCY DIVIDERThe circuit shown in Figure 6.73 is a frequency divider with

the ratio of capacitors C1 and C2 determining division. With apositive pulse applied to the base of Q1, assume that C1 =C2 and that C1 and C2 are discharged. When Q1 turns off,both C1 and C2 charge to 10 volts each through R3. On thenext pulse to the base of Q1, C1 is again discharged but C2

R22.2 k

3 V R13.9 k Q1

MPS6512

R31 k

C1

D11N4001 C2

D2

1N4001

+ 20 Vdc

Q22N6027

R4100

R65.1 k

8 VR55.1 k

OUT

0.01 µF0.01 µF0.01 µF0.01 µF0.01 µF0.01 µF0.01 µF0.01 µF0.01 µF0.01 µF

C1 C2 Division

0.01 µF0.02 µF0.03 µF0.04 µF0.05 µF0.06 µF0.07 µF0.08 µF0.09 µF0.1 µF

234567891011

Table 6.11

Figure 6.73. Low Frequency Divider


+ 20 Vdc

R32 M

C110 µF MYLAR

Q12N5457

R122 M

R2100

Q22N6028

OUTPUT R42 M

Figure 6.74. 20-Minute, Long Duration Timerremains charged to 10 volts. As Q1 turns off this time, C1 andC2 again charge. This time C2 charges to the peak pointfiring voltage of the PUT causing it to fire. This dischargescapacitor C2 and allows capacitor C1 to charge to the linevoltage. As soon as C2 discharges and C1 charges, the PUTturns off. The next cycle begins with another positive pulseon the base of Q1 which again discharges C1.

The input and output frequency can be approximated bythe equation

fin(C1C2)

C1fout

For a 10 kHz input frequency with an amplitude of 3 volts,Table 6.11 shows the values for C1 and C2 needed to divideby 2 to 11.

This division range can be changed by utilizing theprogrammable aspect of the PUT and changing the voltageon the gate by changing the ratio R6/(R6+ R5). Decreasingthe ratio with a given C1 and C2 decreases the division rangeand increasing the ratio increases the division range.

The circuit works very well and is fairly insensitive to theamplitude, pulse width, rise and fall times of the incomingpulses.

PUT LONG DURATION TIMERA long duration timer circuit that can provide a time delay of

up to 20 minutes is shown in Figure 6.74. The circuit is astandard relaxation oscillator with a FET current source inwhich resistor R1 is used to provide reverse bias on the

gate-to-source of the JFET. This turns the JFET off andincreases the charging time of C1. C1 should be a lowleakage capacitor such as a mylar type.

The source resistor of the current source can be computedusing the following equation:

VGS VP (1 IOIDSS )

R1VGSIO

where IO is the current out of the current source.VP is the pinch off voltage,VGS is the voltage gate-to-source and,IDSS is the current, drain-to-source, with the gate

shorted to the source.

The time needed to charge C1 to the peak point firingvoltage of Q2 can be approximated by the followingequation:

t CVI

,

where t is time in secondsC is capacitance in µF,∆V is the change in voltage across capacitor C1,andI is the constant current used to charge C1.

Maximum time delay of the circuit is limited by the peakpoint firing current, lP, needed to fire Q2. For chargingcurrents below IP, there is not enough current available fromthe current source to fire Q2, causing the circuit to lock up.Thus PUTs are attractive for long duration timing circuitsbecause of their low peak point current. This currentbecomes very small when RG (the equivalent parallelresistance of R3 and R4) is made large. For example, the2N6028 has IP guaranteed to be less than 0.15 µA at RG = 1M Ohm as shown in Figure 6.74.

PHASE CONTROLFigure 6.75 shows a circuit using a PUT for phase control

of an SCR. The relaxation oscillator formed by Q2 providesconduction control of Q1 from 1 to 7.8 milliseconds or 21.6°to 168.5°. This constitutes control of over 97% of the poweravailable to the load.

Only one SCR is needed to provide phase control ofboth the positive and negative portion of the sine wavebyputting the SCR across the bridge composed of diodes D1through D4.

115 V rms60 Hz

LOAD100 Ω

Q12N6402

D4D2

D1D3

D51N4114

20 V

R2250 k

C10.1 µF

Q22N6027

R41 k

R31 k

15 k2 WATT

R1

Figure 6.75. SCR Phase Control



115 Vrms

14 Vrms

T1

D11N5240

10 V

R110 k

C10.1 µF

DALE PT50

T211Z12

1:1

PUT

SCR

2N6027

B

R347 k

R250 k

R41 k

A

12 V

–

+

Figure 6.76. (a). 12-Volt BatteryCharger

BATTERY CHARGER USING A PUTA short circuit proof battery charger is shown in Figure 6.76

which will provide an average charging current of about 8amperes to a 12 volt lead acid storage battery. The chargercircuit has an additional advantage in that it will not functionnor will it be damaged by improperly connecting the battery tothe circuit.

With 115 volts at the input, the circuit commences tofunction when the battery is properly attached. The batteryprovides the current to charge the timing capacitor C1 usedin the PUT relaxation oscillator. When C1 charges to thepeak point voltage of the PUT, the PUT fires turning the SCRon, which in turn applies charging current to the battery. Asthe battery charges, the battery voltage increases slightlywhich increases the peak point voltage of the PUT. Thismeans that C1 has to charge to a slightly higher voltage tofire the PUT. The voltage on C1 increases until the zenervoltage of D1 is reached which clamps the voltage on C1 andthus prevents the PUT oscillator from oscillating and charg-ing ceases. The maximum battery voltage is set by poten-tiometer R2 which sets the peak point firing voltage of thePUT.

In the circuit shown, the charging voltage can be setfrom 10 V to 14 V, the lower limit being set by D1 and theupper limit by T1. Lower charging voltages can beobtained by reducing the reference voltage (reducing thevalue of zener diode D1) and limiting the charging current(using either a lower voltage transformer, T1, or addingresistance in series with the SCR).

Resistor R4 is used to prevent the PUT from beingdestroyed if R2 were turned all the way up.

Figure 6.76(b) shows a plot of the charging characteristicsof the battery charger.

90 V rms VOLTAGE REGULATOR USING A PUTThe circuit of Figure 6.77 is an open loop rms voltage

regulator that will provide 500 watts of power at 90 V rmswith good regulation for an input voltage range of 110 – 130V rms.

1200

CHARGING CURRENT versus TIME

2

4

5

6

7

987654321

1150

8

0

SPECIFIC GRAVITY OF ELECTROLYTE versus TIME

TIME (HR)

1250

3

SPEC

IFIC

GR

AVIT

Y

CU

RR

ENT

(AM

PS)

Figure 6.76 (b) Charging Characteristicsof Battery Charger

With the input voltage applied, capacitor C1 charges untilthe firing point of Q3 is reached causing it to fire. This turnsQ5 on which allows current to flow through the load. As theinput voltage increases, the voltage across R10 increaseswhich increases the firing point of Q3. This delays the firing ofQ3 because C1 now has to charge to a higher voltage beforethe peak-point voltage is reached. Thus the output voltage isheld fairly constant by delaying the firing of Q5 as the inputvoltage increases. For a decrease in the input voltage, thereverse occurs.

Another means of providing compensation for increasedinput voltage is achieved by Q2 and the resistive dividerformed by R6 and R7. As input voltage increases, the voltageat the base of Q2 increases causing Q2 to turn on harderwhich decreases the charging rate of C1 and further delaysthe firing of Q5.

To prevent the circuit from latching up at the beginning ofeach charging cycle, a delay network consisting of Q1 and itsassociated circuitry is used to prevent the current sourcefrom turning on until the trigger voltage has reached asufficiently high level. This is achieved in the following way:


LOAD500 W

90 V ± 2

110-130 Vrms

D1

D21N4747

20 V

R56.8 k

R410 k

1 k

R31 k

R2

R110 k

C10.1 µF100 V

R74.7 k

R810 k

R106.8 k

Q22N3903

Q12N3906

R6300 k

Q32N6027

Q5MCR16M

R9100 k

Figure 6.77. (a). rms Voltage Regulator

90

90 100 110 120 130 140 150 160

6

2

3

4

5

8050

60

70

80

170

7

INPUT VOLTAGE (V rms)

100

OU

TPU

T VO

LTAG

E (V

rms)

CO

ND

UC

TIO

N A

NG

LE (m

s)

CONDUCTION TIMEOUTPUT VOLTAGE

(b). Output Voltage and Conduction Angleversus Input Voltage

Prior to the conduction of D2, the voltage on the base of Q1is set by the voltage divider (R4 + R5)/(R1 + R3 + R4 + R5).This causes the base of Q1 to be more positive than theemitter and thus prevents Q1 from conducting until thevoltage across R3 is sufficient to forward bias the base-emit-ter junction of Q1. This occurs when the line voltage hasincreased to about 15 volts.

The circuit can be operated over a different voltage rangeby changing resistors R6 and/or R4 which change thecharging rate of C1.

Figure 6.77(b) provides a plot of output voltage andconduction angle versus input voltage for the regulator. Asthe figure indicates, good regulation can be obtainedbetween the input voltage range of 110 to 130 volts.

SILICON BILATERAL SWITCH (SBS)APPLICATIONS

It is important that thyristor trigger circuitry be capable ofsupplying a fast rising, high current gate pulse to the powerthyristors in order to prevent di/dt failure, especially whenthey are subjected to high inrush load currents. Because ofthe regenerative switching action and low dynamic onresistance of the SBS, it is ideally suited for this use.

These circuits indicate the uses for the SBS. In someapplications the device switches on at VS while in others it isturned on by drawing a small current out of the gate lead.

LAMP DIMMER Figure 6.78 is the schematic diagram of a low cost full

range lamp dimmer. Shunting the SBS with two 20 kΩresistors minimizes the “flash-on” or hysteresis effect. VS ofthe SBS is reduced to about 4 volts, and since this is belowthe operating voltage of the internal zener diodes, thetemperature sensitivity of the device is increased.

An improved full range power controller suitable for lampdimming and similar applications is shown in Figure 6.79.

It operates from a 120 volt, 60 Hz ac source and cancontrol up to 1000 watts of power to incandescent bulbs. Thepower to the bulbs is varied by controlling the conductionangle of TRIAC Q1. Many circuits can be used for phasecontrol, but the single RC circuit used is the simplest by farand was consequently chosen for this particular application.For settings such that no power is delivered to the load, thetiming capacitor would never discharge through the SBS.The result is an abnormal amount of apparent phase shiftcaused by the capacitor starting to charge toward a source ofvoltage with a residual charge of the opposite sign. This is thecause of the hysteresis effect and is eliminated in this circuitby the addition of the two diodes and 5.1 kΩ resistorconnected to the SBS gate. At the end of each positive halfcycle when the applied voltage drops below that of the

LOAD

120 VAC

0.22 µF

500 k

20 k

MAC12D

MBS4991

20 k

Figure 6.78. Low Cost Lamp Dimmer



LOAD

0.22 µF

120 VAC

470

1 M

MBS4991

1N4003

5.1 k

MAC12D

1N4003 0.1 µF

Q1

10 k

Figure 6.79. 1000 W TRIAC Light Dimmer

capacitor, gate current flows out of the SBS and it switcheson, discharging the capacitor to near zero volts.

The RC network shown across the TRIAC represents atypical snubber circuit that is normally adequate to preventline transients from accidentally firing the TRIAC.

ELECTRONIC CROWBAROccasionally the need arises for positive protection of

expensive electrical or electronic equipment against exces-sive supply voltage. Such overvoltage conditions can occurdue to improper switching, wiring, short circuits or failure ofregulators. Where it is economically desirable to shut downequipment rather than allow it to operate on excessive supplyvoltage, an electronic “crowbar” circuit such as the oneshown in Figure 6.80 can be employed to quickly place ashort-circuit across the power lines, thereby dropping thevoltage across the protected device to near zero and blowinga fuse. Since the TRIAC and SBS are both bilateral devices,the circuit is equally useful on ac or dc supply lines. With thevalues shown for R1, R2 and R3, the crowbar operating point

can be adjusted over the range of 60 to 120 volts dc or 42 to84 volts ac. The resistor values can be changed to cover adifferent range of supply voltages. The voltage rating of theTRIAC must be greater than the highest operating point asset by R2. I1 is a low power incandescent lamp with a voltagerating equal to the supply voltage. It may be used to checkthe set point and operation of the unit by opening the testswitch and adjusting the input or set point to fire the SBS. Analarm unit such as the Mallory Sonalert may be connectedacross the fuse to provide an audible indication of crowbaraction. Note that this circuit may not act on short, infrequentpower line transients.

SBS APPLICATIONS IN POWER CONTROL

The incandescent-lamp dimmer was one of the firstcircuits to use thyristors after their invention and hasremained one of the most important applications of thesedevices.

Figure 6.81 shows the basic control circuit. In the positivehalf-cycle, the 0.1 µF capacitor charges through the dual-section phase-shift circuit until its voltage reaches thebreak-over potential of the MBS4991 SBS. The MBS4991potential then drops to about 1 volt, forcing charge from the0.1 µF capacitor through the gate of the MAC12D TRIAC.This current turns the TRIAC on. When the TRIAC turns on, itremoves the voltage from the timing circuit. C1 thendischarges through the latched on TRIAC and the SBS if italso holds. What happens depends on the setting of R1, andthe switching current, switching voltage, latching current andholding current of the SBS. Analysis of the circuit behavior isdifficult and cannot be treated on a half-cycle basisbecause the previous half-cycle must be considered toestablish the initial conditions, and because large residualvoltages remain on C1. Several cycles of the ac line areneeded to establish steady state conduction angles.

SUPPLY VOLTAGEAC OR DC

R31 k

R21 k

R110 k

SET POINT ADJ.

0.1 µFMBS4991

PUSH TO TEST I1

TRIAC

TO ELECTRICAL ORELECTRONIC EQUIPMENT

Figure 6.80. Electronic Crowbar


27 kR2

LINE

R1100 k

MT2 MAC12D

C1

0.22 µF

C2

0.1 µF15

MBS4991

G

MT1

100

LOAD

Figure 6.81. Low Hysteresis Dual SectionPhase Control Circuit

Hysteresis in the single RC phase controller is a result ofthe initial voltage on the capacitor before triggering. If thecontrol is set to completely turn-off the lamp, triggering doesnot occur, and the capacitor voltage alternates up and downto some value less than VS. If the control is advanced, theSBS fires and latches, causing the capacitor to charge fromthe previous polarity on-state voltage of about 1 V. Conse-quently, the control settings for dim illumination depend onwhether the potentiometer is being advanced from an offstate or retarded from a state with the lamp on, because thetiming capacitor must charge through a different voltagegradient in the two cases.

The dual-section phase-shift network prevents hysteresisand allows reliable and stable triggering at all conductionangles. The 100 kΩ variable resistor R1 and the 0.22 µFcapacitor C1 perform the basic phase shifting and serve as a

charging supply for the 0.1 µF charge-storage capacitor C2.The 27 kΩ resistor isolates the trigger circuit from the phaseshifter so that the voltage on C1 is only minimally affected bythe triggering action. It is this isolation that reduces thehysteresis, prevalent in single-section phase-shift systems,to an unnoticeable level.

Anti-parallel SCRs allow the control of full-wave power athigher currents and frequencies than possible with triacs. Forexample, the 55 ampere SCRs in Figure 6.82 provide 75ampere capability compared to 40 amperes with the singleMAC224 triac in Figure 6.81. The current alternates betweenthe SCRs allowing a half-cycle of recovery time. So, there isno commutating dv/dt limitation. This guarantees turn-offeven when the load current contains high frequency compo-nents.

Figure 6.82 illustrates a trigger circuit using a low cost

LINE

100 k

0.22 µF27 k

0.1 µF15

MBS4991

P

S

MCR265-6

T*1N4001

SCR-2

SCR-1 MCR265-6

1N4001

*200 µHMINIMUMPRIMARYINDUCTANCE,1:1 TURN RATIO(SPRAGUE 11Z12)

LOAD

Figure 6.82. Full-Wave SCR Control Circuit Using Low Cost Single Winding Trigger Transformer



*200 µH MINIMUM PRIMARY INDUCTANCE, 1:1 TURN RATIO (DALE PT50)

LINE

27 k

MBS4991

1N4001

T*100 k

0.1 µF

+

15

LOAD

1N4001

–

0.22 µF

MCR265-6 (2)

SCR-2SCR-1

Figure 6.83. Variation of Basic Control Circuit to Provide Controlled DC Output

single winding transformer to fire both SCRs. In thepositive half-cycle, SCR-1 is triggered through the primaryof the pulse transformer. In the negative half-cycle, the 0.1µF triggering capacitor discharges through the shunt G-Kdiode of SCR-1 and the primary of the pulse transformer,inducing a pulse in the secondary, which triggers SCR-2.

The circuits described above were designed for incan-descent-lamp dimmers and are ideally suited for thispurpose. However, they may have many other uses, whichare perhaps not immediately obvious. For example,universal and shaded-pole motors are easily and conve-niently controlled with these circuits. These motors havehigher torque at low speeds when open-loop controlled inthis manner rather than with rheostats or variable trans-formers, owing to the higher voltage pulses applied. Inanother application, a slight modification of the basiccontrol circuit allows control of the dc output of a fullwaverectifier bridge using pulse-transformer coupling (Figure6.83).

The power rating of these circuits is limited only by thethyristors employed. The control circuit will give sufficientdrive for any thyristor that can be triggered with 50 mA orless gate current. For example, with MCR3818-4 con-trolled rectifiers mounted on a suitable heat sink, thesecircuits will control up to 3 kW power from a 120 V line.

TRIAC ZERO-POINT SWITCH APPLICATIONS

BASIC TRIAC ZERO-POINT SWITCHFigure 6.84 shows a manually controlled zero-point switch

useful in power control for resistive loads. Operation of thecircuit is as follows. On the initial part of the positive halfcycle, the voltage is changing rapidly from zero causing alarge current flow into capacitor C2. The current through C2flows through R4, D3, and D4 into the gate of the TRIAC Q2causing it to turn on very close to zero voltage. Once Q2turns on, capacitor C3 charges to the peak of the line voltagethrough D5. When the line voltage passes through the peak,D5 becomes reverse-biased and C3 begins to dischargethrough D4 and the gate of Q2. At this time the voltage on C3lags the line voltage. When the line voltage goes throughzero there is still some charge on C3 so that when the linevoltage starts negative C3 is still discharging into the gate ofQ2. Thus Q2 is also turned on near zero on the negative halfcycle. This operation continues for each cycle until switch S1is closed, at which time SCR Q1 is turned on. Q1 shunts thegate current away from Q2 during each positive half cyclekeeping Q2 from turning on. Q2 cannot turn on during thenegative cycle because C3 cannot charge unless Q2 is onduring the positive half cycle.


115 VAC60 Hz

C31 µF200 V

R51 k2 W

C22 µF200 V

D41N4001

LOAD

+

Q22N6346

+

S1

R31.2 k7 W

+ D61N4372

R210 k

D11N4003

R112 k2 W

D31N4003

Q1MCR1906-4

D21N4003

D51N4003

R4150 Ω1 W

C110 µF

5 V

Figure 6.84. Zero-Point SwitchIf S1 is initially closed during a positive half cycle, SCR Q1turns on but circuit operation continues for the rest of thecomplete cycle and then turns off. If S1 is closed during anegative half cycle, Q1 does not turn on because it is reversebiased. Q1 then turns on at the beginning of the positive halfcycle and Q2 turns off.

Zero-point switching when S1 is opened is ensured by thecharacteristic of SCR Q1. If S1 is opened during the positivehalf cycle, Q1 continues to conduct for the entire half cycleand TRIAC Q2 cannot turn on in the middle of the positivehalf cycle. Q2 does not turn on during the negative half cyclebecause C3 was unable to charge during the positive halfcycle. Q2 starts to conduct at the first complete positive halfcycle. If S1 is opened during the negative half cycle, Q2again cannot turn on until the beginning of the positive halfcycle because C3 is uncharged.

A 3-volt gate signal for SCR Q1 is obtained from D1, R1,C1, and D6.

AN INTEGRATED CIRCUIT ZERO VOLTAGE SWITCHA single CA3059/79 integrated circuit operating directly off

the ac line provides the same function as the discrete circuitshown in Figure 6.84. Figure 6.85 shows its block diagram.The circuit operates a power triac in quadrants one andfour, providing gate pulses synchronized to the zero voltagepoint of the ac cycle. This eliminates the RFI resulting fromthe control of resistive loads like heaters and flashing lamps. Table 6.12 specifies the value of the input series resistor forthe operating line voltage. Figure 6.86 shows the pinconnection for a typical application.

RX

–

+

15 V

ON/OFFSENSINGAMP

100µF

ACINPUT

12

ZEROCROSSINGDETECTOR

5RS

11

CURRENTBOOST

LIMITER

10

9

13

POWERSUPPLY

VCC

TRIACDRIVE

DC MODE or400 Hz INPUT

VCCRL

MT2

ACINPUT

VOLTAGE

3

4

GATE

2

GND

+

78 1

INHIBIT EXTERNAL TRIGGER*NTC SENSOR

VCC

MT1

6

14

–

PROTECTIONCIRCUIT

RP

Figure 6.85. Functional Block Diagram

*



R15 k

R25 k

+

120 Vrms60 Hz

100 µf15 V

RL

CA3059

RS10 k

T2800D

ONOFF

2

3

8

11109

13 14

4

5

7

Figure 6.86. Zero Voltage Switch Using CA3059Integrated Circuit

Table 6.12.

AC Input Voltage(50/60 Hz)

vac

Input SeriesResistor (R S)

kΩ

Dissipation Ratingfor R S

W

24 2 0 0 524 2.0 0.524120

2.010

0.52 0120 10 2.0

208/230 20 4 0208/230 20 4.0277 25 5.0277 25 5.0

TEMPERATURE CONTROL WITH ZERO-POINTSWITCHINGZERO VOLTAGE SWITCH PROPORTIONAL BANDTEMPERATURE CONTROLLER

Figure 6.87 shows the block diagram for the UAA1016Bintegrated circuit temperature controller. Figure 6.88 shows atypical application circuit. This device drives triacs with a zerovoltage full wave technique allowing RFI free power regula-tion of resistive loads and adjustable burst frequency tocomply with standards. It operates directly off the ac linetriggers the triac in Q2 and Q3, is sensor fail-safe, andprovides proportional temperature control over an adjustableband. Consult the device data sheet (DS9641) for detailedinformation.

LOAD

220 VAC

8

220 VAC

2

CPin RSYNC2

–

6+

+

R41.0M

VREF

5– VCC

1

(NTC)TEMP.

SENSOR

RL180 k

4

FAIL-SAFETEMP.SET

3

R2R1

R3

7

MAC224-8

PULSEAMPLIFIER

SAMPLING FULL WAVE

LOGIC

SAWTOOTHGENERATOR

COMPARATOR

UAA1016B

SYNCHRO-NIZATION

POWERSUPPLY

R2R3

Figure 6.87. UA1016B Block Diagram and Pin Assignment

VREFVPin 1R4

R2 | | R3 1

Design Notes: 1. Let R4 5RL

2. Select Ratio for a symmetrical reference deviation centered about Pin 1 output swing, R2 will be slightly greater than R3.

3. Select R2 and R3 values for the desired reference deviation where


6.8k

RT : NTC R @ 25°C = 22 k 10%B = 3700

MOV: 250 VAC VARISTOR

220 VAC

100Ω

0.1µF

50 k

22 k

6.8 k

3

RT

R4

RL

47 µF8.0 V

+2

HEATER2.0 kW

+100 µF

7

UAA1016B

100 k

18 k

1N4005

6

MAC224-8

2.0 W

58

1

4

Figure 6.88. Application Circuit — Electric Radiator with Proportional BandThermostat, Proportional Band 1 °C at 25°C

MO

V

TRIAC RELAY-CONTACT PROTECTIONA common problem in contact switching high current is

arcing which causes erosion of the contacts. A solution tothis problem is illustrated in Figure 6.89. This circuit can beused to prevent relay contact arcing for loads up to 50amperes.

115 VAC60 Hz

R11.5 k10 W

C120 µF250 V

+

115 V RELAY WITH PICK-UP AND DROP-OUT TIMES

OF 10-20 ms

50 AMPLOAD

D1 1N4004

MAC210A6

47

R210

10 W

R3

S1

C20.1 µF

Figure 6.89. TRIAC Prevents Relay Contact Arcing

There is some delay between the time a relay coil isenergized and the time the contacts close. There is also adelay between the time the coil is de-energized and the timethe contacts open. For the relay used in this circuit both timesare about 15 ms. The TRIAC across the relay contacts willturn on as soon as sufficient gate current is present to fire it.This occurs after switch S1 is closed but before the relaycontacts close. When the contacts close, the load currentpasses through them, rather than through the TRIAC, eventhough the TRIAC is receiving gate current. If S1 should beclosed during the negative half cycle of the ac line, the TRIACwill not turn on immediately but will wait until the voltagebegins to go positive, at which time diode D1 conductsproviding gate current through R1. The maximum time thatcould elapse before the TRIAC turns on is 8-1/3 ms for the 60Hz supply. This is adequate to ensure that the TRIAC will beon before the relay contact closes. During the positive halfcycle, capacitor C1 is charged through D1 and R2. Thisstores energy in the capacitor so that it can be used to keepthe TRIAC on after switch S1 has been opened. The timeconstant of R1 plus R2 and C1 is set so that sufficient gatecurrent is present at the time of relay drop-out after theopening of S1, to assure that the TRIAC will still be on. Forthe relay used, this time is 15 ms. The TRIAC therefore limitsthe maximum voltage, across the relay contacts upondropout to the TRIAC’s voltage drop of about 1 volt. TheTRIAC will conduct until its gate current falls below thethreshold level, after which it will turn off when the anodecurrent goes to zero. The TRIAC will conduct for severalcycles after the relay contacts open.



1N4742

0.6 V

4

10 k3 W

MAC228A6FP

1047

++

T

2.54 VREFERENCE

3.0 A

MR506

10 k

1.2 k

220250 V

B +

+75 k

220250 V

RTN

75 kINPUT

92 TO 276VAC

+8

100 k

1.6 M

10 k

1.27 V

1.27 V

6

1

7

2

3

+–

+

+

+–

5

+

+

+

–

–

2.8 V+

Figure 6.90. Automatic AC Line Voltage Selector

This circuit not only reduces contact bounce and arcing butalso reduces the physical size of the relay. Since the relay isnot required to interrupt the load current, its rating can bebased on two factors: the first is the rms rating of thecurrent-carrying metal, and the second is the contact area.This means that many well-designed 5 ampere relays can beused in a 50 ampere load circuit. Because the size of therelay has been reduced, so will the noise on closing. Anotheradvantage of this circuit is that the life of the relay will beincreased since it will not be subjected to contact burning,welding, etc.

The RC circuit shown across the contact and TRIAC (R3and C2) is to reduce dv/dt if any other switching element isused in the line.

AN AUTOMATIC AC LINE VOLTAGE SELECTOR USINGTHE MC34161 AND A TRIAC

Line operated switching regulators run off of 120 or 240VAC by configuring the main reservoir input capacitor filter asa full-wave doubler or full-wave bridge. This integrated circuitprovides the control signals and triggering for a TRIAC toautomatically provide this function.

Channel 1 senses the negative half cycles of the AC linevoltage. If the line voltage is less than 150 V, the circuit willswitch from bridge mode to voltage doubling mode after apreset time delay. The delay is controlled by the 100 kΩresistor and the 10 µF capacitor. If the line voltage is greaterthan 150 V, the circuit will immediately return to fullwavebridge mode.


Prepared by Horst Gempe

INTRODUCTION

The zero–cross family of optically isolated triac drivers in aninexpensive, simple and effective solution for interface ap-plications between low current dc control circuits such as logicgates and microprocessors and ac power loads (120, 240 or380 volt, single or 3–phase).

These devices provide sufficient gate trigger current for highcurrent, high voltage thyristors, while providing a guaranteed7.5 kV dielectric withstand voltage between the line and thecontrol circuitry. An integrated, zero–crossing switch on thedetector chip eliminates current surges and the resulting elec-tromagnetic interference (EMI) and reliability problems formany applications. The high transient immunity of 5000 V/µs,combined with the features of low coupling capacitance, highisolation resistance and up to 800 volt specified VDRM ratingsqualify this triac driver family as the ideal link between sensi-tive control circuitry and the ac power system environment.

Optically isolated triac drivers are not intended for standalone service as are such devices as solid state relays. Theywill, however, replace costly and space demanding discretedrive circuitry having high component count consisting ofstandard transistor optoisolators, support components includ-ing a full wave rectifier bridge, discrete transistors, triggerSCRs and various resistor and capacitor combinations.

This paper describes the operation of a basic driving circuitand the determination of circuit values needed for proper im-plementation of the triac driver. Inductive loads are discussedalong with the special networks required to use triacs in their

presence. Brief examples of typical applications are pres-ented.

CONSTRUCTION

The zero–cross family consists of a liquid phase EPI, in-frared, light emitting diode which optically triggers a silicondetector chip. A schematic representation of the triac driveris shown in Figure 1. Both chips are housed in a small, 6–pindual–in–line (DIP) package which provides mechanical in-tegrity and protection for the semiconductor chips from exter-nal impurities. The chips are insulated by an infraredtransmissive medium which reliably isolates the LED inputdrive circuits from the environment of the ac power load. Thisinsulation system meets the stringent requirements for isola-tion set forth by regulatory agencies such as UL and VDE.

THE DETECTOR CHIP

The detector chip is a complex monolithic IC which containstwo infrared sensitive, inverse parallel, high voltage SCRswhich function as a light sensitive triac. Gates of the individualSCRs are connected to high speed zero crossing detectioncircuits. This insures that with a continuous forward currentthrough the LED, the detector will not switch to the conductingstate until the applied ac voltage passes through a point nearzero. Such a feature not only insures lower generated noise(EMI) and inrush (Surge) currents into resistive loads andmoderate inductive loads but it also provides high noise immu-nity (several thousand V/µs) for the detection circuit.

IF

DETECTOR LED

MT

MT

Figure 6.1. Schematic of Zero Crossing Optically Isolated Triac Driver



SEMICONDUCTOR APPLICATION NOTE

REV 1



MT

MT


IF

VF

V

IDRM

IDRM VDRM

A2–

Figure 6.2. Simplified Schematic of Isolator

Q1BLOCKING

STATEVDRMIH

A2+

ON STATE

IH–

ON STATE

BLOCKING STATEQ111

Figure 6.3. Triac Voltage–Current Characteristic

I

IV

ELECTRICAL CHARACTERISTICS

A simplified schematic of the optically isolated triac driver isshown in Figure 2. This model is sufficient to describe all im-portant characteristics. A forward current flow through theLED generates infrared radiation which triggers the detector.This LED trigger current (IFT) is the maximum guaranteed cur-rent necessary to latch the triac driver and ranges from 5 mAfor the MOC3063 to 15 mA for the MOC3061. The LED’s for-ward voltage drop at IF = 30 mA is 1.5 V maximum. Voltage–current characteristics of the triac are identified in Figure 3.

Once triggered, the detector stays latched in the “on state”until the current flow through the detector drops below theholding current (IH) which is typically 100 µA. At this time, thedetector reverts to the “off” (non–conducting) state. The detec-tor may be triggered “on” not only by IFT but also by exceedingthe forward blocking voltage between the two main terminals(MT1 and MT2) which is a minimum of 600 volts for allMOC3061 family members. Also, voltage ramps (transients,noise, etc.) which are common in ac power lines may triggerthe detector accidentally if they exceed the static dV/dt rating.Since the fast switching, zero–crossing switch provides aminimum dV/dt of 500 V/µs even at an ambient temperatureof 70°C, accidental triggering of the triac driver is unlikely. Ac-cidental triggering of the main triac is a more likely occurrence.Where high dV/dt transients on the ac line are anticipated, aform of suppression network commonly called a “snubber”

must be used to prevent false “turn on” of the main triac. A de-tailed discussion of a “snubber” network is given under thesection “Inductive and Resistive Loads.”

Figure 4 shows a static dV/dt test circuit which can be usedto test triac drivers and power triacs. The proposed test meth-od is per EIA/NARM standard RS–443.

Tests on the MOC3061 family of triac drivers using the testcircuit of Figure 4 have resulted in data showing the effects oftemperature and voltage transient amplitude on static dV/dt.Figure 5 is a plot of dV/dt versus ambient temperature whileFigure 6 is a similar plot versus transient amplitude.

BASIC DRIVING CIRCUIT

Assuming the circuit shown in Figure 7 is in the blocking or“off” state (which means IF is zero), the full ac line voltage ap-pears across the main terminals of both the triac and the triacdriver. When sufficient LED current (IFT) is supplied and the acline voltage is below the inhibit voltage (IH in Figure 3), the triacdriver latches “on.” This action introduces a gate current in themain triac triggering it from the blocking state into full conduc-tion. Once triggered, the voltage across the main terminalscollapses to a very low value which results in the triac driveroutput current decreasing to a value lower than its holding cur-rent, thus forcing the triac driver into the “off” state, even whenIFT is still applied.

Figure 6.4. Static dV/dt Test Circuit

0

τRC

HV

470 Ω

10 k

DUT

–15 V

P8

SCOPE PROBE 100:1

0.001 µF

150 kΩ10 Ω

HV15 V

MERCURYWETTEDRELAY

100 ΩSIGNAL IN

50% DUTY CYCLE0

HV

16 ms

0.63HV

VOLTAGE APPLIED TO DUT –

TEST PROCEDURE –Turn the D.U.T. on, while applying sufficient dV/dt to ensure that it remains on, even after the trigger current is re-

moved. Then decrease dV/dt until the D.U.T. turns off. Measure τRC, the time it takes to rise to 0.63 HV, and divide 0.63HV by τRC to get dV/dt.


TRANSIENT AMPLITUDE (V)600500400300200100

500

1000

2000

5000

10000

TA, AMBIENT TEMPERATURE (°C)

100755025

600

TRANSIENT AMPLITUDE= 600 V

Figure 6.5. Static dV/dt versus Temperature Figure 6.6. Static dV/dt versus Transient Amplitude

dV/d

t [V/

µs]

dV/d

t [V/

µs]

The power triac remains in the conducting state until theload current drops below the power triac’s holding current, asituation that occurs every half cycle. The actual duty cycle forthe triac driver is very short (in the 1 to 3 µs region). When IFTis present, the power triac will be retriggered every half cycleof the ac line voltage until IFT is switched “off” and the powertriac has gone through a zero current point. (See Figure 8).

Resistor R (shown in Figure 7) is not mandatory when RL isa resistive load since the current is limited by the gate triggercurrent (IGT) of the power triac. However, resistor R (in com-bination with R–C snubber networks that are described in thesection “Inductive and Resistive Loads”) prevents possibledestruction of the triac driver in applications where the load ishighly inductive.

Unintentional phase control of the main triac may happen ifthe current limiting resistor R is too high in value. The functionof this resistor is to limit the current through the triac driver incase the main triac is forced into the non–conductive stateclose to the peak of the line voltage and the energy stored ina “snubber” capacitor is discharged into the triac driver. A cal-culation for the current limiting resistor R is shown below for

a typical 220 volt application: Assume the line voltage is 220volts RMS. Also assume the maximum peak repetitive drivercurrent (normally for a 10 micro second maximum time inter-val) is 1 ampere. Then

RVpeak

Ipeak

220 2 volts1 amp

311 ohms

One should select a standard resistor value >311 ohms 330 ohms.

The gate resistor RG (also shown in Figure 7) is only neces-sary when the internal gate impedance of the triac or SCR isvery high which is the case with sensitive gate thyristors.These devices display very poor noise immunity and thermalstability without RG. Value of the gate resistor in this caseshould be between 100 and 500. The circuit designer shouldbe aware that use of a gate resistor increases the required trig-ger current (IGT) since RG drains off part of IGT. Use of a gateresistor combined with the current limiting resistor R can resultin an unintended delay or phase shift between the zero–crosspoint and the time the power triac triggers.

IL

RLMT1RG

4

5

6

Figure 6.7. Basic Driving Circuit — TriacDriver, Triac and Load

MT2R

II

IFT

POWERTRIACTRIAC DRIVER

ZEROCROSSING

CIRCUIT

1

2

3

ACINPUT

IGT

IFT

AC LINE VOLTAGE

TRIAC DRIVER CURRENT I = IGT + II

V – ACROSS MAIN TRIAC

IL

Figure 6.8. Waveforms of a Basic DrivingCircuit



UNINTENDED TRIGGER DELAY TIME

To calculate the unintended time delay, one must rememberthat power triacs require a specified trigger current (IGT) andtrigger voltage (VGT) to cause the triac to become conductive.This necessitates a minimum line voltage VT to be present be-tween terminals MT1 and MT2 (see Figure 7), even when thetriac driver is already triggered “on.” The value of minimum linevoltage VT is calculated by adding all the voltage drops in thetrigger circuit:

VT = VR + VTM + VGT.Current I in the trigger circuit consists not only of IGT but alsothe current through RG:

I = IRG + IGT.Likewise, IRG is calculated by dividing the required gate trig-

ger voltage VGT for the power triac by the chosen value of gateresistor RG:

IRG = VGT/RGThus, I = VGT/RG + IGT.

All voltage drops in the trigger circuit can now be determinedas follows:

VR = I R = VGT/RG R + IGT R = R(VGT/RG+ IGT)

VTM = From triac driver data sheetVGT = From power triac data sheet.IGT = From power triac data sheet.

With VTM, VGT and IGT taken from data sheets, it can be seenthat VT is only dependent on R and RG.

Knowing the minimum voltage between MT1 and MT2 (linevoltage) required to trigger the power triac, the unintendedphase delay angle θd (between the ideal zero crossing of theac line voltage and the trigger point of the power triac) and thetrigger delay time td can be determined as follows:

d sin-1 VTVpeak

sin-1R(VGTRG IGT) VTM VGT

Vpeak

The time delay td is the ratio of θd to θVpeak (which is 90 de-grees) multiplied by the time it takes the line voltage to go fromzero voltage to peak voltage (simply 1/4f, where f is the line fre-quency). Thus

td = θd/90 1/4f.

Figure 9 shows the trigger delay of the main triac versus thevalue of the current limiting resistor R for assumed values ofIGT. Other assumptions made in plotting the equation for td arethat line voltage is 220 V RMS which leads to Vpeak = 311 volts;RG = 300 ohms; VGT = 2 volts and f = 60 Hz. Even though thetriac driver triggers close to the zero cross point of the ac volt-age, the power triac cannot be triggered until the voltage of theac line rises high enough to create enough current flow to latchthe power triac in the “on” state. It is apparent that significanttime delays from the zero crossing point can be observedwhen R is a large value along with a high value of IGT and/ora low value of RG. It should be remembered that low values ofthe gate resistor improve the dV/dt ratinigs of the power triacand minimize self latching problems that might otherwise oc-cur at high junction temperatures.

15001000300 500R (OHMS)

2000

200

02000

Figure 6.9. Time Delay t d versus Current Limiting Resistor R

tµs

)d(

SWITCHING SPEED

The switching speed of the triac driver is a composition ofthe LED’s turn on time and the detector’s delay, rise and falltimes. The harder the LED is driven the shorter becomes theLED’s rise time and the detector’s delay time. Very short IFTduty cycles require higher LED currents to guarantee “turn on”of the triac driver consistent with the speed required by theshort trigger pulses.

Figure 10 shows the dependency of the required LED cur-rent normalized to the dc trigger current required to trigger thetriac driver versus the pulse width of the LED current. LED trig-ger pulses which are less than 100 µs in width need to be high-er in amplitude than specified on the data sheet in order toassure reliable triggering of the triac driver detector.

The switching speed test circuit is shown in Figure 11. Notethat the pulse generator must be synchronized with the 60 Hzline voltage and the LED trigger pulse must occur near thezero cross point of the ac line voltage. Peak ac current in thecurve tracer should be limited to 10 mA. This can be done bysetting the internal load resistor to 3 k ohms.


Motorola isolated triac drivers are trigger devices and de-signed to work in conjunction with triacs or reverse parallelSCRs which are able to take rated load current. However, assoon as the power triac is triggered there is no current flowthrough the triac driver. The time to turn the triac driver “off” de-pends on the switching speed of the triac, which is typically onthe order of 1–2 µs.

1 2 1005001

20

5

5 10 20

10

15

25

Figure 6.10. I FT Normalized to I FT dc As Specified onthe Data Sheet

LED TRIGGER PULSE WIDTH (µs)

I FT,

NO

RM

ALIZ

ED L

ED T

RIG

GER

CU

RR

ENT

NORMALIZED TO:PW IN 100 µs

ZEROCROSSING

CIRCUIT

10 Ω

DUTAMPLITUDE CONTROL

DELAY CONTROL

PULSE WIDTH CONTROL

Figure 6.11. Test Circuit for LED Forward Trigger Current versus Pulse Width

AC LINESYNC

IFMONITOR

SCOPE

PULSEGENERATOR

3

2

1

4

6

5

RL

CURVETRACER (AC MODE)

INDUCTIVE AND RESISTIVE LOADS

Inductive loads (motors, solenoids, etc.) present a problemfor the power triac because the current is not in phase with thevoltage. An important fact to remember is that since a triac canconduct current in both directions, it has only a brief intervalduring which the sine wave current is passing through zero torecover and revert to its blocking state. For inductive loads, thephase shift between voltage and current means that at thetime the current of the power handling triac falls below theholding current and the triac ceases to conduct, there existsa certain voltage which must appear across the triac. If thisvoltage appears too rapidly, the triac will resume conductionand control is lost. In order to achieve control with certain in-ductive loads, the rate of rise in voltage (dV/dt) must be limitedby a series RC network placed in parallel with the power triac.The capacitor Cs will limit the dV/dt across the triac.

The resistor Rs is necessary to limit the surge current fromCs when the triac conducts and to damp the ringing of the ca-pacitance with the load inductance LL. Such an RC network iscommonly referred to as a “snubber.”

Figure 12 shows current and voltage wave forms for thepower triac. Commutating dV/dt for a resistive load is typically

only 0.13 V/µs for a 240 V, 50 Hz line source and 0.063 V/µsfor a 120 V, 60 Hz line source. For inductive loads the “turn off”time and commutating dV/dt stress are more difficult to defineand are affected by a number of variables such as back EMFof motors and the ratio of inductance to resistance (power fac-tor). Although it may appear from the inductive load that therate or rise is extremely fast, closer circuit evaluation revealsthat the commutating dV/dt generated is restricted to some fi-nite value which is a function of the load reactance LL and thedevice capacitance C but still may exceed the triac’s criticalcommuting dV/dt rating which is about 50 V/µs. It is generallygood practice to use an RC snubber network across the triacto limit the rate of rise (dV/dt) to a value below the maximumallowable rating. This snubber network not only limits the volt-age rise during commutation but also suppresses transientvoltages that may occur as a result of ac line disturbances.

There are no easy methods for selecting the values for Rsand Cs of a snubber network. The circuit of Figure 13 is adamped, tuned circuit comprised of Rs, Cs, RL and LL, and toa minor extent the junction capacitance of the triac. When thetriac ceases to conduct (this occurs every half cycle of the linevoltage when the current falls below the holding current), the



load current receives a step impulse of line voltage which de-pends on the power factor of the load. A given load fixes RLand LL; however, the circuit designer can vary Rs and Cs.Commutating dV/dt can be lowered by increasing CS while Rscan be increased to decrease resonant “over ringing” of thetuned circuit. Generally this is done experimentally beginningwith values calculated as shown in the next section and, then,adjusting Rs and Cs values to achieve critical damping and alow critical rate of rise of voltage.

Less sensitive to commutating dV/dt are two SCRs in an in-verse parallel mode often referred to as a back–to–back SCRpair (see Figure 15). This circuit uses the SCRs in an alternat-

ing mode which allows each device to recover and turn “off”during a full half cycle. Once in the “off” state, each SCR canresist dV/dt to the critical value of about 100 V/µs. Opticallyisolated triac drivers are ideal in this application since bothgates can be triggered by one triac driver which also providesisolation between the low voltage control circuit and the acpower line.

It should be mentioned that the triac driver detector does notsee the commutating dV/dt generated by the inductive loadduring its commutation; therefore, the commutating dV/dt ap-pears as a static dV/dt across the two main terminals of thetriac driver.

AC CURRENT THROUGHPOWER TRIAC

TIME

VOLTAGE ACROSS POWER TRIAC

Figure 6.12. Current and Voltage Waveforms During Commutation

Inductive Load

VOLTAGE ACROSS POWER TRIAC

AC LINE VOLTAGE

0

t0

IF(OFF)IF(ON)

Resistive Load

t0TIME

d

AC CURRENT

AC LINE VOLTAGE

IF(OFF)

IF(ON)

COMMUTATINGdV/dt

COMMUTATINGdV/dt


SNUBBER DESIGN — THE RESONANT METHOD

If R, L and C are chosen to resonate, the voltage waveformon dV/dt will look like Figure 14. This is the result of a dampedquarter–cycle of oscillation. In order to calculate the compo-nents for snubbing, the dV/dt must be related to frequency.Since, for a sine wave,

V(t) = VP sin tdV/dt = VP cost tdV/dt(max) = VP = VP 2f

f dVdt

2VA(max)

Where dV/dt is the maximum value of off state dV/dt speci-fied by the manufacturer.

From:

C 1(2f)2L

f 12 LC

We can choose the inductor for convenience. Assuming theresistor is chosen for the usual 30% overshoot:

R LC

Assuming L is 50 µH, then:

f (dVdt)min2VA(max)

50 Vµs

2(294 V) 27 kHz

C 1(2f)2L

0.69 µF

R LC 50 µH

0.69 µF 8.5 Ω

ZEROCROSSING

CIRCUIT

RS

CS

R

LL RL

1

LOAD

Figure 6.13. Triac Driving Circuit — with Snubber

2

3

5

6

4

AC

STEP FUNCTIONVOLTAGE ACROSS TRIAC

RG RS

CS

RRG

AC LINE

RLLL

ZEROCROSSING

CIRCUIT

1

V

2

3

5

6

4

CONTROL

Figure 6.14. Voltage Waveform After Step VoltageRise – Resonant Snubbing

Figure 6.15. A Circuit Using Inverse Parallel SCRs



INRUSH (SURGE) CURRENTS

The zero crossing feature of the triac driver insures lowergenerated noise and sudden inrush currents on resistiveloads and moderate inductive loads. However, the user shouldbe aware that many loads even when started at close to theac zero crossing point present a very low impedance. For ex-ample, incandescent lamp filaments when energized at thezero crossing may draw ten to twenty times the steady statecurrent that is drawn when the filament is hot. A motor whenstarted pulls a “locked rotor” current of, perhaps, six times itsrunning current. This means the power triac switching theseloads must be capable of handling current surges withoutjunction overheating and subsequent degradation of its elec-trical parameters.

Almost pure inductive loads with saturable ferromagneticcores may display excessive inrush currents of 30 to 40 timesthe operating current for several cycles when switched “on” atthe zero crossing point. For these loads, a random phase triac

driver (MOC3020 family) with special circuitry to provide initial“turn on” of the power triac at ac peak voltage may be the opti-mized solution.

ZERO CROSS, THREE PHASE CONTROL

The growing demand for solid state switching of ac powerheating controls and other industrial applications has resultedin the increased use of triac circuits in the control of threephase power. Isolation of the dc logic circuitry from the ac line,the triac and the load is often desirable even in single phasepower control applications. In control circuits for poly phasepower systems, this type of isolation is mandatory becausethe common point of the dc logic circuitry cannot be referredto a common line in all phases. The MOC3061 family’s charac-teristics of high off–state blocking voltage and high isolationcapability make the isolated triac drivers devices for a simpli-fied, effective control circuit with low component count asshown in Figure 16. Each phase is controlled individually by

ZEROCROSSING

CIRCUIT

ZEROCROSSING

CIRCUIT

Figure 6.16. 3 Phase Control Circuit

B AND C SWITCH OFF,A FOLLOWS

LED CURRENT

3 PHASE LINE VOLTAGE

A

RL(3 PLACES)

R

CS

RS

RG

A

R

CS

RS

RG

B

6

4

2

3

5

ZEROCROSSING

CIRCUIT

1

RG

R6

1

5

3

2

4

1

2

3

CB

4

C

6

5

B

RS

C SWITCHES ON

A AND B SWITCH ON

CS

A

C

RL(3 PLACES)


ZEROCROSSING

CIRCUIT

BRIDGE∆ V = 2 mV/°C

–

+

RLR

4.7 k

6

4

1

2

+12 V

Ro

3

4.7 m

VTEMP

TEMP.SENS.

14 MC33074A

1 µF

TEMP. SET

VD OSC

Co

100 k

RG

14 MC33074A

5

GND

RIFT

Figure 6.17. Proportional Zero Voltage Switching Temperature Controller

100 k

AC

100 k

–

+

–

+

4.7 k

COMPARATOR

VOLTAGE CONTROLLED PULSE WIDTH MODULATOR

OSCILLATOR

4.7 k4.7 k

1N4001

GAIN STAGEAV = 1000

Vo = 2 V/°C

10 k

1N40001

14 MC33074A

a power triac with optional snubber network (Rs, Cs) and anisolated triac driver with current limiting resistor R. All LEDsare connected in series and can be controlled by one logicgate or controller. An example is shown in Figure 17.

At startup, by applying IF, the two triac drivers which seezero voltage differential between phase A and B or A and C orC and B (which occurs every 60 electrical degrees of the acline voltage) will switch “on” first. The third driver (still in the“off” state) switches “on” when the voltage difference betweenthe phase to which it is connected approaches the same volt-age as the sum voltage (superimposed voltage) of the phasesalready switched “on.” This guarantees zero current “turn on”of all three branches of the load which can be in Y or Delta con-figuration. When the LEDs are switched “off,” all phasesswitch “off” when the current (voltage difference) between anytwo of the three phases drops below the holding current of thepower triacs. Two phases switched “off” create zero current.In the remaining phase, the third triac switches “off” at thesame time.

PROPORTIONAL ZERO VOLTAGE SWITCHING

The built–in zero voltage switching feature of the zero–cross triac drivers can be extended to applications in which itis desirable to have constant control of the load and a mini-mization of system hysteresis as required in industrial heaterapplications, oven controls, etc. A closed loop heater controlin which the temperature of the heater element or the chamberis sensed and maintained at a particular value is a good exam-ple of such applications. Proportional zero voltage switchingprovides accurate temperature control, minimizes overshootsand reduces the generation of line noise transients.

Figure 17 shows a low cost MC33074 quad op amp whichprovides the task of temperature sensing, amplification, volt-age controlled pulse width modulation and triac driver LEDcontrol. One of the two 1N4001 diodes (which are in a Wheat-stone bridge configuration) senses the temperature in theoven chamber with an output signal of about 2 mV/°C. Thissignal is amplified in an inverting gain stage by a factor of



1000 and compared to a triangle wave generated by an os-cillator. The comparator and triangle oscillator form a volt-age controlled pulse width modulator which controls thetriac driver. When the temperature in the chamber is belowthe desired value, the comparator output is low, the triacdriver and the triac are in the conducting state and full poweris applied to the load. When the oven temperature comesclose to the desired value (determined by the “temp set” po-tentiometer), a duty cycle of less than 100% is introducedproviding the heater with proportionally less power untilequilibrium is reached. The proportional band can be con-trolled by the amplification of the gain stage — more gainprovides a narrow band; less gain a wider band. Typical wa-veforms are shown in Figure 18.

VTEMP.

VOSC

VAC(ACROSS RL)

ILED

Vo COMP.

FINE REG.TOO HOTFINE REG.TOO COLD

Figure 6.18. Typical Waveforms of TemperatureController


By George TempletonThyristor Applications Engineer

INTRODUCTION

This paper describes the series connection of triacs tocreate a high voltage switch suitable for operation atvoltages up to 2000 Volts. They can replace electrome-chanical contactors or extend their current rating andlifetime. Motor starters and controllers operating at linevoltages of 240 Volts or more require high-voltageswitches. Transformer action and resonant snubbercharging result in voltages much greater than the peak ofthe line. Triacs can be subjected to both commutating andstatic dV/dt when multiple switching devices are present inthe circuit. Snubber designs to prevent static dV/dt turn-onresult in higher voltages at turn-off. Variable load imped-ances also raise voltage requirements.

The benefits of series operation include: higher blockingvoltage, reduced leakage, better thermal stability, higherdV/dt capability, reduced snubber costs, possible snub-berless operation, and greater latitude in snubber design.The advantages of triacs as replacements for relaysinclude:• Small size and light weight.• Safety — freedom from arcing and spark initiated explo-

sions.• Long lifespan — contact bounce and burning

eliminated.• Fast operation — turn-on in microseconds and turn-off in

milliseconds.• Quiet operation.

Triacs can be used to replace the centrifugal switch incapacitor start motors. The blocking voltage required of thetriac can be much greater than the line voltage would

suggest. It must block the vector sum of the line, auxiliarywinding, and start capacitor voltage. This voltage increaseswhen triac turn-off occurs at higher rpm.

TRIGGERING

Figure 1 illustrates a series thyristor switching circuit. Inthis circuit, the top triac triggers in Quadrant 1 when thebottom triac triggers in Quadrant 3. When the optocouplerturns on, gate current flows until the triacs latch. At thattime, the voltage between the gate terminals drops toabout 0.6 Volts stopping the gate current. This processrepeats each half cycle. The power rating of the gateresistor can be small because of the short duration of thegate current. Optocoupler surge or triac gate ratingsdetermine the minimum resistance value. For example,when the maximum optocoupler ITSM rating is 1 A:

Rg VpeakImax (1.0)

Rg 750 V1 A 750 Ohm

The triacs retrigger every half cycle as soon as the linevoltage rises to the value necessary to force the triggercurrent. The instantaneous line voltage V is

V IGT Rg 2 VGT 2 VTM (1.1)

where VGT, IGT are data book specifications for the triacand VTM is the on-voltage specification for the optocoup-ler.

The phase delay angle is

d SIN1 V2 VLINE (1.2)

∆I

3 σ

6 σ

3 σ

6 σ

DESIGNCAPABILITY

PROCESS WIDTH

MEANMT1

MT1

MT2

MT2

IG

RG

GIL

G

Figure 6.1. Series Switch Figure 6.2. Designing for Probable Leakage

SEMICONDUCTOR TECHNICAL DATA

REV 1



STATIC VOLTAGE SHARING

Maximum blocking voltage capability results when thetriacs share voltage equally. The blocking voltage can bedc or ac. A combination of both results when the triacswitches the start winding in capacitor start motors. In thesimple series connection, both triacs operate with anidentical leakage current which is less than that of eitherpart operated alone at the same voltage. The voltagesacross the devices are the same only when their leakageresistances are identical. Dividing the voltage by theleakage current gives the leakage resistance. It can rangefrom 200 kohm to 2000 megohm depending on devicecharacteristics, temperature, and applied voltage.

Drawing a line corresponding to the measured seriesleakage on each device’s characteristic curve locates itsoperating point. Figure 3a shows the highest and lowestleakage units from a sample of 100 units. At roomtemperature, a leakage of 350 nA results at 920 Volts. Thelowest leakage unit blocks at the maximum specified valueof 600 Volts, while the highest blocks 320 Volts. A 50percent boost results.

Figure 3b shows the same two triacs at rated TJmax.The magnitude of their leakage increased by a factor ofabout 1000. Matching between the devices improved,allowing operation to 1100 Volts without exceeding the 600Volt rating of either device.

Identical case temperatures are necessary to achievegood matching. Mounting the devices closely together ona common heatsink helps.

A stable blocking condition for operation of a single triacwith no other components on the heatsink results when

dIMTdTJ

dTJdPJ

dPJdIMT

1 (2.0)

Thermal run-away is a regenerative process which occurswhenever the loop gain in the thermal feedback circuitreaches unity. An increase in junction temperature causesincreased leakage current and higher power dissipation.Higher power causes higher junction temperature which inturn leads to greater leakage. If the rate of heat release at the

junction exceeds the rate of removal as temperature in-creases, this process repeats until the leakage current issufficient to trigger the thyristor on.

DC blocking simplifies analysis. A design providing stabledc operation guarantees ac performance. AC operationallows smaller heatsinks.

The last term in the stability equation is the appliedvoltage when the load resistance is low and the leakagecauses negligible voltage drop across it. The second termis the thermal resistance from junction to ambient. The firstterm describes the behavior of leakage at the operatingconditions. For example, if leakage doubles every 10°C, atriac operating with 2 mA of leakage at 800 Vdc with a6°C/W thermal resistance is stable because

2 mA10°C

6°CW

800 V 0.96

Operating two triacs in series improves thermal stability.When two devices have matched leakages, each devicesees half the voltage and current or 1/4 of the power in asingle triac. The total leakage dissipation will approachhalf that of a single device operated at the same voltage.The additional voltage margin resulting from the highertotal blocking voltage reduces the chance that eitherdevice will operate near its breakdown voltage where theleakage current increases rapidly with small increments involtage. Higher voltage devices have lower leakagecurrents when operated near breakdown. Consequently,the highest breakover voltage unit in the pair will carry thegreatest proportion of the burden. If the leakage current islarge enough to cause significant changes in junctiontemperature, (∆TJ = φJC PD), the effect will tend to balancethe voltage division between the two by lowering theleakage resistance of the hotter unit. If the leakagemismatch between the two is large, nearly all the voltagewill drop across one device. As a result there will be littlebenefit connecting two in series.

Series blocking voltage depends on leakage matching.Blocking stability depends on predictable changes in leakagewith temperature. Leakage has three components.

Figure 6.3. Leakage Matching versus Temperature

(a) (b)

HIGH

∆IL

LOW

HIGH

LOW

100 V/ 100 nA/ 25°C 100 V/ 100 µA/ 125°C


Surface LeakagePassivation technique, junction design, and cleanliness

determine the size of this component. It tends to be smalland not very dependent on temperature.

Diffusion LeakageMeasurements with 1 volt reverse bias show that this

component is less than 10 percent of the total leakage forallowed junction temperatures. It follows an equation of theform:

I e(qvkT) (2.1)

and doubles about every 10°C. Its value can be estimatedby extrapolating backward from high temperature datapoints.

Depletion Layer Charge GenerationThis component is a result of carriers liberated from within

the blocking junction depletion layer. It grows with the squareroot of the applied voltage. The slope of the leakage versusapplied voltage is the mechanism allowing for series opera-tion with less than perfect leakage matching. Predictablediffusion processes determine this leakage. At temperaturesbetween 70 and 150°C it is given by:

i e EkT

(2.2)

where E = 1.1 eV, k = 8.62E – 5 eV/k, T = degrees Kelvin,and k = 8.62 x 10 – 5 eV/k.

It is useful to calculate the percentage change in leakagecurrent with temperature:

A 1i

didTJ

EkT2

0.08 8%°C

The coefficient A was evaluated on 3 different die sizetriacs by curve fitting to leakage measurements every 10°from 70 to 150°C. Actual values measured 0.064 at 125° and0.057 at 150°.

Deviations from this behavior will result at voltages andtemperatures where leakage magnitude, current gain, andavalanche multiplication aid unwanted turn-on. Sensitivegate triacs are not recommended for this reason.

DERATING AND LEAKAGE MATCHING

Operation near breakdown increases leakage mismatchbecause of the effects of avalanche multiplication. For

18

1.61.51.41.31.21.110.80.7 0.9

2

4

6

8

10

12

16

14

0.6

20

550 V

TJ = 25°C

Figure 6.4. Normalized Leakage (Mean = 1.0)

650 V

PER

CEN

T (S

AMPL

E SI

ZE =

100

)

series operation, devices should be operated at least 100Volts below their rating.

Figure 4 shows the leakage histogram for a triac sampleoperated at two different voltages. The skewedness in thehigh-voltage distribution is a consequence of some of thesample operating near breakdown.

HEATSINK SELECTIONSolving equations (2.0) and (2.3) for the thermal

resistance required to prevent runaway gives:

θJA1

AVi(3.0)

where θJA is thermal resistance, junction to ambient, in°C/W, A = 0.08 at TJ = 125°C, V = rated VDRM, and i = ratedIDRM.

θJA must be low enough to remove the heat resultingfrom conduction losses and insure blocking stability. Thelatter can be the limiting factor when circuit voltages arehigh. For example, consider a triac operated at 8 amps(rms) and 8 Watts. The allowed case temperature rise at25° ambient is 85°C giving a required θCA (thermalresistance, case to ambient) of 10.6°C/W. Allowing 1°C/Wfor θCHS (thermal resistance, case to heatsink) leaves9.6°C/W for θSA (thermal resistance, heatsink to ambient).However, thermal stability at 600 V and 2 mA IDRM requiresθJA = 10.4°C/W. A heatsink with θSA less than 7.4°C/W isneeded, given a junction to case thermal resistance of2°C/W.

The operation of devices in series does not change thecoefficient A. When matching and thermal tracking isperfect, both devices block half the voltage. The leakagecurrent and power divide by half and the allowed θJA forblocking stability increases by 4.

Low duty cycles allow the reduction of the heatsink size.The thermal capacitance of the heatsink keeps thejunction temperature within specification. The packagetime constant (Cpkg RθJA) is long in comparison with thethermal response time of the die, causing the instanta-neous TJ to rise above the case as it would were thesemiconductor mounted on an infinite heatsink. Heatsinkdesign requires estimation of the peak case temperatureand the use of the thermal derating curves on the datasheet. The simplest model applies to a very small heatsinkwhich could be the semicondutor package itself. When θSAis large in comparison with θCHS, it is sufficient to lump boththe package and heatsink capacitances together and treatthem as a single quantity. The models provide good resultswhen the heatsink is small and the thermal paths are short.

Model C, Figure 5 is a useful simplification for low dutycycle applications. Increasing heatsink mass adds thermalcapacitance and reduces peak junction temperature.Heatsink thermal resistance is proportional to surface areaand determines the average temperature.

SA 32.6 A(0.47) (3.1)

where A = total surface area in square inches, θSA =thermal resistance sink to ambient in °C/W.

Analysis of heatsink thermal response to a train of periodicpulses can be treated using the methods in Motorolaapplication note AN569 and Figure 6. For example:



In Circuit (B):

The steady state case temperature is given by

To account for thermal capacity, a time dependent factor r(t) isapplied to the steady state case-to-ambient thermal resis-tance. The package thermal resistance, at a given on-time,is called transient thermal resistance and is given by:

In terms of measurable temperatures:

In model (b.) this is

Use simplified model C when

Figure 6.5. Transient Thermal Response For a SinglePower Pulse

(5.2) TCpk TCSS(1 eton)

where TC pk TCpk

TA

TCSS TCSS TA

(5.3) r(ton)

TCpk

TCSS

(5.5) CPKG ton

(θCA In (1 r(ton))

ton

TCpk TCSS

(5.6) TCPd tonCPKG

TA

(5.0) TCSS Pd CA TA in °C

(5.1) CA CPKG, seconds

where Pd = Applied average power, wattsθCA = Case to ambient thermal resistance, °C/WTA = ambient temperature, °C

The package rises toward the steady state temperature expo-nentially with time constant

where Cpkg = HM, Joules/°CH = Specific heat, calories/(gm °C)M = Mass in grams

and 1 Calorie = 4.184 Joule1 Joule = 1 Watt Sec

The case temperature rise above ambient at the end ofpower pulse is:

RCA (ton) r(ton) CA

where r(ton) = Unitless transient thermal impedancecoefficient.

(5.4) r(ton) (1 eton)

ton

Pd CPKG θCA

TC

TA

(a.) Standard Thermal Analogue For a Thyristorin Free Air

(b.) Equivalent Circuit For (a)

θCA

Pd θCA

TA

CPKG

TC

(c.) Simplified Model

PdCPKG

TC

TA

Solving 5-4 for the package capacitance gives

Assume the case temperature changes by 40°C for asingle power pulse of 66.67 W and 3 s duration. Then fromequation (5.6):

Cpkg (66.7 Watts) (3 seconds)

40°C 5 Joules°C

The heatsink thermal resistance can be determined byapplying dc power, measuring the final case temperature,and using equation (5.0).

TC TAPD

175-255

30°CW

The application requires a 3 s on-time and 180 s period at66.7 W. Then

Pavg (66.7 W) (3180) 1.111 W


Where ∆ TC (N + 1) = maximum rise above ambientPd = applied average power within a pulsePAV G = average power within a periodr(ton + tp) = time dependent factor for sum of ton

and tpr(ton) = time dependent factor for tonr(tp) = time dependent factor for tp

TC (N 1) [PAVG (Pd PAVG) r(ton tp) Pd r(ton)

Pd r(tp)]CA

tpPAVG

ton

NthPULSE

N + 1PULSE

Pd

0

Figure 6.6. Steady State Peak Case Temperature RiseUsing equation (5.3), the theoretical steady state casetemperature rise is:

TCSS TA (66.7 W) (30°CW) 2000°C

and

R(ton) R (3 s) (40°C measured rise)20000.02

From equation (5.4) and (5.1):

R (Tp) (1 e180150) .6988

R (ton Tp) (1 1183150) .7047

Then from Figure 6:

delta TC = (1.111 + 46.225 + 1.333 – 46.61) 30 = 61.8°CIf the ambient temperature is 25°C, TC = 87°C.

COMPENSATING FOR MAXIMUMSPECIFIED LEAKAGE

Identical value parallel resistors around each triac willprevent breakdown resulting from mismatched leakages.Figure 7 derives the method for selecting the maximumallowed resistor size. A worst case design assumes thatthe series pair will operate at maximum TJ and that one ofthe triacs leaks at the full specified value while the otherhas no leakage at all. A conservative design results whenthe tolerances in the shunt resistors place the highestpossible resistor across the low leakage unit and thelowest possible resistor around the high leakage unit.

This method does not necessarily provide equal voltagebalancing. It prevents triac breakover. Perfect voltagesharing requires expensive high-wattage resistors toprovide large bleeder currents.

COMPENSATION FOR PROBABLE LEAKAGE

Real triacs have a leakage current greater than zero and lessthan the specified value. Knowledge of the leakage distributioncan be used to reduce resistor power requirements. The first

V1VSR1

R1 R2ILR1R2R1R2

Let R1 = R (1 + p) and R2 = R (1 – p) whereR = Nominal resistor valuep = 0.05 for 5% tolerance, etc.

R 2 VDRM VS (1 p)

IL (1 p2)

Worst case becomes:

and IDRM (T1) = 0; IDRM (T2) = Spec. max. value∆IL = Spec. Max. Value

IDRM (T2)

IDRM (T1)

R1T1

∆IL

T2

VS

I1

R2

I2

V1

Figure 6.7. Maximum Allowed Resistor for StaticVoltage Sharing

step is to statistically characterize the product at maximumtemperature. Careful control of the temperature is criticalbecause leakage depends strongly on it.

The process width is the leakage span at plus or minus3 standard deviations (sigma) from the mean. To minimizethe probability of out of spec parts, use a design capabilityindex (Cp) of 2.0.

Cp (design I)(process width) (4.0)

Cp (12 sigma)(6 sigma)

Figure 2 and Figure 7 describe this. Substituting delta ILat 6 sigma in Figure 7 gives the resistor value. Therequired power drops by about 4.

Theoretically there would be no more than 3.4 triacs permillion exceeding the design tolerance even if the meanvalue of the leakage shifted by plus or minus 1.5 sigma.

SELECTING RESISTORS

Small resistors have low voltage ratings which can imposea lower constraint on maximum voltage than the triac. Acommon voltage rating for carbon resistors is:

Rated Power (W) Maximum Voltage (V)1/4 Watt 250 Volts1/2 3501 5002 750

Series resistors are used for higher voltage.



Let VDRM ERmax

RmaxRmin

E VDRM 1 IminImax

Rmax VDRMImin

Rmin VDRMImax

(8.0)

ACTUAL TRIACI

E

Rmin

Rmax

(a) Equivalent Circuit (b) Model

VDRM

VMT2 – 1

MODELTRIAC

IDRM

Figure 6.8. Maximum Voltage Sharing WithoutShunt Resistor

OPERATION WITHOUT RESISTORSFigure 8 derives the method for calculating maximum

operating voltage. The voltage boost depends on the valuesof Imin and Imax. For example :

1 131 A683 A

1.19

A 19 percent voltage boost is possible with the 6 sigmadesign. Testing to the measured maximum and minimum ofthe sample allows the boost to approach the values given inTable 1.

(1 0.8351.228) 1.68

Table 1. Normalized leakage and voltage boost factor.(Mean = 1.0)

Voltage (V) 550 650 550 550 550 550 550

TJ (°C) 25 25 100 125 125 150 150

Rshunt — — — — 1.5M 1.5M 510K

Sample Size 100 100 16 16 16 16 16

Maximum 1.315 1.591 1.187 1.228 1.123 1.346 1.186

Minimum 0.729 0.681 0.840 0.835 0.920 0.820 0.877

Sigma 0.116 0.172 0.106 0.113 0.055 0.132 0.084

Sample Boost 1.55 1.43 1.71 1.68 1.82 1.61 1.74

6 Sigma Boost 1.18 1.00 1.22 1.19 1.50 1.12 1.33

COMPENSATING FOR SURFACE LEAKAGE

A small low power shunt resistance will provide nearlyperfect low temperature voltage sharing and will improvehigh temperature performance. It defines the minimumleakage current of the parallel triac-resistor combination. Thedesign method in Figure 8 can be used by adding the resistorcurrent to the measured maximum and minimum leakagecurrents of the triac sample. This is described in Table 1.

SERIES dVdt

s

The series connection will provide twice the dVdt

scapability of the lowest device in the pair (Figure 9).

Dynamic matching without a snubber network depends onequality of the thyristor self capacitance. There is littlevariation in junction capacitance. Device gain variationsintroduce most of the spread in triac performance.

The blocking junction capacitance of a thyristor is adeclining function of dc bias voltage. Mismatch in staticblocking voltage will contribute to unequal capacitances.However, this effect is small at voltages beyond a few volts.The attachment of a heatsink at the high-impedance nodeformed by connection of the triac main-terminals can alsocontribute to imbalance by introducing stray capacitance toground. This can be made insignificant by adding smallcapacitors in parallel with the triacs. Snubbers will serve thesame purpose.

100

1

R = 270 kΩC = 1000 pFVpk = 1000 V

R C

135

2

2

3

45678

8

9

1

1000

2

3

4567

9

0

10,000

453015 60 75 90 105 150120

JUNCTION TEMPERATURE (TJ) °C

Figure 6.9. Exponential Static dV/dt, SeriesMAC15-4 Triacs

R C

EXPO

NEN

TIAL

STA

TIC

dv/

dtS

(V/

s)

µ


TJ (°C)

700

600

500

400

300

200

100

0

Figure 6.10. Step Blocking Voltage V STJ (Unsnubbed Series Triacs)

800

0 16014012010020 40 60 80

V

dVdt 10 kVs

MAX

IMU

M S

TEP

VOLT

AGE

(V)

f = 10 Hzpw = 100 µs

Triacs can tolerate very high rates of voltage rise when thepeak voltage magnitude is below the threshold needed totrigger the device on. This behavior is a consequence of thevoltage divider action between the device collector andgate-cathode junction capacitances. If the rise-time is madeshort in comparison with minority carrier lifetime, voltage anddisplaced charge determine whether the device triggers onor not. Series operation will extend the range of voltage and

load conditions where a static dVdt

snubber is not needed.

Figure 10 graphs the results of measurements on twoseries connected triacs operated without snubbers. Theseries connection doubled the allowed step voltage. How-ever, this voltage remained far below the combined 1200 Vbreakover voltage of the pair.

Exponential dVdt

stests performed at 1000 V and less

than 2 kV/µs showed that turn-on of the series pair can occur

because of breakdown or dVdt

. The former was the limiting

factor at junction temperatures below 100°C. Performanceimproved with temperature because device gain aidedvoltage sharing. The triac with the highest current gain in thepair is most likely to turn-on. However, this device has thelargest effective capacitance. Consequently it is exposed to

less voltage and dVdt

. At higher temperatures, rate effects

dominated over voltage magnitudes, and the capability of the

series pair fell. dVdt

performance of the series devices was

always better than that of a single triac alone.

TURNOFF

Process tolerances cause small variations in triac turn-offtime. Series operation will allow most of the reappliedblocking voltage to appear across the faster triac when adynamic voltage sharing network is not used.

Figure 11 describes the circuit used to investigate thisbehavior. It is a capacitor discharge circuit with the loadseries resonant at 60 Hz. This method of testing is desirablebecause of the reduced burn and shock hazard resultingfrom the limited energy storage in the load capacitor.

The triacs were mounted on a temperature controlledhotplate. The single pulse non-repetitive test aids junctiontemperature control and allows the use of lower power ratedcomponents in the snubber and load circuit.

CL15K

+

Figure 6.11. Test Circuit

(b) Optocoupler Gate Circuit

S1 = GORDES MR988 REED WOUNDWITH 1 LAYER AWG #18

LL = 320 MHYCL =24 µFD, NON-POLAR

REVERSE S4 AND VCC TOCHECKOPPOSITE POLARITY.

MT1, T1

510S4B

S4A

15K2W

MOC3081

1N4001

G1

2.2 Meg

2.2 MegG2

910

510

CL

2W

PEARSON 301X1 – PROBE

G1

MT1

MT2

T1

T2MT2

G2

MT1LL

S2Hg

RELAY

(c) Load Circuit

CL

270K2W

VCC1.5 kV

S3

(a) Triac Gate Circuit

G1

13K G2

S1

9101/2W

11Ω

2W

PUSH TOTEST

–100 V

+S1

20 µF200 V

MO

C30

81

270K2W

Rs

Cs

Cs

Rs

MT1, T2

TRIA

D C

30X

50H

, 350

0Ω



Snubberless turn-off at 1200 V and 320 milli-henryresulted in 800 V peak and 100 V/µs. Although this testexceeded the ratings of the triacs, they turned offsuccessfully.

Snubberless operation is allowable when:1. The total transient voltage across both triacs does notexceed the rating for a single device. This voltage de-pends on the load phase angle, self capacitance of theload and triac, damping constant, and natural resonanceof the circuit.

2. The total dVdt

c across the series combination does

not exceed the capability of a single device.Maximum turn-off voltage capability and tolerance for

variable loads requires the use of a snubber network toprovide equal dynamic voltage sharing. Figure 12 and Figure13 derives the minimum size snubber capacitor allowed. It isdetermined by the recovery charge of the triac. Measure-ments in fast current crossing applications suggest that thereverse recovery charge is less than 2 micro-coulombs.Recovery currents cannot be much greater than IH or IGT, orthe triac would never turn-off. Recovery can be forward,reverse, or near zero current depending on conditions.

Snubber design for the series switch has the followingobjectives:

• Controlling the voltage peak. Resonant charging will mag-nify the turn-off voltage.

• Controlling the voltage rate. Peak voltage trades with volt-age rate.

• Equalizing the voltage across the series devices by pro-viding for imbalance in turn-off charge.

where C = Nominal value of capacitorand p = 0.1 for 10% tolerance, etc.

∆Q = Reverse recovery charge

Note that T1 has no charge while T2 carries fullrecovery charge.

For the model shown above,

VS Q1C1

Q2C2

Q1

C(1 p)

Q1 Q

C(1 p)

C Q2 VDRM VS(1 p)

Worst case:

C2 C(1 p); C1 C(1 p); Q1 0; Q2 Q

t

(dv/dt)c

VMT2-1ANDIMT2

φ

VMT2-1

∆QIRRM

∆Q

Q + ∆Q

Q1VDRM

V2Q2

C2

C1QT1

T2VS

dIdt

c

Figure 6.12. Minimum Capacitor Size for DynamicVoltage Sharing

Designs that satisfy the first two objectives will usuallyprovide capacitor values above the minimum size. Select thesnubber for a satisfactory compromise between voltage anddVdt

. Then check the capacitor to insure that it is sufficiently

large.Snubber designs for static, commutating, and combined

dVdt

stress are shown in Table 2. Circuits switching the line or

a charged capacitor across a blocking triac require theaddition of a series snubber inductor. The snubber must be

designed for maximum dVdt

with the minimum circuit induc-

tance. This contraint increases the required triac blockingvoltage.

Table 2. Snubber Designs

TypedV

dtc

dVdts Both

L (mh) 320 0.4 320

RL Ohm 8 0 8

Rs Ohm 1820 48 48

Cs (µf) 0.5 0.5 0.5

Damping Ratio 1.14 0.85 .035

Vstep (V) 1200 1200 750

Vpk (V) 1332 1400 1423

tpk (µs) 768 29.8 1230

(V/µs)dVdt

4.6 103 1.3

Note: Divide Rs and by 2, multiply Cs by 2 for each triac.dVdt

dldt

CAPABILITY

The hazard of thyristor damage by dldt

overstress is greater

when circuit operating voltages are high because dldt

is

proportional to voltage. Damage by short duration transientsis possible even though the pulse is undetectable whenobserved with non-storage oscilloscopes. This type ofdamage can be consequence of snubber design, transients,or parasitic capacitances.

A thyristor can be triggered on by gate current, exceeding

its breakdown voltage, or by exceeding its dVdt

s capability.

In the latter case, a trigger current is generated by charging ofthe internal depletion layer capacitance in the device. Thiseffect aids turn-on current spreading, although damage can

still occur if the rate of follow on dldt

is high. Repetitive

operation off the ac line at voltages above breakdown is aworst case condition. Quadrant 3 has a slightly slower gatedturn-on time, increasing the chance of damage in this


direction. Higher operating voltages raise power density andlocal heating, increasing the possibility of die damage due tohot-spots and thermal run-away.

Ideally, turn-on speed mismatch should not be allowed toforce the slower thyristor into breakdown. An RC snubberacross each thyristor prevents this. In the worst case, onedevice turns on instantly while the other switches at theslowest possible turn-on time. The rate of voltage rise at the

slower device is roughly dVdt

VIRs2L

, where VI is the

maximum voltage across L. This rate should not allow thevoltage to exceed VDRM in less than Tgt to prevent breakover.But what if the thyristors are operated without a snubber, or ifavalanche occurs because of a transient overvoltage condi-tion?

The circuit in Figure 13 was constructed to investigatethis behavior. The capacitor, resistor, and inductor createa pulse forming network to shape the current wave. Theinitial voltage on the capacitor was set by a series string ofsidac bidirectional breakover devices.

VciV

CµFD

LµHY

RΩ

dl/dtA/µs

RejectsTested

1000 4.06 3.4 5.7 100 0/100

1900* 1.05 7.9 5.7 179 0/195

1500 0.002 0.3 10 3000 3/10

* Open S1 to test breakover dl/dt

Test results showed that operation of the triac switch wassafe as long as the rate of current rise was below 200 A/µs.This was true even when the devices turned on because ofbreakover. However, a 0.002 µf capacitor with no serieslimiting impedance was sufficient to cause damage in the Q3firing polarity.

Circuit malfunctions because of breakover will be tempo-rary if the triac is not damaged. Test results suggest that therewill be no damage when the series inductance is sufficient tohold dl/dt to acceptable values. Highly energetic transientssuch as those resulting from lightning strikes can causedamage to the thyristor by I2t surge overstress. Devicesurvival requires the use of voltage limiting devices in the

circuit and dVdt

limiting snubbers to prevent unwanted turn-on.

Alternatively, a large triac capable of surviving the surge canbe used.

Q for turn-off at IH

Q t2

t1

Ipk SINt dt Ipk

(cos t1 cos t2)

IH1 Ipk Sint1

thus t1 1

Sin1IH1Ipk

Worst case : IH2 0; 2 t2

Q Ipk

(1 cos[SIN1IH1Ipk

])

Q Ipk

1 I IH1Ipk2

IH2

T1

∆Q

T2

Figure 6.14. Forward Recovery Charge for Turn-Off at l H

IH1

ωt = 0 t1 t2

lpk

∆Q

1K2WCARBON

Figure 6.13. dl/dt Test Circuit

PEARSON411 IPROBE

MT1

MT2

MT2

MT1G*S1

G

L

T106-6

QTY = 6 TO 16 MKP1V130

C

NON-INDUCTIVE

0–6 kV1/2A60 Hz

RRE1

5K200W



!

By George TempletonThyristor Applications Engineer

INTRODUCTION

RC networks are used to control voltage transients thatcould falsely turn-on a thyristor. These networks are calledsnubbers.

The simple snubber consists of a series resistor andcapacitor placed around the thyristor. These componentsalong with the load inductance form a series CRL circuit.Snubber theory follows from the solution of the circuit’sdifferential equation.

Many RC combinations are capable of providing accept-able performance. However, improperly used snubbers cancause unreliable circuit operation and damage to thesemiconductor device.

Both turn-on and turn-off protection may be necessaryfor reliability. Sometimes the thyristor must function with arange of load values. The type of thyristors used, circuitconfiguration, and load characteristics are influential.

Snubber design involves compromises. They include cost,voltage rate, peak voltage, and turn-on stress. Practicalsolutions depend on device and circuit physics.

STATIC dVdt

WHAT IS STATIC dVdt

?

Static dVdt

is a measure of the ability of a thyristor to retain a

blocking state under the influence of a voltage transient.

dVdt

s DEVICE PHYSICS

Static dVdt

turn-on is a consequence of the Miller effect and

regeneration (Figure 1). A change in voltage across thejunction capacitance induces a current through it. This

current is proportional to the rate of voltage change dVdt . It

triggers the device on when it becomes large enough to raisethe sum of the NPN and PNP transistor alphas to unity.

Figure 6.1. ModeldVdt

s

IA CJ

dVdt

1 (N p)

CEFFCJ

1(Np)

IBP

IJ

IJ

IK

IBN

ICN

I1

I2

ICP

IA

TWO TRANSISTOR MODELOF

SCR

CJN

CJP

PNP

A

C

G

CJ

NE

PB

NB

PEV

tGNPN

INTEGRATEDSTRUCTURE

K

A

K

dvdt

CONDITIONS INFLUENCING dVdt

s

Transients occurring at line crossing or when there is noinitial voltage across the thyristor are worst case. Thecollector junction capacitance is greatest then because thedepletion layer widens at higher voltage.

Small transients are incapable of charging theself-capacitance of the gate layer to its forward biasedthreshold voltage (Figure 2). Capacitance voltage divider

PEAK MAIN TERMINAL VOLTAGE (VOLTS)

700 800

80

60

MAC 228-10 TRIACTJ = 110°C

600500400300200

100

120

140

160

201000

180

40

STAT

IC

(

V/

s) µdV dt

Figure 6.2. Exponential versus Peak VoltagedVdt

s

REV 1



action between the collector and gate-cathode junctions andbuilt-in resistors that shunt current away from the cathodeemitter are responsible for this effect.

Static dVdt

does not depend strongly on voltage for

operation below the maximum voltage and temperaturerating. Avalanche multiplication will increase leakage current

and reduce dVdt

capability if a transient is within roughly 50

volts of the actual device breakover voltage.

A higher rated voltage device guarantees increased dVdt

at

lower voltage. This is a consequence of the exponentialrating method where a 400 V device rated at 50 V/µs has a

higher dVdt

to 200 V than a 200 V device with an identical

rating. However, the same diffusion recipe usually applies forall voltages. So actual capabilities of the product are notmuch different.

Heat increases current gain and leakage, lowering dVdt

s,

the gate trigger voltage and noise immunity (Figure 3).

Figure 6.3. Exponential versus TemperaturedVdt

s

STAT

IC

(

V/

s) µdV dt

170

150

130

110

30

50

70

90

100 115 130 14585705540

MAC 228-10VPK = 800 V


2510

dVdt

s

FAILURE MODE

Occasional unwanted turn-on by a transient may beacceptable in a heater circuit but isn’t in a fire preventionsprinkler system or for the control of a large motor. Turn-on isdestructive when the follow-on current amplitude or rate isexcessive. If the thyristor shorts the power line or a chargedcapacitor, it will be damaged.

Static dVdt

turn-on is non-destructive when series imped-

ance limits the surge. The thyristor turns off after a half-cycle

of conduction. High dVdt

aids current spreading in the thyristor,

improving its ability to withstand dIdt

. Breakdown turn-on does

not have this benefit and should be prevented.

IMPROVING dVdt

s

Static dVdt

can be improved by adding an external resistor

from the gate to MT1 (Figure 4). The resistor provides a path

for leakage and dVdt

induced currents that originate in the

drive circuit or the thyristor itself.

Figure 6.4. Exponential versusGate to MT 1 Resistance

dVdt

s

STAT

IC

(

V/

s) µdV dt

20

100 10000

10 10,000GATE-MT1 RESISTANCE (OHMS)

MAC 228-10800 V 110°C

40

60

80

100

120

140

RINTERNAL = 600 Ω

Non-sensitive devices (Figure 5) have internal shortingresistors dispersed throughout the chip’s cathode area. Thisdesign feature improves noise immunity and high tempera-ture blocking stability at the expense of increased trigger andholding current. External resistors are optional for non-sensi-tive SCRs and TRIACs. They should be comparable in sizeto the internal shorting resistance of the device (20 to 100ohms) to provide maximum improvement. The internalresistance of the thyristor should be measured with anohmmeter that does not forward bias a diode junction.

Figure 6.5. Exponential versusJunction Temperature

dVdt

s

STAT

IC

(

V/

s) µdV dt

800

1000

1200

1400

130120110100

2000

2200

1800

1600

9080706050600


MAC 16-8VPK = 600 V



Sensitive gate TRIACs run 100 to 1000 ohms. With an

external resistor, their dVdt

capability remains inferior to

non-sensitive devices because lateral resistance within thegate layer reduces its benefit.

Sensitive gate SCRs (IGT 200 µA) have no built-inresistor. They should be used with an external resistor. Therecommended value of the resistor is 1000 ohms. Higher

values reduce maximum operating temperature and dVdt

s(Figure 6). The capability of these parts varies by more than100 to 1 depending on gate-cathode termination.

GAT

E-C

ATH

OD

E R

ESIS

TAN

CE

(OH

MS)

Figure 6.6. Exponential versus

Gate-Cathode Resistance

dVdt

s

10MEG

1MEG

100K

0.01 100

1010K

0.1 1

MCR22-2 TA = 65°C

0.001

KG

A10V

STATIC dVdt

(Vs)

Figure 6.7. Exponential versus Gate

to MT1 Capacitance

dVdt

s

STAT

IC

(

V/

s) µdV dt

GATE TO MT1 CAPACITANCE (µF)

130

120

110

100

90

80

70

60

MAC 228-10800 V 110°C

10.10.010.001

A gate-cathode capacitor (Figure 7) provides a shunt pathfor transient currents in the same manner as the resistor. Italso filters noise currents from the drive circuit and enhancesthe built-in gate-cathode capacitance voltage divider effect.The gate drive circuit needs to be able to charge the

capacitor without excessive delay, but it does not need tosupply continuous current as it would for a resistor that

increases dVdt

the same amount. However, the capacitor

does not enhance static thermal stability.

The maximum dVdt

s improvement occurs with a short.

Actual improvement stops before this because of spread-ing resistance in the thyristor. An external capacitor ofabout 0.1 µF allows the maximum enhancement at ahigher value of RGK.

One should keep the thyristor cool for the highest

dVdt

s. Also devices should be tested in the application

circuit at the highest possible temperature using thyristorswith the lowest measured trigger current.

TRIAC COMMUTATING dVdt

WHAT IS COMMUTATING dVdt

?

The commutating dVdt

rating applies when a TRIAC has

been conducting and attempts to turn-off with an inductiveload. The current and voltage are out of phase (Figure 8).The TRIAC attempts to turn-off as the current drops belowthe holding value. Now the line voltage is high and in theopposite polarity to the direction of conduction. Successfulturn-off requires the voltage across the TRIAC to rise to theinstantaneous line voltage at a rate slow enough to preventretriggering of the device.

TIMEΦ

i

PHASEANGLE

iVLINE G

1

2R L

TIME

VLINE

MT2

-1V

VOLT

AGE/

CU

RR

ENT

Figure 6.8. TRIAC Inductive Load Turn-Off dVdt

c

dIdt

c

dVdt

c

VMT2-1

dVdt

c DEVICE PHYSICS

A TRIAC functions like two SCRs connected in inverse-parallel. So, a transient of either polarity turns it on.

There is charge within the crystal’s volume because ofprior conduction (Figure 9). The charge at the boundaries of


STORED CHARGEFROM POSITIVECONDUCTION

PreviouslyConducting Side

NP

+ –

LATERAL VOLTAGEDROP

REVERSE RECOVERYCURRENT PATH

G MT1

TOP

MT2

N N N

N

N N N

Figure 6.9. TRIAC Structure and Current Flowat Commutation

the collector junction depletion layer responsible for dVdt

s is

also present. TRIACs have lower dVdt

c than dV

dt

sbecause of this additional charge.

The volume charge storage within the TRIAC depends onthe peak current before turn-off and its rate of zero crossing

dIdt

c. In the classic circuit, the load impedance and line

frequency determine dIdt

c. The rate of crossing for sinusoi-

dal currents is given by the slope of the secant line betweenthe 50% and 0% levels as:

dIdt

c

6 fITM1000

Ams

where f = line frequency and ITM = maximum on-state currentin the TRIAC.

Turn-off depends on both the Miller effect displacement

current generated by dVdt

across the collector capacitance

and the currents resulting from internal charge storage within

CHARGE DUE TOdV/dt

Figure 6.10. TRIAC Current and Voltage atCommutation

didt

c

dVdt

c

TIME

IRRMVOLUME

STORAGECHARGE

VMT2-1

0

VOLT

AGE/

CU

RR

ENT

the volume of the device (Figure 10). If the reverse recoverycurrent resulting from both these components is high, thelateral IR drop within the TRIAC base layer will forward bias

the emitter and turn the TRIAC on. Commutating dVdt

capability is lower when turning off from the positive directionof current conduction because of device geometry. The gateis on the top of the die and obstructs current flow.

Recombination takes place throughout the conductionperiod and along the back side of the current wave as itdeclines to zero. Turn-off capability depends on its shape. If

the current amplitude is small and its zero crossing dIdt

c is

low, there is little volume charge storage and turn-off

becomes limited by dVdt

s. At moderate current amplitudes,

the volume charge begins to influence turn-off, requiring alarger snubber. When the current is large or has rapid zero

crossing, dVdt

c has little influence. Commutating dI

dt and

delay time to voltage reapplication determine whether turn-offwill be successful or not (Figures 11, 12).

MAI

N T

ERM

INAL

VO

LTAG

E (V

)

Figure 6.11. Snubber Delay Time

E

td0

VT

TIME

EV

NO

RM

ALIZ

ED D

ELAY

TIM

E

Figure 6.12. Delay Time To Normalized Voltage

0.2

DAMPING FACTOR

0.02

0.03

0.05

0.1

0.2

0.5

10.50.30.001 0.002 0.005 0.01 0.02 0.2

0.1

0.05

0.02

0.01

0.05 0.1

(t *

= W

d0

0.005VTE

RL = 0M = 1IRRM = 0

t d)



CONDITIONS INFLUENCING dVdt

c

Commutating dVdt

depends on charge storage and

recovery dynamics in addition to the variables influencing

static dVdt

. High temperatures increase minority carrier

life-time and the size of recovery currents, making turn-offmore difficult. Loads that slow the rate of current zero-crossing aid turn-off. Those with harmonic content hinderturn-off.

Figure 6.13. Phase Controlling a Motor in a Bridge

LR8.3 s

+

t

i

CRS

60 Hz

LS

–R L

DC MOTOR

i

dIdtc

Circuit Examples

Figure 13 shows a TRIAC controlling an inductive load in abridge. The inductive load has a time constant longer thanthe line period. This causes the load current to remainconstant and the TRIAC current to switch rapidly as the linevoltage reverses. This application is notorious for causing

TRIAC turn-off difficulty because of high dIdt

c.

High currents lead to high junction temperatures and ratesof current crossing. Motors can have 5 to 6 times the normalcurrent amplitude at start-up. This increases both junctiontemperature and the rate of current crossing, leading toturn-off problems.

The line frequency causes high rates of current crossing in400 Hz applications. Resonant transformer circuits aredoubly periodic and have current harmonics at both theprimary and secondary resonance. Non-sinusoidal currentscan lead to turn-off difficulty even if the current amplitude islow before zero-crossing.

dVdt

c FAILURE MODE

dVdt

c failure causes a loss of phase control. Temporary

turn-on or total turn-off failure is possible. This can bedestructive if the TRIAC conducts asymmetrically causing adc current component and magnetic saturation. The windingresistance limits the current. Failure results because ofexcessive surge current and junction temperature.

IMPROVING dVdt

c

The same steps that improve dVdt

s aid dV

dt

c except

when stored charge dominates turn-off. Steps that reducethe stored charge or soften the commutation are necessarythen.

Larger TRIACs have better turn-off capability than smallerones with a given load. The current density is lower in thelarger device allowing recombination to claim a greaterproportion of the internal charge. Also junction temperaturesare lower.

TRIACs with high gate trigger currents have greaterturn-off ability because of lower spreading resistance in thegate layer, reduced Miller effect, or shorter lifetime.

The rate of current crossing can be adjusted by adding acommutation softening inductor in series with the load. Smallhigh permeability “square loop” inductors saturate causingno significant disturbance to the load current. The inductorresets as the current crosses zero introducing a largeinductance into the snubber circuit at that time. This slowsthe current crossing and delays the reapplication of blockingvoltage aiding turn-off.

The commutation inductor is a circuit element thatintroduces time delay, as opposed to inductance, into the

circuit. It will have little influence on observed dVdt

at the

device. The following example illustrates the improvementresulting from the addition of an inductor constructed bywinding 33 turns of number 18 wire on a tape wound core(52000-1A). This core is very small having an outsidediameter of 3/4 inch and a thickness of 1/8 inch. The delaytime can be calculated from:

ts (N A B 108)

Ewhere:

ts = time delay to saturation in seconds.B = saturating flux density in GaussA = effective core cross sectional area in cm2N = number of turns.

For the described inductor:

ts (33 turns) (0.076 cm2) (28000 Gauss) (1 108)

(175 V) 4.0 s.

The saturation current of the inductor does not need to bemuch larger than the TRIAC trigger current. Turn-off failurewill result before recovery currents become greater than thisvalue. This criterion allows sizing the inductor with thefollowing equation:

Is Hs ML0.4 N

where :

Hs = MMF to saturate = 0.5 OerstedML = mean magnetic path length = 4.99 cm.

Is (.5) (4.99).4 33

60 mA.


SNUBBER PHYSICS

UNDAMPED NATURAL RESONANCE

0ILC

Radianssecond

Resonance determines dVdt

and boosts the peak capacitor

voltage when the snubber resistor is small. C and L are

related to one another by ω02. dVdt

scales linearly with ω0when the damping factor is held constant. A ten to one

reduction in dVdt

requires a 100 to 1 increase in either

component.

DAMPING FACTOR

ρ R2

CL

The damping factor is proportional to the ratio of the circuitloss and its surge impedance. It determines the trade off

between dVdt

and peak voltage. Damping factors between

0.01 and 1.0 are recommended.

The Snubber Resistor

Damping and dVdt

When ρ 0.5, the snubber resistor is small, and dVdt

depends mostly on resonance. There is little improvement indVdt

for damping factors less than 0.3, but peak voltage and

snubber discharge current increase. The voltage wave has a

1-COS (θ) shape with overshoot and ringing. Maximum dVdt

occurs at a time later than t = 0. There is a time delay beforethe voltage rise, and the peak voltage almost doubles.

When ρ 0.5, the voltage wave is nearly exponential in

shape. The maximum instantaneous dVdt

occurs at t = 0.

There is little time delay and moderate voltage overshoot.

When ρ 1.0, the snubber resistor is large and dVdt

depends mostly on its value. There is some overshoot eventhrough the circuit is overdamped.

High load inductance requires large snubber resistors andsmall snubber capacitors. Low inductances imply smallresistors and large capacitors.

Damping and Transient Voltages

Figure 14 shows a series inductor and filter capacitorconnected across the ac main line. The peak to peak voltageof a transient disturbance increases by nearly four times.Also the duration of the disturbance spreads because ofringing, increasing the chance of malfunction or damage tothe voltage sensitive circuit. Closing a switch causes thisbehavior. The problem can be reduced by adding a dampingresistor in series with the capacitor.

V (V

OLT

S)

Figure 6.14. Undamped LC Filter Magnifies andLengthens a Transient

V0.1µF

100 µH 0.05

0 10 µs

340 VVOLTAGESENSITIVECIRCUIT

0

+ 700

– 700

TIME (µs)0 2010

dIdt

Non-Inductive Resistor

The snubber resistor limits the capacitor discharge current

and reduces dIdt

stress. High dIdt

destroys the thyristor even

though the pulse duration is very short.The rate of current rise is directly proportional to circuit

voltage and inversely proportional to series inductance. Thesnubber is often the major offender because of its lowinductance and close proximity to the thyristor.

With no transient suppressor, breakdown of the thyristorsets the maximum voltage on the capacitor. It is possible toexceed the highest rated voltage in the device seriesbecause high voltage devices are often used to supply lowvoltage specifications.

The minimum value of the snubber resistor depends on thetype of thyristor, triggering quadrants, gate current amplitude,voltage, repetitive or non-repetitive operation, and requiredlife expectancy. There is no simple way to predict the rate ofcurrent rise because it depends on turn-on speed of thethyristor, circuit layout, type and size of snubber capacitor,and inductance in the snubber resistor. The equations inAppendix D describe the circuit. However, the valuesrequired for the model are not easily obtained except bytesting. Therefore, reliability should be verified in the actualapplication circuit.

Table 1 shows suggested minimum resistor values esti-mated (Appendix A) by testing a 20 piece sample from thefour different TRIAC die sizes.

Table 1. Minimum Non-inductive Snubber Resistorfor Four Quadrant Triggering.

TRIAC TypePeak VC

VoltsRs

Ohms

dIdt

A/µs

Non-Sensitive Gate(IGT 10 mA)8 to 40 A(RMS)

200300400600800

3.36.8113951

170250308400400



Reducing dIdt

TRIAC dIdt

can be improved by avoiding quadrant 4

triggering. Most optocoupler circuits operate the TRIAC inquadrants 1 and 3. Integrated circuit drivers use quadrants 2and 3. Zero crossing trigger devices are helpful because theyprohibit triggering when the voltage is high.

Driving the gate with a high amplitude fast rise pulse

increases dIdt

capability. The gate ratings section defines the

maximum allowed current.Inductance in series with the snubber capacitor reduces

dIdt

. It should not be more than five percent of the load

inductance to prevent degradation of the snubber’s dVdt

suppression capability. Wirewound snubber resistorssometimes serve this purpose. Alternatively, a separateinductor can be added in series with the snubber capacitor.It can be small because it does not need to carry the loadcurrent. For example, 18 turns of AWG No. 20 wire on aT50-3 (1/2 inch) powdered iron core creates a non-saturat-ing 6.0 µH inductor.

A 10 ohm, 0.33 µF snubber charged to 650 volts resulted

in a 1000 A/µs dIdt

. Replacement of the non-inductive

snubber resistor with a 20 watt wirewound unit lowered therate of rise to a non-destructive 170 A/µs at 800 V. Theinductor gave an 80 A/µs rise at 800 V with the non-inductive resistor.

The Snubber CapacitorA damping factor of 0.3 minimizes the size of the snubber

capacitor for a given value of dVdt

. This reduces the cost and

physical dimensions of the capacitor. However, it raisesvoltage causing a counter balancing cost increase.

Snubber operation relies on the charging of the snubbercapacitor. Turn-off snubbers need a minimum conductionangle long enough to discharge the capacitor. It should be atleast several time constants (RS CS).

STORED ENERGY

Inductive Switching Transients

E 12

L I02 Watt-seconds or Joules

I0 = current in Amperes flowing in the inductor att = 0.

Resonant charging cannot boost the supply voltage atturn-off by more than 2. If there is an initial current flowing inthe load inductance at turn-off, much higher voltages arepossible. Energy storage is negligible when a TRIAC turns offbecause of its low holding or recovery current.

The presence of an additional switch such as a relay,thermostat or breaker allows the interruption of load currentand the generation of high spike voltages at switch opening.The energy in the inductance transfers into the circuitcapacitance and determines the peak voltage (Figure 15).

dVdt

IC

VPK I LC

Figure 6.15. Interrupting Inductive Load Current

VPK

C

L

I

FAST

SLOW

(b.) Unprotected Circuit(a.) Protected Circuit

OPTIONALR

Capacitor Discharge

The energy stored in the snubber capacitor

Ec 12

CV2 transfers to the snubber resistor and thyristor

every time it turns on. The power loss is proportional tofrequency (PAV = 120 Ec @ 60 Hz).

CURRENT DIVERSION

The current flowing in the load inductor cannot changeinstantly. This current diverts through the snubber resistor

causing a spike of theoretically infinite dVdt

with magnitude

equal to (IRRM R) or (IH R).

LOAD PHASE ANGLE

Highly inductive loads cause increased voltage and

dVdt

c at turn-off. However, they help to protect the

dVdt

M = 0.25

M = 0.5

M = 0.75

VPK

1.3

E

0.4

0.2

00 0.2 0.4 0.6 0.8 1

0.9

1

1.1

1.2

1.4

1.5

1.6

1.7

1.4

1.2

1

0.8

0.6

2.2

2.1

2

1.9

1.8

DAMPING FACTOR

M = 0

M = RS / (RL + RS)

M = 1

dV dt( )

0

NO

RM

ALIZ

EDdV dt

M RESISTIVE DIVISION RATIO RS

RL RS

IRRM 0

Figure 6.16. 0 To 63% dVdt

/ (E

W )

NO

RM

ALIZ

ED P

EAK

VOLT

AGE

V

/EPK


thyristor from transients and dVdt

s. The load serves as

the snubber inductor and limits the rate of inrush current if

the device does turn on. Resistance in the load lowers dVdt

and VPK (Figure 16).

CHARACTERISTIC VOLTAGE WAVES

Damping factor and reverse recovery current determinethe shape of the voltage wave. It is not exponential whenthe snubber damping factor is less than 0.5 (Figure 17) orwhen significant recovery currents are present.

V

(VO

LTS)

MT 2-

1

063% dVdt

s 100 Vs, E 250 V,

RL 0, IRRM 0

Figure 6.17. Voltage Waves For DifferentDamping Factors

ρ = 0

1

TIME (µs)

0.30.1

0

ρ = 0.1

ρ = 0.3 ρ = 1

3.52.82.1 4.2 4.9 5.6 6.30.70

100

200

300

400500

1.4 70

NO

RM

ALIZ

ED P

EAK

VOLT

AGE

AND

dV dt

(RL 0, M 1, IRRM 0)

NORMALIZED dVdt

dVdtE 0

NORMALIZED VPK VPK

E

Figure 6.18. Trade-Off Between V PK and dVdt

DAMPING FACTOR (ρ)0

0–63%E

1

10–63%

0.80.60.40.2 1.2 1.81.4 1.6 2

2.8

2.6

2.4

2.2

1.8

1.6

1.4

2

1

1.2

0.80.6

0.4

0.2

0

dVdt

dVdt

o

VPKdVdt

10–63%

dVdtMAX

A variety of wave parameters (Figure 18) describe dVdt

Some are easy to solve for and assist understanding. These

include the initial dVdt

, the maximum instantaneous dVdt

, and

the average dVdt

to the peak reapplied voltage. The 0 to 63%

dVdt

s and 10 to 63% dV

dt

c definitions on device data

sheets are easy to measure but difficult to compute.

NON-IDEAL BEHAVIORS

CORE LOSSES

The magnetic core materials in typical 60 Hz loadsintroduce losses at the snubber natural frequency. Theyappear as a resistance in series with the load inductance and

winding dc resistance (Figure 19). This causes actual dVdt

to

be less than the theoretical value.

Figure 6.19. Inductor Model

L R

C

L DEPENDS ON CURRENT AMPLITUDE, CORESATURATION

R INCLUDES CORE LOSS, WINDING R. INCREASESWITH FREQUENCY

C WINDING CAPACITANCE. DEPENDS ONINSULATION, WIRE SIZE, GEOMETRY

COMPLEX LOADS

Many real-world inductances are non-linear. Their corematerials are not gapped causing inductance to vary withcurrent amplitude. Small signal measurements poorlycharacterize them. For modeling purposes, it is best tomeasure them in the actual application.

Complex load circuits should be checked for transientvoltages and currents at turn-on and off. With a capacitiveload, turn-on at peak input voltage causes the maximumsurge current. Motor starting current runs 4 to 6 times thesteady state value. Generator action can boost voltagesabove the line value. Incandescent lamps have cold startcurrents 10 to 20 times the steady state value. Transform-ers generate voltage spikes when they are energized.Power factor correction circuits and switching devicescreate complex loads. In most cases, the simple CRLmodel allows an approximate snubber design. However,there is no substitute for testing and measuring the worstcase load conditions.



SURGE CURRENTS IN INDUCTIVE CIRCUITS

Inductive loads with long L/R time constants causeasymmetric multi-cycle surges at start up (Figure 20).Triggering at zero voltage crossing is the worst casecondition. The surge can be eliminated by triggering at thezero current crossing angle.

i (AM

PER

ES)

Figure 6.20. Start-Up Surge For Inductive Circuit

240VAC

20 MHY

i 0.1Ω

TIME (MILLISECONDS)

40

ZERO VOLTAGE TRIGGERING, IRMS = 30 A

0

90

80 160120 200

Core remanence and saturation cause surge currents.They depend on trigger angle, line impedance, core charac-teristics, and direction of the residual magnetization. Forexample, a 2.8 kVA 120 V 1:1 transformer with a 1.0 ampereload produced 160 ampere currents at start-up. Soft startingthe circuit at a small conduction angle reduces this current.

Transformer cores are usually not gapped and saturateeasily. A small asymmetry in the conduction angle causesmagnetic saturation and multi-cycle current surges.

Steps to achieve reliable operation include:

1. Supply sufficient trigger current amplitude. TRIACs havedifferent trigger currents depending on their quadrant ofoperation. Marginal gate current or optocoupler LEDcurrent causes halfwave operation.

2. Supply sufficient gate current duration to achievelatching. Inductive loads slow down the main terminalcurrent rise. The gate current must remain above thespecified IGT until the main terminal current exceeds thelatching value. Both a resistive bleeder around the loadand the snubber discharge current help latching.

3. Use a snubber to prevent TRIAC dVdt

c failure.

4. Minimize designed-in trigger asymmetry. Triggering mustbe correct every half-cycle including the first. Use astorage scope to investigate circuit behavior during thefirst few cycles of turn-on. Alternatively, get the gatecircuit up and running before energizing the load.

5. Derive the trigger synchronization from the line insteadof the TRIAC main terminal voltage. This avoidsregenerative interaction between the core hysteresis andthe triggering angle preventing trigger runaway, halfwaveoperation, and core saturation.

6. Avoid high surge currents at start-up. Use a currentprobe to determine surge amplitude. Use a soft startcircuit to reduce inrush current.

DISTRIBUTED WINDING CAPACITANCE

There are small capacitances between the turns andlayers of a coil. Lumped together, they model as a singleshunt capacitance. The load inductor behaves like a capaci-tor at frequencies above its self-resonance. It becomes

ineffective in controlling dVdt

and VPK when a fast transient

such as that resulting from the closing of a switch occurs.This problem can be solved by adding a small snubberacross the line.

SELF-CAPACITANCE

A thyristor has self-capacitance which limits dVdt

when the

load inductance is large. Large load inductances, high powerfactors, and low voltages may allow snubberless operation.

SNUBBER EXAMPLES

WITHOUT INDUCTANCE

Power TRIAC Example

Figure 21 shows a transient voltage applied to a TRIACcontrolling a resistive load. Theoretically there will be aninstantaneous step of voltage across the TRIAC. The onlyelements slowing this rate are the inductance of the wiringand the self-capacitance of the thyristor. There is anexponential capacitor charging component added along witha decaying component because of the IR drop in the snubberresistor. The non-inductive snubber circuit is useful when theload resistance is much larger than the snubber resistor.

e(t o) E RSRS RL

et (1 et)

Figure 6.21. Non-Inductive Snubber Circuit

Vstep ERS

RS RL

RESISTORCOMPONENT

TIMEt = 0

eE

τ = (RL + RS) CS

e

CS

RS

RL

E

CAPACITORCOMPONENT


Opto-TRIAC Examples

Single Snubber, Time Constant Design

Figure 22 illustrates the use of the RC time constantdesign method. The optocoupler sees only the voltageacross the snubber capacitor. The resistor R1 supplies thetrigger current of the power TRIAC. A worst case designprocedure assumes that the voltage across the powerTRIAC changes instantly. The capacitor voltage rises to63% of the maximum in one time constant. Then:

R1 CS 0.63 E

dVdts

where dVdt

sis the rated static dV

dt

for the optocoupler.

dVdt

(Vs)

Power TRIAC Optocoupler

0.99 0.35

The optocoupler conducts current only long enough totrigger the power device. When it turns on, the voltagebetween MT2 and the gate drops below the forwardthreshold voltage of the opto-TRIAC causing turn-off. The

optocoupler sees dVdt

s when the power TRIAC turns off

later in the conduction cycle at zero current crossing.Therefore, it is not necessary to design for the lower

optocoupler dVdt

c rating. In this example, a single snubber

designed for the optocoupler protects both devices.

Figure 6.23. Anti-Parallel SCR Driver

(50 V/µs SNUBBER, ρ = 1.0)

120 V400 Hz

1 MHY

MCR265–4

430

100

MCR265–4

1N4001

0.022µF

1

51

1N4001

100VCC

6

5

4

3

2

MO

C30

31

Optocouplers with SCRs

Anti-parallel SCR circuits result in the same dVdt

across the

optocoupler and SCR (Figure 23). Phase controllable opto-

couplers require the SCRs to be snubbed to their lower dVdt

rating. Anti-parallel SCR circuits are free from the chargestorage behaviors that reduce the turn-off capability ofTRIACs. Each SCR conducts for a half-cycle and has thenext half cycle of the ac line in which to recover. The

turn-off dVdt

of the conducting SCR becomes a static for-

ward blocking dVdt

for the other device. Use the SCR data

sheet dVdt

s rating in the snubber design.

A SCR used inside a rectifier bridge to control an ac loadwill not have a half cycle in which to recover. The availabletime decreases with increasing line voltage. This makesthe circuit less attractive. Inductive transients can besuppressed by a snubber at the input to the bridge oracross the SCR. However, the time limitation still applies.

OPTO dVdt

c

Zero-crossing optocouplers can be used to switch induc-tive loads at currents less than 100 mA (Figure 24). However a power TRIAC along with the optocouplershould be used for higher load currents.

LOAD

CU

RR

ENT

(mA

RM

S)

Figure 6.24. MOC 3062 Inductive Load Current versus T A

CS = 0.01

CS = 0.001

NO SNUBBER

(RS = 100 Ω, VRMS = 220 V, POWER FACTOR = 0.5)


020

80

70

60

50

40

30

20

10

100908030 40 50 60 70

A phase controllable optocoupler is recommended witha power device. When the load current is small, a MAC97TRIAC is suitable.

Unusual circuit conditions sometimes lead to unwanted

operation of an optocoupler in dVdt

c mode. Very large

currents in the power device cause increased voltagesbetween MT2 and the gate that hold the optocoupler on.Use of a larger TRIAC or other measures that limit inrushcurrent solve this problem.

Very short conduction times leave residual charge in theoptocoupler. A minimum conduction angle allows recoverybefore voltage reapplication.

DESIGN dVdt

(0.63) (170)

(2400) (0.1 F) 0.45 Vs

Figure 6.22. Single Snubber For Sensitive Gate TRIACand Phase Controllable Optocoupler

(ρ = 0.67)

φ CNTL

MOC3020/3021

10 V/µs

TIME240 µs

0.63 (170)

L = 318 MHY

1 A, 60 Hz

RinVCC

C10.1 µF

170 V6 2.4 k1801T2322D1 V/µs

4

2



THE SNUBBER WITH INDUCTANCE

Consider an overdamped snubber using a large capaci-tor whose voltage changes insignificantly during the timeunder consideration. The circuit reduces to an equivalentL/R series charging circuit.

The current through the snubber resistor is:

i VR

1 et ,

and the voltage across the TRIAC is:

e i RS.

The voltage wave across the TRIAC has an exponentialrise with maximum rate at t = 0. Taking its derivative givesits value as:

dVdt

0

V RSL

.

Highly overdamped snubber circuits are not practical de-signs. The example illustrates several properties:

1. The initial voltage appears completely across thecircuit inductance. Thus, it determines the rate ofchange of current through the snubber resistor and the

initial dVdt

. This result does not change when there is

resistance in the load and holds true for all dampingfactors.

2. The snubber works because the inductor controls therate of current change through the resistor and the rateof capacitor charging. Snubber design cannot ignorethe inductance. This approach suggests that thesnubber capacitance is not important but that is onlytrue for this hypothetical condition. The snubberresistor shunts the thyristor causing unacceptableleakage when the capacitor is not present. If the power

loss is tolerable, dVdt

can be controlled without the

capacitor. An example is the soft-start circuit used to limitinrush current in switching power supplies (Figure 25).

Figure 6.25. Surge Current Limiting Fora Switching Power Supply

dVdt

ERSL

SNUBBERL G

RS

E

Snubber With No C

E

C1AC LINERECTIFIER

BRIDGE

SNUBBERL

AC LINERECTIFIER

BRIDGE C1G

RS

TRIAC DESIGN PROCEDURE dVdt

c

1. Refer to Figure 18 and select a particular damping

factor (ρ) giving a suitable trade-off between VPK and dVdt

.

Determine the normalized dVdt

corresponding to the cho-

sen damping factor.

The voltage E depends on the load phase angle:

E 2 VRMS Sin () where tan1XLRL where

φ = measured phase angle between line V and load IRL = measured dc resistance of the load.

Then

Z VRMSIRMS

RL2 XL

2 XL Z2RL2 and

L XL

2 fLine.

If only the load current is known, assume a pure inductance.This gives a conservative design. Then:

L VRMS

2 fLine IRMSwhere E 2 VRMS.

For example:

E 2 120 170 V; L 120(8 A) (377 rps)

39.8 mH.

Read from the graph at ρ = 0.6, VPK = (1.25) 170 = 213 V.

Use 400 V TRIAC. Read dVdt (ρ0.6)

1.0.

2. Apply the resonance criterion:

0 spec dVdt dV

dt(P)E.

0 5 106 VS(1) (170 V)

29.4 103 r ps.

C 102 L

0.029 F

3. Apply the damping criterion:

RS 2ρ LC 2(0.6) 39.8 103

0.029 106 1400ohms.


dVdt

c SAFE AREA CURVE

Figure 26 shows a MAC16 TRIAC turn-off safe operatingarea curve. Turn-off occurs without problem under the curve.

The region is bounded by static dVdt

at low values of dIdt

cand delay time at high currents. Reduction of the peakcurrent permits operation at higher line frequency. ThisTRIAC operated at f = 400 Hz, TJ = 125°C, and ITM = 6.0amperes using a 30 ohm and 0.068 µF snubber. Low

damping factors extend operation to higher dIdt

c, but

capacitor sizes increase. The addition of a small, saturablecommutation inductor extends the allowed current rate byintroducing recovery delay time.

dV dt( )

(V/

s)

µc

dIdt

cAMPERESMILLISECOND

Figure 6.26. versus T J = 125°CdVdt

cdIdt

c

100

10

0.15010

1

WITH COMMUTATION L

3014 18 22 26 34 38 42 46

– ITM = 15 A

dIdt

c 6 f ITM 103 Ams

MAC 16-8, COMMUTATIONAL L 33 TURNS # 18,52000-1A TAPE WOUND CORE 34 INCH OD

STATIC dVdt DESIGN

There is usually some inductance in the ac main andpower wiring. The inductance may be more than 100 µH ifthere is a transformer in the circuit or nearly zero when ashunt power factor correction capacitor is present. Usuallythe line inductance is roughly several µH. The minimum

Figure 6.27. Snubbing For a Resistive Load

50 V/µs

0.33 µF10

LS1

100 µH20 A

340V 12 Ω

HEATER

inductance must be known or defined by adding a seriesinductor to insure reliable operation (Figure 27).

One hundred µH is a suggested value for starting thedesign. Plug the assumed inductance into the equation for C.Larger values of inductance result in higher snubber resis-

tance and reduced dIdt

. For example:

Given E = 240 2 340 V.

Pick ρ = 0.3.

Then from Figure 18, VPK = 1.42 (340) = 483 V.

Thus, it will be necessary to use a 600 V device. Using thepreviously stated formulas for ω0, C and R we find:

0 50 106 VS(0.73) (340 V)

201450 rps

C 1(201450)2 (100 106)

0.2464 F

R 2 (0.3) 100 106

0.2464 106 12 ohms

VARIABLE LOADS

The snubber should be designed for the smallest load

inductance because dVdt

will then be highest because of its

dependence on ω0. This requires a higher voltage device foroperation with the largest inductance because of thecorresponding low damping factor.



Figure 28 describes dVdt

for an 8.0 ampere load at various

power factors. The minimum inductance is a component

added to prevent static dVdt

firing with a resistive load.

ρR L Vstep VPK

dvdtρ

Ω MHY V V V/µs

0.75 15 0.1 170 191 86

0.03 0 39.8 170 325 4.0

0.04 10.6 28.1 120 225 3.3

0.06 13.5 17.3 74 136 2.6

EXAMPLES OF SNUBBER DESIGNS

Table 2 describes snubber RC values for dVdt

s. Figures

31 and 32 show possible R and C values for a 5.0 V/µs

dVdt

c assuming a pure inductive load.

Table 2. Static Designs

(E = 340 V, Vpeak = 500 V, ρ = 0.3)

dVdt

5.0 V/µs 50 V/µs 100 V/µs

LµH

CµF

ROhm

CµF

ROhm

CµF

ROhm

47 0.15 10100 0.33 10 0.1 20220 0.15 22 0.033 47500 0.068 51 0.015 1101000 3.0 11 0.033 100

TRANSIENT AND NOISE SUPPRESSION

Transients arise internally from normal circuit operation orexternally from the environment. The latter is particularlyfrustrating because the transient characteristics are unde-fined. A statistical description applies. Greater or smallerstresses are possible. Long duration high voltage transientsare much less probable than those of lower amplitude andhigher frequency. Environments with infrequent lightningand load switching see transient voltages below 3.0 kV.

Figure 6.29. Snubber Resistor For = 5.0 V/ µsdVdtc

R

(OH

MS)

S

80 A

40 A

20 A

0

0.6 A RMS 2.5 A

5 A

DAMPING FACTOR

10.90.80.70.60.50.40.30.20.1

10K

100

1000

10

10 A

PURE INDUCTIVE LOAD, V 120 VRMS,IRRM 0

Figure 6.30. Snubber Capacitor For = 5.0 V/ µsdVdtc

C

( F

)S

µ

0.001

2.5 A0.01

0.6 A

5 A

10 A

20 A

1

0.1

80 A RMS

40 A

0

DAMPING FACTOR

10.90.80.70.60.50.40.30.20.1

PURE INDUCTIVE LOAD, V 120 VRMS,IRRM 0

Figure 6.28. Snubber For a Variable Load

LRMAC 218-6

8 A LOAD

68 Ω 120 V60 Hz

0.033 µF

dVdt

s 100 Vs dV

dt

c 5 Vs


The natural frequencies and impedances of indoor ac wiringresult in damped oscillatory surges with typical frequenciesranging from 30 kHz to 1.5 MHz. Surge amplitude depends onboth the wiring and the source of surge energy. Disturbancestend to die out at locations far away from the source. Spark-over(6.0 kV in indoor ac wiring) sets the maximum voltage whentransient suppressors are not present. Transients closer to theservice entrance or in heavy wiring have higher amplitudes,longer durations, and more damping because of the lowerinductance at those locations.

The simple CRL snubber is a low pass filter attenuatingfrequencies above its natural resonance. A steady statesinusoidal input voltage results in a sine wave output at thesame frequency. With no snubber resistor, the rate of roll offapproaches 12 dB per octave. The corner frequency is at thesnubber’s natural resonance. If the damping factor is low, theresponse peaks at this frequency. The snubber resistordegrades filter characteristics introducing an up-turn at ω = 1/ (RC). The roll-off approaches 6.0 dB/octave at frequenciesabove this. Inductance in the snubber resistor furtherreduces the roll-off rate.

Figure 32 describes the frequency response of thecircuit in Figure 27. Figure 31 gives the theoreticalresponse to a 3.0 kV 100 kHz ring-wave. The snubberreduces the peak voltage across the thyristor. However,

the fast rise input causes a high dVdt

step when series

inductance is added to the snubber resistor. Limiting theinput voltage with a transient suppressor reduces the step.

Figure 6.31. Theoretical Response of Figure 33 Circuitto3.0 kV IEEE 587 Ring Wave (R SC = 27.5 Ω)

V

(VO

LTS)

MT 2-

1

400

WITH 5 µHY

450 V MOVAT AC INPUT

WITH 5 µHY ANDWITHOUT 5 µHY

654210

TIME (µs)

3– 400

0

Figure 6.32. Snubber Frequency Response VoutVin

VOLT

AGE

GAI

N (d

B)

FREQUENCY (Hz)10K

WITH 5 µHY

WITHOUT 5µHY

– 40

0.33 µF

10

5 µH

12

Vin

100 µH

1M

+ 10

0

100K

– 30

– 20

– 10

Vout

The noise induced into a circuit is proportional to dVdt

when

coupling is by stray capacitance, and dIdt

when the coupling is

by mutual inductance. Best suppression requires the use of avoltage limiting device along with a rate limiting CRL snubber.

The thyristor is best protected by preventing turn-on fromdVdt

or breakover. The circuit should be designed for what can

happen instead of what normally occurs.In Figure 30, a MOV connected across the line protects

many parallel circuit branches and their loads. The MOV

defines the maximum input voltage and dIdt

through the load.

With the snubber, it sets the maximum dVdt

and peak voltage

across the thyristor. The MOV must be large because there islittle surge limiting impedance to prevent its burn-out.

Figure 6.33. Limiting Line Voltage

VMAX

In Figure 32, there is a separate suppressor across eachthyristor. The load impedance limits the surge energydelivered from the line. This allows the use of a smallerdevice but omits load protection. This arrangement protectseach thyristor when its load is a possible transientsource.

Figure 6.34. Limiting Thyristor Voltage

It is desirable to place the suppression device directly acrossthe source of transient energy to prevent the induction of energyinto other circuits. However, there is no protection for energyinjected between the load and its controlling thyristor. Placingthe suppressor directly across each thyristor positively limits

maximum voltage and snubber discharge dIdt

.



Figure 6.35. 3 Phase Reversing Motor

MOC3081

SNUBBERALL MOV’S ARE 275VRMSALL TRIACS AREMAC218-10

0.15µF

22 Ω2 W

WIREWOUND

43

4

6

G1

2

91

1/3 HP208 V

3 PHASE

100 µH

REV

φ1

91

G

12

300

6

FWD

4

SNUBBER

N

φ2

φ3

MOC3081

91

G

12

300

64

SNUBBER

MOC3081

91

G

12

300

64

SNUBBER

MOC3081

91

G

12

300

46

SNUBBER

REV

FWD

100 µHMOC3081

SNU

BBER

EXAMPLES OF SNUBBER APPLICATIONS

In Figure 35, TRIACs switch a 3 phase motor on and offand reverse its rotation. Each TRIAC pair functions as aSPDT switch. The turn-on of one TRIAC applies thedifferential voltage between line phases across theblocking device without the benefit of the motor impedanceto constrain the rate of voltage rise. The inductors are

added to prevent static dVdt

firing and a line-to-line short.

Figure 36 shows a split phase capacitor-run motor withreversing accomplished by switching the capacitor inseries with one or the other winding. The forward andreverse TRIACs function as a SPDT switch. Reversing themotor applies the voltage on the capacitor abruptly acrossthe blocking thyristor. Again, the inductor L is added to

prevent dVdt

s firing of the blocking TRIAC. If turn-on

occurs, the forward and reverse TRIACs short thecapacitors (Cs) resulting in damage to them. It is wise toadd the resistor RS to limit the discharge current.


Figure 6.36. Split Phase Reversing Motor

5.6

3.75330 V

MOTOR1/70 HP0.26 A

T2323D

115

500 µH

LS

REV

46 V/µsMAX

FWD

0.191

CS

0.1

RS

91

Figure 37 shows a “ tap changer.” This circuit allows theoperation of switching power supplies from a 120 or 240 vacline. When the TRIAC is on, the circuit functions as aconventional voltage doubler with diodes D1 and D2conducting on alternate half-cycles. In this mode of opera-

tion, inrush current and dIdt

are hazards to TRIAC reliability.

Series impedance is necessary to prevent damage to theTRIAC.

The TRIAC is off when the circuit is not doubling. In thisstate, the TRIAC sees the difference between the line voltageand the voltage at the intersection of C1 and C2. Transients

on the line cause dVdt

s firing of the TRIAC. High inrush

current, dIdt

, and overvoltage damage to the filter capacitor

are possibilities. Prevention requires the addition of a RCsnubber across the TRIAC and an inductor in series withthe line.

Figure 6.37. Tap Changer For Dual VoltageSwitching Power Supply

–C1

+

RL

0 G

CSRS

120 V

240 V

SNUBBER INDUCTOR

120 VACOR

240 VAC

D1D2

D4D3

–C2

+

THYRISTOR TYPES

Sensitive gate thyristors are easy to turn-on because oftheir low trigger current requirements. However, they have

less dVdt

capability than similar non-sensitive devices. A

non-sensitive thyristor should be used for high dVdt

.

TRIAC commutating dVdt

ratings are 5 to 20 times less than

static dVdt

ratings.

Phase controllable optocouplers have lower dVdt

ratings

than zero crossing optocouplers and power TRIACs.These should be used when a dc voltage component ispresent, or to prevent turn-on delay.

Zero crossing optocouplers have more dVdt

capability

than power thyristors; and they should be used in place ofphase controllable devices in static switchingapplications.

APPENDIX A

TESTING SNUBBER DISCHARGE dIdt

The equations in Appendix D do not consider thethyristor’s turn-on time or on-state resistance, thus, they

predict high values of dIdt

.

Figure 38 shows the circuit used to test snubber dischargedIdt

. A MBS4991 supplies the trigger pulse while the quad-

rants of operation are switch selectable. The snubber wasmounted as close to the TRIAC under test as possible toreduce inductance, and the current transformer remained inthe circuit to allow results to be compared with the measureddIdt

value.

What should the peak capacitor voltage be? A conserva-tive approach is to test at maximum rated VDRM, or the clampvoltage of the MOV.

What is the largest capacitor that can be used withoutlimiting resistance? Figure 39 is a photo showing the currentpulse resulting from a 0.001 µF capacitor charged to 800 V.

The 1200 A/µs dIdt

destroyed the TRIAC.

Is it possible for MOV self-capacitance to damage theTRIAC? A large 40 Joule, 2200 A peak current rated MOVwas tested. The MOV measured 440 pF and had an 878volt breakover voltage. Its peak discharge current (12 A)was half that of a 470 pF capacitor. This condition wassafe.



Figure 6.38. Snubber Discharge dl/dt Test

OPTIONAL PEARSON411 CURRENT

TRANSFORMER

120 VAC 60 Hz

500 W

2000

SWEEP FORDESIRED VCi

VTC5–50

2.5 kV5000200 W

X100V PROBE

RS

CS

TRIACUNDER TEST

MT1

50 Ω

G

MT2

91

56

VMT2-1

QUADRANTMAP

2

3 4

1

VG Q1,3

12 V

QUADRANTSWITCH

Q2,41µF

MBS4991

3000

OPT

ION

AL M

OV

APPENDIX B

MEASURING dVdt

s

Figure 40 shows a test circuit for measuring the static dVdt

of power thyristors. A 1000 volt FET switch insures that thevoltage across the device under test (D.U.T.) rises rapidlyfrom zero. A differential preamp allows the use of aN-channel device while keeping the storage scopechassis at ground for safety purposes. The rate of voltagerise is adjusted by a variable RC time constant. Thecharging resistance is low to avoid waveform distortionbecause of the thyristor’s self-capacitance but is large

enough to prevent damage to the D.U.T. from turn-on dIdt

.

Mounting the miniature range switches, capacitors, andG-K network close to the device under test reduces strayinductance and allows testing at more than 10 kV/µs.

Figure 6.39. Discharge Current From 0.001 µFCapacitor

HORIZONTAL SCALE — 50 ms/DIV.VERTICAL SCALE — 10 A/DIV.

CS = 0.001 µF, VCi = 800 V, RS = 0, L = 250 mH, RTRAIC = 10 OHMS


Figure 6.40. Circuit For Static Measurement of Power ThyristorsdVdt

X100 PROBE

X100 PROBE

DIFFERENTIALPREAMP

MOUNT DUT ONTEMPERATURE CONTROLLEDCµ PLATE

DUT

2

1G

RGK

2 W20 k

VDRM/VRRM SELECT 2 W

27

0.33 1000 V 0.0471000 V

100010 WATT

WIREWOUND

10001/4 W

562 W

VERNIER

822 W

1002 W

470 pF

0.001

0.005

0.01

0.047

0.1

0.47

1.2 MEG2 W EACH1 MEG

POWER2 W

TEST

MTP1N100

ALL COMPONENTS ARE NON-INDUCTIVE UNLESS OTHERWISE SHOWN

0–1000 V10 mA

1N967A18 V

1N914

f = 10 HzPW = 100 µs50 Ω PULSEGENERATOR

20 V

dVdt

APPENDIX C

MEASURING dVdt

c

A test fixture to measure commutating dVdt

is shown in

Figure 41. It is a capacitor discharge circuit with the loadseries resonant. The single pulse test aids temperaturecontrol and allows the use of lower power components.The limited energy in the load capacitor reduces burn andshock hazards. The conventional load and snubber circuitprovides recovery and damping behaviors like those in theapplication.

The voltage across the load capacitor triggers the D.U.T.It terminates the gate current when the load capacitorvoltage crosses zero and the TRIAC current is at its peak.

Each VDRM, ITM combination requires different compo-nents. Calculate their values using the equations given inFigure 41.

Commercial chokes simplify the construction of the neces-sary inductors. Their inductance should be adjusted byincreasing the air gap in the core. Removal of the magneticpole piece reduces inductance by 4 to 6 but extends thecurrent without saturation.

The load capacitor consists of a parallel bank of 1500 Vdcnon-polar units, with individual bleeders mounted at eachcapacitor for safety purposes.

An optional adjustable voltage clamp prevents TRIACbreakdown.

To measure dVdt

c, synchronize the storage scope on the

current waveform and verify the proper current amplitude andperiod. Increase the initial voltage on the capacitor tocompensate for losses within the coil if necessary. Adjust thesnubber until the device fails to turn off after the firsthalf-cycle. Inspect the rate of voltage rise at the fastestpassing condition.



–

+

–

+

2 W51+ 5CS

2N3904

0.1

2.2 k1/2SYNC

TRIACUNDERTEST

562 WATT

CASECONTROLLED

HEATSINK

0.1

2N3906

– 5 G1

2

PEARSON301 X

2N3904

1/2 W120

2N3906

1201/2 W

2N39062N3904RS

1/2 W

– +

0.22270 k 1N5343

7.5 V

0.22Q1Q3

2N3906

2N3904

1/2 W360

1 k

– 5 + 5

NON-INDUCTIVERESISTOR DECADE

0–10 k, 1 Ω STEP

2 W51 k

51 k2 W

HG = W AT LOW LD10-1000-1000

+ CLAMP

MR760

– CLAMP

62 µF1 kV

LL

6.2 MEG 2 W

150 k

910 k2 W

2 W

910 k

RL

Q3 Q1

70 mA

1.5 kV

TRIAD C30X50 H, 3500 Ω

2 W51

6.2 MEG 2 W

360

1 k

270 k

2N39042N3906

Q3 Q1

0-1

kV 2

0 m

A

C

(NO

N-P

OLA

R)

L

MR

760

MR

760

2.2

M2.

2 M

2.2

M, 2

W

2.2

M, 2

W2.

2 M

2.2

M

0.01

Figure 6.41. Test Circuit For Power TRIACsdVdt

c

µ

CL IPK

W0 VCi

Ip T

2 VCiLL

VCiW0 IPK

T2

4 2 CLW0

I

LLdIdtc 6f IPK 106

As

dVdt

CAP

ACIT

OR

DEC

ADE

1–10

F

, 0.0

1–1

F,

100

pF–

0.0

1

Fµ

µ

0.01


APPENDIX DdVdt

DERIVATIONS

DEFINITIONS

1.0 RT RL RS Total Resistance

1.1 M RSRT

Snubber Divider Ratio

1.2 0 1L CS Undamped Natural Frequency

Damped Natural Frequency

1.3 RT2 L

Wave Decrement Factor

1.4 χ2 12 LI2

12 CV2

Initial Energy In InductorFinal Energy In Capacitor

1.5 χ IE

LC Initial Current Factor

1.6 ρ RT2

CL

0 Damping Factor

1.7 V0L ERS I Initial Voltage drop at t 0across the load

1.8 ICS

E RL

L

dVdt

0 Initial instantaneous dV

dtat t 0, ignoring

any initial instantaneous voltage step att 0 because of IRRM

1.9 dVdt

0 VOL

RTL . For all damping conditions

2.0 When I 0, dVdt

0

E RSL

dVdt

max Maximum instantaneous dV

dt

tmax Time of maximum instantaneous dVdt

tpeak Time of maximum instantaneous peakvoltage across thyristor

Average dVdt

VPK tPK Slope of the secant line

from t 0 through VPKVPK Maximum instantaneous voltage across the

thyristor.

CONSTANTS (depending on the damping factor):

2.1 No Damping (ρ 0) 0RT ρ 0

2.2 Underdamped (0 ρ 1)

02 2 0 1 ρ2

2.3 Critical Damped (ρ 1)

0, 0, R 2 LC , C 2

RT

2.4 Overdamped (ρ 1)

2 02 0 ρ2 1Laplace transforms for the current and voltage in Figure 42are:

3.0 i(S)ELSI

S2SRTL 1

LC

; e ES

S V0L

S2RTL

S 1LC

INITIAL CONDITIONSI IRRMVCS 0

Figure 6.42. Equivalent Circuit for Load and Snubber

t = 0I

RL L

CS

RSe

The inverse laplace transform for each of the conditionsgives:

UNDERDAMPED (Typical Snubber Design)

4.0 e E V0LCos (t)

sin (t)e t

sin (t) et

4.1 dedt

V0L2Cos (t)

(2 2)

sin (t)et

Cos (t)

sin (t) et

4.2 tPK 1 tan1

2 V0L

V0L22

When M 0, RS 0, I 0 : tPK

4.3 VPK E 0

tPK 02 V0L

2 2 V0L 2When I 0, RL 0, M 1:

4.4VPK

E (1 e tPK)

Average dVdt

VPKtPK



4.5 tmax1

ATN (2 V0L (2 32))

V0L(3 32) (2 2)

4.6 dVdt

max V0L

2022 V0L 2 e– tmax

NO DAMPING

5.0 e E (1 Cos (0t)) IC 0

sin (0t)

5.1 dedt

E 0 sin (0t) IC

Cos (0t)

5.2 dVdt

0 I

C 0 when I 0

5.3 tPK tan1 I

CE 0

0

5.4 VPK E E2 I2

02C2

5.5 dVdtAVG

VPKtPK

5.6 tmax 10tan10 EC

I 1

02

when I 0

5.7 dVdt

max I

CE202 C2I2 0E when I 0

CRITICAL DAMPING

6.0 e E V0L(1 t)et tet

6.1 dedt

VOL (2 t) (1 t)et

6.2 tPK

2

2 V0L

V0L

6.3 VPK E – V0L (1– tPK)– tPK e– tPK

6.4 Average dVdt

VPKtPK

When I 0, RS 0, M 0

e(t) rises asymptotically to E. tPK and average dVdt

do not exist.

6.5 tmax 3V0L 2

2V0L

When I 0, tmax 0

ForRSRT

34,

then dVdt max

dVdt

0

6.6 dVdt

max

V0L (2– tmax) (1– tmax) e– tmax

APPENDIX E

SNUBBER DISCHARGE dIdt

DERIVATIONS

OVERDAMPED

1.0 i VCS LS

–t sinh (t)

1.1 iPK VCS

CSLS e– tPK

1.2 tPK 1 tanh –1

CRITICAL DAMPED

2.0 i VCSLS

te–t

2.1 iPK 0.736VCSRS

2.2 tPK 1

UNDERDAMPED

3.0 i VCS LS

e–t sin (t)

3.1 iPK VCS

CSLS e– tPK

3.2 tPK 1 tan –1


Figure 6.43. Equivalent Circuit for Snubber Discharge

LSRS

CSVCS i

t = 0

INITIAL CONDITIONS :i 0, VCS INITIAL VOLTAGE

NO DAMPING

4.0 iVCS LS

sin (t)

4.1 iPK VCS

CSLS

4.2 tPK

2

BIBLIOGRAPHY

Bird, B. M. and K. G. King. An Introduction To PowerElectronics. John Wiley & Sons, 1983, pp. 250–281.

Blicher, Adolph. Thyristor Physics. Springer-Verlag, 1976.

Gempe, Horst. “Applications of Zero Voltage CrossingOptically Isolated TRIAC Drivers,” AN982, Motorola Inc.,1987.

“Guide for Surge Withstand Capability (SWC) Tests,” ANSI337.90A-1974, IEEE Std 472–1974.

“IEEE Guide for Surge Voltages in Low-Voltage AC PowerCircuits,” ANSI/IEEE C62.41-1980, IEEE Std 587–1980.

Ikeda, Shigeru and Tsuneo Araki. “The dIdt

Capability of

Thyristors,” Proceedings of the IEEE, Vol. 53, No. 8, August1967.

Kervin, Doug. “The MOC3011 and MOC3021,” EB-101,Motorola Inc., 1982.

McMurray, William. “Optimum Snubbers For Power Semicon-ductors,” IEEE Transactions On Industry Applications, Vol.IA-8, September/October 1972.

Rice, L. R. “Why R-C Networks And Which One For YourConverter,” Westinghouse Tech Tips 5-2.

“Saturable Reactor For Increasing Turn-On Switching Capa-bility,” SCR Manual Sixth Edition, General Electric, 1979.

Zell, H. P. “Design Chart For Capacitor-Discharge PulseCircuits,” EDN Magazine, June 10, 1968.



REV 1


CHAPTER 7MOUNTING TECHNIQUES FOR THYRISTORS

INTRODUCTION

Current and power ratings of semiconductors are insepa-rably linked to their thermal environment. Except for lead-mounted parts used at low currents, a heat exchanger isrequired to prevent the junction temperature from exceedingits rated limit, thereby running the risk of a high failure rate.Furthermore, the semiconductor industry’s field history indi-cated that the failure rate of most silicon semiconductorsdecreases approximately by one half for a decrease injunction temperature from 160°C to 135°C.(1) Guidelines fordesigners of military power supplies impose a 110°C limitupon junction temperature.(2) Proper mounting minimizes thetemperature gradient between the semiconductor case andthe heat exchanger.

Most early life field failures of power semiconductors canbe traced to faulty mounting procedures. With metal pack-aged devices, faulty mounting generally causes unnecessar-ily high junction temperature, resulting in reduced componentlifetime, although mechanical damage has occurred onoccasion from improperly mounting to a warped surface.With the widespread use of various plastic-packaged semi-conductors, the prospect of mechanical damage is verysignificant. Mechanical damage can impair the case moistureresistance or crack the semiconductor die.

(1) MIL-HANDBOOK — 2178, SECTION 2.2.(2) “Navy Power Supply Reliability — Design and Manufacturing

Guidelines” NAVMAT P4855-1, Dec. 1982 NAVPUBFORCEN,5801 Tabor Ave., Philadelphia, PA 19120.

Figure 7.1 shows an example of doing nearly everythingwrong. A tab mount TO-220 package is shown being used asa replacement for a TO-213AA (TO-66) part which wassocket mounted. To use the socket, the leads are bent — anoperation which, if not properly done, can crack the package,break the internal bonding wires, or crack the die. Thepackage is fastened with a sheet-metal screw through a 1/4″hole containing a fiber-insulating sleeve. The force used totighten the screw tends to pull the package into the hole,causing enough distortion to crack the die. In addition thecontact area is small because of the area consumed by thelarge hole and the bowing of the package; the result is amuch higher junction temperature than expected. If a roughheatsink surface and/or burrs around the hole were dis-played in the illustration, most but not all poor mountingpractices would be covered.

SPEED NUT(PART OF SOCKET)

PLASTIC BODY

LEADS

EQUIPMENTHEATSINK

PACKAGE HEATSINK

SOCKET FORTO-213AA PACKAGE SHEET METAL SCREW

MICA WASHER

Figure 7.1. Extreme Case of Improperly MountingA Semiconductor (Distortion Exaggerated)



In many situations the case of the semiconductor must beelectrically isolated from its mounting surface. The isolationmaterial is, to some extent, a thermal isolator as well, whichraises junction operating temperatures. In addition, thepossibility of arc-over problems is introduced if high voltagesare present. Various regulating agencies also impose creep-age distance specifications which further complicates de-sign. Electrical isolation thus places additional demandsupon the mounting procedure.

Proper mounting procedures usually necessitate orderlyattention to the following:

1. Preparing the mounting surface 2. Applying a thermal grease (if required) 3. Installing the insulator (if electrical isolation is desired) 4. Fastening the assembly 5. Connecting the terminals to the circuit

In this note, mounting procedures are discussed in generalterms for several generic classes of packages. As newerpackages are developed, it is probable that they will fit intothe generic classes discussed in this note. Unique require-ments are given on data sheets pertaining to the particularpackage. The following classes are defined:

Stud MountFlange MountPressfitPlastic Body MountTab MountSurface MountAppendix A contains a brief review of thermal resistance

concepts. Appendix B discusses measurement difficultieswith interface thermal resistance tests. Appendix C indicatesthe type of accessories supplied by a number ofmanufacturers.

MOUNTING SURFACE PREPARATION

In general, the heatsink mounting surface should have aflatness and finish comparable to that of the semiconductorpackage. In lower power applications, the heatsink surface issatisfactory if it appears flat against a straight edge and isfree from deep scratches. In high-power applications, a moredetailed examination of the surface is required. Mountingholes and surface treatment must also be considered.

Surface FlatnessSurface flatness is determined by comparing the variance

in height (∆h) of the test specimen to that of a referencestandard as indicated in Figure 7.2. Flatness is normallyspecified as a fraction of the Total Indicator Reading (TIR).The mounting surface flatness, i.e., ∆h/TIR, if less than 4 milsper inch, normal for extruded aluminum, is satisfactory inmost cases.

Surface FinishSurface finish is the average of the deviations both above

and below the mean value of surface height. For minimuminterface resistance, a finish in the range of 50 to 60microinches is satisfactory; a finer finish is costly to achieve

SAMPLEPIECE

TIR = TOTAL INDICATOR READING

∆hTIR

REFERENCE PIECEDEVICE MOUNTING AREA

Figure 7.2. Surface Flatness Measurement

and does not significantly lower contact resistance. Testsconducted by Thermalloy using a copper TO-204 (TO-3)package with a typical 32-microinch finish, showed thatheatsink finishes between 16 and 64 µ-in caused less than± 2.5% difference in interface thermal resistance when thevoids and scratches were filled with a thermal joint com-pound.(3) Most commercially available cast or extrudedheatsinks will require spotfacing when used in high-powerapplications. In general, milled or machined surfaces aresatisfactory if prepared with tools in good working condition.

Mounting HolesMounting holes generally should only be large enough

to allow clearance of the fastener. The large thick flangetype packages having mounting holes removed from thesemiconductor die location, such as the TO-3, maysuccessfully be used with larger holes to accommodate aninsulating bushing, but many plastic encapsulated pack-ages are intolerant of this condition. For these packages,a smaller screw size must be used such that the hole forthe bushing does not exceed the hole in the package.

Punched mounting holes have been a source of troublebecause if not properly done, the area around a punchedhole is depressed in the process. This “crater” in theheatsink around the mounting hole can cause twoproblems. The device can be damaged by distortion of thepackage as the mounting pressure attempts to conform itto the shape of the heatsink indentation, or the device mayonly bridge the crater and leave a significant percentage ofits heat-dissipating surface out of contact with theheatsink. The first effect may often be detected immediate-ly by visual cracks in the package (if plastic), but usually anunnatural stress is imposed, which results in an early-lifefailure. The second effect results in hotter operation and isnot manifested until much later.

Although punched holes are seldom acceptable in therelatively thick material used for extruded aluminumheatsinks, several manufacturers are capable of properlyutilizing the capabilities inherent in both fine-edge blank-ing or sheared-through holes when applied to sheet metalas commonly used for stamped heatsinks. The holes arepierced using Class A progressive dies mounted onfour-post die sets equipped with proper pressure pads andholding fixtures.

(3) Catalog #87-HS-9 (1987), page 8, Thermalloy, Inc., P.O. Box810839, Dallas, Texas 75381-0839.


When mounting holes are drilled, a general practice withextruded aluminum, surface cleanup is important. Chamfersmust be avoided because they reduce heat transfer surfaceand increase mounting stress. However, the edges must bebroken to remove burrs which cause poor contact betweendevice and heatsink and may puncture isolation material.

Surface TreatmentMany aluminium heatsinks are black-anodized to improve

radiation ability and prevent corrosion. Anodizing results insignificant electrical but negligible thermal insulation. It needonly be removed from the mounting area when electricalcontact is required. Heatsinks are also available which havea nickel plated copper insert under the semiconductormounting area. No treatment of this surface is necessary.

Another treated aluminum finish is iridite, or chromate-aciddip, which offers low resistance because of its thin surface,yet has good electrical properties because it resists oxida-tion. It need only be cleaned of the oils and films that collect inthe manufacture and storage of the sinks, a practice whichshould be applied to all heatsinks.

For economy, paint is sometimes used for sinks; removalof the paint where the semiconductor is attached is usuallyrequired because of paint’s high thermal resistance. How-ever, when it is necessary to insulate the semiconductorpackage from the heatsink, hard anodized or paintedsurfaces allow an easy installation for low voltage applica-tions. Some manufacturers will provide anodized or paintedsurfaces meeting specific insulation voltage requirements,usually up to 400 volts.

It is also necessary that the surface be free from all foreignmaterial, film, and oxide (freshly bared aluminum forms anoxide layer in a few seconds). Immediately prior to assembly,it is a good practice to polish the mounting area with No. 000steel wool, followed by an acetone or alcohol rinse.

INTERFACE DECISIONS

When any significant amount of power is being dissipated,something must be done to fill the air voids between matingsurfaces in the thermal path. Otherwise the interface thermalresistance will be unnecessarily high and quite dependentupon the surface finishes.

For several years, thermal joint compounds, often calledgrease, have been used in the interface. They have aresistivity of approximately 60°C/W/in whereas air has1200°C/W/in. Since surfaces are highly pock-marked withminute voids, use of a compound makes a significantreduction in the interface thermal resistance of the joint.However, the grease causes a number of problems, asdiscussed in the following section.

To avoid using grease, manufacturers have developed dryconductive and insulating pads to replace the more tradition-al materials. These pads are conformal and thereforepartially fill voids when under pressure.

Thermal Compounds (Grease)Joint compounds are a formulation of fine zinc or other

conductive particles in the silicone oil or other synthetic basefluid which maintains a grease-like consistency with time andtemperature. Since some of these compounds do not spread

well, they should be evenly applied in a very thin layer usinga spatula or lintless brush, and wiped lightly to removeexcess material. Some cyclic rotation of the package will helpthe compound spread evenly over the entire contact area.Some experimentation is necessary to determine the correctquantity; too little will not fill all the voids, while too much maypermit some compound to remain between well mated metalsurfaces where it will substantially increase the thermalresistance of the joint.

To determine the correct amount, several semiconductorsamples and heatsinks should be assembled with differentamounts of grease applied evenly to one side of each matingsurface. When the amount is correct a very small amount ofgrease should appear around the perimeter of each matingsurface as the assembly is slowly torqued to the recom-mended value. Examination of a dismantled assemblyshould reveal even wetting across each mating surface. Inproduction, assemblers should be trained to slowly apply thespecified torque even though an excessive amount of greaseappears at the edges of mating surfaces. Insufficient torquecauses a significant increase in the thermal resistance of theinterface.

To prevent accumulation of airborne particulate matter,excess compound should be wiped away using a clothmoistened with acetone or alcohol. These solvents shouldnot contact plastic-encapsulated devices, as they may enterthe package and cause a leakage path or carry in sub-stances which might attack the semiconductor chip.

The silicone oil used in most greases has been found toevaporate from hot surfaces with time and become depositedon other cooler surfaces. Consequently, manufacturers mustdetermine whether a microscopically thin coating of siliconeoil on the entire assembly will pose any problems. It may benecessary to enclose components using grease. The newersynthetic base greases show far less tendency to migrate orcreep than those made with a silicone oil base. However,their currently observed working temperature range are less,they are slightly poorer on thermal conductivity and dielectricstrength and their cost is higher.

Data showing the effect of compounds on several packagetypes under different mounting conditions is shown in Table7.1. The rougher the surface, the more valuable the greasebecomes in lowering contact resistance; therefore, whenmica insulating washers are used, use of grease is generallymandatory. The joint compound also improves the break-down rating of the insulator.

Conductive PadsBecause of the difficulty of assembly using grease and the

evaporation problem, some equipment manufacturers willnot, or cannot, use grease. To minimize the need for grease,several vendors offer dry conductive pads which approxi-mate performance obtained with grease. Data for a greasedbare joint and a joint using Grafoil, a dry graphite compound,is shown in the data of Figure 7.3. Grafoil is claimed to be areplacement for grease when no electrical isolation isrequired; the data indicates it does indeed perform as well asgrease. Another conductive pad available from Aavid iscalled KON-DUX. It is made with a unique, grain oriented,flake-like structure (patent pending). Highly compressible,it becomes formed to the surface roughness of both of the



Table 7.1Approximate Values for Interface Thermal Resistance Data from Measurements Performed

in Motorola Applications Engineering LaboratoryDry interface values are subject to wide variation because of extreme dependence upon surface conditions. Unless otherwise noted the casetemperature is monitored by a thermocouple located directly under the die reached through a hole in the heatsink. (See Appendix B for adiscussion of Interface Thermal Resistance Measurements.)

Package Type and Data Interface Thermal Resistance ( °C/W)

JEDECTest

Torq eMetal-to-Metal With Insulator

SeeJEDECOutlines Description

Torq ueIn-Lb Dry Lubed Dry Lubed Type

SeeNote

DO-203AA, TO-210AATO-208AB

10-32 Stud7/16″ Hex

15 0.3 0.2 1.6 0.8 3 milMica

DO-203AB, TO-210ACTO-208

1/4-28 Stud11/16″ Hex

25 0.2 0.1 0.8 0.6 5 milMica

DO-208AA Pressfit, 1/2″ — 0.15 0.1 — — —

TO-204AA(TO-3)

Diamond Flange 6 0.5 0.1 1.3 0.36 3 milMica

1

TO-213AA(TO-66)

Diamond Flange 6 1.5 0.5 2.3 0.9 2 milMica

TO-126 Thermopad1/4″ x 3/8″

6 2.0 1.3 4.3 3.3 2 milMica

TO-220AB Thermowatt 8 1.2 1.0 3.4 1.6 2 milMica

1, 2

NOTES: 1. See Figures 3 and 4 for additional data on TO-3 and TO-220 packages.2. Screw not insulated. See Figure 12.

heatsink and semiconductor. Manufacturer’s data shows it toprovide an interface thermal resistance better than a metalinterface with filled silicone grease. Similar dry conductivepads are available from other manufacturers. They are afairly recent development; long term problems, if they exist,have not yet become evident.

INSULATION CONSIDERATIONS

Since most power semiconductors use are vertical deviceconstruction it is common to manufacture power semicon-ductors with the output electrode (anode, collector or drain)electrically common to the case; the problem of isolating thisterminal from ground is a common one. For lowest overallthermal resistance, which is quite important when high powermust be dissipated, it is best to isolate the entire heatsink/semiconductor structure from ground, rather than to use aninsulator between the semiconductor and the heatsink.Heatsink isolation is not always possible, however, becauseof EMI requirements, safety reasons, instances where achassis serves as a heatsink or where a heatsink is commonto several non-isolated packages. In these situations insula-tors are used to isolate the individual components from theheatsink. Newer packages, such as the Motorola FullyIsolated TO-220, contain the electrical isolation materialwithin, thereby saving the equipment manufacturer theburden of addressing the isolation problem.

Insulator Thermal ResistanceWhen an insulator is used, thermal grease is of greater

importance than with a metal-to-metal contact, because twointerfaces exist instead of one and some materials, such as

mica, have a hard, markedly uneven surface. With manyisolation materials reduction of interface thermal resistanceof between 2 to 1 and 3 to 1 are typical when grease is used.

Data obtained by Thermalloy, showing interface resistancefor different insulators and torques applied to TO-204 (TO-3)and TO-220 packages, are shown in Figure 7.3, for bare andgreased surfaces. Similar materials to those shown areavailable from several manufacturers. It is obvious that withsome arrangements, the interface thermal resistance ex-ceeds that of the semiconductor (junction to case).

Referring to Figure 7.3, one may conclude that when highpower is handled, beryllium oxide is unquestionably the best.However, it is an expensive choice. (It should not be cut orabraided, as the dust is highly toxic.) Thermafilm is filledpolyimide material which is used for isolation (variation ofKapton). It is a popular material for low power applicationsbecause of its low cost ability to withstand high temperatures,and ease of handling in contrast to mica which chips andflakes easily.

A number of other insulating materials are also shown.They cover a wide range of insulation resistance, thermalresistance and ease of handling. Mica has been widely usedin the past because it offers high breakdown voltage andfairly low thermal resistance at a low cost but it certainlyshould be used with grease.

Silicone rubber insulators have gained favor because theyare somewhat conformal under pressure. Their ability to fill inmost of the metal voids at the interface reduces the need forthermal grease. When first introduced, they suffered fromcut-through after a few years in service. The ones presentlyavailable have solved this problem by having imbedded padsof Kapton of fiberglass. By comparing Figures 7.3(c) and


(1)

65

(6)

(2)(5)

0

(7)

2

(4)

(3)

3 41

0.1

1

0

0.9

MOUNTING SCREW TORQUE(IN-LBS)

0.8

0.7

0.6

0.5

0.4

0.2

(c). TO-220Without Thermal Grease

5

0

(1)

3

2

1

01 2 4 5 6(IN-LBS)

(3)

4

435362290217

(7)

14572

(6)(5)

(4)

(3)

(7)(4)

(2)

1

(1)

5

4

3

2

(8)

01

MOUNTING SCREW TORQUE(IN-LBS)

654320

INTERFACE PRESSURE (psi)

(7)

(4)

(2)

MOUNTING SCREW TORQUE (IN-LBS)

(3)

(d). TO-220With Thermal Grease

(b). TO-204AA (TO-3)With Thermal Grease

0

(2)

(1)

(5)

(8)

(6)

1

1.6

654320

14572

0.4

0.2

0.6

0.8

1

1.2

1.4

2

0

4353622902170

MOUNTING SCREW TORQUE (IN-LBS)

INTERFACE PRESSURE (psi)

(a). TO-204AA (TO-3)Without Thermal Grease

0.3

Figure 7.3. Interface Thermal Resistance for TO-204, TO-3 and TO-220 Packages using Different Insulating Materialsas a Function of Mounting Screw Torque (Data Courtesy Thermalloy)

(1) Thermalfilm, .002 (.05) thick.(2) Mica, .003 (.08) thick.(3) Mica, .002 (.05) thick.(4) Hard anodized, .020 (.51) thick.(5) Aluminum oxide, .062 (1.57) thick.(6) Beryllium oxide, .062 (1.57) thick.(7) Bare joint — no finish.(8) Grafoil, .005 (.13) thick.**Grafoil is not an insulating material.

(1) Thermalfilm, .022 (.05) thick.(2) Mica, .003 (.08) thick.(3) Mica, .002 (.05) thick.(4) Hard anodized, .020 (.51) thick.(5) Thermalsil II, .009 (.23) thick.(6) Thermalsil III, .006 (.15) thick.(7) Bare joint — no finish.(8) Grafoil, .005 (.13) thick**Grafoil is not an insulating material.

THER

MAL

RES

ISTA

NC

E FR

OM

TR

ANSI

STO

R C

ASE

TO M

OU

NTI

NG

SU

RFA

CE,

R

( C

/WAT

T)θ C

S°

THER

MAL

RES

ISTA

NC

E FR

OM

TR

ANSI

STO

R C

ASE

TO M

OU

NTI

NG

SU

RFA

CE,

R

( C

/WAT

T)θ C

S°

THER

MAL

RES

ISTA

NC

E FR

OM

TR

ANSI

STO

R C

ASE

TO M

OU

NTI

NG

SU

RFA

CE,

R

( C

/WAT

T)θ C

S°

THER

MAL

RES

ISTA

NC

E FR

OM

TR

ANSI

STO

R C

ASE

TO M

OU

NTI

NG

SU

RFA

CE,

R

( C

/WAT

T)θ C

S°

7.3(d), it can be noted that Thermasil, a filled silicone rubber,without grease has about the same interface thermalresistance as greased mica for the TO-220 package.

A number of manufacturers offer silicone rubber insulators.Table 7.2 shows measured performance of a number of theseinsulators under carefully controlled, nearly identical conditions.The interface thermal resistance extremes are over 2:1 for thevarious materials. It is also clear that some of the insulators aremuch more tolerant than others of out-of-flat surfaces. Since thetests were performed, newer products have been introduced.The Bergquist K-10 pad, for example, is described as havingabout 2/3 the interface resistance of the Sil Pad 1000 whichwould place its performance close to the Chomerics 1671 pad.AAVID also offers an isolated pad called Rubber-Duc, howeverit is only available vulcanized to a heatsink and therefore wasnot included in the comparison. Published data from AAVID

Table 7.2 Thermal Resistance of Silicone Rubber Pads

Manufacturer ProductRθCS @3 Mils *

RθCS @7.5 Mils *

WakefieldBergquistStockwell RubberBergquistThermalloyShin-EtsuBergquistChomericsWakefieldBergquistAblestikThermalloyChomerics

Delta Pad 173-7Sil Pad K-41867Sil Pad 400-9Thermalsil IITC-30AGSil Pad 400-71674Delta Pad 174-9Sil Pad 1000Thermal WafersThermalsil III1671

.790

.752

.742

.735

.680

.664

.633

.592

.574

.529

.500

.440

.367

1.1751.4701.0151.2051.0451.2601.0601.190.755.935.9901.035.655

* Test Fixture Deviation from flat from Thermalloy EIR86-1010.



shows RθCS below 0.3°C/W for pressures above 500 psi.However, surface flatness and other details are not specifiedso a comparison cannot be made with other data in this note.

The thermal resistance of some silicone rubber insulatorsis sensitive to surface flatness when used under a fairly rigidbase package. Data for a TO-204AA (TO-3) packageinsulated with Thermasil is shown on Figure 7.4. Observethat the “worst case” encountered (7.5 mils) yields resultshaving about twice the thermal resistance of the “typicalcase” (3 mils), for the more conductive insulator. In order forThermasil III to exceed the performance of greased mica,total surface flatness must be under 2 mils, a situation thatrequires spot finishing.

Figure 7.4. Effect of Total Surface Flatness on InterfaceResistance Using Silicon Rubber Insulators

INTE

RFA

CE

THER

MAL

RES

ISTA

NC

E (

C/W

)°

0.4

Data courtesy of Thermalloy

0.2

TOTAL JOINT DEVIATION FROM FLAT OVERTO-3 HEADER SURFACE AREA (INCHES)

0.0020 0.004 0.0080.0060

0.6

0.8

1

0.01

1.2

(1)

(1) Thermalsil II, .009 inches (.23 mm) thick.(2) Thermalsil III, .006 inches (.15 mm) thick.

(2)

Silicon rubber insulators have a number of unusualcharacteristics. Besides being affected by surface flatnessand initial contact pressure, time is a factor. For example, in astudy of the Cho-Therm 1688 pad thermal interface imped-ance dropped from 0.90°C/W to 0.70°C/W at the end of 1000hours. Most of the change occurred during the first 200 hourswhere RθCS measured 0.74°C/W. The torque on the conven-tional mounting hardware had decreased to 3 in-lb from aninitial 6 in-lb. With non-conformal materials, a reduction intorque would have increased the interface thermal resis-tance.

Because of the difficulties in controlling all variablesaffecting tests of interface thermal resistance, data fromdifferent manufacturers is not in good agreement. Table 7.3shows data obtained from two sources. The relative perfor-mance is the same, except for mica which varies widely inthickness. Appendix B discusses the variables which need tobe controlled. At the time of this writing ASTM Committee D9is developing a standard for interface measurements.

The conclusions to be drawn from all this data is that sometypes of silicon rubber pads, mounted dry, will out perform thecommonly used mica with grease. Cost may be a determin-ing factor in making a selection.

Insulation ResistanceWhen using insulators, care must be taken to keep the

mating surfaces clean. Small particles of foreign matter canpuncture the insulation, rendering it useless or seriouslylowering its dielectric strength. In addition, particularly whenvoltages higher than 300 V are encountered, problems withcreepage may occur. Dust and other foreign material canshorten creepage distances significantly; so having a cleanassembly area is important. Surface roughness and humidityalso lower insulation resistance. Use of thermal greaseusually raises the withstand voltage of the insulating systembut excess must be removed to avoid collecting dust.Because of these factors, which are not amenable toanalysis, hi-pot testing should be done on prototypes and alarge margin of safety employed.

Insulated Electrode PackagesBecause of the nuisance of handling and installing the

accessories needed for an insulated semiconductor mount-ing, equipment manufacturers have longed for cost-effectiveinsulated packages since the 1950’s. The first to appearwere stud mount types which usually have a layer ofberyllium oxide between the stud hex and the can. Althougheffective, the assembly is costly and requires manualmounting and lead wire soldering to terminals on top of thecase. In the late eighties, a number of electrically isolatedparts became available from various semiconductormanufacturers. These offerings presently consist of multiplechips and integrated circuits as well as the more convention-al single chip devices.

The newer insulated packages can be grouped into twocategories. The first has insulation between the semiconduc-tor chips and the mounting base; an exposed area of themounting base is used to secure the part. Case 806(ICePAK) and Case 388A (TO-258AA) (see Figure 7.11) areexamples of parts in this category. The second categorycontains parts which have a plastic overmold covering themetal mounting base. The Fully Isolated, Case 221C,

Table 7.3 Performance of Silicon Rubber InsulatorsTested per MIL-I-49456

Measured Thermal Resistance ( °C/W)

Material Thermalloy Data (1) Berquist Data (2)

Bare Joint greased 0 033 0 008Bare Joint, greasedBeO greased

0.0330 082

0.008—BeO, greased

Cho-Therm 16170.0820 233

——Cho-Therm, 1617

Q Pad (non-insulated)0.233

——

0 009Q Pad (non-insulated)Sil Pad K 10

—0 263

0.0090 200Sil-Pad, K-10

Thermasil III0.2630 267

0.200Thermasil IIIMica greased

0.2670 329

—0 400Mica, greased

Sil Pad 10000.3290 400

0.4000 300Sil-Pad 1000

Cho therm 16740.4000 433

0.300Cho-therm 1674Th il II

0.4330 500

—Thermasil IISil P d 400

0.5000 533

—0 440Sil-Pad 400

Sil P d K 40.5330 583

0.4400 440Sil-Pad K-4 0.583 0.440

1. From Thermalloy EIR 87-1030 2. From Berquist Data Sheet


illustrated in figure 7.13, is an example of parts in the secondcategory.

Parts in the first category — those with an exposed metalflange or tab — are mounted the same as their non-insulatedcounterparts. However, as with any mounting system wherepressure is bearing on plastic, the overmolded type shouldbe used with a conical compression washer, described laterin this note.

FASTENER AND HARDWARE CHARACTERISTICSCharacteristics of fasteners, associated hardware, and the

tools to secure them determine their suitability for use inmounting the various packages. Since many problems havearisen because of improper choices, the basic characteristicsof several types of hardware are discussed next.

Compression HardwareNormal split ring lock washers are not the best choice for

mounting power semiconductors. A typical #6 washerflattens at about 50 pounds, whereas 150 to 300 pounds isneeded for good heat transfer at the interface. A very usefulpiece of hardware is the conical, sometimes called aBelleville washer, compression washer. As shown in Figure7.5, it has the ability to maintain a fairly constant pressureover a wide range of its physical deflection — generally 20%to 80%. When installing, the assembler applies torque untilthe washer depresses to half its original height. (Tests shouldbe run prior to setting up the assembly line to determine theproper torque for the fastener used to achieve 50% deflec-tion.) The washer will absorb any cyclic expansion of thepackage, insulating washer or other materials caused bytemperature changes. Conical washers are the key tosuccessful mounting of devices requiring strict control of themounting force or when plastic hardware is used in themounting scheme. They are used with the large facecontacting the packages. A new variation of the conicalwasher includes it as part of a nut assembly. Called a SyncNut, the patented device can be soldered to a PC board andthe semiconductor mounted with 6-32 machine screw.(4)

PRES

SUR

E O

N P

ACKA

GE

(LB-

F) 240

10080604000

40

80

120

160

200

20

280

DEFLECTION OF WASHER DURING MOUNTING (%)

Figure 7.5. Characteristics of the Conical CompressionWashers Designed for Use with Plastic Body Mounted

Semiconductors

(4) ITW Shakeproof, St. Charles Road, Elgin, IL 60120.

ClipsFast assembly is accomplished with clips. When only a few

watts are being dissipated, the small board mounted orfree-standing heat dissipators with an integral clip, offered byseveral manufacturers, result in a low cost assembly. Whenhigher power is being handled, a separate clip may be usedwith larger heatsinks. In order to provide proper pressure, theclip must be specially designed for a particular heatsinkthickness and semiconductor package.

Clips are especially popular with plastic packages such asthe TO-220 and TO-126. In addition to fast assembly, the clipprovides lower interface thermal resistance than otherassembly methods when it is designed for proper pressure tobear on the top of the plastic over the die. The TO-220package usually is lifted up under the die location whenmounted with a single fastener through the hole in the tabbecause of the high pressure at one end.

Machine ScrewsMachine screws, conical washers, and nuts (or syncnuts)

can form a trouble-free fastener system for all types ofpackages which have mounting holes. However, propertorque is necessary. Torque ratings apply when dry; there-fore, care must be exercised when using thermal grease toprevent it from getting on the threads as inconsistent torquereadings result. Machine screw heads should not directlycontact the surface of plastic packages types as the screwheads are not sufficiently flat to provide properly distributedforce. Without a washer, cracking of the plastic case mayoccur.

Self-Tapping ScrewsUnder carefully controlled conditions, sheet-metal screws

are acceptable. However, during the tapping process with astandard screw, a volcano-like protrusion will develop in themetal being threaded; an unacceptable surface that couldincrease the thermal resistance may result. When standardsheet metal screws are used, they must be used in aclearance hole to engage a speednut. If a self tappingprocess is desired, the screw type must be used whichroll-forms machine screw threads.

RivetsRivets are not a recommended fastener for any of the

plastic packages. When a rugged metal flange-mountpackage is being mounted directly to a heatsink, rivets canbe used provided press-riveting is used. Crimping force mustbe applied slowly and evenly. Pop-riveting should never beused because the high crimping force could cause deforma-tion of most semiconductor packages. Aluminum rivets aremuch preferred over steel because less pressure is requiredto set the rivet and thermal conductivity is improved.

The hollow rivet, or eyelet, is preferred over solid rivets. Anadjustable, regulated pressure press is used such that agradually increasing pressure is used to pan the eyelet. Useof sharp blows could damage the semiconductor die.

SolderUntil the advent of the surface mount assembly technique,

solder was not considered a suitable fastener for powersemiconductors. However, user demand has led to thedevelopment of new packages for this application. Accept-able soldering methods include conventional beltfurnace,



irons, vapor-phase reflow, and infrared reflow. It is importantthat the semiconductor temperature not exceed the specifiedmaximum (usually 260°C) or the die bond to the case couldbe damaged. A degraded die bond has excessive thermalresistance which often leads to a failure under power cycling.

AdhesivesAdhesives are available which have coefficients of expan-

sion compatible with copper and aluminum.(5) Highly con-ductive types are available; a 10 mil layer has approximately0.3°C/W interface thermal resistance. Different types areoffered: high strength types for non-field-serviceable systemsor low strength types for field-serviceable systems. Adhesivebonding is attractive when case mounted parts are used inwave soldering assembly because thermal greases are notcompatible with the conformal coatings used and thegreases foul the solder process.

Plastic HardwareMost plastic materials will flow, but differ widely in this

characteristic. When plastic materials form parts of thefastening system, compression washers are highly valuableto assure that the assembly will not loosen with time andtemperature cycling. As previously discussed, loss of contactpressure will increase interface thermal resistance.

FASTENING TECHNIQUES

Each of the various classes of packages in use requiresdifferent fastening techniques. Details pertaining to each typeare discussed in following sections. Some general consider-ations follow.

To prevent galvanic action from occurring when devicesare used on aluminum heatsinks in a corrosive atmosphere,many devices are nickel- or gold-plated. Consequently,precautions must be taken not to mar the finish.

Another factor to be considered is that when a copperbased part is rigidly mounted to an aluminium heatsink, abimetallic system results which will bend with temperaturechanges. Not only is the thermal coefficient of expansiondifferent for copper and aluminium, but the temperaturegradient through each metal also causes each component tobend. If bending is excessive and the package is mountedby two or more screws the semiconductor chip could bedamaged. Bending can be minimized by:

1. Mounting the component parallel to the heatsink fins toprovide increased stiffness.

2. Allowing the heatsink holes to be a bit oversized so thatsome slip between surfaces can occur as temperaturechanges.

3. Using a highly conductive thermal grease or mountingpad between the heatsink and semicondutor to minimizethe temperature gradient and allow for movement.

Stud MountParts which fall into the stud-mount classification are

shown in Figure 7.6. Mounting errors with non-insulatedstud-mounted parts are generally confined to application of

(5) Robert Batson, Elliot Fraunglass and James P. Moran, “HeatDissipation Through Thermalloy Conductive Adhesives, ”EMTAS’83. Conference, February 1–3, Phoenix, AZ; Society ofManufacturing Engineers, One SME Drive, P.O. Box 930,Dearborn, MI 48128.

Figure 7.6 A Variety of Stud-Mount Parts

CASE 144B-05(.380″ STUD)

6c. RF Stripline Opposed Emitter (SOE) Series

CASE 145A-09(.380″ STUD)

CASE 145A-10(.500″ STUD)

CASE 244-04(.280″ STUD)

CASE 305-01(.204″ STUD)

CASE 332-04(.380″ STUD)

6a. Standard Non-Isolated Types 6b. Isolated Type

CASE 42A(DO-5)

CASE 56-03DO-203AA

(DO-4)

CASE 245(DO-4)

CASE 257DO-203AB

(DO-5)

CASE 263-04

CASE 311-02


excessive torque or tapping the stud into a threaded heatsinkhole. Both these practices may cause a warpage of the hexbase which may crack the semiconductor die. The onlyrecommended fastening method is to use a nut and washer;the details are shown in Figure 7.7.

Insulated electrode packages on a stud mount baserequire less hardware. They are mounted the same as theirnon-insulated counterparts, but care must be exercised toavoid applying a shear or tension stress to the insulationlayer, usually a berrylium oxide (BeO) ceramic. This require-ment dictates that the leads must be attached to the circuitwith flexible wire. In addition, the stud hex should be used tohold the part while the nut is torqued.

R.F. transistors in the stud-mount stripline opposed emitter(SOE) package impose some additional constraints becauseof the unique construction of the package. Special tech-niques to make connections to the stripline leads and tomount the part so no tension or shear forces are applied toany ceramic — metal interface are discussed in the sectionentitled “Connecting and Handling Terminals.”

CHASSIS

INSULATOR

TEFLON BUSHING

INSULATOR

Figure 7.7. Isolating Hardware Used for a Non-IsolatedStud-Mount Package

CONICAL WASHER

HEX NUT

SOLDER TERMINAL

FLAT STEEL WASHER

Press FitFor most applications, the press-fit case should be

mounted according to the instructions shown in Figure 7.8. Aspecial fixture meeting necessary requirements must beused.

The hole edge must be chamfered as shown to preventshearing off the knurled edge of the case during press-in. Thepressing force should be applied evenly on the shoulder ring toavoid tilting or canting of the case in the hole during the pressingoperation. Also, the use of a thermal joint compound will be ofconsiderable aid. The pressing force will vary from 250 to 1000pounds, depending upon the heatsink material. Recommendedhardnesses are: copper-less than 50 on the Rockwell F scale;aluminum-less than 65 on the Brinell scale. A heatsink as thin as1/8″ may be used, but the interface thermal resistance willincrease in direct proportion to the contact area. A thin chasisrequires the addition of a backup plate.

0.0499 ± 0.001 DIA.

Heat Sink Mounting

CHAMFER

.01 NOM.

HEATSINK

.01 NOM.

.24

SHOULDER RING

Figure 7.8. Press-Fit Package

RIVET

INTIMATECONTACT AREA

Thin-Chassis Mounting

COMPLETEKNURL CONTACT

AREA

THIN CHASSIS

ADDITIONALHEATSINK PLATE

.501

.505 DIA.

Flange MountA large variety of parts fit into the flange mount category as

shown in Figure 7.9. Few known mounting difficulties existwith the smaller flange mount packages, such as the TO-204(TO-3). The rugged base and distance between die andmounting holes combine to make it extremely difficult tocause any warpage unless mounted on a surface which isbadly bowed or unless one side is tightened excessivelybefore the other screw is started. It is therefore good practiceto alternate tightening of the screws so that pressure isevenly applied. After the screws are finger-tight the hardwareshould be torqued to its final specification in at least twosequential steps. A typical mounting installation for a popularflange type part is as shown in Figure 7.10. Machine screws(preferred) self-tapping screws, eyelets, or rivets may beused to secure the package using guidelines in the previoussection. “Fastener and Hardware Characteristics.”



Figure 7.9. A Large Array of Parts Fit into the Flange-Mount Classification

(a). TO-3 Variations (b). Plastic Power Tap

CASE 1, 11TO-204AA

(TO-3)CASE 383-01

CASE 357C-03

CASE 211-07 CASE 211-11 CASE 215-02

(d). RF Stripline Isolated Output Opposed Emitter(SOE) Series

CASE 316-01 CASE 319-07(CS-12)

CASE 328A-03

CASE 333-04 CASE 333A-02(MAAC PAC)

CASE 336-03

CASE 337-02 CASE 368-02(HOG PAC)

CASE 744A-01

Some packages specify a tightening procedure. Forexample, with the Power Tap package, Figure 7.9(b), finaltorque should be applied first to the center position.

The RF power modules (MHW series) are more sensitiveto the flatness of the heatsink than other packages becausea ceramic (BeO) substrate is attached to a relatively thin,fairly long, flange. The maximum allowable flange bending toavoid mechanical damage has been determined and pres-ented in detail in EB107 “Mounting Considerations forMotorola RF Power Modules.” Many of the parts can handlea combined heatsink and flange deviation from flat of 7 to 8mils which is commonly available. Others must be held to 1.5mils, which requires that the heatsink have nearly perfectflatness.

Specific mounting recommendations are critical to RFdevices in isolated packages because of the internal ceramicsubstrate. The large area Case 368-02 (HOG PAC) will beused to illustrate problem areas. It is more sensitive to propermounting techniques that most other RF power devices.

Although the data sheets contain information on recom-mended mounting procedures, experience indicates thatthey are often ignored. For example, the recommendedmaximum torque on the 4-40 mounting screws is 5 in/lbs.Spring and flat washers are recommended. Over torquing isa common problem. In some parts returned for failureanalysis, indentions up to 10 mils deep in the mounting screwareas have been observed.

Calculations indicate that the length of the flange in-creases in excess of two mils with a temperature change of75°C. In such cases, if the mounting screw torque isexcessive, the flange is prevented from expanding in length,instead it bends upwards in the mid-section, cracking theBeO and the die. A similar result can also occur during theinitial mounting of the device if an excessive amount ofthermal compound is applied. With sufficient torque, thethermal compound will squeeze out of the mounting holeareas, but will remain under the center of the flange,


INSULATOR

POWERTRANSISTOR

HEATSINK

INSULATINGBUSHING

SOCKET

NO.6 SHEET METAL SCREWS

Figure 7.10. Hardware Used for a TO-204AA (TO-3)Flange Mount Part

deforming it. Deformations of 2–3 mils have been measuredbetween the center and the ends under such conditions(enough to crack internal ceramic).

Another problem arises because the thickness of theflange changes with temperature. For the 75°C temperatureexcursion mentioned, the increased amount is around 0.25mils which results in further tightening of the mountingscrews, thus increasing the effective torque from the initialvalue. With a decrease in temperature, the opposite effectoccurs. Therefore thermal cycling not only causes risk ofstructural damage but often causes the assembly to loosenwhich raises the interface resistance. Use of compressionhardware can eliminate this problem.

Tab MountThe tab mount class is composed of a wide array of

packages as illustrated in Figure 7.11. Mounting consider-ations for all varieties are similar to that for the popularTO-220 package, whose suggested mounting arrangementsand hardware are shown in Figure 7.12. The rectangularwasher shown in Figure 7.12(a) is used to minimize distortionof the mounting flange; excessive distortion could causedamage to the semiconductor chip. Use of the washer is onlyimportant when the size of the mounting hole exceeds 0.140

inch (6–32 clearance). Larger holes are needed to accom-modate the lower insulating bushing when the screw iselectrically connected to the case; however, the holes shouldnot be larger than necessary to provide hardware clearanceand should never exceed a diameter of 0.250 inch. Flangedistortion is also possible if excessive torque is used duringmounting. A maximum torque of 8 inch-pounds is suggestedwhen using a 6–32 screw.

Care should be exercised to assure that the tool used todrive the mounting screw never comes in contact with theplastic body during the driving operation. Such contact canresult in damage to the plastic body and internal deviceconnections. To minimize this problem, Motorola TO-220packages have a chamfer on one end. TO-220 packages ofother manufacturers may need a spacer or combinationspacer and isolation bushing to raise the screw head abovethe top surface of the plastic.

The popular TO-220 Package and others of similar con-struction lift off the mounting surface as pressure is appliedto one end. (See Appendix B, Figure B1.) To counter thistendency, at least one hardware manufacturer offers a hardplastic cantilever beam which applies more even pressure onthe tab.(6) In addition, it separates the mounting screw from

(6) Catalog, Edition 18, Richco Plastic Company, 5825 N. Tripp Ave.,Chicago, IL 60546.

Figure 7.11. Several Types of Tab-Mount Parts

CASE 221A-04(TO-220AB)

221B-03(TO-220AC)

CASE 314B(5 PIN TO-220)

CASE 314D CASE 339

CASE 340-02(TO-218)

CASE 387-01(TO-254AA)

CASE 388A-01(TO-258AA)

CASE 806-05(ICePAK)



(1) Used with thin chassis and/or large hole.(2) Used when isolation is required.(3) Required when nylon bushing is used.

(a). Preferred Arrangementfor Isolated or Non-IsolatedMounting. Screw is atSemiconductor CasePotential. 6-32 Hardware isUsed.

Use Parts ListedBelow

(b). Alternate Arrangementfor Isolated Mounting whenScrew must be at Heat SinkPotential. 4-40 Hardware isused.

Use Parts Listed below.

6-32 HEX NUT 4-40 HEX NUT

(4) CONICAL WASHER

COMPRESSION WASHER

(3) FLAT WASHER

(2) BUSHING

HEATSINK

HEATSINK

RECTANGULARINSULATOR

(2) RECTANGULARINSULATOR

SEMICONDUCTOR(CASE 221,221A)

(1) RECTANGULAR STEELWASHER

SEMICONDUCTOR(CASE 221, 221A)

INSULATING BUSHING

FLAT WASHER

6-32 HEXHEAD SCREW

4-40 PAN OR HEX HEAD SCREW

Figure 7.12. Mounting Arrangements for Tab Mount TO-220

the metal tab. Tab mount parts may also be effectivelymounted with clips as shown in Figure 7.51(c). To obtain highpressure without cracking the case, a pressure spreader barshould be used under the clip. Interface thermal resistancewith the cantilever beam or clips can be lower than withscrew mounting.

The ICePAK (Case 806-05) is basically an elongatedTO-220 package with isolated chips. The mounting precau-tions for the TO-220 consequently apply. In addition, sincetwo mounting screws are required, the alternate tighteningprocedure described for the flange mount package should beused.

In situations where a tab mount package is making directcontact with the heatsink, an eyelet may be used, providedsharp blows or impact shock is avoided.

Plastic Body MountThe Thermopad and fully isolated plastic power packages

shown in Figure 7.13 are typical of packages in this group.They have been designed to feature minimum size with nocompromise in thermal resistance. For the Thermopad (Case77) parts this is accomplished by die-bounding the siliconchip on one side of a thin copper sheet; the opposite side isexposed as a mounting surface. The copper sheet has a holefor mounting; plastic is molded enveloping the chip butleaving the mounting hole open. The low thermal resistanceof this construction is obtained at the expense of arequirement that strict attention be paid to the mountingprocedure.

The fully isolated power package (Case 221C-02) issimilar to a TO-220 except that the tab is encased in plastic.Because the mounting force is applied to plastic, themounting procedure differs from a standard TO-220 and issimilar to that of the Thermopad.

Several types of fasteners may be used to secure thesepackages; machine screws, eyelets, or clips are preferred.With screws or eyelets, a conical washer should be usedwhich applies the proper force to the package over a fairlywide range of deflection and distributes the force over a fairlylarge surface area. Screws should not be tightened with anytype of air-driven torque gun or equipment which may causehigh impact. Characteristics of a suitable conical washer isshown in Figure 7.5.

Figure 7.14 shows details of mounting Case 77 devices.Clip mounting is fast and requires minimum hardware,however, the clip must be properly chosen to insure that theproper mounting force is applied. When electrical isolation isrequired with screw mounting, a bushing inside the mountinghole will insure that the screw threads do not contact themetal base.

The fully isolated power package, (Case 221C, 221D and340B) permits the mounting procedure to be greatly simpli-fied over that of a standard TO-220. As shown in Figure7.15(c), one properly chosen clip, inserted into two slottedholes in the heatsink, is all the hardware needed. Eventhough clip pressure is much lower than obtained with ascrew, the thermal resistance is about the same for eithermethod. This occurs because the clip bears directly on top ofthe die and holds the package flat while the screw causes thepackage to lift up somewhat under the die. (See Figure B1 ofAppendix B.) The interface should consist of a layer ofthermal grease or a highly conductive thermal pad. Ofcourse, screw mounting shown in Figure 7.15(b) may also beused but a conical compression washer should be included.Both methods afford a major reduction in hardware ascompared to the conventional mounting method with aTO-220 package which is shown in Figure 7.15(a).

Figure 7.13. Plastic Body-Mount Packages

CASE 77(TO-225AA/

TO-126)(THERMOPAD)

CASE 221C-02(Fully Isolated)

CASE 221D-02(Fully Isolated)

CASE 340B-03(Fully Isolated)


Figure 7.14. Recommended Mounting Arrangementsfor TO-225AA (TO-126) Thermopad Packages

(c). Clips

(b). Eyelet Mounting

COMPRESSION WASHER

INSULATING WASHER(OPTIONAL)

EYELET

(a). Machine Screw Mounting

MACHINE OR SPEEDNUT

INSULATING WASHER(OPTIONAL)

HEAT SINKSURFACE

COMPRESSION WASHER

MACHINE SCREW ORSHEET METAL SCREW

THERMOPAD PACKAGE

Surface MountAlthough many of the tab mount parts have been surface

mounted, special small footprint packages for mountingpower semiconductors using surface mount assembly tech-niques have been developed. The DPAK, shown in Figure16, for example, will accommodate a die up to 112 mils x 112mils, and has a typical thermal resistance around 2°C/Wjunction to case. The thermal resistance values of the solder

INSULATING BUSHING

HEATSINK

(c). Clip-Mounted Fully Isolated

Figure 7.15. Mounting Arrangements for the Fully Iso-lated Power Package as Compared to a Conventional TO-220

CLIP

COMPRESSION WASHER

NUT

(b). Screw-Mounted Fully Isolated

HEATSINK

PLAIN WASHER

6-32 SCREW

(a). Screw-Mounted TO-220

INSULATOR

HEATSINK

COMPRESSION WASHER

NUT

PLAIN WASHER

4-40 SCREW



interface is well under 1°C/W. The printed circuit board alsoserves as the heatsink.

Standard Glass-Epoxy 2-ounce boards do not make verygood heatsinks because the thin foil has a high thermalresistance. As Figure 7.17 shows, thermal resistance assym-totes to about 20°C/W at 10 square inches of board area,although a point of diminishing returns occurs at about 3square inches.

Boards are offered that have thick aluminium or coppersubstrates. A dielectric coating designed for low thermalresistance is overlayed with one or two ounce copper foil forthe preparation of printed conductor traces. Tests run onsuch a product indicate that case to substrate thermalresistance is in the vicinity of 1°C/W, exact values dependingupon board type.(7) The substrate may be an effectiveheatsink itself, or it can be attached to a conventional finnedheatsink for improved performance.

Since DPAK and other surface mount packages aredesigned to be compatible with surface mount assemblytechniques, no special precautions are needed other than toinsure that maximum temperature/time profiles are notexceeded.

R

,

THER

MAL

RES

ISTA

NC

E (

C/W

)θJ

A°

10

Figure 7.17. Effect of Footprint Area on ThermalResistance of DPAK Mounted on a Glass-Epoxy Board

PCB PAD AREA (IN2)

20

20

40

60

80

100

4 6

PCB, 1/16 IN THICKG10/FR4, 2 OUNCEEPOXY GLASS BOARD,DOUBLE SIDED

Figure 7.16. Surface Mount D-PAK Parts

CASE 369-06 CASE 369A-12

FREE AIR AND SOCKET MOUNTING

In applications where average power dissipation is on theorder of a watt or so, most power semiconductors may bemounted with little or no heatsinking. The leads of the various

(7) Herb Fick, “Thermal Management of Surface Mount PowerDevices,” Power conversion and Intelligent Motion, August 1987.

metal power packages are not designed to support thepackages; their cases must be firmly supported to avoid thepossibility of cracked seals around the leads. Many plasticpackages may be supported by their leads in applicationswhere high shock and vibration stresses are not encounteredand where no heatsink is used. The leads should be as shortas possible to increase vibration resistance and reducethermal resistance. As a general practice however, it is betterto support the package. A plastic support for the TO-220Package and other similar types is offered by heatsinkaccessory vendors.

In many situations, because its leads are fairly heavy, theCASE 77 (TO-225AA)(TO-127) package has supported asmall heatsink; however, no definitive data is available. Whenusing a small heatsink, it is good practice to have the sinkrigidly mounted such that the sink or the board is providingtotal support for the semiconductor. Two possible arrange-ments are shown in Figure 7.18. The arrangement of part (a)could be used with any plastic package, but the scheme of

(a). Simple Plate, Vertically Mounted

CIRCUIT BOARD

HEATSINK

HEATSINK

Figure 7.18. Methods of Using Small Heatsinks WithPlastic Semiconductor Packages

TO-225AACASE 77

HEATSINK SURFACE

TWIST LOCKSOR

SOLDERABLELEGS

TO-225AACASE 77

HEATSINKSURFACE

CIRCUIT BOARD

(b). Commercial Sink, Horizontally Mounted


part (b) is more practical with Case 77 Thermopad devices.With the other package types, mounting the transistor on topof the heatsink is more practical.

In certain situations, in particular where semiconductortesting is required or prototypes are being developed,sockets are desirable. Manufacturers have provided socketsfor many of the packages available from Motorola. The useris urged to consult manufacturers’ catalogs for specificdetails. Sockets with Kelvin connections are necessary toobtain accurate voltage readings across semiconductorterminals.

CONNECTING AND HANDLING TERMINALS

Pins, leads, and tabs must be handled and connectedproperly to avoid undue mechanical stress which couldcause semiconductor failure. Change in mechanical dimen-sions as a result of thermal cycling over operating tempera-ture extremes must be considered. Standard metal, plastic,and RF stripline packages each have some special consider-ations.

Metal PackagesThe pins and lugs of metal packaged devices using glass

to metal seals are not designed to handle any significantbending or stress. If abused, the seals could crack. Wiresmay be attached using sockets, crimp connectors or solder,provided the data sheet ratings are observed. When wiresare attached directly to the pins, flexible or braided leads arerecommended in order to provide strain relief.

Plastic PackagesThe leads of the plastic packages are somewhat flexible

and can be reshaped although this is not a recommendedprocedure. In many cases, a heatsink can be chosen whichmakes lead-bending unnecessary. Numerous-lead and tab-forming options are available from Motorola on large quantityorders. Preformed leads remove the users risk of devicedamage caused by bending.

If, however, lead-bending is done by the user, severalbasic considerations should be observed. When bending thelead, support must be placed between the point of bendingand the package. For forming small quantities of units, a pairof pliers may be used to clamp the leads at the case, whilebending with the fingers or another pair of pliers. Forproduction quantities, a suitable fixture should be made.

The following rules should be observed to avoid damageto the package.

1. A leadbend radius greater than 1/16 inch is advisable forTO-225AA (CASE 77) and 1/32 inch for TO-220.

2. No twisting of leads should be done at the case. 3. No axial motion of the lead should be allowed with re-

spect to the case.The leads of plastic packages are not designed to

withstand excessive axial pull. Force in this direction greaterthan 4 pounds may result in permanent damage to thedevice. If the mounting arrangement imposes axial stress onthe leads, a condition which may be caused by thermalcycling, some method of strain relief should be devised.

When wires are used for connections, care should beexercised to assure that movement of the wire does notcause movement of the lead at the lead-to-plastic junctions.Highly flexible or braided wires are good for providing strainrelief.

Wire-wrapping of the leads is permissible, provided thatthe lead is restrained between the plastic case and the pointof the wrapping. The leads may be soldered; the maximum

METAL HEATSINK SURFACE

SIDE VIEWCROSS SECTION

MOUNTINGHOLES

COPPERCONDUCTORS

HEATSINK

SURFACE

ALIGNMENTSPACER

H

METALHEATSINK

H

TOP VIEWCIRCUITBOARD

METALHEATSINKSURFACE

MOUNTINGHOLES

SIDE VIEWCROSS SECTION

“D” FLAT

(b). Typical Stud Type SOE TransistorMounting Method

PRINTEDCIRCUITBOARD

TOPVIEW

PRINTEDCONDUCTOR

PATTERN

“D” FLAT

WRENCHFLAT

BeODISC

SURFACE S

METALLICPATTERN

CERAMICCAP

LEADS

(a). Component Parts of a Stud Mount StriplinePackage. Flange Mounted Packages

are Similarly Constructed

TRANSISTORCHIP

(c). Flange Type SOE Transistor Mounting Method

Figure 7.19. Mounting Details for SOE Transistors



soldering temperature, however, must not exceed 260°C andmust be applied for not more than 5 seconds at a distancegreater than 1/8 inch from the plastic case.

Stripline PackagesThe leads of stripline packages normally are soldered into

a board while the case is recessed to contact a heatsink asshown in Figure 7.19. The following rules should beobserved:

1. The device should never be mounted in such a manneras to place ceramic-to-metal joints in tension.

2. The device should never be mounted in such a manneras to apply force on the strip leads in a vertical directiontowards the cap.

3. When the device is mounted in a printed circuit boardwith the copper stud and BeO portion of the headerpassing through a hole in the circuit boards, adequateclearance must be provided for the BeO to prevent shearforces from being applied to the leads.

4. Some clearance must be allowed between the leads andthe circuit board when the device is secured to the heat-sink.

5. The device should be properly secured into the heat-sinks before its leads are attached into the circuit.

6. The leads on stud type devices must not be used to pre-vent device rotation during stud torque application. Awrench flat is provided for this purpose.

Figure 7.19(b) shows a cross-section of a printed circuitboard and heatsink assembly for mounting a stud type strip-line device. H is the distance from the top surface of theprinted circuit board to the D-flat heatsink surface. If H is lessthan the minimum distance from the bottom of the leadmaterial to the mounting surface of the package, there is nopossibility of tensile forces in the copper stud — BeO ceramicjoint. If, however, H is greater than the package dimension,considerable force is applied to the cap to BeO joint and theBeO to stud joint. Two occurrences are possible at this point.The first is a cap joint failure when the structure is heated, asmight occur during the lead-soldering operation; while thesecond is BeO to stud failure if the force generated is highenough. Lack of contact between the device and the heat-sink surface will occur as the differences between H and thepackage dimension become larger, this may result in devicefailure as power is applied.

Figure 7.19(c) shows a typical mounting technique forflange-type stripline transistors. Again, H is defined as thedistance from the top of the printed circuit board to theheatsink surface. If distance H is less than the minimumdistance from the bottom of transistor lead to the bottomsurface of the flange, tensile forces at the various joints in thepackage are avoided. However, if distance H exceeds thepackage dimension, problems similar to those discussed forthe stud type devices can occur.

CLEANING CIRCUIT BOARDS

It is important that any solvents or cleaning chemicals usedin the process of degreasing or flux removal do not affect thereliability of the devices. Alcohol and unchlorinated Freonsolvents are generally satisfactory for use with plastic

devices, since they do not damage the package. Hydrocar-bons such as gasoline and chlorinated Freon may cause theencapsulant to swell, possibly damaging the transistor die.

When using an ultrasonic cleaner for cleaning circuitboards, care should be taken with regard to ultrasonic energyand time of application. This is particularly true if anypackages are free-standing without support.

THERMAL SYSTEM EVALUATION

Assuming that a suitable method of mounting the semicon-ductor without incurring damage has been achieved, it isimportant to ascertain whether the junction temperature iswithin bounds.

In applications where the power dissipated in the semicon-ductor consists of pulses at a low duty cycle, the instanta-neous or peak junction temperature, not averagetemperature, may be the limiting condition. In this case, usemust be made of transient thermal resistance data. For a fullexplanation of its use, see Motorola Application Note,AN569.

Other applications, notably RF power amplifiers orswitches driving highly reactive loads, may create severecurrent crowding conditions which render the traditionalconcepts of thermal resistance or transient thermal imped-ance invalid. In this case, transistor safe operating area,thyristor di/dt limits, or equivalent ratings as applicable, mustbe observed.

Fortunately, in many applications, a calculation of theaverage junction temperature is sufficient. It is based on theconcept of thermal resistance between the junction and atemperature reference point on the case. (See Appendix A.)A fine wire thermocouple should be used, such as #36 AWG,to determine case temperature. Average operating junctiontemperature can be computed from the following equation:

TJ TCRJC PD

where TJ = junction temperature (°C)TC = case temperature (°C)RθJC = thermal resistance junction-

to-case as specified on thedata sheet (°C/W)

PD = power dissipated in the device (W)The difficulty in applying the equation often lies in

determining the power dissipation. Two commonly usedempirical methods are graphical integration and substitution.

Graphical IntegrationGraphical integration may be performed by taking oscillo-

scope pictures of a complete cycle of the voltage and currentwaveforms, using a limit device. The pictures should betaken with the temperature stabilized. Corresponding pointsare then read from each photo at a suitable number of timeincrements. Each pair of voltage and current values aremultiplied together to give instantaneous values of power.The results are plotted on linear graph paper, the number ofsquares within the curve counted, and the total divided by thenumber of squares along the time axis. The quotient is theaverage power dissipation. Oscilloscopes are available toperform these measurements and make the necessarycalculations.


SubstitutionThis method is based upon substituting an easily measur-

able, smooth dc source for a complex waveform. A switchingarrangement is provided which allows operating the load withthe device under test, until it stabilizes in temperature. Case

temperature is monitored. By throwing the switch to the “test”position, the device under test is connected to a dc powersupply, while another pole of the switch supplies the normalpower to the load to keep it operating at full power level. Thedc supply is adjusted so that the semiconductor casetemperature remains approximately constant when theswitch is thrown to each position for about 10 seconds. Thedc voltage and current values are multiplied together toobtain average power. It is generally necessary that a Kelvinconnection be used for the device voltage measurement.

APPENDIX ATHERMAL RESISTANCE CONCEPTS

The basic equation for heat transfer under steady-stateconditions is generally written as:

q hAT (1)where q = rate of heat transfer or power

dissipation (PD)h = heat transfer coefficient,A = area involved in heat transfer,∆T = temperature difference between

regions of heat transfer.However, electrical engineers generally find it easier to

work in terms of thermal resistance, defined as the ratio oftemperature to power. From Equation 1, thermal resistance,Rθ, is

R Tq 1hA (2)

The coefficient (h) depends upon the heat transfer mecha-nism used and various factors involved in that particularmechanism.

An analogy between Equation (2) and Ohm’s Law is oftenmade to form models of heat flow. Note that T could bethought of as a voltage thermal resistance corresponds toelectrical resistance (R); and, power (q) is analogous tocurrent (I). This gives rise to a basic thermal resistance modelfor a semiconductor as indicated by Figure A1.

The equivalent electrical circuit may be analyzed by usingKirchoff’s Law and the following equation results:

TJ PD(RJCR

CSRSA) TA(3)

where TJ = junction temperature,PD = power dissipationRθJC = semiconductor thermal resistance

(junction to case),RθCS = interface thermal resistance

(case to heatsink),RθSA = heatsink thermal resistance

(heatsink to ambient),TA = ambient temperature.

The thermal resistance junction to ambient is the sum ofthe individual components. Each component must be mini-mized if the lowest junction temperature is to result.

The value for the interface thermal resistance, RθCS, maybe significant compared to the other thermal-resistanceterms. A proper mounting procedure can minimize RθCS.

The thermal resistance of the heatsink is not absolutelyconstant; its thermal efficiency increases as ambient temper-ature increases and it is also affected by orientation of thesink. The thermal resistance of the semiconductor is alsovariable; it is a function of biasing and temperature. Semicon-ductor thermal resistance specifications are normally atconditions where current density is fairly uniform. In someapplications such as in RF power amplifiers and short-pulseapplications, current density is not uniform and localizedheating in the semiconductor chip will be the controllingfactor in determining power handling ability.

Figure A1. Basic Thermal Resistance Model Showing Thermal to Electrical Analogy for a Semiconductor

SOLDER TERMINAL

FLAT WASHER

NUT

HEATSINK

INSULATORS

DIETC, CASE TEMPERATURE

TJ, JUNCTION TEMPERATURE

TS, HEATSINKTEMPERATURE

TA, AMBIENTTEMPERATURE

RθSA

RθCS

RθJC

REFERENCE TEMPERATURE

PD



APPENDIX BMEASUREMENT OF INTERFACE THERMAL RESISTANCE

Measuring the interface thermal resistance RθCS appearsdeceptively simple. All that’s apparently needed is a thermo-couple on the semiconductor case, a thermocouple on theheatsink, and a means of applying and measuring DC power.However, RθCS is proportional to the amount of contact areabetween the surfaces and consequently is affected bysurface flatness and finish and the amount of pressure on thesurfaces. The fastening method may also be a factor. Inaddition, placement of the thermocouples can have asignificant influence upon the results. Consequently, valuesfor interface thermal resistance presented by differentmanufacturers are not in good agreement. Fastening meth-ods and thermocouple locations are considered in thisAppendix.

When fastening the test package in place with screws,thermal conduction may take place through the screws, forexample, from the flange ear on a TO-3 package directly tothe heatsink. This shunt path yields values which areartificially low for the insulation material and dependent uponscrew head contact area and screw material. MIL-I-49456allows screws to be used in tests for interface thermalresistance probably because it can be argued that this is“application oriented.”

Thermalloy takes pains to insulate all possible shuntconduction paths in order to more accurately evaluateinsulation materials. The Motorola fixture uses an insulatedclamp arrangement to secure the package which also doesnot provide a conduction path.

As described previously, some packages, such as aTO-220, may be mounted with either a screw through the tabor a clip bearing on the plastic body. These two methodsoften yield different values for interface thermal resistance.Another discrepancy can occur if the top of the package isexposed to the ambient air where radiation and convectioncan take place. To avoid this, the package should be coveredwith insulating foam. It has been estimated that a 15 to 20%error in RθCS can be incurred from this source.

Another significant cause for measurement discrepanciesis the placement of the thermocouple to measure the

E.I.A.

THERMALLOYDIE

MOTOROLA

Figure B1. JEDEC TO-220 Package Mounted toHeatsink Showing Various Thermocouple Locations

and Lifting Caused by Pressure at One End

semiconductor case temperature. Consider the TO-220package shown in Figure B1. The mounting pressure at oneend causes the other end — where the die is located — to liftoff the mounting surface slightly. To improve contact,Motorola TO-220 Packages are slightly concave. Use of aspreader bar under the screw lessens the lifting, but some isinevitable with a package of this structure. Three thermocou-ple locations are shown:

a. The Motorola location is directly under the die reachedthrough a hole in the heatsink. The thermocouple is held inplace by a spring which forces the thermocouple into intimatecontact with the bottom of the semi’s case.

b. The JEDEC location is close to the die on the topsurface of the package base reached through a blind holedrilled through the molded body. The thermocouple isswaged in place.

c. The Thermalloy location is on the top portion of the tabbetween the molded body and the mounting screw. Thethermocouple is soldered into position.

Temperatures at the three locations are generally not thesame. Consider the situation depicted in the figure. Becausethe only area of direct contact is around the mounting screw,nearly all the heat travels horizontally along the tab from thedie to the contact area. Consequently, the temperature at theJEDEC location is hotter than at the Thermalloy location andthe Motorola location is even hotter. Since junction-to-sinkthermal resistance must be constant for a given test setup,the calculated junction-to-case thermal resistance valuesdecrease and case-to-sink values increase as the “case”temperature thermocouple readings become warmer. Thusthe choice of reference point for the “case” temperature isquite important.

There are examples where the relationship between thethermocouple temperatures are different from the previoussituation. If a mica washer with grease is installed betweenthe semiconductor package and the heatsink, tightening thescrew will not bow the package; instead, the mica will bedeformed. The primary heat conduction path is from the diethrough the mica to the heatsink. In this case, a smalltemperature drop will exist across the vertical dimension ofthe package mounting base so that the thermocouple at theEIA location will be the hottest. The thermocouple tempera-ture at the Thermalloy location will be lower but close to thetemperature at the EIA location as the lateral heat flow isgenerally small. The Motorola location will be coolest.

The EIA location is chosen to obtain the highest tempera-ture on the case. It is of significance because power ratingsare supposed to be based on this reference point. Unfortu-nately, the placement of the thermocouple is tedious andleaves the semiconductor in a condition unfit for sale.

The Motorola location is chosen to obtain the highesttemperature of the case at a point where, hopefully, the caseis making contact to the heatsink. Once the special heatsinkto accommodate the thermocouple has been fabricated, thismethod lends itself to production testing and does not markthe device. However, this location is not easily accessible tothe user.


The Thermalloy location is convenient and is often chosenby equipment manufacturers. However, it also blemishes thecase and may yield results differing up to 1°C/W for a TO-220package mounted to a heatsink without thermal grease andno insulator. This error is small when compared to thethermal resistance of heat dissipaters often used with thispackage, since power dissipation is usually a few watts.When compared to the specified junction-to-case values ofsome of the higher power semiconductors becoming avail-able, however, the difference becomes significant and it isimportant that the semiconductor manufacturer and equip-ment manufacturer use the same reference point.

Another EIA method of establishing reference tempera-

tures utilizes a soft copper washer (thermal grease is used)between the semiconductor package and the heatsink. Thewasher is flat to within 1 mil/inch, has a finish better than 63µ-inch, and has an imbedded thermocouple near its center.This reference includes the interface resistance under nearlyideal conditions and is therefore application-oriented. It isalso easy to use but has not become widely accepted.

A good way to improve confidence in the choice of casereference point is to also test for junction-to-case thermalresistance while testing for interface thermal resistance. If thejunction-to-case values remain relatively constant as insula-tors are changed, torque varied, etc., then the case referencepoint is satisfactory.

APPENDIX CSources of Accessories

Insulators

ManufacturerJoint

Compound Adhesives BeO AIO2 Anodize MicaPlastic

FilmSiliconeRubber Heatsinks Clips

Aavid Eng. — — — — — — X X X X

AHAM-TOR — — — — — — — — X —

Asheville-Schoonmaker

— — — — — X — — — —

Astrodynamics X — — — — — — — X —

Delbert Blinn — — X — X X X X X —

IERC X — — — — — — — X —

Staver — — — — — — — — X —

Thermalloy X X X X X X X X X X

Tran-tec X — X X X X — X X —

Wakefield Eng. X X X — X — — X X X

Other sources for silicone rubber pads: Chomerics, Berquist

Suppliers AddressesAavid Engineering, Inc., P.O. Box 400, Laconia, NewHampshire 03247 (603) 528-1478

AHAM-TOR Heatsinks, 27901 Front Street, Rancho,California 92390 (714) 676-4151

Asheville-Schoonmaker, 900 Jefferson Ave., Newport News,VA 23607 (804) 244-7311

Astro Dynamics, Inc., 2 Gill St., Woburn, Massachusetts01801 (617) 935-4944

Berquist, 5300 Edina Industrial Blvd., Minneapolis, Minnesota55435 (612) 835-2322

Chomerics, Inc., 16 Flagstone Drive, Hudson, New Hamp-shire 03051 1-800-633-8800

Delbert Blinn Company, P.O. Box 2007, Pomona, California91769 (714) 623-1257

International Electronic Research Corporation, 135 WestMagnolia Boulevard, Burbank, California 91502

(213) 849-2481

The Staver Company, Inc., 41-51 Saxon Avenue, Bay Shore,Long Island, New York 11706 (516) 666-8000

Thermalloy, Inc., P.O. Box 34829, 2021 West Valley ViewLane, Dallas, Texas 75234 (214) 243-4321

Tran-tec Corporation, P.O. Box 1044, Columbus, Nebraska68601 (402) 564-2748

Wakefield Engineering, Inc., Wakefield, Massachusetts01880 (617) 245-5900



PACKAGE INDEX

PREFACE

When the JEDEC registration system for package outlinesstarted in 1957, numbers were assigned sequentially when-ever manufacturers wished to establish a package as anindustry standard. As minor variations developed from theseindustry standards, either a new, non-related number wasissued by JEDEC or manufacturers would attempt to relatethe part to an industry standard via some appendeddescription.

In an attempt to ease confusion, JEDEC established thepresent system in late 1968 in which new packages areassigned into a category, based on their general physicalappearance. Differences between specific packages in acategory are denoted by suffix letters. The older package

designations were re-registered to the new system as timepermitted.

For example the venerable TO-3 has many variations. Canheights differ and it is available with 30, 40, 50, and 60 milpins, with and without lugs. It is now classified in the TO-204family. The TO-204AA conforms to the original outline for theTO-3 having 40 mil pins while the TO-204AE has 60 mil pins,for example.

The new numbers for the old parts really haven’t caught onvery well. It seems that the DO-4, DO-5 and TO-3 still conveysufficient meaning for general verbal communication.

FlangeFlangeStudFlangeFlangeFlangeStudStudStudFlangeStudStudFlangeStudStudPlasticFlangeStudStudStudStudStudStudStudStudStudPressfit

001003009011011A012036042A04405405605861-0463-0263-03077080086086L144B-05145A-09145A-10145C157160-03167174-04

TO-3TO-3TO-61TO-3TO-3TO-3TO-60DO-5DO-4TO-3DO-4DO-5

TO-64TO-64TO-126TO-66——

TO-232—TO-59—

TO-204AA

TO-210ACTO-204AA——TO-210ABDO-203ABDO-203AA———

TO-208ABTO-2088ABTO-225AATO-213AATO-208TO-298

DO-203TO-210AADO-203

2

—22———2—2

——11

11—1

Notes: 1. Would fit within this family outline ifregistered with JEDEC.2. Not within all JEDEC dimensions.

MotorolaCase

Number

JEDEC Outline

OriginalSystem

RevisedSystem

MountingClassNotes

StudFlangeFlangeFlangeFlangeTabPlasticPlastic

StudStudStudStudStudStudStudStudStudStudStudStudPressfitStudPressfitStudTab

175-03197211-07211-11215-02221221C-02221D-02

235235-03238239244-04245257-01263263-04283289305-01310-02311-02311-02311-02314B-03

—

—

—

—

——

DO-4DO-5—

DO-4—

TO-204AE

TO-220AB

—

TO-208

TO-208TO-208

——TO-208

—TO-209

—

—

IsolatedTO-220

1

1—

———

—1

Isolated

MotorolaCase

Number

JEDEC Outline

OriginalSystem

RevisedSystem

MountingClassNotes

TabFlangeFlangeFlangeStudFlangeFlangeFlangeFlangeTabPlasticPlastic

FlangeFlangeFlangeFlangeInsertionSurfaceFlangeFlangeTabTabFlangeFlangePressfit

314D-03316-01319-06328A-03332-04333-04333A-02336-03337-02340340A-02340B-03

342-01357B-01361-01368-02369-06369A-12373-01383-01387-01388A-01744-02744A-01043-07 DO-21

TO-218AC

TO-251TO-252

TO-254AATO-258AA

DO-208AA

IsolatedTO-218

IsolatedIsolated

Isolated 2Isolated 2

MotorolaCase

Number

JEDEC Outline

OriginalSystem

RevisedSystem

MountingClassNotes


CHAPTER 8RELIABILITY AND QUALITY

USING TRANSIENT THERMAL RESISTANCEDATA IN HIGH POWER PULSED THYRISTORAPPLICATIONS

INTRODUCTIONFor a certain amount of dc power dissipated in a

semiconductor, the junction temperature reaches a valuewhich is determined by the thermal conductivity from thejunction (where the power is dissipated) to the air or heatsink. When the amount of heat generated in the junctionequals the heat conducted away, a steady–state condition isreached and the junction temperature can be calculated bythe simple equation:

TJ = PD RθJR + TR (1a)

where TJ = junction temperatureTR = temperature at reference pointPD = power dissipated in the junctionRθJR = steady–state thermal resistance fromRθJR = junction to the temperature referenceRθJR = point.

Power ratings of semiconductors are based upon steady–state conditions, and are determined from equation (1a)under worst case conditions, i.e.:

PD(max)TJ(max) – TR

RJR(max)(1b)

TJ(max) is normally based upon results of an operating lifetest or serious degradation with temperature of an importantdevice characteristic. TR is usually taken as 25°C, and RθJRcan be measured using various techniques. The referencepoint may be the semiconductor case, a lead, or the ambientair, whichever is most appropriate. Should the referencetemperature in a given application exceed the referencetemperature of the specification, PD must be correspondinglyreduced.

Thermal resistance allows the designer to determinepower dissipation under steady state conditions. Steadystate conditions between junction and case are generallyachieved in one to ten seconds while minutes may berequired for junction to ambient temperature to become

stable. However, for pulses in the microsecond and millisec-ond region, the use of steady–state values will not yield truepower capability because the thermal response of thesystem has not been taken into account.

Note, however, that semiconductors also have pulsepower limitations which may be considerably lower – or evengreater – than the allowable power as deduced from thermalresponse information. For transistors, the second breakdownportion of the pulsed safe operating area defines power limitswhile surge current or power ratings are given for diodes andthyristors. These additional ratings must be used in conjunc-tion with the thermal response to determine power handlingcapability.

To account for thermal capacity, a time dependent factorr(t) is applied to the steady–state thermal resistance.Thermal resistance, at a given time, is called transientthermal resistance and is given by:

RθJR(t) = r(t) RθJR (2)

The mathematical expression for the transient thermalresistance has been determined to be extremely complex.The response is, therefore, plotted from empirical data.Curves, typical of the results obtained, are shown in Figure8.1. These curves show the relative thermal response of thejunction, referenced to the case, resulting from a stepfunction change in power. Observe that during the fast part ofthe response, the slope is 1/2 for most of the devices; (i.e.,

TJ t ), a characteristic generally found true of metalpackage devices. The curves shown are for a variety oftransistor types ranging from rather small devices in TO–5packages to a large 10 ampere transistor in a TO–3package. Observe that the total percentage difference is

about 10:1 in the short pulse ( t ) region. However, thevalues of thermal resistance vary over 20:1. As an aid toestimating response, Appendix C provides data for a numberof packages having different die areas.

Many Motorola data sheets have a graph similar to that ofFigure 8.2. It shows not only the thermal response to a stepchange in power (the D = 0, or single pulse curve) but alsohas other curves which may be used to obtain an effectiver(t) value for a train of repetitive pulses with different dutycycles. The mechanics of using the curves to find TJ at theend of the first pulse in the train, or to find TJ(pk) once steady



state conditions have been achieved, are quite simple andrequire no background in the subject. However, problemswhere the applied power pulses are either not identical inamplitude or width, or the duty cycle is not constant, requirea more thorough understanding of the principles illustrated inthe body of this report.

USE OF TRANSIENT THERMAL RESISTANCE DATAPart of the problem in applying thermal response data

stems from the fact that power pulses are seldom rectangu-lar, therefore to use the r(t) curves, an equivalent rectangularmodel of the actual power pulse must be determined.Methods of doing this are described near the end of this note.

Before considering the subject matter in detail, an examplewill be given to show the use of the thermal response datasheet curves. Figure 8.2 is a representative graph whichapplies to a 2N5632 transistor.

Pulse power PD = 50 WattsDuration t = 5 millisecondsPeriod τp = 20 millisecondsCase temperature, TC = 75°CJunction to case thermal resistance,

RθJC = 1.17°C/W

The temperature is desired, a) at the end of the first pulseb) at the end of a pulse under steady state conditions.

For part (a) use:

TJ = r(5 ms) RθJCPD + TC

The term r(5 ms) is read directly from the graph of Figure8.2 using the D = 0 curve,

∴TJ = 0.49 1.17 50 + 75 = 28.5 + 75 = 103.5

The peak junction temperature rise under steady conditionsis found by:

TJ = r(t, D) RθJC PD + TC

D = t/τp = 5/20 – 0.25. A curve for D= 0.25 is not on thegraph; however, values for this duty cycle can be interpo-lated between the D = 0.2 and D = 0.5 curves. At 5 ms,read r(t) ≈ 0.59.

TJ = 0.59 1.17 50 + 75 = 34.5 + 75 = 109.5°C

Figure 8.1. Thermal Response, Junction to Case, of Various Semiconductor Types For a Step of Input Power

1.0

0.1

0.010.01 0.1 1.0 10 100 1000

D = 0.5

0.2

r (t)

, Tra

nsie

nt T

herm

al R

esis

tanc

e(N

orm

aliz

ed)

0.10.050.02

0.01

10,0003,6003,60016,8008,0003,6003,60014,400

SINGLE PULSE

0.2

0.02

0.3

0.03

0.5

0.05

0.7

0.07

Figure 8.2. Thermal Response Showing the Duty Cycle Family of Curves

0.02 0.2 2.0 20 2000.05 0.5 5.0 50 500

1.0

0.1

0.010.1 1.0 10 100 1000 10,000

t, Time (ms)

r (t)

, Tra

nsie

nt T

herm

al R

esis

tanc

e(N

orm

aliz

ed) 0.2

0.02

0.3

0.03

0.5

0.05

0.7

0.07

0.2 2.0 20 200 20000.5 5.0 50 500 5000

8

1

2

3

4 56

7

TO–61TO–3, TO–66Case 77TO–3, TO–66Case 77TO–5 (Kovar)TO–5 (Steel)TO–5 (Steel)

CASEDIE SIZE(Sq. Mils)

12345678

TO–3 & TO–66 packages are all copperor have a copper slug under die

t, Time (ms)


The average junction temperature increase aboveambient is:

TJ(average) – TC = RθJC PD D

(3)= (1.17) (50) (0.25)= 14.62°C

Note that TJ at the end of any power pulse does not equalthe sum of the average temperature rise (14.62°C in theexample) and that due to one pulse (28.5°C in example),because cooling occurs between the power pulses.

While junction temperature can be easily calculated for asteady pulse train where all pulses are of the same amplitudeand pulse duration as shown in the previous example, asimple equation for arbitrary pulse trains with randomvariations is impossible to derive. However, since the heatingand cooling response of a semiconductor is essentially thesame, the superposition principle may be used to solveproblems which otherwise defy solution.

Using the principle of superposition each power interval isconsidered positive in value, and each cooling intervalnegative, lasting from time of application to infinity. Bymultiplying the thermal resistance at a particular time by themagnitude of the power pulse applied, the magnitude of thejunction temperature change at a particular time can beobtained. The net junction temperature is the algebraic sumof the terms.

The application of the superposition principle is mosteasily seen by studying Figure 8.3.

Figure 8.3(a) illustrates the applied power pulses. Figure8.3(b) shows these pulses transformed into pulses lastingfrom time of application and extending to infinity; at to, P1starts and extends to infinity; at t1, a pulse (– P1) isconsidered to be present and thereby cancels P1 from timet1, and so forth with the other pulses. The junctiontemperature changes due to these imagined positive andnegative pulses are shown in Figure 8.3(c). The actualjunction temperature is the algebraic sum as shown in Figure8.3(d).

Problems may be solved by applying the superpositionprinciple exactly as described; the technique is referred to asMethod 1, the pulse–by–pulse method. It yields satisfactoryresults when the total time of interest is much less than thetime required to achieve steady state conditions, and mustbe used when an uncertainty exists in a random pulse trainas to which pulse will cause the highest temperature.Examples using this method are given in Appendix A underMethod 1.

For uniform trains of repetitive pulses, better answersresult and less work is required by averaging the powerpulses to achieve an average power pulse; the temperatureis calculated at the end of one or two pulses following theaverage power pulse. The essence of this method is shownin Figure 8.6. The duty cycle family of curves shown in Figure8.2 and used to solve the example problem is based on thismethod; however, the curves may only be used for a uniformtrain after steady state conditions are achieved. Method 2 inAppendix A shows equations for calculating the temperatureat the end of the nth or n + 1 pulse in a uniform train. Where aduty cycle family of curves is available, of course, there is noneed to use this method.

Figure 8.3. Application of Superposition Principle

Figure 8.4. Non–Repetitive Pulse Train (Values ShownApply to Example in Appendix)

Figure 8.5. A Train of Equal Repetitive Pulses

(a)Input

Power

(b)PowerPulses

SeparatedInto

Components

(c)TJ

ChangeCaused

byComponents

(d)Composite

TJ

P1

Pin

Pin

–P1

P1

P2

P2

–P2

P3

P3

–P3

P4

P4

–P4

TJ

t0 t1 t2 t3 t4 t5 t6 t7 Time

Time

Time

Time

t0t1 t2 t3 t4 t50

P1

P2

P3

1.0 2.0 3.0 4.0t, Time (ms)

5040

30

20

100

PPe

ak P

ower

(Wat

ts)

PK1

t0 t1 t2 t3 t4 t5 t6 t7 t8 t9

Po

T5

(Conditions for numerical examples

t

Po = 5 Wattst = 5 ms = 20 ms

2



Figure 8.6. Model For a Repetitive Equal Pulse Train

nthpulse

n+1pulse

Po

Pavg

t t

Temperature rise at the end of a pulse in a uniform trainbefore steady state conditions are achieved is handled byMethod 3 (a or b) in the Appendix. The method is basicallythe same as for Method 2, except the average power ismodified by the transient thermal resistance factor at the timewhen the average power pulse ends.

A random pulse train is handled by averaging the pulsesapplied prior to situations suspected of causing high peaktemperatures and then calculating junction temperature atthe end of the nth or n + 1 pulse. Part c of Method 3 shows anexample of solving for temperature at the end of the 3rdpulse in a three pulse burst.

HANDLING NON–RECTANGULAR PULSESThe thermal response curves, Figure 8.1, are based on a

step change of power; the response will not be the same forother waveforms. Thus far in this treatment we haveassumed a rectangular shaped pulse. It would be desirableto be able to obtain the response for any arbitrary waveform,but the mathematical solution is extremely unwieldy. Thesimplest approach is to make a suitable equivalent rectangu-lar model of the actual power pulse and use the giventhermal response curves; the primary rule to observe is thatthe energy of the actual power pulse and the model areequal.

Experience with various modeling techniques has lead tothe following guidelines:

For a pulse that is nearly rectangular, a pulse modelhaving an amplitude equal to the peak of the actual pulse,with the width adjusted so the energies are equal, is aconservative model. (See Figure 8.7(a)).

Sine wave and triangular power pulses model well with theamplitude set at 70% of the peak and the width adjusted to91% and 71%, respectively, of the baseline width (asshown on Figure 8.7(b)).

A power pulse having a sin2 shape models as a triangularwaveform.

Power pulses having more complex waveforms could bemodeled by using two or more pulses as shown in Figure8.7(c).

A point to remember is that a high amplitude pulse of agiven amount of energy will produce a higher rise in junctiontemperature than will a lower amplitude pulse of longerduration having the same energy.

Figure 8.7. Modeling of Power Pulses

T1

P1T1 = A

P1

t t

PP PP

0.7 PP0.7 PP(b)

(c)

(a)

P1 (t1 – t0) + P2 (t2 – t1) = AP1

P2

t0 t1 t2

0.91 t0.71 t

ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ

A

ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ

A

As an example, the case of a transistor used in a dc to acpower converter will be analyzed. The idealized waveformsof collector current, IC, collector to emitter voltage, VCE, andpower dissipation PD, are shown in Figure 8.8.

A model of the power dissipation is shown in Figure 8.8(d).This switching transient of the model is made, as wassuggested, for a triangular pulse.

For example, TJ at the end of the rise, on, and fall times,T1, T2 and T3 respectively, will be found.

Conditions:TO–3 package,

RθJC = 0.5°C/W, IC = 60A, VCE(off) = 60 VTA = 50°Ctf = 80 µs, tr = 20 µsVCE(sat) = 0.3 V @ 60 AFrequency = 2 kHz∴τ = 500 µsPon = (60) (0.3) = 18 WPf = 30 30 = 900 W = Pr

Assume that the response curve in Figure 8.1 for a diearea of 58,000 square mils applies. Also, that the device ismounted on an MS–15 heat sink using Dow CorningDC340 silicone compound with an air flow of 1.0 lb/min


flowing across the heat–sink. (From MS–15 Data Sheet,RθCS = 0.1°C/W and RθSA = 0.55°C/W).

Procedure: Average each pulse over the period usingequation 1–3 (Appendix A, Method 2), i.e.,

Pavg 0.7 Pr 0.71tr Pon ton

0.7 Pf 0.71

tf

(0.7) (900) (0.71)(20)500

(18)(150)500

(0.7) (900) (0.71) 80500

17.9 5.4 71.5

94.8 W

From equation 1–4, Method 2A:

T1 = [Pavg + (0.7 Pr – Pavg) r(t1 – to)] RθJC

At this point it is observed that the thermal responsecurves of Figure 8.1 do not extend below 100 µs. Heattransfer theory for one dimensional heat flow indicates that

the response curve should follow the t law at small times.Using this as a basis for extending the curve, the response at14.2 µs is found to be 0.023.

We then have:

T1 = [94.8 + (630 – 94.8).023] (0.5)

T1 = (107.11)(0.5) = 53.55°C

For T2 we have, by using superposition:

T2 = [Pavg – Pavg r(t2 – to) + 0.7 Pr

T2 = r(t2 – to) – 0.7 Pr r(t2 – t1) + Pon

T2 = r(t2 – t1)] RθJCT2 = [Pavg + (0.7 Pr – Pavg) r(t2 – to) +

T2 = (Pon – 0.7 Pr) r(t2 – t1)] RθJCT2 = [94.8 + (630 – 94.8) r(164 µs) + (18 – 630)

T2 = r(150 µs)] (0.5)

T2 = [94.8 + (535.2)(.079) – (612)(.075)] (0.5)

T2 = [94.8 + 42.3 – 45.9] (0.5)

T2 = (91.2)(0.5) = 45.6°C

Figure 8.8. Idealized Waveforms of I C, VCE and PD in aDC to AC Inverter

(a)

(b)

(c)

(d) PD

Pon

Pf

t0 t1 t2 t3

Time

Time

t(Time)

PD

IC

VCE

Col

lect

or–E

mitt

er V

olta

geC

olle

ctor

Cur

rent

Pow

er D

issi

patio

nt(Time)

Pon

Pr

T1 T2T30.7 Pf0.7 Pf 0.7 Pr

0.7 tr 0.7 tfton

tontofftf tr

For the final point T3 we have:

T3 = [Pavg – Pavg r(t3 – to) + 0.7 Pr

T3 = r(t3 – to) – 0.7 Pr r(t3 – t1) + Pon T3 = r(t3 – t1) – Pon r(t3 – t2)

T3 = + 0.7 Pf r(t3 – t2)] RθJCT3 = [Pavg + (0.7 Pr – Pavg) r(t3 – to) +

T3 = (Pon – 0.7 Pr) r(t3 – t1) + (0.7 Pf – Pon)

T3 = r(t3 – t2)] RθJCT3 = [94.8 + (535.2) r(221 µs) + (–612) r(206.8 µs)

T3 = + (612) r(56.8µs)] (0.5)

T3 = [94.8 + (535.2)(0.09) – (612) (0.086) +

T3 = (612)(0.045)] (0.5)

T3 = [94.8 + 481.7– 52.63 + 27.54] (0.5)

T3 = (117.88)(0.5) = 58.94°C



The junction temperature at the end of the rise, on, and falltimes, TJ1, TJ2, and TJ3, is as follows:

TJ1 = T1 + TA + RθCA PavgRθCA = RθCS = RθSA = 0.1 + 0.55

TJ1 = 53.55 + 50 + (0.65)(94.8) = 165.17°C

TJ2 = T2 + TA + RθCA PavgTJ2 = 45.6 + 50 + (0.65)(94.8)

TJ2 = 157.22°C

TJ3 = T3 + TA + RθCA PavgTJ3 = 58.94 + 50 + (0.65)(94.8)

TJ3 = 170.56°C

TJ(avg) = Pavg (RθJC + RθCS + RθSA) + TATJ(avg) = (94.8)(0.5 + 0.1 + 0.55) + 50

TJ(avg) = (94.8)(1.15) + 50 = 159.02°C

Inspection of the results of the calculations T1, T2, and T3reveal that the term of significance in the equations is theaverage power. Even with the poor switching times there wasa peak junction temperature of 11.5°C above the averagevalue. This is a 7% increase which for most applicationscould be ignored, especially when switching times areconsiderably less. Thus the product of average power andsteady state thermal resistance is the determining factor forjunction temperature rise in this application.

SUMMARYThis report has explained the concept of transient thermal

resistance and its use. Methods using various degrees ofapproximations have been presented to determine thejunction temperature rise of a device. Since the thermalresponse data shown is a step function response, modelingof different wave shapes to an equivalent rectangular pulseof pulses has been discussed.

The concept of a duty cycle family of curves has also beencovered; a concept that can be used to simplify calculation ofthe junction temperature rise under a repetitive pulse train.

APPENDIX A METHODS OF SOLUTIONIn the examples, a type 2N3647 transistor will be used; its

steady state thermal resistance, RθJC, is 35°C/W and itsvalue for r(t) is shown in Figure A1.

Definitions:

P1, P2, P3 ... Pn = power pulses (Watts)

T1, T2, T3 ... Tn = junction to case temperature atT1, T2, T3 ... Tn = end of P1, P2, P3 ... Pn

t0, t1, t2, ... tn = times at which a power pulset0, t1, t2, ... tn = begins or ends

r(tn – tk) = transient thermal resistance factor atr(tn – tk) = end of time interval (tn – tk).

Table 8.1. Several Possible Methods of Solutions

1Junction Temperature Rise Using Pulse–By–Pulse MethodA. Temperature rise at the end of the nth pulse for pulses

with unequal amplitude, spacing, and duration.B. Temperature rise at the end of the nth pulse for pulses

with equal amplitude, spacing, and duration.2Temperature Rise Using Average Power Concept UnderSteady State Conditions For Pulses Of Equal Amplitude,Spacing, And Duration

A. At the end of the nth pulse.B. At the end of the (n + 1) pulse.

3Temperature Rise Using Average Power Concept UnderTransient Conditions.

A. At the end of the nth pulse for pulses of equal amplitude,spacing and duration.

B. At the end of the n + 1 pulse for pulses of equal ampli-tude, spacing and duration.

C. At the end of the nth pulse for pulses of unequal ampli-tude, spacing and duration.

D. At the end of the n + 1 pulse for pulses of unequal ampli-tude, spacing and duration.

METHOD 1A – FINDING TJ AT THE END OF THE NthPULSE IN A TRAIN OF UNEQUAL AMPLITUDE,SPACING, AND DURATION

General Equation:

Tn n

i1Pi [r(t2n–1 – t2i–2) (1–1)

– r(tn–1 – t2i–1)]RθJC

where n is the number of pulses and Pi is the peak value ofthe ith pulse.

To find temperature at the end of the first three pulses,Equation 1–1 becomes:

T1 = P1 r(t1) RθJC (1–1A)

T2 = [P1 r(t3) – P1 r(t3 – t1) (1–1B)

T2 = + P2 r(t3 – t2)] RθJCT3 = [P1 r(t5) – P1 r(t5 – t1) + P2 r(t5 – t2) (1–1C)

T3 = – P2 r(t5 – t3) + P3 r(t5 – t4)] RθJC

Example:

Conditions are shown on Figure 4 as:P1 = 40 WP2 = 20 WP3 = 30 W

t0 = 0t1 = 0.1 mst2 = 0.3 ms

t3 = 1.3 mst4 = 3.3 mst5 = 3.5 ms

Therefore,t1 – t0 = 0.1 mst2 – t1 = 0.2 mst3 – t2 = 1 mst4 – t3 = 2 mst5 – t4 = 0.2 ms

t3 – t1 = 1.2 mst5 – t1 = 3.4 mst5 – t2 = 3.2 mst5 – t3 = 2.2 ms


Procedure:Find r(tn – tk) for preceding time intervals from Figure 8.2,

then substitute into Equations 1–1A, B, and C.

T1 = P1 r(t1) RθJC = 40 0.05 35 = 70°C

T2 = [P1 r(t3) – P1 r(t3 – t1) + P2 r(t3 – t2)] RθJCT2 = [40 (0.175) – 40 (0.170) + 20 (0.155)] 35

T2 = [40 (0.175 – 0.170) + 20 (0.155)] 35

T2 = [0.2 + 3.1] 35 = 115.5°C

T3 = [P1 r(t5) – P1 r(t5 – t1) + P2 r(t5 – t2)

T3 = – P2 r(t5 – t3) + P3 r(t5 – t4)] θJCT3 = [40 (0.28) – 40 (0.277) + 20 (0.275) – 20 (0.227)

T3 = + 30 (0.07)] 35

T3 = [40 (0.28 – 0.277) + 20 (0.275 – 0.227)

T3 = + 30 (0.07)] 35

T3 = [0.12 + 0.96 + 2.1] 35 = 3.18 35 = 111.3°C

Note, by inspecting the last bracketed term in theequations above that very little residual temperature is leftfrom the first pulse at the end of the second and third pulse.Also note that the second pulse gave the highest value ofjunction temperature, a fact not so obvious from inspection ofthe figure. However, considerable residual temperature fromthe second pulse was present at the end of the third pulse.

METHOD 1B – FINDING TJ AT THE END OF THE NthPULSE IN A TRAIN OF EQUAL AMPLITUDE, SPACING,AND DURATION

The general equation for a train of equal repetitive pulsescan be derived from Equation 1–1. Pi = PD, ti = t, and thespacing between leading edges or trailing edges of adjacentpulses is τ.

General Equation:

n

i1r[(n – i) τ +t]

(1–2)

– r[(n – i) τ]

Tn = PDRθJC

Expanding:

Tn = PD RθJC r[(n – 1) τ + t] – r[(n – 1) τ]Tn = + r[(n – 2) τ + t) – r[(n – 2) τ] + r[(n – 3)Tn = τ + t] – r[(n – 3) τ] + . . . + r[(n – i) τ + t]Tn = – r[(n – i) τ] . . . . . + r(t)] (1–2A)

Relative amounts of temperature residual from P1, P2, andP3 respectively are indicated by the terms in brackets.

For 5 pulses, equation 1–2A is written:

T5 = PD RθJC [r(4 τ + t) – r(4τ) + r(3τ + t)]T5 = – r(3τ) + r(2τ + t) – r(2τ) + r(τ + t)T5 = – r(τ) + r(t)]

Example:

Conditions are shown on Figure 8.5 substituting valuesinto the preceding expression:

T5 = (5) (35) [r(4.20 + 5) – r(4.20) + r(3.20 + 5)T5 = + r(3.20) + r(2.20 + 5) – r(2.20) + r(20 + 5)T5 = – r(20) + r(5)]T5 = (5) (35) [0.6 – 0.76 + 0.73 – 0.72 + 0.68T5 = – 0.66 + 0.59 – 0.55 + 0.33] – (5)(35)(0.40)T5 = 70.0°C

Note that the solution involves the difference betweenterms nearly identical in value. Greater accuracy will beobtained with long or repetitive pulse trains using thetechnique of an average power pulse as used in Methods 2and 3.

METHOD 2 – AVERAGE POWER METHOD, STEADYSTATE CONDITION

The essence of this method is shown in Figure 8.6. Pulsesprevious to the nth pulse are averaged. Temperature due tothe nth or n + 1 pulse is then calculated and combinedproperly with the average temperature.

Assuming the pulse train has been applied for a period oftime (long enough for steady state conditions to beestablished), we can average the power applied as:

Pavg PDt

(1–3)

METHOD 2A – FINDING TEMPERATURE AT THE ENDOF THE Nth PULSE

Applicable Equation:

(1–4)Tn = [Pavg + (PD – Pavg) r(t)] RθJC

or, by substituting Equation 1–3 into 1–4,

Tn t 1– t

r(t) PD RJC (1–5)

The result of this equation will be conservative as it adds atemperature increase due to the pulse (PD – Pavg) to theaverage temperature. The cooling between pulses has notbeen accurately accounted for; i.e., TJ must actually be lessthan TJ(avg) when the nth pulse is applied.



Example: Find Tn for conditions of Figure 8.5.Procedure: Find Pavg from equation (1–3) and

substitute values in equation (1–4) or(1–5).

Tn = [(1.25) + (5.0 – 1.25)(0.33)] (35)Tn = 43.7 + 43.2 = 86.9°C

METHOD 2B – FINDING TEMPERATURE AT THE ENDOF THE N + 1 PULSE


Tn + 1 = [Pavg + (PD – Pavg) r(t + τ)Tn + 1 + PD r(t) – PD r(τ)] RθJC

(1–6)

or, by substituting equation 1–3 into 1–6,

(1–7)

t 1– t

r(t )Tn + 1 =

r(t) r() PDRθJC

Example: Find Tn for conditions of Figure 8.5.Procedure: Find Pavg from equation (1–3) and

substitute into equation (1–6) or (1–7).

Tn + 1 = [(1.25) + (5 – 1.25)(0.59) + (5)(0.33)Tn + 1 – (5)(0.56)] (35) = 80.9°C

Equation (1–6) gives a lower and more accurate value fortemperature than equation (1–4). However, it too gives ahigher value than the true TJ at the end of the n + 1th pulse.The error occurs because the implied value for TJ at the endof the nth pulse, as was pointed out, is somewhat high.Adding additional pulses will improve the accuracy of thecalculation up to the point where terms of nearly equal valueare being subtracted, as shown in the examples using thepulse by pulse method. In practice, however, use of thismethod has been found to yield reasonable design valuesand is the method used to determine the duty cycle of familyof curves – e.g., Figure 8.2.

Note that the calculated temperature of 80.9°C is 10.9°Chigher than the result of example 1B, where the temperaturewas found at the end of the 5th pulse. Since the thermalresponse curve indicates thermal equilibrium in 1 second, 50pulses occurring 20 milliseconds apart will be required toachieve stable average and peak temperatures; therefore,steady state conditions were not achieved at the end of the5th pulse.

METHOD 3 – AVERAGE POWER METHOD,TRANSIENT CONDITIONS

The idea of using average power can also be used in thetransient condition for a train of repetitive pulses. Thepreviously developed equations are used but Pavg must bemodified by the thermal response factor at time t(2n – 1).

METHOD 3A – FINDING TEMPERATURE AT THE ENDOF THE Nth PULSE FOR PULSES OF EQUALAMPLITUDE, SPACING AND DURATION


(1–8)Tn t

r t(2n–1) 1 – tr(t) PD RθJC

Conditions: (See Figure 8.5)Procedure: At the end of the 5th pulse (See Figure

8.7 . . .

T5 = [5/20 r(85) + (1 – 5/20)r(5)] (5)(35)T5 = [(0.25)(0765) + (0.75)(0.33)] (175)T5 = 77°C

This value is a little higher than the one calculated bysumming the results of all pulses; indeed it should be,because no cooling time was allowed between Pavg and thenth pulse. The method whereby temperature was calculatedat the n + 1 pulse could be used for greater accuracy.

METHOD 3B – FINDING TEMPERATURE AT THE ENDOF THE N + 1 PULSE FOR PULSES OF EQUALAMPLITUDE, SPACING AND DURATION


(1–9)

t

r(t2n–1) 1 – tTn + 1 =

r(t ) r(t) r() PD RθJC

Example: Conditions as shown on Figure 8.5. Findtemperature at the end of the 5th pulse.

For n + 1 = 5, n = 4, t2n–1 = t7 = 65 ms,

520

r(65 ms) 1 – 520 r(25 ms)T5 =

r(5 ms) r(20 ms) (5)(35)

T5 = [(0.25)(0.73) + (0.75)(0.59) + 0.33 – 0.55](5)(35)

T5 = 70.8°C


The answer agrees quite well with the answer of Method1B where the pulse–by–pulse method was used for arepetitive train.

METHOD 3C – FINDING TJ AT THE END OF THE NthPULSE IN A RANDOM TRAIN

The technique of using average power does not limit itselfto a train of repetitive pulses. It can be used also where thepulses are of unequal magnitude and duration. Since themethod yields a conservative value of junction temperaturerise it is a relatively simple way to achieve a first approxima-tion. For random pulses, equations 1–4 through 1–7 can bemodified. It is necessary to multiply Pavg by the thermalresponse factor at time t(2n – 1). Pavg is determined byaveraging the power pulses from time of application to thetime when the last pulse starts.

Applicable Equations:

n

i1Pi (1–10)General: Pavg =

t(2i–1)–t(2i–2)t(2n)–t(2i–2)

For 3 Pulses:

(1–11)Pavg = P1t1 – t0t4 – t0

t3 – t2t4 – t2

+ P2

Example: Conditions are shown on Figure 8.4 (refer toMethod 1A).

Procedure: Find Pavg from equation 1–3 and the junctiontemperature rise from equation 1–4.

Conditions: Figure 8.4

Pavg0.13.3 20 1

3 1.21 6.67= 40

= 7.88 WattsT3 = [Pavg r(t5) + (P3 – Pavg) r(t5 – t4)] RθJC

= [7.88 (0.28) + (30 – 7.88) 0.07] 35= [2.21 + 1.56] 35 = 132°C

This result is high because in the actual case considerablecooling time occurred between P2 and P3 which allowed TJto become very close to TC. Better accuracy is obtainedwhen several pulses are present by using equation 1–10 inorder to calculate TJ – tC at the end of the nth + 1 pulse. Thistechnique provides a conservative quick answer if it is easyto determine which pulse in the train will cause maximumjunction temperature.

METHOD 3D – FINDING TEMPERATURE AT THE ENDOF THE N + 1 PULSE IN A RANDOM TRAIN

The method is similar to 3C and the procedure is identical.Pavg is calculated from Equation 1–10 modified by r(t2n – 1)and substituted into equation 1–6, i.e.,

Tn + 1 = [Pavg r(t2n–1) + (PD – Pave) r(t2n–1 –Tn + 1 = t2n–2) + PD r(t2n+1 – t2n) – PD r(t2n+1Tn + 1 = – t2n–1)] RθJC

The previous example cannot be worked out for the n + 1pulse because only 3 pulses are present.

Table 8.2. Summary Of Numerical Solution For TheRepetitive Pulse Train Of Figure 5

Tempera -Temperature Obtained, °C

Temperature

Desired Pulse by PulseAverage Power

Nth PulseAverage Power

N + 1 Pulse

At End of5th Pulse

70.0 (1B) 77 (3A) 70.8 (3B)

Steady StatePeak

– 86.9 (2A) 80.9 (2B)

Note: Number in parenthesis is method used.

Figure 8.9. 2N3467 Transient Thermal Response

1.0

0.1

0.010.01 0.1 1.0 10 100 1000

t, Time (ms)

r (t)

, Tra

nsie

nt T

herm

al R

esis

tanc

e(N

orm

aliz

ed) 0.2

0.02

0.3

0.03

0.5

0.05

0.7

0.07

0.02 0.2 2.0 20 2000.05 0.5 5.0 50 500



Figure 8.10. Case 77 (Thermopad) and TO–220 (Thermowatt) Thermal Response

1.0

0.1

0.010.1 1.0 10 100 1000 10,000

t, Time (ms)

r (t)

, Tra

nsie

nt T

herm

al R

esis

tanc

e(N

orm

aliz

ed) 0.2

0.02

0.3

0.03

0.5

0.05

0.7

0.07

0.2 2.0 20 200 20000.5 5.0 50 500 5000

Thermowatt Case 221All other curves are for Case 77

Figure 8.11. TO–5 (Solid Steel Header) Thermal Response

1.0

0.1

0.010.1 1.0 10 100 1000 10,000

t, Time (ms)

r (t)

, Tra

nsie

nt T

herm

al R

esis

tanc

e(N

orm

aliz

ed) 0.2

0.02

0.3

0.03

0.5

0.05

0.7

0.07

0.2 2.0 20 200 20000.5 5.0 50 500 5000

12

3

4

Figure 8.12. TO–92 (Unibloc) Thermal Response, Applies to All Commonly Used Die

1.0

0.1

0.01

r (t)

, Tra

nsie

nt T

herm

al R

esis

tanc

e(N

orm

aliz

ed) 0.2

0.02

0.3

0.03

0.5

0.05

0.7

0.07

0.1 1.0 10 100 1000 10,000

t, Time (ms)

0.2 2.0 20 200 20000.5 5.0 50 500 5000

8501,2253,60014,400

MM4005, 2N4406MM3006

2N3719, 2N5334No Standard Devices

DEVICE TYPEDIE SIZE(Sq. Mils)

1234

1

2 3

4 5

6

1,2002,0003,6006,3008,10016,900

MJE170, MJE180MJE210, MJE2002N4918, 2N49212N5190, 2N5193MCR1062N6342

DEVICE TYPEDIE SIZE(Sq. Mils)

123456


Figure 8.13. Typical Thermal Resistance As a Functionof Case Material and Die Area. Data Applies to SolidHeader Parts Only. Use Copper Curve for Aluminumand Steel Packages With a Copper Slug Under the Die,Which is the Standard Motorola Design.

100

5.0

0.10.1 1.0 10 100

Die Area x 1000 (mil2)

RJC

, The

rmal

Res

ista

nce

Junc

tion

to C

ase

( C

/W)

10

0.2

20

0.5

50

1.0

2.0

0.2 2.0 200.5 5.0 50

1

2

3

Kovar HeaderSteel HeaderCopper Header

123

°



As the price of semiconductor devices decreases, reliabil-ity and quality have become increasingly important inselecting a vendor. In many cases these considerations evenoutweigh price, delivery and service.

The reason is that the cost of device fallout and warrantyrepairs can easily equal or exceed the original cost of thedevices. Consider the example shown in Figure 8.14.Although the case is simplistic, the prices and costs arerealistic by today’s standards. In this case, the cost of failuresraised the device cost from 15 cents to 21 cents, an increaseof 40%. Clearly, then, investing in quality and reliability canpay big dividends.

With nearly three decades of experience as a majorsemiconductor supplier, Motorola is the largest manufacturerof discrete semiconductors in the world today. Sincesemiconductor prices are strongly influenced by manufactur-ing volume, this leadership has permitted Motorola to bestrongly competitive in the marketplace while making mas-sive investments in equipment, processes and procedures toguarantee that the company’s after–purchase costs will beamong the lowest in the industry. As a result of theprocedures, Motorola is projecting an outgoing quality levelof less than 3 PPM by 1992.

Given:Purchase = 100,000 components @ 15¢ eachAssumptions: Line Fallout = 0.1%Assumptions: Warranty Failures = 0.01%

Components Cost =100,000 15¢ = $15,000Line Fallout Cost = 100 $40 = 4,000

@ $40 per repairWarranty Cost = 10 $200 = 2,000

@ $200 per repair$21,000

Adjusted CostPer Component = $21,000 100,000 = 21¢

Definitions:Line Fall out = Module or subassembly failure

requiring troubleshooting, partsreplacement and retesting

Warranty Failure = System field failure requir-ing in warranty repair

Figure 8.14. Component Costs to the User(including line fallout and warranty costs)

Quality and reliability are two essential elements in orderfor a semiconductor company to be successful in themarketplace today. Quality and reliability are interrelatedbecause reliability is quality extended over the expected lifeof the product.

Quality is the assurance that a product will fulfill custom-ers’ expectations.

Reliability is the probability that a product will perform itsintended function satisfactorily for a prescribed life undercertain stated conditions.

The quality and reliability of Motorola thyristors areachieved with a four step program:

1. Thoroughly tested designs and materials2. Stringent in–process controls and inspections3. Process average testing along with 100% quality

assurance redundant testing4. Reliability verifications through audits and reliability

studies

ESSENTIALS OF RELIABILITYParamount in the mind of every semiconductor user is the

question of device performance versus time. After theapplicability of a particular device has been established, itseffectiveness depends on the length of trouble free service itcan offer. The reliability of a device is exactly that — anexpression of how well it will serve the customer. Reliabilitycan be redefined as the probability of failure free perfor-mance, under a given manufacturer’s specifications, for agiven period of time. The failure rate of semiconductors ingeneral, when plotted versus a long period of time, exhibitwhat has been called the “bath tub curve” (Figure 8.15).

Figure 8.15. Failure Rate of Semiconductor

INFANTMORTALITY

RANDOM FAILUREMECHANISM

WEAROUTPHENOMENON

FAIL

UR

E R

ATE


RELIABILITY MECHANICSSince reliability evaluations usually involve only samples

of an entire population of devices, the concept of the centrallimit theorem applies and a failure rate is calculated using theλ2 distribution through the equation:

2 (, 2r 2)2 nt

λ ≤

λ2 = chi squared distribution

where 100 – cl

100

λclrnt

= Failure rate= Confidence limit in percent= Number of rejects= Number of devices= Duration of tests

The confidence limit is the degree of conservatism desiredin the calculation. The central limit theorem states that thevalues of any sample of units out of a large population willproduce a normal distribution. A 50% confidence limit istermed the best estimate, and is the mean of this distribution.A 90% confidence limit is a very conservative value andresults in a higher λ which represents the point at which 90%of the area of the distribution is to the left of that value (Figure8.16).

Figure 8.16. Confidence Limits and the Distribution ofSample Failure Rates

50% CLX

FREQ

UEN

CY

90% CL

, FAILURE RATE

The term (2r + 2) is called the degrees of freedom and isan expression of the number of rejects in a form suitable toλ2 tables. The number of rejects is a critical factor since thedefinition of rejects often differs between manufacturers. Dueto the increasing chance of a test not being representative ofthe entire population as sample size and test time aredecreased, the λ2 calculation produces surprisingly highvalues of λ for short test durations even though the true longterm failure rate may be quite low. For this reason relativelylarge amounts of data must be gathered to demonstrate thereal long term failure rate. Since this would require years oftesting on thousands of devices, methods of acceleratedtesting have been developed.

Years of semiconductor device testing have shown thattemperature will accelerate failures and that this behavior fitsthe form of the Arrhenius equation:

R(t) = Ro(t)e–o/KT

Where R(t) = reaction rate as a function of time andtemperature

Ro = A constantt = TimeT = Absolute temperature, °Kelvin (°C + 273°)o = Activation energy in electron volts (ev)

K = Boltzman’s constant = 8.62 10–5 ev/°KThis equation can also be put in the form:

AF = Acceleration factorT2 = User temperatureT1 = Actual test temperature

The Arrhenius equation states that reaction rate increasesexponentially with the temperature. This produces a straightline when plotted on log–linear paper with a slope expressedby o. o may be physically interpreted as the energy thresholdof a particular reaction or failure mechanism. The overallactivation energy exhibited by Motorola thyristors is 1 ev.

RELIABILITY QUALIFICATIONS/EVALUATIONSOUTLINE:

Some of the functions of Motorola Reliability and QualityAssurance Engineering are to evaluate new products forintroduction, process changes (whether minor or major), andproduct line updates to verify the integrity and reliability ofconformance, thereby ensuring satisfactory performance inthe field. The reliability evaluations may be subjected to aseries of extensive reliability testing, such as in the testsperformed section, or special tests, depending on the natureof the qualification requirement.

AVERAGE OUTGOING QUALITY (AOQ)With the industry trend to average outgoing qualities

(AOQ) of less than 100 PPM, the role of device final test, andfinal outgoing quality assurance have become a keyingredient to success. At Motorola, all parts are 100% testedto process average limits then the yields are monitoredclosely by product engineers, and abnormal areas of falloutare held for engineering investigation. Motorola also 100%redundant tests all dc parameters again after marking thedevice to further reduce any mixing problems associatedwith the first test. Prior to shipping, the parts are againsampled, tested to a tight sampling plan by our QualityAssurance department, and finally our outgoing final inspec-tion checks for correct paperwork, mixed product, visual andmechanical inspections prior to packaging to the customers.



AVERAGE OUTGOING QUALITY (AOQ)

AOQ = Process Average Probability of Acceptance 106 (PPM)

Process AverageNo. of Reject DevicesNo. of Devices Tested

Probability of Acceptance (1–No. of Lots RejectedNo. of Lots Tested

)

106 = To Convert to Parts Per Million

AOQNo. of Reject DevicesNo. of Devices Tested

(1 –No. of Lots RejectedNo. of Lots Tested

) 106(PPM)

Current AOQ levels (1988) are less than 50 PPM. Theprojected goal, by 1992, is less than 3 PPM, a defect rate solow that it becomes virtually invisible to the user. Figure 8.17shows AOQ of Motorola Thyristors.

Figure 8.17. Average Outgoing Quality (AOQ) ofMotorola Thyristors

4000

3000

2000

1000

19793264

19802561

19811546

19821057

1983644

1984200

1985*100

1986*50

1987*0

THYRISTOR PPM

*PROJECTION

THYRISTOR RELIABILITYThe reliability data described herein applies to Motorola’s

extensive offering of thyristor products for low and mediumcurrent applications. The line includes not only the pervasiveSilicon Controlled Rectifiers (SCRs) and TRIACs, but also avariety of Programmable Unijunction Transistors (PUTs),Silicon Bidirectional Switches (SBSs), SIDACs and otherassociated devices used for SCR and TRIAC triggeringpurposes. Moreover, these devices are available in differentpackage styles with overlapping current ranges to provide anintegral chip–and–package structure that yields lowest cost,consistent with the overriding consideration of high reliability.

The various packages and the range of electrical specifi-cations associated with the resultant products are shown inFigure 8.18.

To evaluate the reliability of these structures, productionline samples from each type of package are being subjectedto a battery of accelerated reliability tests deliberatelydesigned to induce long–term failure. Though the tests arebeing conducted on a continuing basis, the results so far are

Case 29–04/TO–226AA(TO–92)Devices Available:SCRs, TRIACs,PUTs, SBSsCurrent Range: to 0.8 AVoltage Range: 25 to 600 V

Case 77–08/TO–225AA(TO–126)Devices Available:SCRs, TRIACsCurrent Range: to 4 AVoltage Range: 25 to 600 V

Case 267–03/Axial Lead(Surmetic 50)Devices Available:SIDACVoltage Range: 104 to 240 V

Case 221A–04/TO–220ABDevices Available:SCRs, TRIACsCurrent Range: to 40 AVoltage Range: 50 to 1000 V

Figure 8.18. Motorola Thyristor Packages

both meaningful and impressive. They are detailed on thefollowing pages in the hope that they will provide for thereaders a greater awareness of the potential for thyristors intheir individual application.


THYRISTOR CONSTRUCTION THROUGH ATIME TESTED DESIGN AND ADVANCEDPROCESSING METHODS

A pioneer in discrete semiconductor components and theworld’s largest supplier thereof, Motorola has pyramidedcontinual process and material improvements into thyristorproducts whose inherent reliability meets the most criticalrequirements of the market.

These improvements are directed towards long–termreliability in the most strenuous applications and the mostadverse environments.

DIE GLASSIVATIONAll Motorola thyristor die are glass–sealed with a Motorola

patented passivation process making the sensitive junctionsimpervious to moisture and impurity penetration. Thisimparts to low–cost plastic devices the same freedom fromexternal contamination formerly associated only with hermet-ically sealed metal packages. Thus, metal encapsulation isrequired primarily for higher current devices that wouldnormally exceed the power–dissipation capabilities of plasticpackages — or for applications that specify the hermeticpackage.

VOID–FREE PLASTIC ENCAPSULATIONA fifth generation plastic package material, combined with

improved copper piece–part designs, maximize packageintegrity during thermal stresses. The void–free encapsula-tion process imparts to the plastic package a mechanicalreliability (ability to withstand shock and vibration) evenbeyond that of metal packaged devices.

IN–PROCESS CONTROLS AND INSPECTIONS

INCOMING INSPECTIONSApparently routine procedures, inspection of incoming

parts and materials, are actually among the most criticalsegments of the quality and reliability assurance program.That’s because small deviations from materials specifica-tions can traverse the entire production cycle before beingdetected by outgoing Quality Control, and, if undetected,

could affect long–term reliability. At Motorola, piece–partcontrol involves the services of three separate laborato-ries . . . Radiology, Electron Optics and Product Analysis. Allthree are utilized to insure product integrity:

Raw Wafer Quality, in terms of defects, orientation,flatness and resistivity;Physical Dimensions, to tightly specified tolerances;Metal Hardness, to highly controlled limits;Gaseous Purity and Doping Level;Mold Compounds, for void–free plastic encapsulation.

IN–PROCESS INSPECTIONSAs illustrated in Figure 8.19, every major manufacturing

step is followed by an appropriate in–process QA inspection.Quality control in wafer processing, assembly and final testimpart to Motorola standard thyristors a reliability level thateasily exceeds most industrial, consumer and militaryrequirements . . . built–in quality assurance aimed at insuringfailure–free shipments of Motorola products.

RELIABILITY AUDITSReliability audits are performed following assembly. Reli-

ability audits are used to detect process shifts which canhave an adverse effect on long–term reliability. Extremestress testing on a real–time basis, for each product run,uncovers process abnormalities that may have escaped thestringent in–process controls. Typical tests include HTRB/FB(high–temperature reverse bias and forward bias) storagelife and temperature cycling. When abnormalities are de-tected, steps are taken to correct the process.

OUTGOING QCThe most stringent in–process controls do not guarantee

strict adherence to tight electrical specifications. Motorola’s100% electrical parametric test does — by eliminating alldevices that do not conform to the specified characteristics.Additional parametric tests, on a sampling basis, providedata for continued improvement of product quality. And tohelp insure safe arrival after shipment, antistatic handlingand packaging methods are employed to assure that theproduct quality that has been built in stays that way.

From rigid incoming inspection of piece parts and materi-als to stringent outgoing quality verification, assembly andprocess controls encompass an elaborate system of test andinspection stations that ensure step–by–step adherence to aprescribed procedure designed to yield a high standard ofquality.



Figure 8.19. In–Process Quality Assurance Inspection Points for Thyristors

IN–COMING

INSP.WAFER &

CHEMICALS

DIFFUSION,MOAT ETCH,

PHOTOGLASSRESIS–TIVITY

INSPECTION

METALLIZATION,100% DIE ELECT, TESTS

SCRIBE & BREAKELEC.

& VISUALINSPECTION

INC.INSP.

FORM &CLEAN

PC. PARTSQA INSPECTION

DIE BOND QAINSPECTION

QAINSPECTION

LEADATTACHMENT

INJECTION MOLD& DEFLASH PLASTIC,

CLEAN & SOLDERDIP LEADS,

CURE PLASTIC

RELIA–BILITY

AUDITS

100% ELECT.SELECTION, 100%

BIN SPECIFICATIONTEST, 100% QA

INSPECTIONLASER MARKING

OUTGOINGQC

SAMPLING

100%ANTISTATIC

HANDLING/PACKAGING

FINALVISUAL

&MECHANICAL

SHIPPING

RELIABILITY TESTS

Only actual use of millions of devices, under a thousanddifferent operating conditions, can conclusively establish thereliability of devices under the extremes of time, tempera-ture, humidity, shock, vibration and the myriads of otheradverse variables likely to be encountered in practice. Butthorough testing, in conjunction with rigorous statisticalanalysis, is the next–best thing. The series of torture testsdescribed in this document instills a high confidence levelregarding thyristor reliability. The tests are conducted atmaximum device ratings and are designed to deliberatelystress the devices in their most susceptible failure models.The severity of the tests compresses into a relatively shorttest cycle the equivalent of the stresses encountered duringyears of operation under more normal conditions. The resultsnot only indicate the degree of reliability in terms ofanticipated failures; they trigger subsequent investigationsinto failure modes and failure mechanisms that serve as thebasis of continual improvements. And they represent aclear–cut endorsement that, for Motorola thyristors, low–costand high quality are compatible attributes.

BLOCKING LIFE TEST

This test is used as an indicator of long–term operatingreliability and overall junction stability (quality). All semicon-ductor junctions exhibit some leakage current underreverse–bias conditions. Thyristors, in addition, exhibitleakage current under forward–bias conditions in the offstate. As a normal property of semiconductors, this junctionleakage current increases proportionally with temperature ina very predictable fashion.

Leakage current can also change as a function of time —particularly under high–temperature operation. Moreover,this undesirable “drift” can produce catastrophic failureswhen devices are operated at, or in excess of, ratedtemperature limits for prolonged periods.

The blocking life test operates representative numbers ofdevices at rated (high) temperature and reverse–biasvoltage limits to define device quality (as measured byleakage drifts) and reliability (as indicated by the number ofcatastrophic failures*). The results of these tests are shownin Table 8.3. Table 8.4 shows leakage–current drift after 1000hours HTRB.


Table 8.3. Blocking Life TestHigh Temperature Reverse Bias (HTRB)

and High Temperature Forward Bias (HTFB)

CaseTest Conditions

TA@ Rated Voltage

SampleSize

Duration(Hours)

TotalDeviceHours

CatastrophicFailures*

29–04/TO–226AA(TO–92)

100°C 1000 1000 1,000,000 1

77–08/TO–225AA(TO–126)

110°C 1000 1000 1,000,000 0

221A–04/TO–220AB 100°C 1000 1000 1,000,000 0

267–03/Axial Lead(Surmetic 50)

125°C 150 1000 150,000 0

* Failures are at maximum rated values. The severe nature of these testsis normally not seen under actual conditions.

Table 8.4. Leakage–Current Drift after 1000 Hours HTRB

The favorable blocking–life–test drift results shown here are attributed toMotorola’s unique “glassivated junction” process which imparts a high degreeof stability to the devices.

–40 µA –20 µA +20 µA +40 µA0

Leakage Shift from Initial Value

VDRM = 400 V

TA = 100°C

HIGH TEMPERATURE STORAGE LIFE TESTThis test consists of placing devices in a high–temperature

chamber. Devices are tested electrically prior to exposure tothe high temperature, at various time intervals during thetest, and at the completion of testing. Electrical readoutresults indicate the stability of the devices, their potential towithstand high temperatures, and the internal manufacturingintegrity of the package. Readouts at the various intervalsoffer information as to the time period in which failures occur.Although devices are not exposed to such extreme hightemperatures in the field, the purpose of this test is toaccelerate any failure mechanisms that could occur during

long periods at actual storage temperatures. Results of thistest are shown in Table 8.5.

Table 8.5. High Temperature Storage Life

CaseTest

ConditionsSample

SizeDuration(Hours)

TotalDeviceHours


29–04/TO–226AA(TO–92)

TA = 150°C 1000-2000

400 1,500,000 0

77–08/TO–225AA(TO–126)

** 1000-2000

350 550,000 0

221A–04/TO–220 1000 300 300,000 0

267–03/Axial Lead(Surmetic 50)

1000 100 100,000 0

* Failures are at maximum rated values. The severe nature of these testsis normally not seen under actual conditions.

** Same for all.

STRESS TESTING — POWER CYCLING ANDTHERMAL SHOCK

POWER CYCLING TESTHow do the devices hold up when they are repeatedly

cycled from the off state to the on state and back to the offstate under conditions that force them to maximum ratedjunction temperature during each cycle? The Power CyclingTest was devised to provide the answers.

In this test, devices are subjected to intermittent operatingfile (IOL), on–state power until the junction temperature (TJ)has increased to 100°C. The devices are then turned off andTJ decreases to near ambient, at which time the cycle isrepeated.

This test is important to determine the integrity of the chipand lead frame assembly since it repeatedly stresses thedevices. It is unlikely that these worst–case conditions wouldbe continuously encountered in actual use. Any reduction inTJ results in an exponential increase in operating longevity.Table 8.6 shows the results of IOL testing.

THERMAL SHOCKCONDITIONS BEYOND THE NORM

Excesses in temperature not only cause variations inelectrical characteristics, they can raise havoc with themechanical system. Under temperature extremes, contrac-tion and expansion of the chip and package can causephysical dislocations of mechanical interfaces and inducecatastrophic failure.

To evaluate the integrity of Motorola thyristors under themost adverse temperature conditions, they are subjected tothermal shock testing.

AIR–TO–AIR (TEMPERATURE CYCLING)This thermal shock test is conducted to determine the

ability of the devices to withstand exposure to extreme highand low temperature environments and to the shock ofalternate exposures to the temperature extremes. Results ofthis test are shown in Table 8.6.



Table 8.6. Air–to–Air

Case Test ConditionsSample

SizeNumberof cycles

TotalDeviceCycles


29–04/TO–226AA (TO–92) –40°C or –65°C 900 400 360,000 0

77–08/TO–225AA (TO–126) to +150°CD ll 15 i t t h t

500 400 200,000 0

221A–04/TO–220Dwell—15 minutes at each extreme

Immediate Transfer400 400 160,000 0

267–03/Axial Lead (Surmetic 50)Immediate Transfer

100 400 40,000 0

* Failures are at maximum rated values. The severe nature of these tests is normally not seen under actual conditions.

ENVIRONMENTAL TESTING

MOISTURE TESTS

Humidity has been a traditional enemy of semiconductors,particularly plastic packaged devices. Most moisture–relateddegradations result, directly or indirectly, from penetration ofmoisture vapor through passivating materials, and fromsurface corrosion. At Motorola, this erstwhile problem hasbeen effectively controlled through the use of a unique

junction “glassivation” process and selection of packagematerials. The resistance to moisture–related failures isindicated by the tests described here.

BIASED HUMIDITY TESTThis test was devised to determine the resistance of

component parts and constituent materials to the combineddeteriorative effects of prolonged operation in a high–tem-perature/high–humidity environment. H3TRB test results areshown in Table 8.7.

Table 8.7. Biased Humidity TestHigh humidity, high Temperature, reverse bias (H 3TRB)

Case Test ConditionsSample

SizeDuration

Hours

TotalDeviceCycles


29–04/TO–226AA(TO–92)

Relative Humidity 85%TA = 85°C

400 500–1000 300,000 0

77–08/TO–225AA Reverse Voltage–Ratedor 200 V Maximum

200 500–1000 150,000 0

221A–04/TO–220or 200 V Maximum

100 500–1000 75,000 0

267–03/Axial Lead (Surmetic 50) 30 1000 30,000 0

* Failures are at maximum rated values. The severe nature of these tests is normally not seen under actual conditions.


CHAPTER 9APPENDICES

APPENDIX I

USING THE TWO TRANSISTOR ANALYSIS

DEFINITIONS:IC IB

ICS

IA IK α

IG

Collector currentBase currentCollector leakage current(saturation component)Anode currentCathode currentCurrent amplification factorGate current

The subscript “i” indicates theappropriate transistor.

FOR TRANSISTOR #1:IC1 = α1 IA + ICSIand

IB1 = IA – IC1Combining these equations,

IB1 = (1 – α1) IA – ICS1 (1)

LIKEWISE, FOR TRANSISTOR #2IC2 = α2IK + ICS2 (2)

IB1 = IC2and by combining Equations (1) and(2) and substituting IK = IA + IG, itis found that

IA2IG ICS1 ICS2

1 – 1 – 2(3)

Equation (3) relates IA to IG, and note that as α1 + α2 = 1, IAgoes to infinity. IA can be put in terms of IK and α’s as follows:

IB1 = IC2

Combining equations (1) and (2):

IAICS1 ICS2

1 – 1 – (IKIA

) 2

IA — ∞ if denominator approaches zero, i.e., if

IKIA

1 – 12

Note that just prior to turn–on there is a majority carrierbuild–up in the P2 “base.” If the gate bias is small there willactually be hole current flowing out from P2 into the gatecircuit so that IG is negative, IK = IA + IG is less than IA so:(see Figure 3.2 for the directions of current components)IKIA

< 1 which corresponds to α1 + α2 > 1

Figure 9.1. Schematic Diagram of the Two TransistorModel of a Thyristor

IA

IB1

IC1

IC2

IK

IB2IG

A

G

K

P1

N1

P2 N1

N2

P2

DEVICE #1

DEVICE #2



APPENDIX II

CHARGE AND PULSE WIDTH

In the region of large pulse widths using current triggering,where transit time effects are not a factor, we can considerthe input gate charge for triggering, Qin, as consisting ofthree components: 1. Triggering charge Qtr, assumed to be constant. 2. Charge lost in recombination, Qr, during current regen-

eration prior to turn–on. 3. Charge drained, Qdr, which is by–passed through the

built–in gate cathode shunt resistance (the presence ofthis shunting resistance is required to increase the dv/dtcapability of the device).

Mathematically, we have

Qin = Qtr + Qdr + Qr = IGτ (1)

Qr is assumed to be proportional to Qin; to be exact,

Qr = Qin (1 – exp–τ/τ1) (2)

where IG =τ =

τ1 =

gate current,pulse width of gate current,effective life time of minority carriers in thebases

The voltage across the gate to cathode P–N junction duringforward bias is given by VGK (usually 0.6 V for silicon).* Thegate shunt resistance is Rs (for the MCR729, typically 100ohms), so the drained charge can be expressed by

QdrVGCRs

(3)

Combining equations (1), (2), and (3), we get

Qin IG (QtrVGCRs

) exp. 1 (4)

Note that at region A and C of Figure 3.3(c) Qin has anincreasing trend with pulse width as qualitatively describedby Equation (4).

Assume life time at the temperature range of operationincreases as some power of temperature

τ1 = KTm (5)

where K and m are positive real numbers. CombiningEquations (4) and (5), we can get the slope of Qin withrespect to temperature to be

slopedQindT

– m(QtrVGCRs

)

1

exp.1T

(6)

In reality, Qtr is not independent of temperature, in whichcase the Equation (6) must be modified by adding anadditional term to become:

slope –m(QtrVGCRs

)

1

exp.1T

dQtrdT

exp1 (7)

Physically, not only does Qtr decrease with temperature sothat dQtr/dT is a negative number, but also |dQtr/dTIdecreased with temperature as does |dα/dTI in the tempera-ture range of interest.

Equation (6) [or (7)] indicates two things:

1. The rate of change of input trigger charge decreases astemperature (life time) increases.

2. The larger the pulse width of gate trigger current, thefaster the rate of change of Qin with respect to change intemperature. Figure 3.11 shows these trends.

*VGC is not independent of IG. For example, for the MCR729the saturation VGC is typically 1 V, but at lower IG’s the VGC isalso smaller, e.g. for IG = 5 mA, VGC is typically 0.3 V.


APPENDIX III

TTL SOA TEST CIRCUIT

Using the illustrated test circuit, the two TTL packages(quad, 2–input NAND gates) to be tested were powered bythe simple, series regulator that is periodically shorted by theclamp transistor, Q2, at 10% duty cycle rate. By varying theinput to the regulator V1 and the clamp pulse width, variouspower levels can be supplied to the TTL load. Thus, as an

example, VCC could be at 5 V for 90 ms and 10 V for 10 ms,simulating a transient on the bus or a possibly shorted powersupply pass transistor for that duration. These energy levelsare progressively increased until the gate (or gates) fail, asdetected by the status of the output LEDs, the voltage andcurrent waveforms and the device case temperature.

Figure 9.2. TTL SOA Test Circuit

1 k

MJE220

Q1V1 VCC

2 W220 5.6 V

1 W

1N4739

Q2 MJE230

VCC

1 k

2N3904

V1

100 µF

V2 = 10 V

10 V1N5240

10 M

MC14011

470

Q3

3.9 M 0.1 µF

10 k

10 k

10 k

10 k10 k

V2 V2

100 k

0.47 µF

1N914 1N914

2.2 M

1 k

2N3904

Q4

5 M500 k

G1G2

G3G4

300

VCCVCC

300LED

LED

220

220

(2) MC7400DUT

SQUARE WAVE GENERATORf 1 Hz

10% DUTY CYCLE GENERATOR

T1 T2

5 ms < T2 < 250 ms50 ms < T2 < 1.9 s

1A2A

2D1D



APPENDIX IV

SCR CROWBAR LIFE TESTING

This crowbar life test fixture can simultaneously test tenSCRs under various crowbar energy and gate drive condi-tions and works as follows.

The CMOS Astable M.V. (Gates 1 and 2) generate anasymmetric Gate 2 output of about ten seconds high, onesecond low. This pulse is amplified by Darlington Q22 to turnon the capacitor charging transistors Q1–Q10 for the tenseconds. The capacitors for crowbarring are thus charged inabout four seconds to whatever power supply voltage towhich VCC1 is set. The charging transistors are then turnedoff for one second and the SCRs are fired by an approxi-mately 100 µs delayed trigger derived from Gates 3 and 4.The R–C network on Gate 3 input integrates the complemen-tary pulse from Gate 1, resulting in the delay, thus insuringnon–coincident firing of the test circuit. The shaped pulse outof Gate 4 is differentiated and the positive–going pulse isamplified by Q21 and the following ten SCR gate drivers(Q11–Q20) to form the approximate 2 ms wide, 1 µs rise

time, SCR gate triggers, IGT. IGT is set by the collectorresistors of the respective gate drivers and the supplyvoltage, VCC2; thus, for IGT ≈ 100 mA, VCC2 ≈ 30 V, etc.

The LEDs across the storage capacitors show the state ofthe voltage on the capacitors and help determine whetherthe circuit is functioning properly. The timing sequence wouldbe an off LED for the one–second capacitor dump periodfollowed by an increasingly brighter LED during the capacitorcharge time. Monitoring the current of VCC1 will also indicateproper operation.

The fixture’s maximum energy limits are set by the workingvoltage of the capacitors and breakdown voltage of thetransistors. For this illustration, the 60 V, 8400 µF capacitors(ESR ≈ 20 mΩ) produced a peak current of about 2500 Alasting for about 0.5 ms when VCC1 equals 60 V. Otherenergy values (lower ipk, greater tw) can be obtained byplacing a current limiting resistor between the positive side ofthe capacitor and the crowbar SCR anode.

Figure 9.3. Schematic for SCR Crowbar Life Test

10 k

MJE803

MC14011B

VDD

1N914

2.2 M

+15 V

100 k

0.001 µF

+15 V

22 M22 M

0.47 µF

2.2 k

2.2 k

2.2 k

2 W

2 W

2 W

Q22

VSS

0.1 µF+ 15 V

10 k

1N914

470

470

VCC1

VCC1

MJE803

Q21

MJE250

Q1

Q10

Q11

MJE250

MJE250

470

2.2 k

VCC2

470

VCC2

270

2.7 k1 W

5 W100

5 W100

2.7 k

1 W

R1

270

2.2 kQ20

MJE250

8400 µF

8400 µF

C1

C10(10) LED

DUT #10

DUT #1

43

21


APPENDIX V

DERIVATION OF THE RMS CURRENTOF AN EXPONENTIALLY DECAYING

CURRENT WAVEFORM

Irms 1T i2(t)dt T

0

1T (Ipke–t)2dt

12T

0

Ipk2

Te–2t

(–2)

12T

0

Ipk2

T–

2 (e–2T – e0)

12

where T = 5τ,

–Ipk2

10(e–10 – 1)

12

Irms Ipk

10 0.316 Ipk

Ipk

T = 5 τ

i = Ipke–t/τ

APPENDIX VI

DERIVATION OF I2t FOR VARIOUS TIMES

Thermal Equation ∆t = Z(θ)PDwhere Z(θ) = r(t)RθJC

and r(t) = K t

Therefore, for the same ∆t,

t K t1 R

JCPD1 K t2

RJC PD2,

PD1PD2

t2t1

I1

2R

I22R,

I12

I22

t2t1

Multiplying both sides by (t1/t2),

I12t1

I22t2 t2

t112 t1

t2 t1

t212

,

I12t1 I2

2t2t1t2



APPENDIX VII

THERMAL RESISTANCE CONCEPTS

The basic equation for heat transfer under steady–stateconditions is generally written as:

q = hA∆T (1)

where q =h =A =

∆T =

rate of heat transfer or power dissipation (PD),heat transfer coefficient,area involved in heat transfer,temperature difference between regions of heattransfer.

However, electrical engineers generally find it easier to workin terms of thermal resistance, defined as the ratio oftemperature to power. From Equation (1), thermal resis-tance, Rθ, is

Rθ = ∆T/q = 1/hA (2)

The coefficient (h) depends upon the heat transfer mecha-nism used and various factors involved in that particularmechanism.

An analogy between Equation (2) and Ohm’s Law is oftenmade to form models of heat flow. Note that ∆T could bethought of as a voltage; thermal resistance corresponds toelectrical resistance (R); and, power (q) is analogous tocurrent (l). This gives rise to a basic thermal resistancemodel for a semiconductor (indicated by Figure 9.4).

The equivalent electrical circuit may be analyzed by usingKirchoff’s Law and the following equation results:

TJ = PD(RθJC + RθCS + RθSA) + TA (3)

where TJ =PD =

RθJC =

RθCS =

RθSA =

TA =

junction temperature,power dissipation,semiconductor thermal resistance(junction to case),interface thermal resistance(case to heat sink),heat sink thermal resistance(heat sink to ambient),ambient temperature.

The thermal resistance junction to ambient is the sum ofthe individual components. Each component must beminimized if the lowest junction temperature is to result. Thevalue for the interface thermal resistance, RθCS, is affectedby the mounting procedure and may be significant comparedto the other thermal–resistance terms.

The thermal resistance of the heat sink is not constant; itdecreases as ambient temperature increases and is affectedby orientation of the sink. The thermal resistance of thesemiconductor is also variable; it is a function of biasing andtemperature. In some applications such as in RF poweramplifiers and short–pulse applications, the concept may beinvalid because of localized heating in the semiconductorchip.

Figure 9.4. Basic Thermal Resistance Model Showing Thermal to Electrical Analogy for a Semiconductor

SOLDER TERMINAL

FLAT WASHER

NUT

HEAT SINK

MICA INSULATORS

DIETC, CASE TEMPERATURE

TJ, JUNCTION TEMPERATURE

TS, HEAT SINKTEMPERATURE

TA, AMBIENTTEMPERATURE

RθSA

RθCS

RθJC

REFERENCE TEMPERATURE

PD


APPENDIX VIII

DERIVATION OF RFI DESIGN EQUATIONS

The relationship of flux to voltage and time is E = N ddt

or

E = NAc dBdt

since φ = BAc and Ac is a constant. Rearranging

this equation and integrating we get:

E dt = NAc (B2 – B1) = NAc ∆ B (1)

which says that the volt–second integral required determinesthe size of the core. In an L–R circuit such as we have with athyristor control circuit, the volt–second characteristic is thearea under an exponential decay. A conservative estimate ofthe area under the curve may be obtained by considering atriangle whose height is the peak line voltage and the base is

the allowable switching time. The area is then 1/2 bh or Eptr

2.

Substituting in Equation (1):

(2)Eptr

2 N Ac B

where:Ep is the peak line voltagetr is the allowable current rise timeN is the number of turns on the coilAc is the usable core area in cm2∆ B is the maximum usable flux density of the core material

in W/m2

Rewriting Equation (2) to change ∆B from W/m2 to gauss,

substituting 2 Erms for Ep and solving for N, we get:

N 2 Erms tr2 Ac B

108 0.707 Erms tr 108

BMAX Ac

Ac in this equation is in cm2. To change to in2, multiply Acby 6.452. Then:

(3)N 10.93 Erms tr 106

BMAX Ac

where:

N is total turnsErms is line voltagetr is allowable current rise time in secondsBMAX is maximum usable flux density of core materialAc is usable core area in square inchesWindow area necessary is:

(4)Aw = N Awire3

The factor of 3 is an approximation which allows forinsulation and winding space not occupied by wire. Substitut-ing equation (3) in (4):

Aw 10.93 Erms tr 106

BMAX AcAwire 3

(The factor 10.93 may be rounded to 11 since two significantdigits are all that are necessary.)

The factor AcAw can easily be found for most cores and is aneasy method for selecting a core.

AcAw 33 Erms trAwire 106

BMAX

In this equation, the core area is in in2. To work with circularmils, multiply by 0.78 10–6 so that:

AcAw 26 Erms trAwire

BMAX

where Awire is the wire area in circular mils.Inductance of an iron core inductor is

L 3.19 N2 Ac 10–8

Ig1c

Rearranging terms,

Ig 3.19 N2 Ac 10–8

L–

1c

APPENDIX IX

BIBLIOGRAPHY ON RFIElectronic Transformers and Circuits, Reuben Lee, John Wiley and Sons, Inc., New York, 1955.

Electrical Interference, Rocco F. Ficchi, Hayden Book Company, Inc., New York, 1964.

“Electromagnetic–Interference Control,” Norbert J. Sladek, Electro Technology, November, 1966, p. 85.

“Transmitter–Receiver Pairs in EMI Analysis,” J. H. Vogelman, Electro Technology, November, 1964, p. 54.

“Radio Frequency Interference,” Onan Division of Studebaker Corporation, Minneapolis, Minnesota.

“Interference Control Techniques,” Sprague Electric Company, North Adams, Massachusetts, Technical Paper 62–1, 1962.

“Applying Ferrite Cores to the Design of Power Magnetics,” Ferroxcube Corporation of America, Saugerties, New York, 1966.

2–1

In Brief . . .Selector Guide

PageNew Products 2–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Silicon Controlled Rectifiers 5.7–2. . . . . . . . . . . . . . . . . . . . . . TRIACs 5.7–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

General Purpose 5.7–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . Thyristor Triggers 5.7–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SIDACs 5.7–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmable Unijunction Transistors — PUT 5.7–14. . Silicon Bidirectional Switch (SBS) 5.7–14. . . . . . . . . . . . . High Voltage Bidirectional TVS Devices 5.7–14. . . . . . . .

Motorola’s broad line of Thyristors includes. . . .• A full line of TRIACs and SCRs covering a forward

current range from 0.5 to 55 amperes and blockingvoltages from 15 to 800 volts.

• Plastic package for lowest cost which includes the fullyinsulated plastic Case 221C (TO–220 Isolated).

• An extensive line of trigger devices that includesSIDACs, PUTs and SBS.

Then there are the special applications devices forIgnition circuits and Crowbar applications. Also included areisolated packaged devices for appliances and surfacemount packages for surface mounting in space–savingrequirements.

Finally, there is the continued Motorola investment indiscrete–product R & D producing new capabilities such astransient SIDACs for use in circuits sensitive to high voltagetransients.

Selector Guide2–2


Numeric Index

Device Page

2N Devices2N3870–73 2–82N5060–64 2–32N6027–28 2–212N6071 Series 2–112N6071A Series 2–112N6071B Series 2–112N6171–74 2–82N6237–41 2–42N6342–45 2–132N6346A–49A 2–162N6394–99 2–62N6400 Series 2–72N6504–09 2–7

European Part NumbersBRX44–49 2–3BRY55–30 2–3BRY55–60 2–3BRY55–100 2–3BRY55–200 2–3BRY55–400 2–3BRY55–500 2–3BRY55–600 2–3

“C” Devices (SCRs)C106 Series 2–4C122 Series 2–5

Device Page

MAC Devices (TRIACs)MAC08BT1 2–10MAC08DT1 2–10MAC08MT1 2–10MAC8 SeriesMAC9 SeriesMAC12 SeriesMAC15 Series 2–16MAC15A Series 2–16MAC15AFP Series 2–17MAC15FP Series 2–17MAC16 Series 2–16MAC97,A,B Series 2–10MAC210 Series 2–14MAC210A Series 2–14MAC210AFP Series 2–15MAC210FP Series 2–15MAC212 Series 2–15MAC212A 2–15MAC212AFP Series 2–15MAC210FP Series 2–15MAC213 Series 2–16MAC218 Series 2–12MAC218A Series 2–12MAC218AFP Series 2–13MAC218FP Series 2–13MAC219 Series 2–13MAC223 Series 2–18MAC223A Series 2–18MAC223AFP Series 2–17MAC223FP Series 2–17MAC224 Series 2–18MAC224A Series 2–18MAC228 Series 2–14MAC228A Series 2–14MAC228AFP Series 2–14MAC228FP Series 2–14MAC229 Series 2–14MAC229A Series 2–14MAC229AFP Series 2–14MAC229FP Series 2–14MAC310 Series 2–15MAC310A Series 2–15MAC320 Series 2–17MAC320A Series 2–17MAC320AFP Series 2–17MAC320FP Series 2–17MAC321 Series 2–17

Device Page

MCR Devices (SCRs)MCR08BT1 2–3MCR08DT1 2–3MCR08MT1 2–3MCR8 SeriesMCR8S SeriesMCR12 SeriesMCR16 SeriesMCR22 Series 2–3MCR25 SeriesMCR63A Series 2–9MCR64 2–9MCR65 Series 2–9MCR68 Series 2–6MCR69 Series 2–7MCR72 Series 2–6MCR100 Series 2–3MCR102–103 2–3MCR106 Series 2–4MCR218 Series 2–5MCR218FP 2–5MCR225FP Series 2–7MCR264 Series 2–8MCR265 2–9MCR310 Series 2–6MCR506 Series 2–5MCR703A Series 2–5MCR703A1 Series 2–4

“S” Devices (SCRs)S2800 Series 2–6

“T” Devices (TRIACs)T2322 Series 2–10T2323 Series 2–11T2500 Series 2–11T2500FP Series 2–12T2800 Series 2–13

MK Devices (SIDACs)MKP1V Series 2–21MKP3V Series 2–21

MBS Devices (SBS)MBS4991 Series 2–21

MMT DevicesMMT10V275MMT10V400

2–3Selector GuideMotorola Thyristor Device Data

New Products

High Performance T0–220

• Snubberless Triacs

This new series of devices is designed for high performance full–wave ac control applications where noise immunityand high dv/dt capability are required. Snubber networks can be reduced or eliminated in many cases which savesdesign time and money. Two levels of gate sensitivity and dv/dt are offered. Combined with our low cost / high qualityATLAS package these new triacs set a performance standard for the industry. Offerings include MAC8, MAC9,MAC12, MAC15, MAC16 series which are available at 400 – 800 volts.

• High Performance SCR’S

The MCR8, MCR8S, MCR12, MCR16, MCR25 series are the latest high performance, new generation thyristors fromMotorola. The devices are rated at 8, 12, 16, 25 Amperes and are available with voltage ranges of 400, 600, 800 Volts.They are designed primarily for half–wave a/c control applications, such as motor controls, heating controls andpower supplies or wherever half–wave silicon gate–controlled devices are needed. Minimum and maximum valuesare specified on critical parameters such as IGT, VGT, IH. The MCR8S series offers 200 µA IGT for applications wheredrive current is limited such as direct drive from an integrated circuit.

More to come . . . . . . . We have more planned for this exciting new series of High Performance Thyristors in’95 . . . 4 quadrant Triacs at 8–25 Amperes, sensitive gate 8 and 12 Ampere triacs, and sensitive gate 12 AmpereSCR’s . . . look for the next edition of this data book!!

High Voltage Bidirectional TVS Devices

MMT10V275 and MMT10V400 are designed to protect sensitive telecom switching equipment from overvoltagedamage induced by lightning, power line crossings, electrostatic discharge and induction. Designed to protect primarylines, applications include current loop lines in telephony and control systems, central office stations, repeaters,building and residence entrance terminals and electronic telecom equipment. These new devices offer surgecapability up to 100 amperes peak, high holding current and extended temperature operation in the blocking orconducting state of –40°C to +125°C. These surge suppressors are also immune from the wearout mechanisms thatcan be present in other non solid state technologies.

For more information . . . . . . . on any of these new products see sections 2 & 3 of this data book.

I (–)

V (–) V (+)IRRM VDRM

REVERSEBLOCKINGREGION

REVERSEAVALANCHE REGION

FORWARDBREAKOVERPOINT

FORWARDBLOCKINGREGION

IHIDRMVRRM

IT

I (+)

VT

Selector Guide2–2


SCRs

SiliconControlledRectifiers

Table 1. SCRs — General Purpose Plastic Packages0.8 to 55 Amperes RMS, 25 to 800 Volts

On–State (RMS) Current

0.8 AMP 1.5 AMPS

TC = 58°C TC = 80°C TC = 50°C

KG A

K

GA

A

KG A

Sensitive Gate VDRMCase 29–04

TO–226AA (TO–92) Style 10Case 318E

SOT–223 STYLE 10Case 29–04

TO–226AA (TO–92)Style 10

VDRMVRRM (Volts)

MCR1022N5060

BRX44/BRY55–30(4) 25

MCR1032N5061

BRX45/BRY55–60(4) MCR22–2 50

MCR100–3 2N5062

BRX46/BRY55–100(4) MCR22–3 100

MCR100–42N5064

BRX47/BRY55–200(4) MCR08BT1 MCR22–4 200

MCR100–6 BRX49/BRY55–400(4) MCR08DT1 MCR22–6 400

BRY55–500(4) 500

MCR100–8 BRY55–600(4) MCR08MT1 MCR22–8 600

Maximum Electrical Characteristics

10 15(1)150(3)

10 15(1)150(3)

ITSM (Amps)60 Hz

0.2 IGT (mA)

0.8 VGT (V)

–65 to+110

–40 to+125

–40 to+110

–40 to+125

TJ OperatingRange (°C)

(3) Exponential decay 2 µs wide at 5 time constants, f = 12 Hz.(4) European Part Numbers. Package is Case 29 with

Leadform 18. Case style is 3.Devices listed in bold, italic are Motorola preferred devices.


SCRs (continued)

Table 1. SCRs — General Purpose Plastic Packages (continued)


4 AMPS 6 AMPS

TC = 93°C TC = 30°C

G A K

A

GA

K

A

GA

K

A

G A K

A

VSensitive Gate Surface Mount Sensitive Gate

VDRMVRRM(Volts)

Case 77TO–225AA (TO–126)

Style 2

Case 369Style 5

Case 369AStyle 5


Style 2

50 MCR106–22N6237

C106F MCR506–2

100 MCR106–32N6238

C106A MCR703A1 MCR703A (5) MCR506–3

200 MCR106–42N6239

C106B MCR704A1 MCR704A (5) MCR506–4

400 MCR106–62N6240

C106D MCR706A1 MCR706A (5) MCR506–6

600 MCR106–82N6241

C106M MCR708A1 MCR708A (5) MCR506–8

800


ITSM (Amps)60 Hz

25 20 25 40

IGT (mA) 0.2 0.075 0.2

VGT (V) 1 0.8 1


–40 to+110

(5) Available in tape and reel — add RL suffix to part number.

Indicates UL Recognized — File #E69369

Devices listed in bold, italic are Motorola preferred devices.

Selector Guide2–4


SCRs (continued)



8 AMPS 10 AMPS

TC = 70°C TC = 83°C TC = 80°C TC = 75°C

KA

GK

AG

A

KAG

A

KA

G

A

High Performance

Isolated Sensitive Gate Sensitive GateVCase 221C–02

Style 2Case 221A–04

TO–220ABStyle 3

Case 221A–06TO–220AB

Style 3


Style 3

VDRMVRRM(Volts)

MCR72–2 50

MCR72–3 MCR310–3 100

MCR218–4FP MCR72–4 MCR310–4 200

MCR218–6FP MCR72–6 MCR8D MCR8SD MCR310–6 400

MCR218–8FP MCR72–8 MCR8M MCR8SM MCR310–8 600

MCR218–10FP MCR72–10 MCR8N MCR8SN MCR310–10 800


80 100 80 100 ITSM (Amps)60 Hz

25 0.2 15 0.2 IGT (mA)

1.5 1 1.5 VGT (V)

–40 to+125

–40 to+110

–40 to+125

–40 to+110


(5) Available in tape and reel — add RL suffix to part number.




SCRs (continued)



10 AMPS 12 AMPS 16 AMPS 25 AMPS

TC = 75°C TC = 80°C TC = 85°C

KA

G

A

KA

G

A

KA

G

A

V

Sensitive Gate High PerformanceVDRMVRRM(Volts)


Style 3


Style 3


Style 3

50 2N6504

100 S2800A 2N6505

200 S2800B 2N6506

400 S2800D MCR12D MCR16D MCR25D 2N6507

600 S2800M MCR12M MCR16M MCR25M 2N6508

800 S2800N MCR12N MCR16N MCR25N 2N6509


ITSM (Amps)60 Hz

100 150 300

IGT (mA) 15 20 30 40

VGT (V) 1.5 2.2 1.7 1 1.5


–40 to+100

–40 to+125


Selector Guide2–6


SCRs (continued)



25 AMPS 40 AMPS 55 AMPS

TC = 85°C TC = 80°C TC = 70°C

KA

A

KA

G KA

A

AG Isolated

AG

VCase 221A–04TO–220AB

Style 3

Case 221C–02Style 2


Style 3

VDRMVRRM(Volts)

MCR69–2 MCR225–2FP 50

MCR69–3 100

MCR225–4FP MCR264–4 MCR265–4 200

MCR69–6 MCR225–6FP MCR264–6 MCR265–6 400

MCR225–8FP MCR264–8 MCR265–8 600

MCR225–10FP MCR264–10 MCR265–10 800


(1)750(2) 300 400 550 ITSM (Amps)60 Hz

30 40 50 IGT (mA)

1.5 VGT (V)

–40 to+125


(2) Peak capacitor discharge current for tw = 1 ms. tw is defined as five time constants of an exponentially decaying current pulse(crowbar applications).


TRIACs



Table 2. TRIACs — General Purpose Plastic Packages0.6 to 40 Amperes, 200 to 800 Volts


0.6 AMP 0.8 AMPS 2.5 AMPS

TC = 50°C TC = 80°C TC = 70°C

MT1G

MT2

MT1

GMT2

MT2

GMT2 MT1

MT2

Sensitive Gate

VDRM(Volts)

Case 29–04TO–226AA (TO–92)

Style 12

Case 318EStyle 11SOT–223


Style 5

200 MAC97–4 MAC97A4 MAC97B4 MAC08BT1 T2322B

400 MAC97–6 MAC97A6 MAC97B6 MAC08DT1 T2322D

600 MAC97–8 MAC97A8 MAC97B8 MAC08MT1 T2322M


ITSM (Amps) 8 10 25

IGT @ 25°C (mA)MT2(+)G(+)MT2(+)G(–)MT2(–)G(–)MT2(–)G(+)

10101010

5557

3335

10101010

10101010

VGT @ 25°C (V)MT2(+)G(+)MT2(+)G(–)MT2(–)G(–)MT2(–)G(+)

222

2.5

0.82222

2.22.22.22.2


–40 to+110


Selector Guide2–8


TRIACs (continued)

Table 2. TRIACs (continued)


2.5 AMPS 4 AMPS 6 AMPS

TC = 70°C TC = 85°C TC = 80°C

GMT2 MT1

MT2

MT1MT2

MT2

Sensitive GateMT2

G


Style 5


Style 4

VDRM(Volts)

T2323B 2N6071 2N6071A 2N6071B T2500B 200

T2323D 2N6073 2N6073A 2N6073B T2500D 400

T2323M 2N6075 2N6075A 2N6075B T2500M 600

T2500N 800


25 30 60 ITSM (Amps)

25402540

30—30—

55510

3335

25602560


2.22.22.22.2

@ –40°C2.5—2.5—

@ –40°C2.52.52.52.5

2.52.52.52.5


–40 to+110

–40 to+100




TRIACs (continued)



6 AMPS 8 AMPS

TC = 80°C TC = 80°C TC = 70°C TC = 80°C

MT1MT2

G

MT1MT2

G

MT2

MT1MT2

G

Sensitive Gate

Isolated High Performance Isolated

VDRM(Volts)



Style 4


Style 4


200 T2500BFP MAC218–4MAC218A4

MAC218–4FPMAC218A4FP

400 T2500DFP MAC218–6MAC218A6

MAC8SD MAC8D MAC9D MAC218–6FPMAC218A6FP

600 T2500MFP MAC218–8MAC218A8

MAC8SM MAC8M MAC9M MAC218–8FPMAC218A8FP

800 T2500NFPMAC218–10MAC218A10

MAC8SN MAC8N MAC9N MAC218–10FPMAC218A10FP


ITSM (Amps) 100 70 80 100

IGT @ 25°C (mA)Min. Max.

IGT @ 25 C (mA)MT2(+)G(+)MT2(+)G(–)MT2(–)G(–)MT2(–)G(+)

25602560

505050

(1)75(1)

0.80.80.8—

5.05.05.0—

353535—

505050—

505050

(1)75(1)


2.52.52.52.5

222

(1)2.5(1)

0.450.450.45—

1.51.51.5—

1.51.51.5—

222

(1)2.5(1)


–40 to+100

–40 to+125

–40 to+110

–40 to+125

(1) Applied to A–version only. Non A–version is unspecified.



Selector Guide2–10


TRIACs (continued)



8 AMPS

TC = 80°C

MT1MT2

G

MT2

MT1MT2

G

Isolated

Sensitive Gate


Style 4

Case 221C–02Style 3 VDRM

(Volts)

2N63422N6346

T2800B MAC228–4MAC228A4

MAC229–4MAC229A4



200

2N63432N6347

T2800D MAC228–6MAC228A6

MAC229–6MAC229A6



400

2N63442N6348

T2800M MAC228–8MAC228A8

MAC229–8MAC229A8



600

2N63452N6349

MAC228–10MAC228A10

MAC229–10MAC229A10



800


100 80 ITSM (Amps)

50(6)75(6)

50(6)75(6)

25602560

555

(1)10(1)

101010

(1)20(1)

555

(1)10(1)

101010

(1)20(1)


2(6)2.5(6)

2.5(6)2.5(6)

2.52.52.52.5

222

(1)2.5(1)


–40 to+125

–40 to+100

–40 to+110


(1) Applied to A–version only. Non A–version is unspecified.(6) Denotes 2N6346–49 Series only.



TRIACs (continued)



10 AMPS 12 AMPS

TC = 70°C TC = 75°C TC = 85°C

MT1MT2

G

MT2

MT1MT2

GMT1

MT2G

MT2

MT1MT2

G

MT1MT2

G

MT2

GIsolated Sensitive Gate Isolated

VDRM(Volts)


Style 4



Style 4



Style 4

200 MAC210–4MAC210A4


MAC310–4MAC310A4


MAC212–4MAC212A4

400 MAC210–6MAC210A6


MAC310–6MAC310A6


MAC212–6MAC212A6

600 MAC210–8MAC210A8


MAC310–8MAC310A8


MAC212–8MAC212A8

800 MAC210–10MAC210A10


MAC310–10MAC310A10


MAC212–10MAC212A10


ITSM (Amps) 100


505050

(1)75(1)

555

(1)10(1)

505050

(1)75(1)


222

(1)2.5(1)


–40 to+125





TRIACs (continued)



12 AMPS 15 AMPS

TC = 80°C TC = 70°C TC = 90°C TC = 80°C TC = 90°C

MT1MT2

G

MT2

MT1MT2

GSensitive Gate

G

High PerformanceHigh

Performance Isolated


Style 4


Style 4


Style 4


Style 4

Case 221C–02Style 3 VDRM

(Volts)

2N6346A MAC15–4MAC15A4


200

2N6347A MAC12D MAC15D MAC15SD MAC15–6MAC15A6

MAC16D MAC15–6FPMAC15A6FP

400

2N6348A MAC12M MAC15M MAC15SM MAC15–8MAC15A8

MAC16M MAC15–8FPMAC15A8FP

600

2N6349A MAC12N MAC15N MAC15SN MAC15–10MAC15A10

MAC16N MAC15–10FPMAC15A10FP

800


120 150 120 150 ITSM (Amps)

Min. Max.IGT @ 25°C (mA)

50755075

353535—

0.80.80.8—

5.05.05.0—

505050

75(1)

505050—

505050

(1)75(1)

IGT @ 25 C (mA)MT2(+)G(+)MT2(+)G(–)MT2(–)G(–)MT2(–)G(+)

22.52

2.5

1.51.51.5—

0.450.450.45—

1.51.51.5—

222

2.5(1)

1.51.51.5—

222

(1)2.5(1)


–40 to+125

–40 to+110

–40 to+125






TRIACs (continued)



20 AMPS 25 AMPS 40 AMPS

TC = 75°C TC = 80°C TC = 75°C

MT1MT2

G MT1MT2

G

MT2

MT1MT2

G MT1MT2

MT2

IsolatedMT2

G IsolatedMT2

G

VDRM(Volts)



Style 4



Style 4

200 MAC320–4FPMAC320A4FP

MAC320–4MAC320A4

MAC321–4 MAC223–4FPMAC223A4FP

MAC223–4MAC223A4

MAC224–4MAC224A4


MAC320–6MAC320A6


MAC223–6MAC223A6

MAC224–6MAC224A6


MAC320–8MAC320A8


MAC223–8MAC223A8

MAC224–8MAC224A8


MAC320–10MAC320A10


MAC223–10MAC223A10

MAC224–10MAC224A10


ITSM (Amps) 150 250 350


505050

(1)75(1)

100100100—

505050

(1)75(1)


222

(1)2.5(1)

222—

222

(1)2.5(1)


–40 to+125






Thyristor Triggers

Table 3. SIDACs

High voltage trigger devices similar in operation to a Triac.Upon reaching the breakover voltage in either direction, thedevice switches to a low–voltage on–state.

VBO Volts

Device Type ITSM Amps Min Max

Case 267–03/1

MKP3V110MKP3V120MKP3V130

202020

100110120

120130140

Case 59–04/1

MKP1V120MKP1V130

44

110120

130140

Table 4. ProgrammableTable 6. UnijunctionTable 6. TransistorTable 6. — PUT

Similar to UJTs, except that IV, IP and intrinsic standoffvoltage are programmable (adjustable) by means of externalvoltage divider. This stabilizes circuit performance forvariations in device parameters. General operatingfrequency range is from 0.01 Hz to 10 kHz, making themsuitable for long–duration timer circuits.

IP IV

DeviceType

RG =10 kΩ

RG =1 MΩ

IGAO@ 40 VnA Max

RG =10 kΩ

RG =1 MΩ

µA MaxnA Max

µA Min µA Max

Plastic TO–92 (Case 29–04/16)

2N60272N6028

51

20.15

1010

7025

5025

Table 5. SiliconTable 7. BidirectionalTable 7. Switch (SBS)

This versatile trigger device exhibits highly symmetrical bi-directional switching characteristics which can be modifiedby means of a gate lead. Requires a gate trigger current ofonly 250 µAdc for triggering.

Device

VSVolts

IS IHDeviceType Min Max

ISµA Max

IHmA Max

Plastic TO–92/TO–226AA (Case 29–04/12)

MBS4991MBS4992MBS4993

67.57.5

1099

500120250

1.50.50.75

Table 6. High Voltage Bidirectional TVS DevicesPrimary Protection

Transient Voltage Suppression (TVS) devices are break-over–triggered crowbar protectors. Turn–off occurs when thesurge current falls below the holding current value.

Device Type ITSM AmpsVBR Volts

(Min)VBO Volts

(Max)

Case 416A–01

MMT10V275MMT10V400

100100

200265

275400

Thyristor Surge Suppressors–Secondary Protection

Package SO–8

MGSS150–1 30 AMP, 150 mA lh, Programmable BidirectionalSurge Suppressor


V (–) V (+)

I (+)

I (–)

ITM VTMIS

I (BO)

VDRM V(BO)

IDRMIH

VS

PEAK POINT

IFIVIPIGAO(0,0)

VPVS

VAKVFVV

IA

VALLEY POINT

V (–)IS

VSIH

V (+)

IS

VS

I (+)

IH

I (–)


Package 8 Pin PDIP

MGSS150–2 30 AMP, 150 mA lh, Programmable BidirectionalSurge Suppressor

• Telecom Line Card Protection• Dual Line Protection in a Single Package• 2 Package Choices• Bidirectional Capability• 30 AMP Surge• 150 mA lh• Low Gate Trigger Current

1

Data Sheets

2 Motorola Thyristor Device Data

Reverse Blocking Triode Thyristors

. . . Annular PNPN devices designed for high volume consumer applications such asrelay and lamp drivers, small motor controls, gate drivers for larger thyristors, andsensing and detection circuits. Supplied in an inexpensive plastic TO-226AA (TO-92)package which is readily adaptable for use in automatic insertion equipment.

• Sensitive Gate Trigger Current — 200 µA Maximum• Low Reverse and Forward Blocking Current — 50 µA Maximum, TC = 125°C• Low Holding Current — 5 mA Maximum• Passivated Surface for Reliability and Uniformity

MAXIMUM RATINGS (TJ = 25°C unless otherwise noted.)

Rating Symbol Value Unit

*Peak Repetitive Forward and Reverse Blocking Voltage(1)

(TJ = 25 to 125°C)(RGK = 1000 ohms) 2N5060

2N50612N50622N5064

VDRMor

VRRM 3060100200

Volts

On-State Current RMS(All Conduction Angles)

IT(RMS) 0.8 Amp

*Average On-State Current(TC = 67°C)(TC = 102°C)

IT(AV)0.510.255

Amp

*Peak Non-repetitive Surge Current, TA = 25°C(1/2 cycle, Sine Wave, 60 Hz)

ITSM 10 Amps

Circuit Fusing Considerations(t = 8.3 ms)

I2t 0.4 A2s

*Peak Gate Power, TA = 25°C PGM 0.1 Watt

*Average Gate Power, TA = 25°C PG(AV) 0.01 Watt

*Peak Forward Gate Current, TA = 25°C(300 µs, 120 PPS)

IFGM 1 Amp

*Peak Reverse Gate Voltage VRGM 5 Volts

*Indicates JEDEC Registered Data. (cont.)

1. VDRM and VRRM for all types can be applied on a continuous basis. Ratings apply for zero or negative gate voltage; however, positive gatevoltage shall not be applied concurrent with negative potential on the anode. Blocking voltages shall not be tested with a constant currentsource such that the voltage ratings of the devices are exceeded.

Preferred devices are Motorola recommended choices for future use and best overall value.


*Motorola preferred devices

CASE 29-04(TO-226AA)STYLE 10

SCRs0.8 AMPERES RMS30 thru 200 VOLTS

K

G

A

KG A

REV 1

3Motorola Thyristor Device Data

MAXIMUM RATINGS — continued


*Operating Junction Temperature Range @ Rated VRRM and VDRM TJ –65 to +125 °C

*Storage Temperature Range Tstg –65 to +150 °C

*Lead Solder Temperature(Lead Length 1/16″ from case, 10 s Max)

— +230* °C

THERMAL CHARACTERISTICS

Characteristic Symbol Max Unit

*Thermal Resistance, Junction to Case(1) RθJC 75 °C/W

Thermal Resistance, Junction to Ambient RθJA 200 °C/W

ELECTRICAL CHARACTERISTICS (TC = 25°C, RGK = 1000 Ω unless otherwise noted.), (2)

Characteristic Symbol Min Typ Max Unit

*Peak Repetitive Forward or Reverse Blocking Current(VAK = Rated VDRM or VRRM) TC = 25°C

TC = 125°C

IDRM, IRRM––

––

1050

µAµA

*Forward “On” Voltage(3)

(ITM = 1.2 A peak @ TA = 25°C)VTM – – 1.7 Volts

Gate Trigger Current (Continuous dc)(4)

*(Anode Voltage = 7 Vdc, RL = 100 Ohms) TC = 25°CTC = –65°C

IGT––

––

200350

µA

Gate Trigger Voltage (Continuous dc) TC = 25°C*(Anode Voltage = 7 Vdc, RL = 100 Ohms) TC = –65°C(Anode Voltage = Rated VDRM, RL = 100 Ohms) TC = 125°C

VGT

VGD

––

0.1

0.81.2–

Volts

Holding Current TC = 25°C*(Anode Voltage = 7 Vdc, initiating current = 20 mA) TC = –65°C

IH ––

––

510

mA

Turn-On TimeDelay TimeRise Time(IGT = 1 mA, VD = Rated VDRM,Forward Current = 1 A, di/dt = 6 A/µs

tdtr

––

30.2

––

µs

Turn-Off Time(Forward Current = 1 A pulse,Pulse Width = 50 µs,0.1% Duty Cycle, di/dt = 6 A/µs,dv/dt = 20 V/µs, IGT = 1 mA) 2N5060, 2N5061

2N5062, 5063, 5064

tq

––

1030

––

µs

Forward Voltage Application Rate(Rated VDRM, Exponential)

dv/dt – 30 – V/µs

*Indicates JEDEC Registered Data.

1. This measurement is made with the case mounted “flat side down” on a heat sink and held in position by means of a metal clamp over thecurved surface.

2. For electrical characteristics for gate-to-cathode resistance other than 1000 ohms see Motorola Bulletin EB-30.3. Forward current applied for 1 ms maximum duration, duty cycle 1%.4. RGK current is not included in measurement.


P (AV

), M

AXIM

UM

AVE

RAG

E PO

WER

DIS

SIPA

TIO

N (W

ATTS

)

5.0

0.05

0.01

0.02

0 0.5 1.0 1.5 2.0

3.0

2.5

vT, INSTANTANEOUS ON-STATE VOLTAGE (VOLTS)

0.07

0.03

0.1

0.2

0.3

0.5

0.7

1.0

2.0

5.0

25°C

TJ = 125°C

120

FIGURE 3 – TYPICAL FORWARD VOLTAGE

50

60

70

80

90

100

110

0 0.1 0.2 0.3 0.4

130

0.5

IT(AV), AVERAGE ON-STATE CURRENT (AMP)

α

dc

FIGURE 1 – MAXIMUM CASE TEMPERATURE

CURRENT DERATING

110

30

50

70

90

130

30

FIGURE 2 – MAXIMUM AMBIENT TEMPERATURE

dc

7.0

α

1.0

3.0

2.0

10

1.0 2.0 3.0 5.0 7.0 10 20 50 70

FIGURE 4 – MAXIMUM NON-REPETITIVE SURGE CURRENT

100

0

0.2

0.4

0.6

α

0.1 0.4

dc

0.8

0 0.2 0.5

FIGURE 5 – POWER DISSIPATION

α = CONDUCTION ANGLE

0.3

NUMBER OF CYCLES

0 0.1 0.2 0.3 0.4



T C, M

AXIM

UM

ALL

OW

ABLE

CAS

E TE

MPE

RAT

UR

E ( C

)°

i T, I

NST

ANTA

NEO

US

ON

-STA

TE C

UR

REN

T (A

MP)

I TSM

, PEA

K SU

RG

E C

UR

REN

T (A

MP)

T A, M

AXIM

UM

ALL

OW

ABLE

AM

BIEN

T°

TEM

PER

ATU

RE

( C

)

α = 30°

α = 30°

α = 30°

60°

60°

90°

90°

90°

120°

120°

120°

180°

180°

CASE MEASUREMENTPOINT – CENTER OFFLAT PORTION

60°

180°

TYPICAL PRINTEDCIRCUIT BOARDMOUNTING

α = CONDUCTION ANGLEα = CONDUCTION ANGLE


0.02 0.2 20105.02.01.00.050.010.002 0.005 0.5

0.02

0.01

0.5

0.1

0.05

0.1

0.2

t, TIME (SECONDS)

FIGURE 8 – GATE TRIGGER CURRENT

FIGURE 10 – CHARACTERISTICS AND SYMBOLSFIGURE 9 – HOLDING CURRENT

FIGURE 7 – GATE TRIGGER VOLTAGE

0.7

0.3

0.4

0.5

0.6

0.8VAK = 7.0 V

RL = 100RGK = 1.0 k

3.0

0.8

0.4

0.6

1.0

2.0

500–75 –50 –25

4.0

25 10075 125


FIGURE 6 – THERMAL RESPONSE

2N5060,61

2N5062-64

100

VAK = 7.0 VRL = 100

RGK = 1.0 k

0.2

0.5

1.0

2.0

5.0

10

20

50

200VAK = 7.0 V

RL = 100

2N5062-64

2N5060-61

TYPICAL CHARACTERISTICS

1.0

TYPICAL V – I CHARACTERISTICSBLOCKINGSTATE

+ V

A –

V– V

VRRM

ON STATEIH A +

VDRMIV

120V60 ~

LOADA

K

G

500–75 –50 –25 25 10075 125


500–75 –50 –25 25 10075 125


i

V G, G

ATE

TRIG

GER

VO

LTAG

E (V

OLT

S)

I GT,

GAT

E TR

IGG

ER C

UR

REN

T (N

OR

MAL

IZED

)

I H, H

OLD

ING

CU

RR

ENT

(NO

RM

ALIZ

ED)

i

NO

RM

ALIZ

EDr(t

), TR

ANSI

ENT

THER

MAL

RES

ISTA

NC

E


Silicon Programmable Unijunction Transistors

. . . designed to enable the engineer to ”program’’ unijunction characteristics such asRBB, η, IV, and IP by merely selecting two resistor values. Application includesthyristor–trigger, oscillator, pulse and timing circuits. These devices may also be usedin special thyristor applications due to the availability of an anode gate. Supplied in aninexpensive TO–92 plastic package for high–volume requirements, this package isreadily adaptable for use in automatic insertion equipment.

• Programmable — RBB, η, IV and IP.• Low On–State Voltage — 1.5 Volts Maximum @ IF = 50 mA• Low Gate to Anode Leakage Current — 10 nA Maximum• High Peak Output Voltage — 11 Volts Typical• Low Offset Voltage — 0.35 Volt Typical (RG = 10 k ohms)



*Power DissipationDerate Above 25°C

PF1/θJA

3004

mWmW/°C

*DC Forward Anode CurrentDerate Above 25°C

IT 1502.67

mAmA/°C

*DC Gate Current IG 50 mA

Repetitive Peak Forward Current100 µs Pulse Width, 1% Duty Cycle

*20 µs Pulse Width, 1% Duty Cycle

ITRM12

Amps

Non–repetitive Peak Forward Current10 µs Pulse Width

ITSM 5 Amps

*Gate to Cathode Forward Voltage VGKF 40 Volts

*Gate to Cathode Reverse Voltage VGKR –5 Volts

*Gate to Anode Reverse Voltage VGAR 40 Volts

*Anode to Cathode Voltage(1) VAK 40 Volts

Operating Junction Temperature Range TJ –50 to +100 °C


*Indicates JEDEC Registered Data

1. Anode positive, RGA = 1000 ohmsAnode negative, RGA = open



PUTs40 VOLTS300 mW

KGA

K

G

A


ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted.)

Characteristic Fig. No. Symbol Min Typ Max Unit

*Peak Current(VS = 10 Vdc, RG = 1 MΩ) 2N6027

2N6028(VS = 10 Vdc, RG = 10 k ohms) 2N6027

2N6028

2,9,11 IP————

1.250.08

40.70

20.15

51

µA

*Offset Voltage(VS = 10 Vdc, RG = 1 MΩ) 2N6027

2N6028(VS = 10 Vdc, RG = 10 k ohms) (Both Types)

1 VT0.20.20.2

0.700.500.35

1.60.60.6

Volts

*Valley Current(VS = 10 Vdc, RG = 1 MΩ) 2N6027

2N6028(VS = 10 Vdc, RG = 10 k ohms) 2N6027

2N6028(VS = 10 Vdc, RG = 200 ohms) 2N6027

2N6028

1,4,5 IV——70251.51

1818150150——

5025————

µA

mA

*Gate to Anode Leakage Current(VS = 40 Vdc, TA = 25°C, Cathode Open)(VS = 40 Vdc, TA = 75°C, Cathode Open)

— IGAO——

13

10—

nAdc

Gate to Cathode Leakage Current(VS = 40 Vdc, Anode to Cathode Shorted)

— IGKS — 5 50 nAdc

*Forward Voltage (IF = 50 mA Peak) 1,6 VF — 0.8 1.5 Volts

*Peak Output Voltage(VG = 20 Vdc, CC = 0.2 µF)

3,7 Vo 6 11 — Volt

Pulse Voltage Rise Time(VB = 20 Vdc, CC = 0.2 µF)

3 tr — 40 80 ns


FIGURE 1 – ELECTRICAL CHARACTERIZATION

K

GA

Programmable Unijunctionwith “Program” ResistorsR1 and R2

1A –

VAK

+VBIA

R1R1 + R2

R1

R2

– VS = VB

VAK

IA

+

VS

RG

RG = R1 R2R1 + R2

Equivalent Test Circuit forFigure 1A used for electricalcharacteristics testing(also see Figure 2)

1B –

FIGURE 2 – PEAK CURRENT (IP) TEST CIRCUIT FIGURE 3 – Vo AND t r TEST CIRCUIT

Adjustfor

Turn–onThreshold

100k1.0%

2N5270

VB0.01 µF

20

R

R

RG = R/2VS = VB/2(See Figure 1)

+

–IP (SENSE)100 µV = 1.0 nA

Scope

PutUnderTest

CC

510k 16k

27k

20 Ω

vo

+VB+V

Vo6 V

0.6 Vtf

t

IC – Electrical Characteristics

VA

VS

VFVV

–VP

IAIFIVIP

VT = VP – VS

IGAO


FIGURE 4 – EFFECT OF SUPPLY VOLTAGE FIGURE 5 – EFFECT OF TEMPERATURE

VS, SUPPLY VOLTAGE (VOLTS) TA, AMBIENT TEMPERATURE (°C)

I , V

ALLE

Y C

UR

REN

T (

A)

V

100

10

1000

105 15 20

500

5

10

0–50 +50 +100

100RG = 10 kΩ

100 kΩ

1 MΩ

–25 +25 +75

RG = 10 kΩ

100 kΩ

1 MΩ

µ

TYPICAL VALLEY CURRENT BEHAVIOR

FIGURE 6 – FORWARD VOLTAGE FIGURE 7 – PEAK OUTPUT VOLTAGE

IF, PEAK FORWARD CURRENT (AMP) VS, SUPPLY VOLTAGE (VOLTS)

V ,

PEAK

FO

RWAR

D V

OLT

AGE

(VO

LTS)

F

0.1

0.05

0.02

0.01

0.2

0.5

1.0

0.020.01 0.05 0.1

10

20

5.0

0

15

100 20 30

25

TA = 25°C

5.0 15 25

CC = 0.2 µF

1000 pF

V ,

PEAK

OU

TPU

T VO

LTAG

E (V

OLT

S)o

TA = 25°C(SEE FIGURE 3)

I , V

ALLE

Y C

UR

REN

T (

A)

Vµ

2.0

5.0

10

0.2 2.00.5 1.0 5.0 35 40

A

K

G

K

A

G

E

PN

NP

Circuit Symbol

B2

B1

R1

R2

R1R1 + R2

RBB = R1 + R2

η =

Equivalent Circuitwith External “Program”Resistors R1 and R2

FIGURE 8PROGRAMMABLE UNIJUNCTION

Typical Application

CC

RT

K

A G

R2

R1

+


FIGURE 9 – EFFECT OF SUPPLY VOLTAGE AND R G FIGURE 10 – EFFECT OF TEMPERATURE AND RG


I , P

EAK

CU

RR

ENT

( A

)P

1.0

0.5

0.30.2

0.1

2.03.0

5.0

10

105.0 15 20

1.0

0.5

20

0.2

0.1

2.0

50

5.0

10

0–50 +50 +100

100


RG = 10 kΩ

100 kΩ

VS = 10 VOLTS(SEE FIGURE 2)

1.0 MΩ

–25 +25 +75

RG = 10 kΩ

100 kΩ

1.0 MΩ

µ

I , P

EAK

CU

RR

ENT

( A

)P

µ

TYPICAL PEAK CURRENT BEHAVIOR

2N6027

FIGURE 11 – EFFECT OF SUPPLY VOLTAGE AND R G FIGURE 12 – EFFECT OF TEMPERATURE AND RG


I , P

EAK

CU

RR

ENT

( A

)P

0.1

0.05

0.030.02

0.01

0.20.3

0.5

1.0

105.0 15 20

0.1

0.05

2.0

0.02

0.01

0.2

5.0

0.5

1.0

0–50 +50 +100

10


RG = 10 kΩ

100 kΩVS = 10 VOLTS(SEE FIGURE 2)

1.0 MΩ

–25 +25 +75

RG = 10 kΩ

100 kΩ

1.0 MΩ

µ

I , P

EAK

CU

RR

ENT

( A

)P

µ

2N6028

0.07

0.7


Silicon Bidirectional Thyristors

. . . designed primarily for full-wave ac control applications, such as light dimmers,motor controls, heating controls and power supplies; or wherever full-wave silicongate controlled solid-state devices are needed. Triac type thyristors switch from ablocking to a conducting state for either polarity of applied anode voltage with positiveor negative gate triggering.

• Sensitive Gate Triggering (A and B versions) Uniquely Compatible for DirectCoupling to TTL, HTL, CMOS and Operational Amplifier Integrated Circuit LogicFunctions

• Gate Triggering 2 Mode — 2N6071, 2N6073, 2N60754 Mode — 2N6071,A,B, 2N6073,A,B, 2N6075,A,B

• Blocking Voltages to 600 Volts• All Diffused and Glass Passivated Junctions for Greater Parameter Uniformity

and Stability• Small, Rugged, Thermopad Construction for Low Thermal Resistance, High Heat

Dissipation and Durability



*Peak Repetitive Off-State Voltage(1)

(Gate Open, TJ = 25 to 110°C) 2N6071,A,B2N6073,A,B2N6075,A,B

VDRM200400600

Volts

*On-State Current RMS (TC = 85°C) IT(RMS) 4 Amps

*Peak Surge Current(One Full cycle, 60 Hz, TJ = –40 to +110°C)

ITSM 30 Amps


I2t 3.7 A2s

*Peak Gate Power PGM 10 Watts

*Average Gate Power PG(AV) 0.5 Watt

*Peak Gate Voltage VGM 5 Volts


1. VDRM for all types can be applied on a continuous basis. Blocking voltages shall not be tested with a constant current source such that thevoltage ratings of the devices are exceeded.



CASE 77-08(TO-225AA)

STYLE 5

TRIACs4 AMPERES RMS

200 thru 600 VOLTS


MT1

GMT2

MT1MT2G

MT2


MAXIMUM RATINGS


*Operating Junction Temperature Range TJ –40 to +110 °C


Mounting Torque (6-32 Screw)(1) — 8 in. lb.


1. Torque rating applies with use of compression washer (B52200F006). Mounting torque in excess of 6 in. lb. does not appreciably lowercase-to-sink thermal resistance. Main terminal 2 and heatsink contact pad are common.For soldering purposes (either terminal connection or device mounting), soldering temperatures shall not exceed +200°C, for 10 seconds.Consult factory for lead bending options.



*Thermal Resistance, Junction to Case RθJC 3.5 °C/W





*Peak Blocking Current(VD = Rated VDRM, gate open, TJ = 25°C)(TJ = 110°C)

IDRM——

——

102

µAmA

*On-State Voltage (Either Direction)(ITM = 6 A Peak)

VTM — — 2 Volts

*Peak Gate Trigger Voltage (Continuous dc)(Main Terminal Voltage = 12 Vdc, RL = 100 Ohms, TJ = –40°C)

MT2(+), G(+); MT2(–), G(–) All TypesMT2(+), G(–); MT2(–), G(+) 2N6071,A,B, 2N6073,A,B 2N6075,A,B

(Main Terminal Voltage = Rated VDRM, RL = 10 k ohms,TJ = 110°C)

MT2(+), G(+); MT2(–), G(–) All TypesMT2(+), G(–); MT2(–), G(+) 2N6071,A,B, 2N6073,A,B, 2N6075,A,B

VGT

——

0.20.2

1.41.4

——

2.52.5

——

Volts

*Holding Current (Either Direction)(Main Terminal Voltage = 12 Vdc, Gate Open, TJ = –40°C)(Initiating Current = 1 Adc) 2N6071, 2N6073, 2N6075,

2N6071A,B, 2N6073A,B, 2N6075A,B(TJ = 25°C) 2N6071, 2N6073, 2N6075

2N6071A,B, 2N6073A,B, 2N6075A,B

IH

————

————

70303015

mA

Turn-On Time (Either Direction)(ITM = 14 Adc, IGT = 100 mAdc)

ton — 1.5 — µs

Blocking Voltage Application Rate at Commutation@ VDRM, TJ = 85°C, Gate Open, ITM = 5.7 A,Commutating di/dt = 2.0 A/ms

dv/dt(c) — 5 — V/µs



QUADRANT(See Definition Below)

TypeIGT

@ TJ

ImA

IImA

IIImA

IVmA

Gate Trigger Current (Continuous dc)(Main Terminal Voltage = 12 Vdc RL = 100 ohms)

2N60712N6073

+25°C 30 — 30 —(Main Terminal Voltage = 12 Vdc, RL = 100 ohms) 2N6073

2N6075 –40°C 60 — 60 —

Maximum Value2N6071A2N6073A

+25°C 5 5 5 10Maximum Value 2N6073A

2N6075A –40°C 20 20 20 30

2N6071B2N6073B

+25°C 3 3 3 52N6073B2N6075B –40°C 15 15 15 20


SENSITIVE GATE LOGIC REFERENCE

IC Logic Firing QuadrantgFunctions I II III IV

TTL 2N6071ASeries

2N6071ASeries

HTL 2N6071ASeries

2N6071ASeries

CMOS (NAND) 2N6071BSeries

2N6071BSeries

CMOS (Buffer) 2N6071BSeries

2N6071BSeries

OperationalAmplifier

2N6071ASeries

2N6071ASeries

Zero VoltageSwitch

2N6071ASeries

2N6071ASeries

MBS100MBS4993MBS4991Part Number

General Lamp DimmerUsage

VS

IS

VS1 – VS2

TemperatureCoefficient

6.0 – 10 V 7.5 – 9.0 V 3.0 – 5.0 V

350 µA Max

0.5 V Max

250 µA Max

0.2 V Max

0.02%/°C Typ

100 – 400 µA

0.35 V Max

For 2N6071, 2N6073, 2N6075ELECTRICAL CHARACTERISTICS of RECOMMENDED

BIDIRECTIONAL SWITCHES

Trigger devices are recommended for gating on Triacs. They provide:

1. Consistent predictable turn-on points.2. Simplified circuitry.3. Fast turn-on time for cooler, more efficient and reliable operation.

QUADRANT DEFINITIONS



MT2(+)

MT2(–)

MT2(+), G(–) MT2(+), G(+)

MT2(–), G(–) MT2(–), G(+)

G(–) G(+)

SAMPLE APPLICATION:TTL-SENSITIVE GATE 4 AMPERE TRIAC

TRIGGERS IN MODES II AND III

0 V

–VEE VEE = 5.0 V

MC7400

14

7

+

510Ω

2N6071ALOAD

4115 VAC

60 Hz



140120100806040200–20–40–600.3

0.5

0.7

1.0

2.0 2.0

3.0

0.5

0.3

0.7

1.0

120

3.0

–60 –40 –20 0 20 40 60 80 100 140

OFF-STATE VOLTAGE = 12 VdcALL MODES


TJ, JUNCTION TEMPERATURE (°C)TJ, JUNCTION TEMPERATURE (°C)

120°

90°

30°

dc

0

2.0

4.0

8.0

6.0

4.03.02.01.0IT(RMS), RMS ON-STATE CURRENT (AMP)

3.0 00

2.0

4.0

6.0

0 1.0 2.0

8.0

4.0

α = 30°

60°

90°120°

180°dc


80

3.0

90

70

100

0 1.0 2.0

110

4.0

60°

120°

dc


α

α

α


α

70

80

3.0

100

0 1.0 2.0

90

α

α

110

120°

180°

dc

90°

α = 30°

α

α


4.0IT(RMS), RMS ON-STATE CURRENT (AMP)

180°

α = 30°

90°


60°

60°

T ,

CAS

E TE

MPE

RAT

UR

E (

C)

C°

T ,

CAS

E TE

MPE

RAT

UR

E (

C)

C°

P

, A

VER

AGE

POW

ER (W

ATTS

)(A

V)V

, G

ATE

TRIG

GER

VO

LTAG

E (N

OR

MAL

IZED

)G

TM

P

, A

VER

AGE

POW

ER (W

ATTS

)(A

V)I

, G

ATE

TRIG

GER

CU

RR

ENT

(NO

RM

ALIZ

ED)

GTM

FIGURE 1 – AVERAGE CURRENT DERATING FIGURE 2 – RMS CURRENT DERATING


FIGURE 5 – TYPICAL GATE-TRIGGER VOLTAGE


FIGURE 6 – TYPICAL GATE-TRIGGER CURRENT

α = 180°


, TR

ANSI

ENT

THER

MAL

IMPE

DAN

CE

(FIGURE 7 – MAXIMUM ON-STATE CHARACTERISTICS FIGURE 8 – TYPICAL HOLDING CURRENT

FIGURE 9 – MAXIMUM ALLOWABLE SURGE CURRENT


40

7.0

5.0

3.0

2.0

1.0

0.7

0.5

0.3

0.2

0.10 1.0 2.0 3.0 4.0 5.0

VTM, ON-STATE VOLTAGE (VOLTS)

TJ = 110°C

TJ = 25°C

3.0

2.0

1.0

0.7

0.5

0.3–60 –40 –20 0 20 40 60 80 100 120 140


GATE OPENAPPLIES TO EITHER DIRECTION

34

32

30

28

26

24

22

20

18

16

141.0 2.0 3.0 4.0 5.0 7.0 10

NUMBER OF FULL CYCLES

TJ = –40 to +110°Cf = 60 Hz

0.20.1 0.5 1.0 2.0 5.0 10 20 50 100 200 500 1.0 k 2.0 k 5.0 k 10 k

MAXIMUM

TYPICAL

0.1

0.2

0.5

1.0

2.0

3.0

5.0

10

0.3

t, TIME (ms)

I H, H

OLD

ING

CU

RR

ENT

(NO

RM

ALIZ

ED)

I TM

, ON

-STA

TE C

UR

REN

T (A

MP)

PEAK

SIN

EWAV

E C

UR

REN

T (A

MP)

Z θJC

(t)°C

/W)

30

20

10



. . . PNPN devices designed for high volume consumer applications such astemperature, light, and speed control; process and remote control, and warningsystems where reliability of operation is important.

• Passivated Surface for Reliability and Uniformity• Power Rated at Economical Prices• Practical Level Triggering and Holding Characteristics• Flat, Rugged, Thermopad Construction for Low Thermal Resistance, High Heat

Dissipation and Durability• Recommended Electrical Replacement for C106



*Repetitive Peak Forward and Reverse Blocking Voltage(1)

(1/2 Sine Wave) 2N6237(RGK = 1000 ohms, TC = –40 to +110°C) 2N6238

2N62392N62402N6241

VDRMor

VRRM

50100200400600

Volts

*Non–repetitive Peak Reverse Blocking Voltage(1/2 Sine Wave, RGK = 1000 ohms, 2N6237TC = –40° to +110°C) 2N6238

2N62392N62402N6241

VRSM100150250450650

Volts

*Average On–State Current(TC = –40 to + 90°C)(TC = +100°C)

IT(AV)2.61.6

Amps

*Surge On–State Current(1/2 Sine Wave, 60 Hz, TC = +90°C)(1/2 Sine Wave, 1.5 ms, TC = +90°C)

ITSM2535

Amps

Circuit Fusing(t = 8.3 ms)

I2t 2.6 A2s

*Peak Gate Power(Pulse Width = 10 µs, TC = 90°C)

PGM 0.5 Watts

*Indicates JEDEC Registered Data. (continued)




STYLE 2

SCRs4 AMPERES RMS50 thru 600 VOLTS

KA

G

A

KAG


MAXIMUM RATINGS — continued (TJ = 25°C unless otherwise noted.)

Rating UnitValueSymbol

*Average Gate Power(t = 8.3 ms, TC = 90°C)

PG(AV) 0.1 Watt

Peak Forward Gate Current IGM 0.2 Amp

Peak Reverse Gate Voltage VRGM 6 Volts



Mounting Torque(1) 6 in. lb.


Characteristic Symbol Min Max Unit

*Thermal Resistance, Junction to Case RθJC — 3 °C/W

Thermal Resistance, Junction to Ambient RθJA — 75 °C/W


ELECTRICAL CHARACTERISTICS (TC = 25°C and RGK = 1000 ohms unless otherwise noted.)


*Peak Forward or Reverse Blocking Current(VAK = Rated VDRM or VRRM) TC = 25°C

TC = 110°C

IDRM, IRRM——

——

10200

µAµA

*Peak Forward “On” Voltage(ITM = 8.2 A Peak, Pulse Width = 1 to 2 ms, 2% Duty Cycle)

VTM — — 2.2 Volts


(VAK = 12 Vdc, RL = 24 Ohms)*(VAK = 12 Vdc, RL = 24 Ohms, TC = –40°C)

IGT——

——

200500

µA

Gate Trigger Voltage (Continuous dc)(Source Voltage = 12 V, RS = 50 Ohms)

*(VAK = 12 Vdc, RL = 24 Ohms, TC = –40°C)

VGT — — 1 Volts

Gate Non–Trigger Voltage(VAK = Rated VDRM, RL = 100 Ohms, TC = 110°C)

VGD 0.2 — — Volts

Holding Current(VAK = 12 Vdc, IGT = 2 mA) TC = 25°C

*(Initiating On–State Current = 200 mA) TC = –40°C

IH——

——

510

mA

*Total Turn–On Time(Source Voltage = 12 V, RS = 6 k Ohms)(ITM = 8.2 A, IGT = 2 mA, Rated VDRM)(Rise Time = 20 ns, Pulse Width = 10 µs)

tgt — 2 — µs

Forward Voltage Application Rate(VD = Rated VDRM, TC = 110°C)

dv/dt — 10 — V/µs


1. Torque rating applies with use of compression washer (B52200F006 or equivalent). Mounting torque in excess of 6 in. lb. does not appreciablylower case-to-sink thermal resistance. Anode lead and heatsink contact pad are common. (See AN–209 B)For soldering purposes (either terminal connection or device mounting), soldering temperatures shall not exceed +200°C. For optimumresults an activated flux (oxide removing) is recommended.

2. Measurement does not include RGK current.


dc

106

82

94

110

102

98

0 0.8 1.6 2.4 3.2

90

4.0

IT(AV), AVERAGE FORWARD CURRENT (AMP)

86

90

50

30

110

FIGURE 1 – MAXIMUM CASE TEMPERATURE

0

FIGURE 2 – MAXIMUM AMBIENT TEMPERATURE


0.1 0.2 0.3 0.4

180°90°60°α = 30°

dc

C°

T ,

MAX

IMU

M A

LLO

WAB

LE C

ASE

TEM

PER

ATU

RE

( C

)

A°

T ,

MAX

IMU

M A

LLO

WAB

LE A

MBI

ENT

0.4 1.2 2.0 2.8 3.6

α0 π

f = 60 Hz

120°

70

0.5 0.6 0.7 0.8

180°90°60°α = 30°

α0 π

f = 60 Hz

TEM

PER

ATU

RE

( C

)


Silicon Bidirectional Triode Thyristors

. . . designed primarily for full-wave ac control applications, such as light dimmers,motor controls, heating controls and power supplies; or wherever full–wave silicongate controlled solid–state devices are needed. Triac type thyristors switch from ablocking to a conducting state for either polarity of applied anode voltage with positiveor negative gate triggering.

• Blocking Voltage to 800 Volts• All Diffused and Glass Passivated Junctions for Greater Parameter Uniformity

and Stability• Small, Rugged, Thermowatt Construction for Low Thermal Resistance, High Heat

Dissipation and Durability• Gate Triggering Guaranteed in Two Modes (2N6342, 2N6343, 2N6344, 2N6345)

or Four Modes (2N6346, 2N6347, 2N6348, 2N6349)• For 400 Hz Operation, Consult Factory• 12 Ampere Devices Available as 2N6342A thru 2N6349A



*Peak Repetitive Off–State Voltage(1)

(Gate Open, TJ = –40 to +110°C)1/2 Sine Wave 50 to 60 Hz, Gate Open 2N6342, 2N6346

2N6343, 2N63472N6344, 2N63482N6345, 2N6349

VDRM

200400600800

Volts

*RMS On–State Current (TC = +80°C)Full Cycle Sine Wave 50 to 60 Hz (TC = +90°C)

IT(RMS) 84

Amps

*Peak Non-repetitive Surge Current(One Full Cycle, 60 Hz, TC = +80°C)Preceded and followed by Rated Current

ITSM 100 Amps


I2t 40 A2s

*Peak Gate Power (TC = +80°C, Pulse Width = 2 µs) PGM 20 Watts

*Average Gate Power (TC = +80°C, t = 8.3 ms) PG(AV) 0.5 Watt

*Peak Gate Current IGM 2 Amps

*Peak Gate Voltage VGM 10 Volts




REV 1



STYLE 4

TRIACs8 AMPERES RMS

200 thru 800 VOLTS

MT1

G

MT2




*Thermal Resistance, Junction to Case RθJC 2.2 °C/W

ELECTRICAL CHARACTERISTICS (TC = 25°C, and Either Polarity of MT2 to MT1 Voltage, unless otherwise noted.)


*Peak Blocking Current(VD = Rated VDRM, gate open) TJ = 25°C

TJ = 100°C

IDRM——

——

102

µAmA

*Peak On–State Voltage(ITM = 11 A Peak; Pulse Width = 1 to 2 ms, Duty Cycle 2%)

VTM — 1.3 1.55 Volts

Gate Trigger Current (Continuous dc)(VD = 12 Vdc, RL = 100 Ohms)(Minimum Gate Pulse Width = 2 µs)

MT2(+), G(+) All TypesMT2(+), G(–) 2N6346 thru 49MT2(–), G(–) All TypesMT2(–), G(+) 2N6346 thru 49*MT2(+), G(+); MT2(–), G(–) TC = –40°C All Types*MT2(+), G(–); MT2(–), G(+) TC = –40°C 2N6346 thru 49

IGT

——————

12122035——

50755075100125

mA

Gate Trigger Voltage (Continuous dc)(VD = 12 Vdc, RL = 100 Ohms)(Minimum Gate Pulse Width = 2 µs)

MT2(+), G(+) All TypesMT2(+), G(–) 2N6346 thru 49MT2(–), G(–) All TypesMT2(–), G(+) 2N6346 thru 49*MT2(+), G(+); MT2(–), G(–) TC = –40°C All Types*MT2(+), G(–); MT2(–), G(+) TC = –40°C 2N6346 thru 49

(VD = Rated VDRM, RL = 10 k Ohms, TJ = 100°C)*MT2(+), G(+); MT2(–), G(–) All Types*MT2(+), G(–); MT2(–), G(–) 2N6346 thru 49

VGT

——————

0.20.2

0.90.91.11.4——

——

22.52

2.52.53

——

Volts

*Holding Current(VD = 12 Vdc, Gate Open) TC = 25°C(IT = 200 mA) *TC = –40°C

IH——

6—

4075

mA

* Turn-On Time(VD = Rated VDRM, ITM = 11 A, IGT = 120 mA,Rise Time = 0.1 µs, Pulse Width = 2 µs)

tgt — 1.5 2 µs

Critical Rate of Rise of Commutation Voltage(VD = Rated VDRM, ITM = 11 A, Commutating di/dt = 4.0 A/ms,Gate Unenergized, TC = 80°C)



FIGURE 1 – RMS CURRENT DERATING FIGURE 2 – ON-STATE POWER DISSIPATION

80

84

88

96

100

8.06.05.04.03.02.01.0IT(RMS), RMS ON-STATE CURRENT, (AMP)

0

2.0

00

IT(RMS), RMS ON-STATE CURRENT (AMP)

4.0

8.0

6.0

10

1.0 2.0 3.0 4.0 6.0 7.0 8.0

TJ 100°C60°

α = 180°

120°90°

T ,

CAS

E TE

MPE

RAT

UR

E (

C)

°C

P

, AV

ERAG

E PO

WER

(WAT

TS)

AV


α

α

α = 30°

60°90°

120°

180°

dc

92

7.0 5.0


α

α

dc

30°


FIGURE 3 – TYPICAL GATE TRIGGER VOLTAGE FIGURE 4 – TYPICAL GATE TRIGGER CURRENT

FIGURE 5 – ON-STATE CHARACTERISTICS FIGURE 6 – TYPICAL HOLDING CURRENT


12

3

QUADRANTS

QUADRANT 4

–60 20–20 0 40 60 80 100 120 140TJ, JUNCTION TEMPERATURE (°C)

0.4–40

0.6

0.8

1.0

1.2

1

TJ = 100°Cf = 60 Hz

1.0

1.4

1.6

1.8 50

30

20

10

7.0

5.0140120100806040200–20–40–60


02.0 3.0 5.0 7.0 10

NUMBER OF CYCLES

20

40

60

CYCLE

80

100

TJ = 100°C

0.5

0.7

1.0

0.1

25°C

vTM, INSTANTANEOUS ON-STATE VOLTAGE (VOLTS)

–40

0.80.4 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4

0.2

0.3

–60 –20 200 40 10080 140TJ, JUNCTION TEMPERATURE (°C)

12060

MAIN TERMINAL #2POSITIVE

2.0

20

10

7.0

5.0

3.0

3.0

5.0

7.0

10

2.0

20

30

50

100

70

OFF-STATE VOLTAGE = 12 V

234

GATE OPEN

MAIN TERMINAL #1 POSITIVE

V

, GAT

E TR

IGG

ER V

OLT

AGE

(VO

LTS)

QUADRANT

gti

,

INST

ANTA

NEO

US

ON

-STA

TE C

UR

REN

T (A

MP)

TM

I TSM

I ,

HO

LDIN

G C

UR

REN

T (m

A)H

I

, G

ATE

TRIG

GER

CU

RR

ENT

(mA)

GT

Surge is preceded and followed by rated current


, PEA

K SU

RG

E C

UR

REN

T (A

MP)


2.0 k 10 k20 5.0 k1.0 k500200100505.02.01.00.50.2

ZθJC(t) = r(t) • RθJC

0.02

0.05

0.2

0.1

0.5

1.0

t,TIME (ms)0.1

0.01

r(t),

TRAN

SIEN

T TH

ERM

AL R

ESIS

TAN

CE

(NO

RM

ALIZ

ED)

FIGURE 8 – TYPICAL THERMAL RESPONSE






Dissipation and Durability• Gate Triggering Guaranteed in Four Modes (2N6346A, 2N6347A, 2N6348A,

2N6349A)• For 400 Hz Operation, Consult Factory• 8 Ampere Devices Available as 2N6342 thru 2N6349



*Peak Repetitive Off-State Voltage(1)

(Gate Open, TJ = –40 to +110°C1/2 Sine Wave 50 to 60 Hz, Gate Open

2N6346A2N6347A2N6348A2N6349A

VDRM

200400600800

Volts

*RMS On-State Current (TC = +80°C)(Full Cycle Sine Wave 50 to 60 Hz) (TC = +95°C)

IT(RMS) 126

Amps

*Peak Non-repetitive Surge Current(One Full Cycle, 60 Hz, TC = +80°C)Preceded and Followed by Rated Current

ITSM 120 Amps

Circuit Fusing (t = 8.3 ms) I2t 59 A2s

*Peak Gate Power (TC = +80°C, Pulse Width = 2 µs) PGM 20 Watts

*Average Gate Power (TC = +80°C, t = 8.3 ms) PG(AV) 0.5 Watt

*Peak Gate Current IGM 2 Amps

*Peak Gate Voltage VGM ±10 Volts







STYLE 4

TRIACs12 AMPERES RMS200 thru 800 VOLTS

MT1

G

MT2




*Thermal Resistance, Junction to Case RθJC 2 °C/W

ELECTRICAL CHARACTERISTICS (TC = 25°C, unless otherwise noted.)


*Peak Blocking Current(VD = Rated VDRM, gate open) TJ = 25°C

TJ = 110°C

IDRM——

——

102

µAmA

*Peak On-State Voltage (Either Direction)(ITM = 17 A Peak; Pulse Width = 1 to 2 ms, Duty Cycle 2%)


Gate Trigger Current (Continuous dc)(VD = 12 Vdc, RL = 100 Ohms)

MT2(+), G(+)MT2(+), G(–) 2N6346A thru 2N6349AMT2(–), G(–) MT2(–), G(+) 2N6346A thru 2N6349A

*MT2(+), G(+); MT2(–), G(–) TC = –40°C *MT2(+), G(–); MT2(–), G(+) TC = –40°C 2N6346A thru 2N6349A

IGT

——————

661025——

50755075100125

mA

Gate Trigger Voltage (Continuous dc)(VD = 12 Vdc, RL = 100 ohms)

MT2(+), G(+) MT2(+), G(–) 2N6346A thru 2N6349AMT2(–), G(–) MT2(–), G(+) 2N6346A thru 2N6349A

*MT2(+), G(+); MT2(–), G(–) TC = –40°C *MT2(+), G(–); MT2(–), G(+) TC = –40°C 2N6346A thru 2N6349A

(VD = Rated VDRM, RL = 10 k ohms, TJ = 100°C)*MT2(+), G(+); MT2(–), G(–) *MT2(+), G(–); MT2(–), G(–) 2N6346A thru 2N6349A

VGT

——————

0.20.2

0.90.91.11.4——

——

22.52

2.52.53

——

Volts

Holding Current (Either Direction)(VD = 12 Vdc, Gate Open) TC = 25°C(IT = 200 mA) *TC = –40°C

IH——

6—

4075

mA

*Turn-On Time(VD = Rated VDRM, ITM = 17 A, IGT = 120 mA,Rise Time = 0.1 µs, Pulse Width = 2 µs)

tgt — 1.5 2 µs




FIGURE 1 – RMS CURRENT DERATING FIGURE 2 – ON-STATE POWER DISSIPATION

70

80

90

100

110

1412108.06.04.02.0

30°

dc

IT(RMS), RMS ON-STATE CURRENT, (AMP)

120°180°

90°

0


α

α4.0

00


8.0

16

12

20

2.0 4.0 6.0 8.0 10 12 14

TJ = 110°C

α

α


dc

60°α = 30°

60°

180°120°

90°

T ,

CAS

E TE

MPE

RAT

UR

E (

C)

°C

P

, AV

ERAG

E PO

WER

(WAT

TS)

AV



FIGURE 5 – ON-STATE CHARACTERISTICS FIGURE 6 – TYPICAL HOLDING CURRENT


12

3

QUADRANTS

QUADRANT 4

–60 20–20 0 40 60 80 100 120 140TJ, JUNCTION TEMPERATURE (°C)

0.4–40

0.6

0.8

1.0

1.2

1

TJ = 100°Cf = 60 Hz

1.0

1.4

1.6

1.8 50

30

20

10

7.0

5.0140120100806040200–20–40–60


02.0 3.0 5.0 7.0 10

NUMBER OF CYCLES

20

40

60

CYCLE

80

100

TJ = 100°C

0.5

0.7

1.0

0.1

25°C

vTM, MAXIMUM INSTANTANEOUS ON-STATE VOLTAGE (VOLTS)

–40

0.80.4 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4

0.2

0.3

–60 –20 200 40 10080 140TJ, JUNCTION TEMPERATURE (°C)

12060


2.0

20

10

7.0

5.0

3.0

3.0

5.0

7.0

10

2.0

20

30

50

100

70


234

GATE OPEN

MAIN TERMINAL #1 POSITIVE

V

, GAT

E TR

IGG

ER V

OLT

AGE

(VO

LTS)

QUADRANT

gti

,

INST

ANTA

NEO

US

ON

-STA

TE C

UR

REN

T (A

MP)

TM

I TSM

I ,

HO

LDIN

G C

UR

REN

T (m

A)H

I

, G

ATE

TRIG

GER

CU

RR

ENT

(mA)

GT



, PEA

K SU

RG

E C

UR

REN

T (A

MP)


2.0 k 10 k20 5.0 k1.0 k500200100505.02.01.00.50.2


0.02

0.05

0.2

0.1

0.5

1.0

t,TIME (ms)0.1

0.01

r(t),

TRAN

SIEN

T TH

ERM

AL R

ESIS

TAN

CE

(NO

RM

ALIZ

ED)

FIGURE 8 – TYPICAL THERMAL RESPONSE



. . . designed primarily for half-wave ac control applications, such as motor controls,heating controls and power supply crowbar circuits.

• Glass Passivated Junctions with Center Gate Fire for Greater ParameterUniformity and Stability

• Small, Rugged, Thermowatt Constructed for Low Thermal Resistance, High HeatDissipation and Durability

• Blocking Voltage to 800 Volts• 300 A Surge Current Capability



*Peak Forward and Reverse Blocking Voltage(1)

(Gate Open, TJ = 25 to 125°C) 2N65042N65052N65062N65072N65082N6509

VDRM, VRRM50100200400600800

Volts

Forward Current (TC = 85°C)(180° Conduction Angle)

IT(RMS)IT(AV)

2516

Amps

Peak Non-repetitive Surge Current — 8.3 ms(1/2 Cycle, Sine Wave) 1.5 ms

ITSM 300350

Amps

Forward Peak Gate Power PGM 20 Watts

Forward Average Gate Power PG(AV) 0.5 Watt

Forward Peak Gate Current IGM 2 Amps


Storage Temperature Range Tstg –40 to +150 °C

*THERMAL CHARACTERISTICS


Thermal Resistance, Junction to Case RθJC 1.5 °C/W




REV 1



STYLE 3


KA

G





*Peak Forward or Reverse Blocking Current(VAK = Rated VDRM or VRRM, Gate Open) TJ = 25°C

TJ = 125°C

IDRM, IRRM——

——

102

µAmA

*Forward “On” Voltage(1)

(ITM = 50 A)VTM — — 1.8 Volts

*Gate Trigger Current (Continuous dc) TC = 25°C(Anode Voltage = 12 Vdc, RL = 100 Ohms) TC = –40°C

IGT ——

—25

4075

mA

*Gate Trigger Voltage (Continuous dc)(Anode Voltage = 12 Vdc, RL = 100 Ohms, TC = –40°C)

VGT — 1 1.5 Volts

Gate Non-Trigger Voltage(Anode Voltage = Rated VDRM, RL = 100 Ohms, TJ = 125°C)


*Holding Current(Anode Voltage = 12 Vdc, TC = –40°C)

IH — 35 40 mA

* Turn-On Time(ITM = 25 A, IGT = 50 mAdc)

tgt — 1.5 2 µs

Turn-Off Time (VDRM = rated voltage)(ITM = 25 A, IR = 25 A)(ITM = 25 A, IR = 25 A, TJ = 125°C)

tq——

1535

——

µs

Critical Rate of Rise of Off-State Voltage(Gate Open, Rated VDRM, Exponential Waveform)



1. Pulse Test: Pulse Width 300 µs, Duty Cycle 2%.

CT ,

MAX

IMU

M C

ASE

TEM

PER

ATU

RE

( C

)°

dc180°

16

120

80

90

100

110

130

60°α = 30°

0 4.0 8.0 12 20


FIGURE 1 — AVERAGE CURRENT DERATING

IT(AV), ON-STATE FORWARD CURRENT (AMPS)

α

90°

P

, A

VER

AGE

POW

ER (W

ATTS

)(A

V)

180°

90°24

0

8.0

16

32

TJ = 125°C

dc60°α = 30°

FIGURE 2 — MAXIMUM ON-STATE POWER DISSIPATION

IT(AV), AVERAGE ON-STATE FORWARD CURRENT (AMPS)160 4.0 8.0 12 20


α


FIGURE 3 — MAXIMUM FORWARD VOLTAGE FIGURE 4 — MAXIMUM NON-REPETITIVE SURGE CURRENT

FIGURE 5 — CHARACTERISTICS AND SYMBOLS

FIGURE 6 — THERMAL RESPONSE

IT

1.0

0.02

0.03

0.050.070.1

100

0.2

0.3

0.50.7

0.2 0.3 0.5 1.0 2.0

25°C

125°C

0.4

0.1

ZθJC(t) = RθJC • r(t)

1 CYCLE

1.0

200SURGE IS PRECEDED ANDFOLLOWED BY RATED CURRENT

TC = 85°Cf = 60 Hz

NUMBER OF CYCLES

225

250

275

300

20

2.0 3.0 4.0 6.0 8.0 10

–I

+V

+I

–VIDRM

VDRMIRRM

VTIH

VRRMFORWARDBLOCKINGREGION



REVERSEAVALANCHEREGION

0.10

0.01

t, TIME (ms)3.0 5.0

175

0.2

0.3

0.5

0.7

7.0

5.0

1.0

2.0

10

50

3.0

20

30

70

vF, INSTANTANEOUS VOLTAGE (VOLTS)1.2 2.01.6 2.4 2.80.8

30 50 100 200 300 500 2.0 k10 3.0 k 5.0 k 10 k1.0 k

I

,

PEAK

SU

RG

E C

UR

REN

T (A

MP)

TSM

r(t),

TRAN

SIEN

T TH

ERM

AL R

ESIS

TAN

CE

(NO

RM

ALIZ

ED)

Fi ,

INST

ANTA

NEO

US

FOR

WAR

D C

UR

REN

T (A

MPS

)


I ,

HO

LDIN

G C

UR

REN

T (m

A)H

TYPICAL TRIGGER CHARACTERISTICS

1401201008060400–60

30

–20–40 20


50

20

10

5.0

40

0.9

1.1

0.8

0.7

0.6

0.5

0.4

7.0

1.0OFF-STATE VOLTAGE = 12 V

FIGURE 8 — GATE TRIGGER VOLTAGE

FIGURE 9 — HOLDING CURRENT

FIGURE 7 — GATE TRIGGER CURRENT

OFF-STATE VOLTAGE = 12 V30

50

20

10

5.0

40

7.0

1401201008060400–60 –20–40 20TJ, JUNCTION TEMPERATURE (°C)

1401201008060400–60 –20–40 20TJ, JUNCTION TEMPERATURE (°C)

I

, GAT

E TR

IGG

ER C

UR

REN

T (m

A)G

T

V

, G

ATE

TRIG

GER

VO

LTAG

E (V

OLT

S)G

T


PNPN devices designed for high volume, line–powered consumer applications suchas relay and lamp drivers, small motor controls, gate drivers for large thyristors, andsensing and detection circuits. Supplied in an inexpensive TO–226AA (TO–92)package which is readily adaptable for use in automatic insertion equipment.

• Sensitive Gate Trigger Current — 200 µA Maximum• Low Reverse and Forward Blocking Current — 100 µA Maximum, TC = 125°C• Low Holding Current — 5 mA Maximum• Glass–Passivated Surface for Reliability and Uniformity



Peak Repetitive Forward and Reverse Blocking Voltage BRX44(TJ = 25 to 125°C, RGK = 1000 Ω) BRX45

BRX46BRX47BRX49

VDRM, VRRM 3060100200400

Volts

Forward Current RMS(All Conduction Angles)

IT(RMS) 0.8 Amp

Peak Forward Surge Current, TA = 25°C(1/2 Cycle, Sine Wave, 60 Hz)

ITSM 8 Amps

Circuit Fusing Considerations, TA = 25°C(t = 8.3 ms)

I2t 0.15 A2s

Peak Gate Power — Forward, TA = 25°C PGM 0.1 Watt

Peak Gate Current Forward, TA = 25°C(300 µs, 120 PPS)

IGFM 1 Amp

Peak Gate Voltage — Reverse VGRM 5 Volts

Operating Junction Temperature Range @ RatedVRRM and VDRM

TJ –40 to +125 °C


Lead Solder Temperature(1.5 mm from case, 10 s max.)

+230 °C

*European part numbers only. Package is Case 29 with Leadform 18.




STYLE 3WITH TO–18 LEADFORM*

SCRs0.8 AMPERE RMS30 TO 400 VOLTS




Thermal Resistance, Junction to Case RθJC 75 °C/W


ELECTRICAL CHARACTERISTICS (TC = 25°C, RGK = 1000 Ω unless otherwise noted.)


Peak Forward Blocking Current(VD = Rated VDRM @ TC = 125°C)

IDRM — 100 µA

Peak Reverse Blocking Current(VR = Rated VRRM @ TC = 125°C)

IRRM — 100 µA

Forward “On’’ Voltage(1)

(ITM = 1 A Peak @ TA = 25°C)VTM — 1.7 Volts

Gate Trigger Current (Continuous dc)(2) TC = 25°C(Anode Voltage = 7 Vdc, RL = 100 Ohms)

IGT — 200 µA

Gate Trigger Voltage (Continuous dc) TC = 25°C(Anode Voltage = 7 Vdc, RL = 100 Ohms) TC = –40°C(Anode Voltage = Rated VDRM, RL = 100 Ohms) TC = 125°C

VGT ——0.1

0.81.2—

Volts

Holding Current TC = 25°C(Anode Voltage = 7 Vdc, initiating current = 20 mA) TC = –40°C

IH ——

510

mA

1. Forward current applied for 1 ms maximum duration, duty cycle 1%.2. RGK current is not included in measurement.

dc

120

50

60

90

130

110

100

0 0.1 0.2 0.3 0.4

80

0.5


70

90

70

50

30

110

FIGURE 1 – CURRENT DERATING(REFERENCE: CASE TEMPERATURE)

0

130

FIGURE 2 – CURRENT DERATING(REFERENCE: AMBIENT TEMPERATURE)




0.1 0.2 0.3 0.4


1801209060α = 30

180


1209060

α = 30

C°

T ,

MAX

IMU

M A

LLO

WAB

LE C

ASE

TEM

PER

ATU

RE

( C

)

°T

, M

AXIM

UM

ALL

OW

ABLE

AM

BIEN

TTE

MPE

RAT

UR

E (

C)

α α

C


PNPN devices designed for high volume, line–powered consumer applications suchas relay and lamp drivers, small motor controls, gate drivers for large thyristors, andsensing and detection circuits. Supplied in an inexpensive TO–226AA (TO–92)package which is readily adaptable for use in automatic insertion equipment.

• Sensitive Gate Trigger Current — 200 µA Maximum• Low Reverse and Forward Blocking Current — 100 µA Maximum, TC = 125°C• Low Holding Current — 5 mA Maximum• Glass–Passivated Surface for Reliability and Uniformity



Peak Repetitive Forward and Reverse Blocking Voltage(1)

(RGK = 1000 Ω, TJ = 25 to 125°C)Marking: BRY55–1 . . . BRY55–30Marking: BRY55–2 . . . BRY55–60Marking: BRY55–3 . . . BRY55–100Marking: BRY55–4 . . . BRY55–200Marking: BRY55–6 . . . BRY55–400Marking: BRY55–7 . . . BRY55–500Marking: BRY55–8 . . . BRY55–600

VRRM, VDRM

3060100200400500600

Volts

Forward Current RMS (All Conduction Angles) IT(RMS) 0.8 Amp


ITSM 8 Amps

Circuit Fusing Considerations, TA = 25°C(t = 8.3 ms)

I2t 0.15 A2s


Peak Gate Current Forward, TA = 25°C(300 µs, 120 PPS)

IGFM 1 Amp


Operating Junction Temperature Range @ Rated VRRM and VDRM TJ –40 to +125 °C


Lead Solder Temperature (1.5 mm from case, 10 s max.) +230 °C

*European part numbers only. Package is Case 29 with Leadform 18.




STYLE 3WITH TO–18 LEADFORM*

SCRs0.8 AMPERE RMS30 TO 600 VOLTS






ELECTRICAL CHARACTERISTICS (TC = 25°C, RGK = 1000 Ω unless otherwise noted.)


Peak Forward Blocking Current(VD = Rated VDRM @ TC = 125°C)

IDRM — 100 µA

Peak Reverse Blocking Current(VR = Rated VRRM @ TC = 125°C)

IRRM — 100 µA

Forward “On’’ Voltage(1)



IGT — 200 µA


VGT ——0.1

0.81.2—

Volts


IH ——

510

mA

1. Forward current applied for 1 ms maximum duration, duty cycle 1%.2. RGK current is not included in measurement.3. MARKING: BRY55–30 = BRY55–1

BRY55–60 = BRY55–2BRY55–100 = BRY55–3BRY55–200 = BRY55–4BRY55–400 = BRY55–6BRY55–500 = BRY55–7BRY55–600 = BRY55–8

dc

120

50

60

90

130

110

100

0 0.1 0.2 0.3 0.4

80

0.5


70

90

70

50

30

110


0

130





0.1 0.2 0.3 0.4


1801209060α = 30

180


1209060

α = 30

C°

T ,

MAX

IMU

M A

LLO

WAB

LE C

ASE

TEM

PER

ATU

RE

( C

)

°T

, M

AXIM

UM

ALL

OW

ABLE

AM

BIEN

TTE

MPE

RAT

UR

E (

C)

α α

C



. . . Glassivated PNPN devices designed for high volume consumer applications suchas temperature, light, and speed control; process and remote control, and warningsystems where reliability of operation is important.

• Glassivated Surface for Reliability and Uniformity• Power Rated at Economical Prices• Practical Level Triggering and Holding Characteristics• Flat, Rugged, Thermopad Construction for Low Thermal Resistance, High Heat





(RGK = 1 kΩ) C106F(TC = –40° to 110°C) C106A

C106BC106DC106M

VDRMor

VRRM

50100200400600

Volts

RMS Forward Current(All Conduction Angles)

IT(RMS) 4 Amps

Average Forward Current(TA = 30°C)

IT(AV) 2.55 Amps

Peak Non-repetitive Surge Current(1/2 Cycle, 60 Hz, TJ = –40 to +110°C)

ITSM 20 Amps

Circuit Fusing (t = 8.3 ms) I2t 1.65 A2s

Peak Gate Power PGM 0.5 Watt

Average Gate Power PG(AV) 0.1 Watt

Peak Forward Gate Current IGFM 0.2 Amp

1. VDRM and VRRM for all types can be applied on a continuous basis. Ratings apply for zero or negative gate voltage; however, (cont.)positive gate voltage shall not be applied concurrent with negative potential on the anode. Blocking voltages shall not be tested with aconstant current source such that the voltage ratings of the devices are exceeded.




STYLE 2


KA

G

KA

G

A





Peak Reverse Gate Voltage VGRM 6 Volts



Mounting Torque(1) — 6 in. lb.

1. Torque rating applies with use of compression washer (B52200F006). Mounting torque in excess of 6 in. lb. does not appreciably lowercase-to-sink thermal resistance. Anode lead and heatsink contact pad are common. For soldering purposes (either terminal connection or device mounting), soldering temperatures shall not exceed +200°C. For optimumresults, an activated flux (oxide removing) is recommended.

THERMAL CHARACTERISTICS (TC = 25°C, RGK = 1 kΩ unless otherwise noted.)






Peak Forward or Reverse Blocking Current(VAK = Rated VDRM or VRRM, RGK = 1000 Ohms) TJ = 25°C

TJ = 110°C

IDRM, IRRM——

——

10100

µAµA

Forward “On” Voltage(IFM = 1 A Peak)


Gate Trigger Current (Continuous dc)(VAK = 6 Vdc, RL = 100 Ohms)(VAK = 6 Vdc, RL = 100 Ohms, TC = –40°C)

IGT——

3075

200500

µA

Gate Trigger Voltage (Continuous dc)(VAK = 6 Vdc, RL = 100 Ohms, RGK = 1000 Ohms) TJ = 25°C(VAK = Rated VDRM, RL = 3000 Ohms,RGK = 1000 Ohms, TJ = 110°C) TJ = –40°C

VGT0.40.50.2

———

0.81—

Volts

Holding Current TJ = 25°C(VD = 12 Vdc, RGK = 1000 Ohms) TJ = –40°C

TJ = +110°C

IHX 0.30.40.14

———

362

mA

Forward Voltage Application Rate(TJ = 110°C, RGK = 1000 Ohms, VD = Rated VDRM)


Turn-On Time tgt — 1.2 — µs

Turn-Off Time tq — 40 — µs

DC

DC

JUNCTION TEMPERATURE ≈ 110°C100

1020

30

40

70

110

90

3.6

80

0 .4 .8 1.61.2 2.0 2.4 3.2

60

4.0

IT(AV) AVERAGE ON-STATE CURRENT (AMPERES)

HALF SINE WAVERESISTIVE OR INDUCTIVE LOAD.50 to 400 Hz

50

6

4

2

0

8

FIGURE 1 – AVERAGE CURRENT DERATING

0

10

2.8

FIGURE 2 – MAXIMUM ON-STATE POWER DISSIPATION

3.6.4 .8 1.61.2 2.0 2.4 3.2 4.02.6

IT(AV) AVERAGE ON-STATE CURRENT (AMPERES)

HALF SINE WAVERESISTIVE OR INDUCTIVE LOAD50 TO 400Hz.

C°

T ,

CAS

E TE

MPE

RAT

UR

E (

C)

P

, A

VER

AGE

ON

-STA

TE P

OW

ER D

ISSI

PATI

ON

(WAT

TS)

(AV)


Package Interchangeability

The dimensional diagrams below compare the critical dimensions of the Motorola C-106 packagewith competitive devices. It has been demonstrated that the smaller dimensions of the Motorolapackage make it compatible in most lead-mount and chassis-mount applications. The user isadvised to compare all critical dimensions for mounting compatibility.

Motorola C-106 Package Competitive C-106 Package

.315____

.285

.105____

.095

.054____

.046

.420____

.400

.400____

.360

.385____

.365

.135____

.115

.520____

.480

.127____

.123DIA

.105____

.095.190____.170

.026____

.019

.025____

.035

.295____

.305

.148____

.158

.115____

.130

.015____

.025

.050____

.095

.145____

.155

5 TYP.425____.435

.575____

.655

.020____

.026

1 2 3

.045____

.055

.095____

.105

.040

.094 BSC



. . . designed primarily for full-wave ac control applications, such as motor controls,heating controls and power supplies; or wherever half–wave silicon gate–controlled,solid–state devices are needed.

• Glass Passivated Junctions and Center Gate Fire for Greater ParameterUniformity and Stability

• Small, Rugged, Thermowatt Construction for Low Thermal Resistance, High HeatDissipation and Durability

• Blocking Voltage to 800 Volts• Different Leadform Configurations,

Suffix (2) thru (6) available, see Leadform Options (Section 4) for Information



Repetitive Peak Off–State Voltage(1) (TJ = 25 to 100°C, Gate Open)Repetitive Peak Reverse Voltage C122F1

C122A1C122B1C122D1C122M1C122N1

VDRMVRRM 50

100200400600800

Volts

Peak Non–repetitive Reverse Voltage(1)

C122F1C122A1C122B1C122D1C122M1C122N1

VRSM75200300500700800

Volts

Forward Current RMS TC 75°C(All Conduction Angles)

IT(RMS) 8 Amps

Peak Forward Surge Current(1/2 Cycle, Sine Wave, 60 Hz)

ITSM 90 Amps


I2t 34 A2s

1. VDRM and VRRM for all types can be applied on a continuous basis. Ratings apply for zero or negative gate voltage; however, (cont.)positive gate voltage shall not be applied concurrent with negative potential on the anode. Blocking voltages shall not be tested with aconstant current source such that the voltage ratings of the devices are exceeded.



STYLE 3


A KG




Forward Peak Gate Power (t = 10 µs) PGM 5 Watts










Peak Forward or Reverse Blocking Current(VAK = Rated VDRM or VRRM, Gate Open) TC = 25°C

TC = 100°C

IDRM, IRRM——

——

100.5

µAmA

Peak On–State Voltage(1)

(ITM = 16 A Peak, TC = 25°C)VTM — — 1.83 Volts

Gate Trigger Current (Continuous dc)(VD = 6 V, RL = 91 Ohms, TC = 25°C)(VD = 6 V, RL = 45 Ohms, TC = –40°C)

IGT——

——

2540

mA

Gate Trigger Voltage (Continuous dc)(VD = 6 V, RL = 91 Ohms, TC = 25°C)(VD = 6 V, RL = 45 Ohms, TC = –40°C)(VD = Rated VDRM, RL = 1000 Ohms, TC = 100°C)

VGT——0.2

———

1.52—

Volts

Holding Current(VD = 24 Vdc, IT = 0.5 A, 0.1 to 10 ms Pulse,Gate Trigger Source = 7 V, 20 Ohms) TC = 25°C

TC = –40°C

IH

——

——

3060

mA

Turn-Off Time (VD = Rated VDRM)(ITM = 8 A, IR = 8 A)

tq — 50 — µs

Critical Rate–of–Rise of Off–State Voltage(VD = Rated VDRM, Linear, TC = 100°C)


1. Pulse Test: Pulse Width = 1 ms, Duty Cycle 2%.

FIGURE 1 – CURRENT DERATING (HALF–WAVE) FIGURE 2 – CURRENT DERATING (FULL–WAVE)

100

90

80

70

600 1 2 3 4 5 6 7 8T

, M

AXIM

UM

ALL

OW

ABLE

CAS

E TE

MPE

RAT

UR

E (

C)

C°

IT(AV), AVERAGE ON–STATE FORWARD CURRENT (AMPERES)

CONDUCTIONANGLE = 30°

60° 90° 120° 180°

DC

CONDUCTIONANGLE

3600

100

95

90

85

80

75

70

65

600 1 2 3 4 5 6 7 8T

, M

AXIM

UM

ALL

OW

ABLE

CAS

E TE

MPE

RAT

UR

E (

C)

C°

IT(AV), AVERAGE ON–STATE CURRENT (AMPERES)


240° 360°120° 180°

CONDUCTIONANGLE

3600

RESISTIVE ORINDUCTIVE LOAD.50 TO 400 Hz

CONDUCTIONANGLE

ONE CYCLE OF SUPPLYFREQUENCY


FIGURE 3 – MAXIMUM POWER DISSIPATION(HALF–WAVE)

FIGURE 4 – MAXIMUM POWER DISSIPATION(FULL–WAVE)

14

6

4

2

00 1 2 3 4 5 6 7 8


CONDUCTIONANGLE 30°

8

10

12 DC

180°120°

90°60°

P, A

VER

AGE

ON

–STA

TE P

OW

ER D

ISSI

PATI

ON

(WAT

TS)

10

8

6

4

2

00 1 2 3 4 5 6 7 8T

, A

VER

AGE

ON

–STA

TE P

OW

ER D

ISSI

PATI

ON

(WAT

TS)

C



240° 360°

120°

180°

CONDUCTIONANGLE

3600

RESISTIVE OR INDUCTIVE LOAD, 50 TO 400 Hz

CONDUCTIONANGLE

ONE CYCLE OF SUPPLYFREQUENCY

RESISTIVE OR INDUCTIVE LOAD, 50 TO 400 Hz

(AV)



Designed for use in solid state relays, MPU interface, TTL logic and other lightindustrial or consumer applications. Supplied in surface mount package for use inautomated manufacturing.

• Sensitive Gate Trigger Current in Four Trigger Modes• Blocking Voltage to 600 Volts• Glass Passivated Surface for Reliability and Uniformity• Surface Mount Package• Devices Supplied on 1 K Reel

MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)


Peak Repetitive Blocking Voltage(1)

(1/2 Sine Wave, Gate Open, TJ = 25 to 110°C)MAC08BT1MAC08DT1MAC08MT1

VDRM

200400600

Volts

On–State Current RMS (TC = 80°C) IT(RMS) 0.8 Amps

Peak Non–repetitive Surge Current(One Full Cycle, 60 Hz, TC = 25°C)

ITSM 10 Amps

Circuit Fusing Considerations (t = 8.3 ms) I2t 0.4 A2s

Peak Gate Power (t 2.0 µs) PGM 5.0 Watts

Average Gate Power (TC = 80°C, t = 8.3 ms) PG(AV) 0.1 Watts



Maximum Device Temperature for Soldering Purposes (for 5 Seconds Maximum) TL 260 °C



Thermal Resistance, Junction to AmbientPCB Mounted per Figure 1

RθJA 156 °C/W

Thermal Resistance, Junction to TabMeasured on Anode Tab Adjacent to Epoxy

RθJT 25 °C/W




CASE 318E–04(SOT–223)STYLE 11

TRIAC0.8 AMPERE RMS200 thru 600 Volts


REV 1


ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted)


Peak Repetitive Blocking Current(VD = Rated VDRM Gate Open) TJ = 25°C

TJ = 110°C

IDRM——

——

10200

µAµA

Maximum On–State Voltage (Either Direction)(IT = 1.1 A Peak, TA = 25°C)


Gate Trigger Current (Continuous dc) All Quadrants(VD = 7.0 Vdc, RL = 100 Ω)

IGT — — 10 mA

Holding Current (Either Direction) (VD = 7.0 Vdc, Gate Open,Initiating Current = 20 mA, Gate Open)

IH — — 5.0 mA

Gate Trigger Voltage (Continuous dc) All Quadrants(VD = 7.0 Vdc, RL = 100 Ω)

VGT — — 2.0 Volts

Critical Rate of Rise of Commutation Voltage(f = 250 Hz, ITM = 1.0 A, Commutating di/dt = 1.5 A/mSOn–State Current Duration = 2.0 mS, VDRM = 200 V,Gate Unenergized, TC = 110°C,Gate Source Resistance = 150 Ω, See Figure 10)

dv/dtc 1.5 — — V/µs

Critical Rate–of–Rise of Off State Voltage(Vpk = Rated VDRM, TC= 110°C, Gate Open, Exponential Method)

dv/dt 10 — — V/µs

Figure 1. PCB for Thermal Impedance andPower Testing of SOT-223

0.0792.0

0.0792.0

0.0591.5

0.0912.3

0.0912.3

mminches

0.47212.0

0.0962.44

BOARD MOUNTED VERTICALLY IN CINCH 8840 EDGE CONNECTOR.BOARD THICKNESS = 65 MIL., FOIL THICKNESS = 2.5 MIL.

MATERIAL: G10 FIBERGLASS BASE EPOXY0.98425.0

0.2446.2

0.0591.5

0.0591.5

0.0962.44

0.0962.44

0.0591.5

0.0591.5

0.153.8


T A, M

AXIM

UM

ALL

OW

ABLE

AMBI

ENT

TEM

PER

ATU

RE

( C

)°

110

100

90

80

60

50

70

IT(RMS), RMS ON-STATE CURRENT (AMPS)

110

100

90

80

60

50

40

30

20

70

T A, M

AXIM

UM

ALL

OW

ABLE

AMBI

ENT

TEM

PER

ATU

RE

( C

)°

Figure 2. On-State Characteristics Figure 3. Junction to Ambient ThermalResistance versus Copper Tab Area

Figure 4. Current Derating, Minimum Pad SizeReference: Ambient Temperature

Figure 5. Current Derating, 1.0 cm Square PadReference: Ambient Temperature

FOIL AREA (cm2)

θJA

, JU

NC

TIO

N T

O A

MBI

ENT

THER

MAL

vT, INSTANTANEOUS ON-STATE VOLTAGE (VOLTS)

I T, I

NST

ANTA

NEO

US

ON

-STA

TE C

UR

REN

T (A

MPS


Figure 6. Current Derating, 2.0 cm Square PadReference: Ambient Temperature

10

1.0

0.1

0.015.04.03.02.0

30

60708090

160

2.00

110

0.50.30.20.10


0.70.60.50.40.30.20.10

0.50.40.30.20.10

1.00 4.0 6.0 8.0 10

100

90

80

60

50

40

30

20

0.6 0.7 0.8

RES

ISTA

NC

E,

C/W

°

150140130120110

4050

100

TYPICALMAXIMUM

4

1 2 3

MINIMUMFOOTPRINT = 0.076 cm2

DEVICE MOUNTED ONFIGURE 1 AREA = L2PCB WITH TAB AREAAS SHOWN

0.4

70T A

, MAX

IMU

M A

LLO

WAB

LEAM

BIEN

T TE

MPE

RAT

UR

E (

C)

°dc

30°60°

90°

α = 180°

dc

30°

MINIMUM FOOTPRINT50 OR 60 Hz

120°

T (ta

b), M

AXIM

UM

ALL

OW

ABLE

TAB

TEM

PER

ATU

RE

( C

)°

110

105

100

95

90

85

80

IT(RMS), ON-STATE CURRENT (AMPS)

Figure 7. Current DeratingReference: MT2 Tab

0.50.40.30.20.10 0.6 0.7 0.8

120°

dc

30°

120°

R

L

L

90°

120°

90°

60°30°

90°

TYPICAL AT TJ = 110°CMAX AT TJ = 110°CMAX AT TJ = 25°C

60°

α = 180°

1.0 cm2 FOIL AREA50 OR 60 Hz

dc

α = 180°α = 180°

REFERENCE: FIGURE 1

60°

αα

αα

α = CONDUCTIONANGLE

αα

αα4.0 cm2 FOIL AREA





CO

MM

UTA

TIN

G d

v/dt

dv/d

t ,

(V/

S)

cµ

Figure 8. Power Dissipation

P (AV

), M

AXIM

UM

AVE

RAG

EPO

WER

DIS

SIPA

TIO

N (W

ATTS

)

1.0

0.8

0.7

0.5

0.4

0.2

0


Figure 9. Thermal Response, DeviceMounted on Figure 1 Printed Circuit Board

0.50.40.30.20.10 0.6 0.7 0.8

dc 90°

120°

10

1.0

di/dtc, RATE OF CHANGE OF COMMUTATING CURRENT (A/mS)

Figure 10. Simplified Q 1 (dv/dt) c Test Circuit

t, TIME (SECONDS)

r(t),

TRAN

SIEN

T TH

ERM

AL

Figure 11. Typical Commutating dv/dt versusCurrent Crossing Rate and Junction Temperature

0.01

1.0

0.0010.0001

1.0

0.01 0.1 10 100

10

RES

ISTA

NC

E (N

OR

MAL

IZED

)

0.1

10

1.0


Figure 12. Typical Commutating dv/dt versusJunction Temperature at 0.8 Amps RMS

90807060 100 110

VDRM = 200 V

400 Hz

300 Hz

0.9

0.6

0.3

0.1

1.0

CHARGECONTROL

TRIG

GER

CO

NTR

OL

75 VRMS,ADJUST FOR

ITM, 60 Hz VAC

CHARGE5 µF

NON-POLAR

80 mHYLL

MEASURE I

1N914 51

2

1

RS 56

0.047 CSADJUST FORdv/dt(c)

1N4007

200 V

C LG

110°

VDRM

ITM

60 Hz

tw

30°

TRIGGER

Component values are for verification of rated (dv/dt)c. See AN1048 for additional information.

f =1

2 tw

CO

MM

UTA

TIN

G d

v/dt

dv/d

t ,

(V/

S)

cµ

60°80°180 Hz

α = 180° 60°

(didt)c 6f ITM1000

100°

αα



STAT

IC d

v/dt

(V/

s)

60

20

RG, GATE – MAIN TERMINAL 1 RESISTANCE (OHMS)

Figure 13. Exponential Static dv/dt versus Gate – Main Terminal 1 Resistance

10 10,000

HO

LDIN

G C

UR

REN

T (m

A)

6.0

0


Figure 14. Typical Gate Trigger Current Variation


Figure 15. Typical Holding Current Variation

0.1

10

0– 40

– 40

20 100

I

1.0

V

, G

ATE

TRIG

GER

VO

LTAG

E (V

OLT

S)

1.1

0.3


Figure 16. Gate Trigger Voltage Variation

– 40

µ

GT

600 VpkTJ = 110°C

IGT4IGT1

50

40

30

1000100

5.0

4.0

3.0

2.0

1.0

IGT3

IGT2

GT,

GAT

E TR

IGG

ER C

UR

REN

T (m

A)

I , H

– 20 40 60 80

0 20 100– 20 40 60 80 0 20 100– 20 40 60 80

VGT2VGT1

VGT3VGT4






INFORMATION FOR USING THE SOT-223 SURFACE MOUNT PACKAGE

MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS

Surface mount board layout is a critical portion of the totaldesign. The footprint for the semiconductor packages mustbe the correct size to insure proper solder connection

interface between the board and the package. With thecorrect pad geometry, the packages will self align whensubjected to a solder reflow process.

SOT-223

0.0792.0

0.153.8

0.2486.3

0.0792.0

0.0591.5

0.0591.5

0.0591.5

0.0912.3

0.0912.3

mm

inches

SOT-223 POWER DISSIPATION

The power dissipation of the SOT-223 is a function of theMT2 pad size. This can vary from the minimum pad size forsoldering to a pad size given for maximum power dissipation.Power dissipation for a surface mount device is determinedby TJ(max), the maximum rated junction temperature of thedie, RθJA, the thermal resistance from the device junction toambient, and the operating temperature, TA. Using thevalues provided on the data sheet for the SOT-223 package,PD can be calculated as follows:

PD =TJ(max) – TA

RθJA

The values for the equation are found in the maximumratings table on the data sheet. Substituting these values intothe equation for an ambient temperature TA of 25°C, one cancalculate the power dissipation of the device which in thiscase is 550 milliwatts.

PD = 110°C – 25°C = 550 milliwatts156°C/W

The 156°C/W for the SOT-223 package assumes the useof the recommended footprint on a glass epoxy printed circuitboard to achieve a power dissipation of 550 milliwatts. Thereare other alternatives to achieving higher power dissipationfrom the SOT-223 package. One is to increase the area ofthe MT2 pad. By increasing the area of the MT2 pad, thepower dissipation can be increased. Although one canalmost double the power dissipation with this method, onewill be giving up area on the printed circuit board which candefeat the purpose of using surface mount technology. Agraph of RθJA versus MT2 pad area is shown in Figure 3.

Another alternative would be to use a ceramic substrate oran aluminum core board such as Thermal Clad . Using aboard material such as Thermal Clad, an aluminum coreboard, the power dissipation can be doubled using the samefootprint.

SOLDER STENCIL GUIDELINES

Prior to placing surface mount components onto a printedcircuit board, solder paste must be applied to the pads. Asolder stencil is required to screen the optimum amount ofsolder paste onto the footprint. The stencil is made of brass

or stainless steel with a typical thickness of 0.008 inches.The stencil opening size for the SOT-223 package should bethe same as the pad size on the printed circuit board, i.e., a1:1 registration.


SOLDERING PRECAUTIONS

The melting temperature of solder is higher than the ratedtemperature of the device. When the entire device is heatedto a high temperature, failure to complete soldering within ashort time could result in device failure. Therefore, thefollowing items should always be observed in order tominimize the thermal stress to which the devices aresubjected.• Always preheat the device.• The delta temperature between the preheat and

soldering should be 100°C or less.*• When preheating and soldering, the temperature of the

leads and the case must not exceed the maximumtemperature ratings as shown on the data sheet. Whenusing infrared heating with the reflow soldering method,the difference should be a maximum of 10°C.

• The soldering temperature and time should not exceed260°C for more than 5 seconds.

• When shifting from preheating to soldering, themaximum temperature gradient should be 5°C or less.

• After soldering has been completed, the device shouldbe allowed to cool naturally for at least three minutes.Gradual cooling should be used as the use of forcedcooling will increase the temperature gradient and resultin latent failure due to mechanical stress.

• Mechanical stress or shock should not be applied duringcooling.

* Soldering a device without preheating can cause excessivethermal shock and stress which can result in damage to thedevice.

TYPICAL SOLDER HEATING PROFILE

For any given circuit board, there will be a group of controlsettings that will give the desired heat pattern. The operatormust set temperatures for several heating zones, and afigure for belt speed. Taken together, these control settingsmake up a heating “profile” for that particular circuit board.On machines controlled by a computer, the computerremembers these profiles from one operating session to thenext. Figure 17 shows a typical heating profile for use whensoldering a surface mount device to a printed circuit board.This profile will vary among soldering systems but it is a goodstarting point. Factors that can affect the profile include thetype of soldering system in use, density and types ofcomponents on the board, type of solder used, and the typeof board or substrate material being used. This profile showstemperature versus time. The line on the graph shows the

actual temperature that might be experienced on the surfaceof a test board at or near a central solder joint. The twoprofiles are based on a high density and a low density board.The Vitronics SMD310 convection/infrared reflow solderingsystem was used to generate this profile. The type of solderused was 62/36/2 Tin Lead Silver with a melting pointbetween 177–189°C. When this type of furnace is used forsolder reflow work, the circuit boards and solder joints tend toheat first. The components on the board are then heated byconduction. The circuit board, because it has a large surfacearea, absorbs the thermal energy more efficiently, thendistributes this energy to the components. Because of thiseffect, the main body of a component may be up to 30degrees cooler than the adjacent solder joints.

STEP 1PREHEATZONE 1“RAMP”

STEP 2VENT

“SOAK”

STEP 3HEATING

ZONES 2 & 5“RAMP”

STEP 4HEATING

ZONES 3 & 6“SOAK”

STEP 5HEATING

ZONES 4 & 7“SPIKE”

STEP 6VENT

STEP 7COOLING

200°C

150°C

100°C

50°C

TIME (3 TO 7 MINUTES TOTAL) TMAX

SOLDER IS LIQUID FOR40 TO 80 SECONDS

(DEPENDING ONMASS OF ASSEMBLY)

205° TO219°C

PEAK ATSOLDER

JOINT

DESIRED CURVE FOR LOWMASS ASSEMBLIES

DESIRED CURVE FOR HIGHMASS ASSEMBLIES

100°C

150°C160°C

170°C

140°C

Figure 17. Typical Solder Heating Profile


Designed for high performance full-wave ac control applications where highnoise immunity and high commutating di/dt are required.

• Blocking Voltage to 800 Volts

• On-State Current Rating of 8.0 Amperes RMS at 100°C• Uniform Gate Trigger Currents in Three Modes

• High Immunity to dv/dt — 250 V/µs minimum at 125°C• Minimizes Snubber Networks for Protection

• Industry Standard TO-220AB Package

• High Commutating di/dt — 6.5 A/ms minimum at 125°C


Symbol Parameter Value Unit

VDRM Peak Repetitive Off-State Voltage (1)(–40 to 125°C, Sine Wave, 50 to 60 Hz, Gate Open) MAC8D

MAC8M MAC8N

400600800

Volts

IT(RMS) On-State RMS Current(60 Hz, TC = 100°C)

8.0 A

ITSM Peak Non-repetitive Surge Current(One Full Cycle, 60 Hz, TJ = 125°C)

80 A

I2t Circuit Fusing Consideration (t = 8.3 ms) 26 A2sec

PGM Peak Gate Power (Pulse Width ≤ 1.0 µs, TC = 80°C) 16 Watts

PG(AV) Average Gate Power (t = 8.3 ms, TC = 80°C) 0.35 Watts

TJ Operating Junction Temperature Range –40 to +125 °C

Tstg Storage Temperature Range –40 to +150 °C


RθJCRθJA

Thermal Resistance — Junction to CaseThermal Resistan ce — Junction to Ambient

2.262.5

°C/W

TL Maximum Lead Temperature for Soldering Purposes 1/8″ from Case for 10 Seconds 260 °C

(1) VDRM for all types can be applied on a continuous basis. Blocking voltages shall not be tested with a constant current source such that thevoltage ratings of the devices are exceeded.



CASE 221A–06(TO-220AB)

Style 4

MT2

MT1MT2

G

TRIACS8 AMPERES RMS

400 thru 800VOLTS



ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)

Symbol Characteristic Min Typ Max Unit

OFF CHARACTERISTICS

IDRM Peak Repetitive Blocking Current(VD = Rated VDRM, Gate Open) TJ = 25°C

TJ = 125°C——

——

0.012.0

mA

ON CHARACTERISTICS

VTM Peak On-State Voltage*(ITM = ±11 A Peak) — 1.2 1.6

Volts

IGT Continuous Gate Trigger Current (VD = 12 V, RL = 100 Ω)MT2(+), G(+) MT2(+), G(–) MT2(–), G(–)

5.05.05.0

131618

353535

mA

IH Hold Current(VD = 12 V, Gate Open, Initiating Current = ±150 mA) — 20 40

mA

IL Latch Current (VD = 24 V, IG = 35 mA)MT2(+), G(+); MT2(–), G(–)MT2(+), G(–)

——

2030

5080

mA

VGT Gate Trigger Voltage (VD = 12 V, RL = 100 Ω)MT2(+), G(+)MT2(+), G(–)MT2(–), G(–)

0.50.50.5

0.690.770.72

1.51.51.5

Volts

DYNAMIC CHARACTERISTICS

(di/dt)c Rate of Change of Commutating Current* See Figure 10.(VD = 400 V, ITM = 4.4 A, Commutating dv/dt = 18 V/µs, CL = 10 µFGate Open, TJ = 125°C, f = 250 Hz, No Snubber) LL = 40 mH

6.5 — — A/ms

dv/dt Critical Rate of Rise of Off-State Voltage(VD = Rated VDRM, Exponential Waveform, Gate Open, TJ = 125°C)

250 — — V/µs

*Indicates Pulse Test: Pulse Width ≤ 2.0 ms, Duty Cycle ≤ 2%.

120°

Figure 1. RMS Current Derating


125

120

115

110

105

100876543210

T C, C

ASE

TEM

PER

ATU

RE

(C)

°

Figure 2. On-State Power Dissipation

IT(RMS), ON-STATE CURRENT (AMP)

876543210

12

10

8

6

4

2P AV,

AVE

RAG

E PO

WER

(WAT

TS)

0

α = 120, 90, 60, 30°

α = 180°

α = 30°

DC

DC

180°

90°60°


Figure 3. On-State Characteristics

VT, INSTANTANEOUS ON-STATE VOLTAGE (VOLTS)

100

0

I T, I

NST

ANTA

NEO

US

ON

-STA

TE C

UR

REN

T (A

MP)

0.5 1 1.5 2 2.5 3 4 5

10

1

0.1

MAXIMUM @ TJ = 125°C

TYPICAL ATTJ = 25°C


Figure 4. Thermal Response

t, TIME (ms)

r(t),

TRAN

SIEN

T TH

ERM

AL R

ESIS

TAN

CE

(NO

RM

ALIZ

ED)

1

0.1

0.011 · 10410001001010.1

Figure 5. Hold Current Variation

TJ, JUNCTION TEMPERATURE (°C)– 50

I H, H

OLD

CU

RR

ENT

(mA)

40

5– 10 30 50 70 110 130


Figure 6. Gate Trigger Current Variation


I GT,

GAT

E TR

IGG

ER C

UR

REN

T (m

A)

V GT,

GAT

E TR

IGG

ER V

OLT

AGE

(VO

LT)

– 50 – 30 10 50 90 110 130

100

1

Q2

1

0.4– 50 – 30 – 10 10 50 110 130

Q1


3.5 4.5 10 90– 30

10

15

20

25

30

35

10

– 10 30 70 30 90

0.45

0.5

0.55

0.65

075

0.85

0.9

0.95

0.6

0.7

0.8

Q1

Q3

Q3

70

Q2

MT2 POSITIVE

MT2 NEGATIVE


Figure 8. Critical Rate of Rise of Off-StateVoltage (Exponential)

RG, GATE TO MAIN TERMINAL 1 RESISTANCE (OHMS)

5000

4K

3K

2K

1K

01000100101

dv/d

t, C

RIT

ICAL

RAT

E O

F R

ISE

OF

OFF

-STA

TE V

OLT

AGE

Figure 9. Critical Rate of Rise ofCommutating Voltage

(di/dt)c, RATE OF CHANGE OF COMMUTATING CURRENT (A/ms)

(V/

s)µ

tw

VDRM(di/dt)c =

6f ITM1000

f =1

2 tw

TJ = 125°C 100°C 75°C

10 60

100

10

1

LL 1N4007

400V+

MEASUREI

–CHARGE

CONTROLCHARGETRIGGER

NON-POLARCL

51

2

1

1N914

GTRIG

GER

CO

NTR

OL

200 VRMSADJUST FOR

ITM, 60 Hz VAC

Note: Component values are for verification of rated (dv/dt)c. See AN1048 for additional information.

Figure 10. Simplified Test Circuit to Measure the Critical Rate of Rise of Commutating Voltage

(dv/

dt)

, CR

ITIC

AL R

ATE

OF

RIS

E O

F(V

/s)µ

cC

OM

MU

TATI

NG

VO

LTAG

E

15 20 25 30 35 40 45 50 55

4.5K

3.5K

2.5K

1.5K

1K1K

500 MT2 POSITIVE

MT2 NEGATIVE




• On-State Current Rating of 8.0 Amperes RMS at 100°C• Uniform Gate Trigger Currents in Three Modes







MAC9M MAC9N

400600800

Volts


8.0 A


80 A







RθJCRθJA

Thermal Resistance — Junction to CaseThermal Resistance — Junction to Ambient

2.262.5

°C/W


(1) VDRM for all types can be applied on a continuous basis. Blocking voltages shall not be tested with a constant current source such that the voltage ratings of the devices are exceeded.




Style 4

MT2

MT1

MT2G

TRIACS8.0 AMPERES RMS

400 thru 800VOLTS





OFF CHARACTERISTICS


TJ = 125°C——

——

0.012.0

mA

ON CHARACTERISTICS


Volts

IGT Continuous Gate Trigger Current (VD = 12 V, RL = 100 Ω)MT2(+), G(+)MT2(+), G(–) MT2(–), G(–)

101010

161822

505050

mA


mA

IL Latch Current (VD = 24 V, IG = 50 mA)MT2(+), G(+); MT2(–), G(–) MT2(+), G(–)

——

2030

5080

mA


0.50.50.5

0.690.770.72

1.51.51.5

Volts



6.5 — — A/ms


500 — — V/µs




125

120

115

110

105

100876543210

T C, C

ASE

TEM

PER

ATU

RE

(C)

°



876543210

12

10

8

6

4

2P AV,

AVE

RAG

E PO

WER

(WAT

TS)

0

α = 120, 90, 60, 30°

α = 180°

α = 30°

DC

DC

180°

120°

90°60°



I GT,

GAT

E TR

IGG

ER C

UR

REN

T (m

A)

– 50 – 30 10 50 90 110 130

100

1

Q2

10

– 10 30 70

Q1

Q3


100

0

I T, I

NST

ANTA

NEO

US

ON

-STA

TE C

UR

REN

T (A

MP)

0.5 1 1.5 2 2.5 3 4 5

10

1

0.1


TYPICAL ATTJ = 25°C


t, TIME (ms)

r(t),

TRAN

SIEN

T TH

ERM

AL R

ESIS

TAN

CE

(NO

RM

ALIZ

ED)

1

0.1

0.011 · 10410001001010.1


V GT,

GAT

E TR

IGG

ER V

OLT

AGE

(VO

LT)

1

0.4– 50 – 30 – 10 10 70 110 130

Q1

Q2

3.5 4.5

50 90

0.45

0.5

0.55

0.65

0.75

0.85

0.9

0.95

0.6

0.7

0.8


I H, H

OLD

CU

RR

ENT

(mA)

40

5– 10 30 50 70 110 13010 90– 30

10

15

20

25

30

35

Q3

30




Figure 6. Gate Trigger Current Variation Figure 7. Gate Trigger Voltage Variation

MT2 POSITIVE

MT2 NEGATIVE


Figure 8. Critical Rate of Rise of Off-State Voltage(Exponential)


5000

4K

3K

2K

1K

01000100101

dv/d

t, C

RIT

ICAL

RAT

E O

F R

ISE

OF

OFF

-STA

TE V

OLT

AGE



(V/

s)µ

tw

VDRM(di/dt)c =

6f ITM1000

f =1

2 tw

TJ = 125°C 100°C 75°C

10 60

100

10

1

LL 1N4007

400V+

MEASUREI

–CHARGE


NON-POLARCL

51

2

1

1N914

GTRIG

GER

CO

NTR

OL

200 VRMSADJUST FOR

ITM, 60 Hz VAC



(dv/

dt)

, CR

ITIC

AL R

ATE

OF

RIS

E O

F(V

/s)µ

cC

OM

MU

TATI

NG

VO

LTAG

E

15 20 25 30 35 40 45 50 55

4.5K

3.5K

2.5K

1.5K

1K1K

500 MT2 POSITIVE

MT2 NEGATIVE



Designed for high performance full–wave ac control applications where highnoise immunity and commutating di/dt are required.

• Blocking Voltage to 800 Volts• On–State Current Rating of 12 Amperes RMS at 70°C• Uniform Gate Trigger currents in Three Modes• High Immunity to dv/dt — 250 V/µs minimum at 125°C• High Commutating di/dt — 6.5 A/ms minimum at 125°C• Industry Standard TO–220 AB Package• High Surge Current Capability — 120 Amperes


Parameter Symbol Value Unit

Peak Repetitive Off–State Voltage(1)

(TJ = –40 to 125°C, Sine Wave, 50 to 60 Hz, Gate Open) MAC12DMAC12MMAC12N

VDRM400600800

Volts

On–State RMS Current(Full Cycle Sine Wave, 60 Hz, TC = 70°C)

IT(RMS) 12 A

Peak Non–repetitive Surge Current(One Full Cycle, 60 Hz, TJ = 125°C)

ITSM 100 A

Circuit Fusing Consideration (t = 8.3 ms) I2t 41 A2sec

Peak Gate Power (Pulse Width 1.0 µs, TC = 80°C) PGM 16 Watts

Average Gate Power (t = 8.3 ms, TC = 80°C) PG(AV) 0.35 Watts




Thermal Resistance — Junction to Case— Junction to Ambient

RθJCRθJA

2.262.5

°C/W

Maximum Lead Temperature for Soldering Purposes 1/8″ from Case for 10 Seconds TL 260 °C



OFF CHARACTERISTICS

Peak Repetitive Blocking Current TJ = 25°C(VD = Rated VDRM, Gate Open) TJ = 125°C

IDRM ——

——

0.012.0

mA

(1) VDRM and VRRM for all types can be applied on a continuous basis. Ratings apply for zero or negative gate voltage; positive gate voltage shallnot be applied concurrent with negative potential on the anode. Blocking voltages shall not be tested with a constant current source such that thevoltage ratings of the devices are exceeded.

This document contains information on a new product. Specifications and information herein are subject to change without notice.




Style 4

TRIACS12 AMPERES RMS

400 thru 800VOLTS


MT2

MT1MT2

G

REV 1




ON CHARACTERISTICS

Peak On–State Voltage* (ITM = 17 A) VTM — — 1.85 Volts

Continuous Gate Trigger Current (VD = 12 V, RL = 100 Ω)MT2(+), G(+)MT2(+), G(–)MT2(–), G(–)

IGT5.05.05.0

131618

353535

mA

Hold Current (VD = 12 V, Gate Open, Initiating Current = 150 mA) IH — 20 40 mA

Latch Current (VD = 24 V, IG = 35 mA)MT2(+), G(+); MT2(–), G(–)MT2(+), G(–)

IL——

2030

5080

mA

Gate Trigger Voltage (VD = 12 V, RL = 100 Ω)MT2(+), G(+)MT2(+), G(–)MT2(–), G(–)

VGT0.50.50.5

0.690.770.72

1.51.51.5

Volts


Rate of Change of Commutating Current*(VD = 400 V, ITM = 4.4A, Commutating dv/dt = 18 V/µs, Gate Open,TJ = 125°C, f = 250 Hz, No Snubber)

(dv/dt)c 6.5 — — A/ms

Critical Rate of Rise of Off–State Voltage(VD = Rated VDRM, Exponential Waveform, Gate Open, TJ = 125°C)

dv/dt 250 — — V/µs

*Indicates Pulse Test: Pulse Width 2.0 ms, Duty Cycle 2%.




• On-State Current Rating of 15 Amperes RMS at 80°C• Uniform Gate Trigger Currents in Three Modes







MAC15MMAC15N

400600800

Volts


15 A


150 A







RθJCRθJA


2.062.5

°C/W


(1) VDRM for all types can be applied on a continuous basis. Blocking voltages shall not be tested with a constant current source such that thevoltage ratings of the devices are exceeded.



CASE 221A-06(TO–220AB)

Style 4

MT2

MT1

MT2G


400 thru 800VOLTS





OFF CHARACTERISTICS


TJ = 125°C——

——

0.012.0

mA

ON CHARACTERISTICS


Volts

IGT Continuous Gate Trigger Current (VD = 12 V, RL = 100 Ω)MT2(+), G(+)MT2(+), G(–)MT2(–), G(–)

5.05.05.0

131618

353535

mA


mA

IL Latch Current (VD = 24 V, IG = 35 mA)MT2(+), G(+) MT2(+), G(–) MT2(–), G(–)

———

333633

508050

mA


0.50.50.5

0.750.720.82

1.51.51.5

Volts



9.0 — — A/ms


250 — — V/µs




125

120

115

110

105

100

95

90

85

801614121086420

T C, C

ASE

TEM

PER

ATU

RE

(C)

°



1614121086420

20

18

16

14

12

10

8

6

4

2

P AV,

AVE

RAG

E PO

WER

(WAT

TS)

0

DC

α = 30 and 60°

α = 90°

α = 120°α = 180°

DC180°

120°

90°60°

α = 30°




100

0

I T, I

NST

ANTA

NEO

US

ON

-STA

TE C

UR

REN

T (A

MP)

0.5 1 1.5 2 2.5 3 3.5 4

10

1

0.1

MAXIMUM @ TJ = 125°CTYPICAL ATTJ = 25°C



t, TIME (ms)

r(t),

TRAN

SIEN

T TH

ERM

AL R

ESIS

TAN

CE

(NO

RM

ALIZ

ED)

1

0.1

0.011 · 10410001001010.1



I H, H

OLD

CU

RR

ENT

(mA)

40

5– 10 20 50 80 110 125

MT2 POSITIVE

MT2 NEGATIVE


I GT,

GAT

E TR

IGG

ER C

UR

REN

T (m

A)

V GT,

GAT

E TR

IGG

ER V

OLT

AGE

(VO

LT)

– 40 – 10 20 50 80 110 125

100

1

Q3

Q1

Q2

OFF-STATE VOLTAGE = 12 VRL = 140 Ω

1

0.5– 40 – 10 +20 50 80 110 125

Q1

Q2

Q3


Figure 16. Gate Trigger Current Variation Figure 17. Gate Trigger Voltage Variation


Figure 18. Critical Rate of Rise of Off-StateVoltage (Exponential)


5000

4K

3K

2K

1K

010000100010010

dv/d

t, C

RIT

ICAL

RAT

E O

F R

ISE

OF

OFF

-STA

TE V

OLT

AGE



(V/

s)µVD = 800 VpkTJ = 125°C

ITM

tw

VDRM(di/dt)c =

6f ITM1000

f =1

2 tw

TJ = 125°C 100°C 75°C

10 100

100

10

1

LL 1N4007

400V+

MEASUREI

–CHARGE


NON-POLARCL

51

2

1

1N914

GTRIG

GER

CO

NTR

OL

200 VRMSADJUST FOR

ITM, 60 Hz VAC



(dv/

dt)

, CR

ITIC

AL R

ATE

OF

RIS

E O

F(V

/s)µ

cC

OM

MU

TATI

NG

VO

LTAG

E

20 30 40 50 60 70 80 90



. . . designed primarily for full-wave ac control applications, such as solid–state relays,motor controls, heating controls and power supplies; or wherever full–wave silicongate controlled solid–state devices are needed. Triac type thyristors switch from ablocking to a conducting state for either polarity of applied anode voltage with positiveor negative gate triggering.



Dissipation and Durability• Gate Triggering Guaranteed in Three Modes (MAC15 Series) or Four Modes

(MAC15A Series)




(Gate Open, TJ = –40 to +125°C) MAC15–4, MAC15A4MAC15–6, MAC15A6MAC15–8, MAC15A8MAC15–10, MAC15A10

VDRM200400600800

Volts

Peak Gate Voltage VGM 10 Volts

On–State Current RMSFull Cycle Sine Wave 50 to 60 Hz (TC = +90°C)

IT(RMS) 15 Amps


Peak Surge Current(One Full Cycle, 60 Hz, TC = +80°C)Preceded and followed by rated current

ITSM 150 Amps

Peak Gate Power (TC = +80°C, Pulse Width = 2 µs) PGM 20 Watts

Average Gate Power (TC = +80°C, t = 8.3 ms) PG(AV) 0.5 Watt

Peak Gate Current IGM 2 Amps







REV 1



STYLE 4


MT1

G

MT2


ELECTRICAL CHARACTERISTICS (TC = 25°C, and either polarity of MT2 to MT1 Voltage, unless otherwise noted.)


Peak Blocking Current(VD = Rated VDRM, Gate Open) TJ = 25°C

TJ = 125°C

IDRM——

——

102

µAmA

Peak On–State Voltage(ITM = 21 A Peak; Pulse Width = 1 or 2 ms, Duty Cycle 2%)


Gate Trigger Current (Continuous dc)(VD = 12 Vdc, RL = 100 Ohms)MT2(+), G(+)MT2(+), G(–)MT2(–), G(–)MT2(–), G(+) “A’’ SUFFIX ONLY

IGT

————

————

50505075

mA

Gate Trigger Voltage (Continuous dc)(VD = 12 Vdc, RL = 100 Ohms)MT2(+), G(+)MT2(+), G(–)MT2(–), G(–)MT2(–), G(+) “A’’ SUFFIX ONLY(VD = Rated VDRM, RL = 10 k Ohms, TJ = 110°C)MT2(+), G(+); MT2(–), G(–); MT2(+), G(–)MT2(–), G(+) “A’’ SUFFIX ONLY

VGT

————

0.20.2

0.90.91.11.4

——

222

2.5

——

Volts

Holding Current (Either Direction)(VD = 12 Vdc, Gate Open)(IT = 200 mA)

IH — 6 40 mA

Turn-On Time(VD = Rated VDRM, ITM = 17 A)(IGT = 120 mA, Rise Time = 0.1 µs, Pulse Width = 2 µs)

tgt — 1.5 — µs



FIGURE 1 – RMS CURRENT DERATING FIGURE 2 – ON–STATE POWER DISSIPATION

130

120

110

100

90

800 2 4 6 8 10 12 14 16

IT(RMS), RMS ON–STATE CURRENT (AMP)

T C, C

ASE

TEM

PER

ATU

RE

(C

)°

α = 30°

α = 180°

α = 60°α = 90°

dc

TJ ≈ 125°

20

16

12

8

4

00 2 4 6 8 10 12 14 16

IT(RMS), ON–STATE CURRENT (AMP)

30°

α = 180°

dcTJ ≈ 125°

60°

90°

120°

P AV,

AVE

RAG

E PO

WER

(WAT

TS)


α

α


α

α



FIGURE 5 – ON–STATE CHARACTERISTICS FIGURE 6 – TYPICAL HOLDING CURRENT

FIGURE 7 – MAXIMUM NON–REPETITIVE SURGE CURRENT

1.8

1.6

1.4

1.2

1.0

0.4–60 –40 –20 0 20 40 60 80 100


1

QUADRANT 4

0.8

0.6

120 140

2

3

QUADRANTS

OFF–STATE VOLTAGE = 12 VV G

T, G

ATE

TRIG

GER

VO

LTAG

E (V

OLT

S)50

30

20

10

7.0

5.0–60 –40 –20 0 20 40 60 80 100


1

120 140

23QUADRANT


4

I GT,

GAT

E TR

IGG

ER C

UR

REN

T (m

A)

100

70

50

30

20

0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6

vTM, INSTANTANEOUS ON–STATE VOLTAGE (VOLTS)

TJ = 25°C

4 4.4

10

7

5

3

2

1

0.7

0.5

0.3

0.2

0.1

i TM

, IN

STAN

TAN

EOU

S FO

RWAR

D C

UR

REN

T (A

MP)

125°C

20

10

7.0

5.0

3.0

2.0–60 –40 –20 0 20 40 60 80 100


120 140

GATE OPEN

300

200

100

70

50

301 2 3 5

NUMBER OF CYCLES

7 10




TC = 80°CT f = 60 HzT S

M, P

EAK

SUR

GE

CU

RR

ENT

(AM

P)I H

, HO

LDIN

G C

UR

REN

T (m

A)



1

0.5

0.1

0.05

0.02

0.010.1 0.2 0.5

t, TIME (ms)

1

ZθJC(t) = r(t) • RθJC0.2

2 5 10 20 50 100 200 500 1 k 2 k 5 k 10 k

r(t) T

RAN

SIEN

T TH

ERM

AL R

ESIS

TAN

CE

(NO

RM

ALIZ

ED)



. . . designed primarily for full-wave ac control applications, such as solid-state relays,motor controls, heating controls and power supplies; or wherever full-wave silicongate controlled solid-state devices are needed. Triac type thyristors switch from ablocking to a conducting state for either polarity of applied anode voltage with positiveor negative gate triggering.



Dissipation and Durability• Gate Triggering Guaranteed in Three Modes (MAC15FP Series) or Four Modes

(MAC15AFP Series)



Repetitive Peak Off-State Voltage(1) (TJ = –40 to +125°C,1/2 Sine Wave 50 to 60 Hz, Gate Open)

MAC15-4FP, MAC15A4FPMAC15-6FP, MAC15A6FPMAC15-8FP, MAC15A8FPMAC15-10FP, MAC15A10FP

VDRM

200400600800

Volts

On-State RMS Current (TC = +80°C )(2)

Full Cycle Sine Wave 50 to 60 Hz (TC = +95°C )IT(RMS) 15

12Amps

Peak Nonrepetitive Surge Current (One Full Cycle, 60 Hz, TC = +80°C)preceded and followed by rated current

ITSM 150 Amps





RMS Isolation Voltage (TA = 25°C, Relative Humidity 20%) V(ISO) 1500 Volts

Operating Junction Temperature TJ –40 to +125 °C



2. The case temperature reference point for all TC measurements is a point on the center lead of the package as close as possible to the plasticbody.


MT1

G

MT2

CASE 221C-02STYLE 3

ISOLATED TRIACsTHYRISTORS

15 AMPERES RMS200 thru 800 VOLTS





Thermal Resistance, Case to Sink RθCS 2.2 (typ) °C/W




Peak Blocking Current (Either Direction) TJ = 25°C(VD = Rated VDRM, TJ = 125°C, Gate Open)

IDRM ——

——

102

µAmA

Peak On-State Voltage (Either Direction)(ITM = 21 A Peak; Pulse Width = 1 to 2 ms, Duty Cycle 2%)


Gate Trigger Current (Continuous dc)(Main Terminal Voltage = 12 Vdc, RL = 100 Ohms)MT2(+), G(+)MT2(+), G(–)MT2(–), G(–)MT2(–), G(+) “A” SUFFIX ONLY

IGT

————

————

50505075

mA

Gate Trigger Voltage (Continuous dc)(Main Terminal Voltage = 12 Vdc, RL = 100 Ohms)MT2(+), G(+)MT2(+), G(–)MT2(–), G(–)MT2(–), G(+) “A” SUFFIX ONLY(Main Terminal Voltage = Rated VDRM, RL = 10 kΩ, TJ = +110°C)MT2(+), G(+); MT2(–), G(–); MT2(+), G(–)MT2(–), G(+) “A” SUFFIX ONLY

VGT

————

0.20.2

0.90.91.11.4

——

222

2.5

——

Volts

Holding Current (Either Direction)(Main Terminal Voltage = 12 Vdc, Gate Open,Initiating Current = 200 mA)

IH — 6 40 mA

Turn-On Time(VD = Rated VDRM, ITM = 17 A, IGT = 120 mA,Rise Time = 0.1 µs, Pulse Width = 2 µs)

tgt — 1.5 — µs



MT2(+)



MT2(–)

G(–) G(+)

MT2(+), G(–) MT2(+), G(+)

MT2(–), G(–) MT2(–), G(+)

Trigger devices are recommended for gating on Triacs. They provide:1. Consistent predictable turn–on points.

2. Simplified circuitry.

3. Fast turn–on time for cooler, more efficient and reliable operation.

ELECTRICAL CHARACTERISTICS of RECOMMENDEDBIDIRECTIONAL SWITCHES


Part Number

Usage General

MBS4992MBS4991

VS

ISVS1–VS2


6–10 V 7.5–9 V

350 µA Max 120 µA Max

0.5 V Max 0.2 V Max

0.02%/°C Typ

1. Ratings apply for open gate conditions. Thyristor devices shall not be tested with a constant current source for blocking capability such that thevoltage applied exceeds the rated blocking voltage.




Figure 22. On–State Power Dissipation

Figure 23. Typical Gate Trigger Voltage

Figure 24. Typical Gate Trigger Current

Figure 25. Maximum On–State Characteristics

130

120

110

100

90

800 2 4 6 8 10 12 14 16


T C, C

ASE

TEM

PER

ATU

RE

(C

)°

30°

125°C

60°

90°

dc

20

16

12

8

4

00 2 4 6 8 10 12 14 16


30°

α = 180°

dc

TJ = 125°C

60°

90°

120°

3

2

1

0.7

0.3–60 –40 –20 0 20 40 60 80 100


0.5

120 140

OFF–STATE VOLTAGE = 12 VdcALL MODES

V GTM

, GAT

E TR

IGG

ER V

OLT

AGE

(NO

RM

ALIZ

ED)

3

2

1

0.7

0.5

0.3–60 –40 –20 0 20 40 60 80 100


120 140


I GTM

, GAT

E TR

IGG

ER C

UR

REN

T (N

OR

MAL

IZED

)

100

70

50

30

20

0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6

vT, INSTANTANEOUS ON–STATE VOLTAGE (VOLTS)

TJ = 25°C

4 4.4

10

7

5

3

2

1

0.7

0.5

0.3

0.2

0.1

125°C

150° to 180°

P

,

AVE

RAG

E PO

WER

DIS

SIPA

TIO

N (W

ATTS

)D

(AV)

i ,

INST

ANTA

NEO

US

FORW

ARD

CU

RR

ENT

(AM

P)F


α

α


α

α


Figure 26. Typical Holding Current Figure 27. Maximum Nonrepetitive Surge Current


3

2

1

0.7

0.5

0.3–60 –40 –20 0 20 40 60 80 100


120 140


I H, H

OLD

ING

CU

RR

ENT

(NO

RM

ALIZ

ED)

300

200

100

70

50

301 2 3 5

NUMBER OF CYCLES

7 10

SURGE IS PRECEDED AND FOLLOWED BY RATED CURRENT

TC = 80°Cf = 60 HzI T

SM, P

EAK

SUR

GE

CU

RR

ENT

(AM

P)

1

0.5

0.1

0.05

0.02

0.010.1 0.2 0.5

t, TIME (ms)

1

ZθJC(t) = r(t) • RθJC0.2

2 5 10 20 50 100 200 500 1 k 2 k 5 k 10 k

r(t) T

RAN

SIEN

T TH

ERM

AL R

ESIS

TAN

CE

(NO

RM

ALIZ

ED)




• On-State Current Rating of 15 Amperes RMS at 80°C• Uniform Gate Trigger Currents in Three Modes







MAC16M MAC16N

400600800

Volts


15 A


150 A







RθJCRθJA


2.062.5

°C/W


(1) VDRM for all types can be applied on a continuous basis. Blocking voltages shall not be tested with a constant current source such that the voltage ratings of the devices are exceeded.




400 thru 800VOLTS



Style 4

MT2

MT1MT2

G




OFF CHARACTERISTICS


TJ = 125°C——

——

0.012.0

mA

ON CHARACTERISTICS


Volts

IGT Continuous Gate Trigger Current (VD = 12 V, RL = 100 Ω)MT2(+), G(+) MT2(+), G(–)MT2(–), G(–)

101010

161822

505050

mA


mA

IL Latch Current (VD = 24 V, IG = 50 mA)MT2(+), G(+)MT2(+), G(–)MT2(–), G(–)

———

333633

508050

mA


0.50.50.5

0.750.720.82

1.51.51.5

Volts



9.0 — — A/ms


500 — — V/µs




125

120

115

110

105

100

95

90

85

801614121086420

T C, C

ASE

TEM

PER

ATU

RE

(C)

°



1614121086420

20

18

16

14

12

10

8

6

4

2

P AV,

AVE

RAG

E PO

WER

(WAT

TS)

0

DC

α = 30 and 60°

α = 90°

α = 120°α = 180°

DC180°

120°

90°60°

α = 30°




100

0

I T, I

NST

ANTA

NEO

US

ON

-STA

TE C

UR

REN

T (A

MP)

0.5 1 1.5 2 2.5 3 3.5 4

10

1

0.1

MAXIMUM @ TJ = 125°CTYPICAL ATTJ = 25°C



t, TIME (ms)

r(t),

TRAN

SIEN

T TH

ERM

AL R

ESIS

TAN

CE

(NO

RM

ALIZ

ED)

1

0.1

0.011 · 10410001001010.1



I H, H

OLD

CU

RR

ENT

(mA)

40

5– 10 20 50 80 110 125

MT2 POSITIVE

MT2 NEGATIVE


Figure 6. Gate Trigger Current Variation


I GT,

GAT

E TR

IGG

ER C

UR

REN

T (m

A)

V GT,

GAT

E TR

IGG

ER V

OLT

AGE

(VO

LT)

– 40 – 10 20 50 80 110 125

100

1

Q3

Q1

Q2


1

0.5– 40 – 10 +20 50 80 110 125

Q1

Q2

Q3




Figure 8. Critical Rate of Rise of Off-State Voltage(Exponential)


5000

4K

3K

2K

1K

010000100010010

dv/d

t, C

RIT

ICAL

RAT

E O

F R

ISE

OF

OFF

-STA

TE V

OLT

AGE



(V/

s)µVD = 800 VpkTJ = 125°C

ITM

tw

VDRM(di/dt)c =

6f ITM1000

f =1

2 tw

TJ = 125°C 100°C 75°C

10

100

10

1

LL 1N4007

400V+

MEASUREI

–CHARGE


NON-POLARCL

51

2

1

1N914

GTRIG

GER

CO

NTR

OL

200 VRMSADJUST FOR

ITM, 60 Hz VAC



(dv/

dt)

, CR

ITIC

AL R

ATE

OF

RIS

E O

F(V

/s)µ

cC

OM

MU

TATI

NG

VO

LTAG

E

20 30 40 50 60 70 80 90 100


. . . designed for use in solid state relays, MPU interface, TTL logic and any other lightindustrial or consumer application. Supplied in an inexpensive TO–92 package whichis readily adaptable for use in automatic insertion equipment.

• One–Piece, Injection–Molded Unibloc Package• Sensitive Gate Triggering in Four Trigger Modes for all possible Combinations of

Trigger Sources, and Especially for Circuits that Source Gate Drives• All Diffused and Glassivated Junctions for Maximum Uniformity of Parameters

and Reliability



Peak Repetitive Off-State Voltage(Gate Open, TJ = –40 to +110°C)(1)1/2 Sine Wave 50 to 60 Hz, Gate Open

MAC97–4, MAC97A4MAC97–6, MAC97A6MAC97–8, MAC97A8

VDRM

200400600

Volts

On-State RMS CurrentFull Cycle Sine Wave 50 to 60 Hz (TC = +50°C)

IT(RMS) 0.8 Amp

Peak Non–repetitive Surge Current(One Full Cycle, 60 Hz, TA = 110°C)

ITSM 8.0 Amps

Circuit Fusing ConsiderationsTJ = –40 to +110°C (t = 8.3 ms)

I2t 0.26 A2s

Peak Gate Voltage (t 2.0 s) VGM 5.0 Volts

Peak Gate Power (t 2.0 s) PGM 5.0 Watts

Average Gate Power (TC = 80°C, t 8.3 ms) PG(AV) 0.1 Watt

Peak Gate Current (t 2.0 s) IGM 1.0 Amp







1 VDRM for all types can be applied on a continuous basis. Blocking voltages shall not betested with a constant current source such that the voltage ratings of the devices areexceeded.



CASE 29–04TO–226AA, STYLE 12

(TO–92)

TRIACs0.8 AMPERE RMS200 — 600 VOLTS

Motorola preferred devices

MT1

G

MT2

MT1

MT2G

(Device Date Code9625 and Up)

REV 2


ELECTRICAL CHARACTERISTICS (TC = 25°C, and Either Polarity of MT2 to MT1 Voltage unless otherwise noted)


Peak Blocking Current(1)

(VD = Rated VDRM, TJ = 110°C, Gate Open)IRRM — — 0.1 mA

Peak On-State Voltage (Either Direction)(ITM = 1.1 A Peak; Pulse Width 2.0 ms, Duty Cycle 2.0%)


Gate Trigger Current (Continuous dc)(VD = 12 Vdc, RL = 100 Ohms)MT2(+), G(+)MT2(+), G(–)MT2(–), G(–)MT2(–), G(+) MAC97

MT2(+), G(+)MT2(+), G(–)MT2(–), G(–)MT2(–), G(+) MAC97A

IGT

————

————

————

————

10101010

5.05.05.07.0

mA

Gate Trigger Voltage, (Continuous dc)(VD = 12 Vdc, RL = 100 Ohms)MT2(+), G(+) All TypesMT2(+), G(–) All TypesMT2(–), G(–) All TypesMT2(–), G(+) All Types(VD = Rated VDRM, RL = 10 k Ohms, TJ = 110°C)MT2(+), G(+); MT2(–), G(–); MT2(+), G(–) All TypesMT2(–), G(+) All Types

VGT

————

0.10.1

————

——

2.02.02.02.5

——

Volts

Holding Current(VD = 12 Vdc, ITM = 200 mA, Gate Open)

IH — — 5.0 mA

Gate Controlled Turn–On Time(VD = Rated VDRM, ITM = 1.0 A pk, IG = 25 mA)

tgt — 2.0 — s

Critical Rate–of–Rise of Commutation Voltage(f = 250 Hz, ITM = 1.0 A, Commutating di/dt = 1.5 A/mS,On–State Current Duration = 2.0 mS, VDRM = 200 V,Gate Unenergized, TC = 110°C,Gate Source Resistance = 150 , See Figure 13)

dv/dtc 1.5 — — Vs

Critical Rate–of–Rise of Off State Voltage(Vpk = Rated VDRM, TC = 110°C, Gate Open, Exponential Method)

dv/dt 10 — — Vs


Figure 1. RMS Current Derating Figure 2. RMS Current Derating

Figure 3. Power Dissipation Figure 4. On–State Characteristics

Figure 5. Transient Thermal Response Figure 6. Maximum Allowable Surge Current

α

α


0.5 0.6 0.7 0.80.1 0.2 0.3 0.40

110

100

90

80

70

60

IT(RMS), RMS ON–STATE CURRENT (AMPS)

α

α


0.25 0.3 0.35 0.40.05 0.1 0.15 0.20

90

80

70

60

50

40


30

20

0.4 0.5 0.6 0.70 0.1 0.2 0.3

0.6

0.4

0.2

0


0.1 1.0 10 100

1.0

t, TIME (ms)

0.1

0.01

0.8

1103 1104 3.0 30 501.0 2.0 100

3.0

2.0

1.0

NUMBER OF CYCLES

5.0

10

T ,

MAX

IMU

M A

LLO

WAB

LE C

ASE

TEM

PER

ATU

RE

( C

C°

= 30°

60°90°DC

180°

120°

ZJC(t) = RJC(t) r(t)

50

40

30

100

110

2.5 3.0 3.5 4.00.5 1.0 1.5 2.0 4.5

10

1.0

0.1

0.01

VT, INSTANTANEOUS ON–STATE VOLTAGE (VOLTS)

5.0I , I

NST

ANTA

NEO

US

ON

–STA

TE C

UR

REN

T (A

MPS

)T

TYPICAL @ TJ = 25°C


MAXIMUM @ TJ = 110°Cα

α


105.0

0.8

1.0

1.2

Surge is preceded and followed by rated current.

TJ = 110°Cf = 60 Hz

CYCLE


= 30°

60°90°DC

180°120°

, MAX

IMU

M A

LLO

WAB

LEAM

BIEN

T TE

MPE

RAT

UR

E (

C)

°T(

RM

S)I

P

, M

AXIM

UM

AVE

RAG

E PO

WER

DIS

SIPA

TIO

N (W

ATTS

)(A

V)

I

,

PEAK

SU

RG

E C

UR

REN

T (A

MPS

)TS

M

R

, TR

ANSI

ENT

THER

MAL

RES

ISTA

NC

E (N

OR

MAL

IZED

)(t)


Figure 7. Typical Holding Current Variation Figure 8. Typical Gate Trigger CurrentVariation

Figure 9. Gate Trigger Voltage Variation Figure 10. Exponential Static dv/dt versusGate MT1 Resistance

Figure 11. Typical Commutating dv/dt versusCurrent Crossing Rate and Junction Temperature

Figure 12. Typical Commutating dv/dt versusJunction Temperature at 0.8 Amps RMS

6.0

4.0

2.0

0


10

1.0


0.1

–40 –20

1.1

0.9

0.7

0.5

0.3


10 100 1000

40

RGK, GATE – MT1 RESISTANCE (OHMS)

30

2010,000

1.0 101.0

di/dtc, RATE OF CHANGE OF COMMUTATING CURRENT (A/mS)

10


40 60 80–40 –20 0 20 100 110 40 60 80–40 –20 0 20 100 110

0 20 40 60 80 100

50

60

60 70

10

1.080 90 100 110

I ,

HO

LDIN

G C

UR

REN

T (m

A)H

I

, GAT

E TR

IGG

ER C

UR

REN

T (m

A)G

TST

ATIC

dv/

dt (V

/ S)

VDRM = 200 V

400 Hz

600 VpkTJ = 110°C

Q2

Q1

(didt)c 6f ITM

1000

tw

VDRM

5.0

3.0

1.0

300 Hz

180 Hz

60 Hz

MAIN TERMINAL#2 NEGATIVE

MAIN TERMINAL#2 POSITIVE

Q4

Q3

MAIN TERMINAL#2 NEGATIVE

MAIN TERMINAL#2 POSITIVE

Q2

Q1

Q4Q3

ITM

f 12tw

100°C

110°C

80°C

60°C

CO

MM

UTA

TIN

G d

v/dt

dv/d

t , (

V/ S

)c

CO

MM

UTA

TIN

G d

v/dt

dv/d

t , (

V/ S

)c

V

, G

ATE

TRIG

GER

VO

LTAG

E (V

OLT

S)G

T


Figure 13. Simplified Q 1 (dv/dt) c Test Circuit

1N4007

200 V0.047 CSADJUST FORdv/dt(c)

56RS

CS

80 mHYLL

MEASUREI

1N914

2

75 VRMSADJUST FOR

ITM, 60 Hz VAC

CHARGECONTROL

5 FNON–POLAR

CL

151

G

TRIG

GER

CO

NTR

OL

CHARGE

TRIGGER

NOTE: Component values are for verification of rated (dv/dt)c. See AN1048 for additional information.

–

+







(MAC210A Series)



Repetitive Peak Off-State Voltage(1)

(TJ = –40 to +125°C,1/2 Sine Wave 50 to 60 Hz, Gate Open) MAC210-4, MAC210A4

MAC210-6, MAC210A6MAC210-8, MAC210A8MAC210-10, MAC210A10

VDRM

200400600800

Volts

On-State Current RMS (TC = +70°C)Full Cycle Sine Wave 50 to 60 Hz

IT(RMS) 10 Amps

Peak Non-repetitive Surge Current(One Full Cycle, 60 Hz, TC = +70°C)Preceded and followed by Rated Current

ITSM 100 Amps


I2t 40 A2s

Peak Gate Power(TC = +70°C, Pulse Width = 10 µs)

PGM 20 Watts


Peak Gate Current(TC = +70°C, Pulse Width = 10 µs)

IGM 2 Amps



(1) VDRM for all types can be applied on a continuous basis. Blocking voltages shall not be tested with a constant current source such thatthe voltage ratings of the devices are exceeded.



STYLE 4


MT1

G

MT2







Peak Blocking Current (VD = Rated VDRM, Gate Open) TJ = 25°C

TJ = +125°C

IDRM——

——

102

µAmA



Gate Trigger Current (Continuous dc)(Main Terminal Voltage = 12 Vdc, RL = 100 Ohms)MT2(+), G(+) MT2(+), G(–) MT2(–), G(–)MT2(–), G(+) “A” SUFFIX ONLY

IGT

————

12122035

50505075

mA

Gate Trigger Voltage (Continuous dc)(Main Terminal Voltage = 12 Vdc, RL = 100 Ohms)MT2(+), G(+) MT2(+), G(–)MT2(–), G(–) MT2(–), G(+) “A” SUFFIX ONLY(Main Terminal Voltage = Rated VDRM, RL = 10 k ohms,TJ = +125°C)MT2(+), G(+); MT2(–), G(–); MT2(+), G(–) MT2(–), G(+) “A” SUFFIX ONLY

VGT

————

0.20.2

0.90.91.11.4

——

222

2.5

——

volts

Holding Current (Either Direction)(Main Terminal Voltage = 12 Vdc, Gate Open,Initiating Current = 500 mA, TC = +25°C)

IH — 6 50 mA

Turn-On Time(Rated VDRM, ITM = 14 A)(IGT = 120 mA, Rise Time = 0.1 µs, Pulse Width = 2 µs)

tgt — 1.5 — µs



Critical Rate of Rise of Off-State Voltage(VD = Rated VDRM, Exponential Voltage Rise,Gate Open, TC = +70°C)

dv/dt — 100 — V/µs


90


4.00.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2

1.0

4.43.60.1

0.2

50

TJ = 25°C

0.5

2.0

5.0

10

20

100


FIGURE 4 — MAXIMUM NON-REPETITIVE SURGE CURRENT

80

0

20

40

5.0

60

1.0 2.0 3.0 7.0

100

TC = 70°Cf = 60 Hz

CYCLE

10

60 80

2.0

IT(RMS), RMS ON-STATE CURRENT (AMPS) IT(RMS), RMS ON-STATE CURRENT (AMPS)0

0

4.0

2.0

–40


0 40

CONDUCTION ANGLE = 360°

60

130

120

110

TC, CASE TEMPERATURE (°C)

FIGURE 3 — MAXIMUM ON-STATE CHARACTERISTICS

–60 –20

70

20

80

FIGURE 1 — CURRENT DERATING FIGURE 2 — POWER DISSIPATION

0

0.4

0.8

1.2

1.6

FIGURE 5 — TYPICAL GATE TRIGGER VOLTAGE

100

1.0 10.0 8.07.05.0 6.04.0 9.0

10.0

12.0

14.0

8.0

6.0

10.03.02.01.00

NUMBER OF CYCLES

3.02.0 4.0 6.05.0 7.0 8.0 9.0

CONDUCTION ANGLE = 360°

T ,

MAX

IMU

M A

LLO

WAB

LE C

ASE

CTE

MPE

RAT

UR

E (

C)

°

P

,

AVER

AGE

POW

ER D

ISSI

PATI

ON

(AV)

I , I

NST

ANTA

NEO

US

ON

-STA

TE C

UR

REN

T (A

MPS

)T

I

, P

EAK

SUR

GE

CU

RR

ENT

(AM

P)TS

MV

,

GAT

E TR

IGG

ER V

OLT

AGE

(NO

RM

ALIZ

ED)

GT

TJ = 125°C


806040200–20–40–60

0.4

0

0.8

1.2

1.6

2.0

FIGURE 7 — TYPICAL HOLDING CURRENTFIGURE 6 — TYPICAL GATE TRIGGER CURRENT



2.4

0

0.4

0.8

1.2

1.6

2.0

2.8


80


–60 –20 0–40 20 40 60

I ,

HO

LDIN

G C

UR

REN

T (N

OR

MAL

IZED

)H

I

, GAT

E TR

IGG

ER C

UR

REN

T (N

OR

MAL

IZED

)G

Tr(t

), TR

ANSI

ENT

THER

MAL

RES

ISTA

NC

E(N

OR

MAL

IZED

)

10 k200 5.0 k2.0 k1.0 k5000.1

t, TIME (ms)

10050205.02.01.0

0.02

0.5

1.0

0.5

0.2

0.1

0.05

0.20.01








Dissipation and Durability• Gate Triggering Guaranteed in Three Modes (MAC210FP Series)

or Four Modes (MAC210AFP Series)



Repetitive Peak Off-State Voltage(1) (TJ = –40 to +125°C)1/2 Sine Wave 50 to 60 Hz, Gate Open


VDRM

200400600800

Volts

On-State RMS Current (TC = +70°C ) Full Cycle Sine Wave 50 to 60 Hz(2) IT(RMS) 10 Amps


ITSM 100 Amps




Peak Gate Current (TC = +70°C, Pulse Width = 10 µs) IGM 2 Amps










2. The case temperature reference point for all TC measurements is a point on the center lead of the package as close as possible to the plastic body.


MT1

G

MT2

CASE 221C-02STYLE 3






Peak Blocking Current (Either Direction)(VD = Rated VDRM, Gate Open) TJ = 25°C

TJ = +125°C

IDRM——

——

102

µAmA



Gate Trigger Current (Continuous dc)(Main Terminal Voltage = 12 Vdc, RL = 100 OhmsMinimum Gate Pulse Width = 2 µs)

MT2(+), G(+)MT2(+), G(–)MT2(–), G(–)MT2(–), G(+) “A” SUFFIX ONLY

IGT

————

12122035

50505075

mA

Gate Trigger Voltage (Continuous dc)(Main Terminal Voltage = 12 Vdc, RL = 100 OhmsMinimum Gate Pulse Width = 2 µs)


(Main Terminal Voltage = Rated VDRM, RL = 10 kΩ, TJ = +125°C)MT2(+), G(+); MT2(+), G(–); MT2(–), G(–)MT2(–), G(+) “A” SUFFIX ONLY

VGT

————

0.20.2

0.90.91.11.4

——

222

2.5

——

Volts

Holding Current (Either Direction)(Main Terminal Voltage = 12 Vdc, Gate Open,Initiating Current = 500 mA, TC = +25°C)

IH — 6 50 mA

Turn-On Time(Rated VDRM, ITM = 14 A, IGT = 120 mA,Rise Time = 0.1 µs, Pulse Width = 2 µs)

tgt — 1.5 — µs

Critical Rate of Rise of Commutation Voltage(VD = Rated VDRM, ITM = 14 A, Commutating di/dt = 5.0 A/ms,Gate Unenergized, TC = +70°C)


Critical Rate of Rise of Off–State Voltage(VD = Rated VDRM, Exponential Voltage Rise, Gate Open,TC = +70°C)

dv/dt — 100 — V/µs


T ,

MAX

IMU

M A

LLO

WAB

LE C

ASE

TEM

PER

ATU

RE

( C

)C

°

P D(A

V)

i T, I

NST

ANTA

NEO

US

ON

–STA

TE C

UR

REN

T (A

MPS

)

V GT,

GAT

E TR

IGG

ER V

OLT

AGE

(NO

RM

ALIZ

ED)

130

120

110

100

90

80

70

60

14

12

10

8

6

4

2

0100 1 2 3 4 5 6 7 8 9


Figure 1. Current Derating

100 1 2 3 4 5 6 7 8 9



CONDUCTION ANGLE = 360° CONDUCTION ANGLE = 360°

100

0.1

0.2

0.5

1

2

5

10

20

50

0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4 4.4



TJ = 125°C

TJ = 25°C

I TSM

, PEA

K SU

RG

E C

UR

REN

T (A

MP)

100

80

60

40

20

0101 2 3 5 7

NUMBER OF CYCLES

Figure 4. Maximum Nonrepetitive Surge Current

2

1.6

1.2

0.8

0.4

0– 60 – 40 – 20 0 20 40 60 80



CYCLE

TC = 70°Cf = 60 HzSURGE IS PRECEDED AND FOLLOWED BY RATED CURRENT



, AVE

RAG

E PO

WER

DIS

SIPA

TIO

N (W

ATTS

)


I GT,

GAT

E TR

IGG

ER C

UR

REN

T (N

OR

MAL

IZED

) 2

1.6

1.2

0.8

0.4

0– 60 – 40 – 20 0 20 40 60 80




2.8

2.4

2

1.6

1.2

0.8

0.4

0


I H, H

OLD

ING

CU

RR

ENT

(NO

RM

ALIZ

ED)

– 60 – 40 – 20 0 20 40 60 80

Figure 7. Typical Holding Current


r(t),

TRAN

SIEN

T TH

ERM

AL R

ESIS

TAN

CE

(NO

RM

ALIZ

ED)

1

0.01

0.02

0.05

0.1

0.2

0.5

0.1 0.2 0.5 1 2 5 20 50 100 200 500 1 k 2 k 5 k 10 kt, TIME (ms)









(MAC212A Series)




MAC212-4, MAC212A4MAC212-6, MAC212A6MAC212-8, MAC212A8 MAC212-10, MAC212A10

VDRM

200400600800

Volts

On-State Current RMS (TC = +85°C)Full Cycle Sine Wave 50 to 60 Hz

IT(RMS) 12 Amp

Peak Non-repetitive Surge Current (One Full Cycle, 60 Hz, TC = +85°C)preceded and followed by Rated Current

ITSM 100 Amp

Circuit Fusing Considerations (t = 8.3 ms) I2t 40 A2s



Peak Gate Current (TC = +85°C, Pulse Width = 10 µs) IGM 2 Amp






STYLE 4


MT1

GMT2








TJ = +125°C

IDRM——

——

102

µAmA

Peak On-State Voltage (Either Direction)ITM = 17 A Peak; Pulse Width = 1 to 2 ms, Duty Cycle 2%


Gate Trigger Current (Continuous dc)(Main Terminal Voltage = 12 Vdc, RL = 100 Ohms)

MT2(+), G(+) MT2(+), G(–) MT2(–), G(–) MT2(–), G(+) “A” SUFFIX ONLY

IGT

————

12122035

50505075

mA

Gate Trigger Voltage (Continuous dc)(Main Terminal Voltage = 12 Vdc, RL = 100 Ohms)


(Main Terminal Voltage = Rated VDRM, RL = 10 kΩ, TJ = +125°C)MT2(+), G(+); MT2(–), G(–); MT2(+), G(–)MT2(–), G(+) “A” SUFFIX ONLY

VGT

————

0.20.2

0.90.91.11.4

——

222

2.5

——

Volts


IH — 6 50 mA


tgt — 1.5 — µs



Critical Rate of Rise of Off-State Voltage(VD = Rated VDRM, Exponential Voltage Rise, Gate Open,TC = +85°C)

dv/dt — 100 — V/µs

30°60°90°

0

4.0

8.0

12

16

20

24

28

1412106.0 8.04.02.00


115

FIGURE 2 — POWER DISSIPATION

75

85

95

105

0 2.0 4.0 6.0 8.0 10 12

125

14


dc

180°90°


α

α

FIGURE 1 — CURRENT DERATING

60°

α

α


T ,

MAX

IMU

M A

LLO

WAB

LE C

ASE

TEM

PER

ATU

RE

( C

)C

°

P

,

AVE

RAG

E PO

WER

DIS

SIPA

TIO

N (W

ATT)

D(A

V)

α = 30°

dc

α = 180°


20

100

2.0

50

10

0.2

5.0

1.0

0.5

0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.00.1

4.4



0

20

40

60

80

FIGURE 4 — MAXIMUM NON-REPETITIVE SURGE CURRENT100

7.01.0 2.0 3.0 5.0

1.6

1.2

0.8

0.4

FIGURE 5 — TYPICAL GATE TRIGGER VOLTAGE2.0

CYCLE

TC = 70°Cf = 60 HzSurge is preceded and followed by rated current

NUMBER OF CYCLES

10

0806040200–20–40–60



806040200–20–40

1.2

800

0.4

0.8

1.6

–60–60 –40 –20 0 20

2.4

400

0.4

0.8

1.2

1.6

2.0

2.82.0


60

FIGURE 6 — TYPICAL GATE TRIGGER CURRENT


FIGURE 7 — TYPICAL HOLDING CURRENT

TC, CASE TEMPERATURE (°C) TC, CASE TEMPERATURE (°C)

I T

I

, P

EAK

SUR

GE

CU

RR

ENT

(AM

P)TS

M

V

, G

ATE

TRIG

GER

VO

LTAG

E (N

OR

MAL

IZED

)G

TI

, H

OLD

ING

CU

RR

ENT

(NO

RM

ALIZ

ED)

H

I

, GAT

E TR

IGG

ER C

UR

REN

T (N

OR

MAL

IZED

)G

T

TJ = 125°C

, IN

STAN

TAN

EOU

S O

N-S

TATE

CU

RR

ENT

(AM

PS)

TJ = 25°C



r(t),

TRAN

SIEN

T TH

ERM

AL R

ESIS

TAN

CE

(NO

RM

ALIZ

ED)

10 k200 5.0 k2.0 k1.0 k5000.1

t, TIME (ms)

10050205.02.01.0

0.02

0.5

1.0

0.5

0.2

0.1

0.05

0.20.01







Dissipation and Durability• Gate Triggering Guaranteed in Three Modes (MAC212FP Series) or

Four Modes (MAC212AFP Series)





VDRM

200400600800

Volts



ITSM 100 Amps
















MT1

G

MT2

CASE 221C-02STYLE 3







TJ = +125°C

IDRM——

——

102

µAmA



Gate Trigger Current (Continuous dc)(Main Terminal Voltage = 12 Vdc, RL = 100 Ohms,Minimum Gate Pulse Width = 2 µs)


IGT

————

12122035

50505075

mA

Gate Trigger Voltage (Continuous dc)(Main Terminal Voltage = 12 Vdc, RL = 100 Ohms,Minimum Gate Pulse Width = 2 µs)


(Main Terminal Voltage = Rated VDRM, RL = 10 kΩ, TJ = +125°C)MT2(+), G(+); MT2(+), G(–); MT2(–), G(–)MT2(–), G(+) “A” SUFFIX ONLY

VGT

————

0.20.2

0.90.91.11.4

——

222

2.5

——

Volts


IH — 6 50 mA


tgt — 1.5 — µs



Critical Rate of Rise of Off–State Voltage(VD = Rated VDRM, Exponential Voltage Rise, Gate Open,TC = +85°C)

dv/dt — 100 — V/µs

T ,

MAX

IMU

M A

LLO

WAB

LE C

ASE

TEM

PER

ATU

RE

( C

)C

°

P D(A

V)

125

115

105

95

85

75

28

24

20

16

12

8.0

4.0

0100 2.0 4.0 6.0 8.0






, AVE

RAG

E PO

WER

DIS

SIPA

TIO

N (W

ATTS

)

12 14


αα

α = 30°

60°90°

180°

dc

100 2.0 4.0 6.0 8.0 12 14


αα

30°60°90°

α = 180°

dc


i T, I

NST

ANTA

NEO

US

ON

–STA

TE C

UR

REN

T (A

MPS

)

V GT,

GAT

E TR

IGG

ER V

OLT

AGE

(NO

RM

ALIZ

ED)

100

0.1

0.2

0.5

1

2

5

10

20

50

0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4 4.4



TJ = 125°C

TJ = 25°C

I TSM

, PEA

K SU

RG

E C

UR

REN

T (A

MP)

100

80

60

40

20

0101 2 3 5 7

NUMBER OF CYCLES


2

1.6

1.2

0.8

0.4

0– 60 – 40 – 20 0 20 40 60 80



CYCLE



I GT,

GAT

E TR

IGG

ER C

UR

REN

T (N

OR

MAL

IZED

) 2

1.6

1.2

0.8

0.4

0– 60 – 40 – 20 0 20 40 60 80




2.8

2.4

2

1.6

1.2

0.8

0.4

0


I H, H

OLD

ING

CU

RR

ENT

(NO

RM

ALIZ

ED)

– 60 – 40 – 20 0 20 40 60 80




r(t),

TRAN

SIEN

T TH

ERM

AL R

ESIS

TAN

CE

(NO

RM

ALIZ

ED)

1

0.01

0.02

0.05

0.1

0.2

0.5

0.1 0.2 0.5 1 2 5 20 50 100 200 500 1 k 2 k 5 k 10 kt, TIME (ms)





. . . designed primarily for full-wave ac control applications, such as light dimmers,motor controls, heating controls and power supplies.

• Blocking Voltage to 800 Volts• Glass Passivated Junctions for Greater Parameter Uniformity and Stability• TO-220 Construction Low Thermal Resistance, High Heat Dissipation and

Durability• Gate Triggering Guaranteed in Three Modes (MAC218 Series) or Four Modes

(MAC218A Series)



Peak Repetitive Off-State Voltage(1)

(Gate Open, TJ = 25 to 125°C) MAC218-4, MAC218A4MAC218-6, MAC218A6MAC218-8, MAC218A8MAC218-10, MAC218A10

VDRM200400600800

Volts

On-State Current RMS(Conduction Angle = 360°, TC = +80°C)

IT(RMS) 8 Amps

Peak Non-repetitive Surge Current(One Full Cycle, 60 Hz, TC = 80°C, preceded and followed by rated current)

ITSM 100 Amps

Fusing Current(t = 8.3 ms)

I2t 40 A2s


PGM 16 Watts

Average Gate Power(TC = +80°C, t = 8.3 ms)

PG(AV) 0.35 Watt

Peak Gate Trigger Current(Pulse Width = 1 µs)

IGTM 4 Amps






STYLE 4

TRIACs8 AMPERES RMS

200 thru 800 VOLTS

MT1

G

MT2







Peak Blocking Current(VD = Rated VDRM, gate open) TJ = 25°C

TJ = 125°C

IDRM——

——

102

µAmA

Peak On-State Voltage (Either Direction)(ITM = 11.3 A Peak; Pulse Width = 1 to 2 ms, Duty Cycle 2%)

VTM — 1.7 2 Volts

Gate Trigger Current (Continuous dc)(VD = 12 Vdc, RL = 12Ω)Trigger ModeMT2(+), Gate(+); MT2(+), Gate(–); MT2(–), Gate(–)MT2(–), Gate(+) “A” SUFFIX ONLY

IGT

——

——

5075

mA



(Main Terminal Voltage = Rated VDRM, RL = 10 kΩ, TJ = +125°C)MT2(+), G(+); MT2(–), G(–); MT2(+), G(–) MT2(–), G(+) “A” SUFFIX ONLY

VGT

————

0.20.2

0.90.91.11.4

——

222

2.5

——

Volts

Holding Current (Either Direction)(VD = 24 Vdc, Gate Open,Initiating Current = 200 mA)

IH — — 50 mA

Critical Rate of Rise of Commutating Off-State Voltage(VD = Rated VDRM, ITM = 11.3 A, Commutating di/dt = 4.1 A/ms, Gate Unenergized, TC = 80°C)


Critical Rate of Rise of Off-State Voltage(VD = Rated VDRM, Exponential Voltage Rise, Gate Open,TJ = 125°C)

dv/dt — 100 — V/µs

105

115

7.06.05.04.03.02.01.000

IT(RMS) RMS ON STATE CURRENT (AMPS)

8.0


10

8.0

6.0

4.0

2.0

750

IT(RMS), RMS ON STATE CURRENT (AMPS)

FIGURE 1 — CURRENT DERATING

85

95

125

8.07.06.05.04.03.02.01.0

T ,

MAX

IMU

M A

LLO

WAB

LE C

ASE

CTE

MPE

RAT

UR

E (

C)

°

P

, A

VER

AGE

POW

ER D

ISSI

PATI

ON

(WAT

TS)

(AV)


–40


4

QUADRANT


80 140120100–40 604020–20 0–600.5

0.7

1.0

2.0

3.0

5.0

FIGURE 3 — NORMALIZED GATE TRIGGER CURRENT


1.8

1.6

1.0

14012040–20 100

0.3

0.5

0.7

80602000.2

–60

1.4

2.0

–20 200 40 60

0.6

–40 100 120 14080

0.8

1.0

1.2

0.4–60

3

2

FIGURE 4 — NORMALIZED GATE TRIGGER VOLTAGE

1


QUADRANT 4

QUADRANTS


FIGURE 5 — NORMALIZED HOLDING CURRENT

I

, NO

RM

ALIZ

ED G

ATE

TRIG

GER

CU

RR

ENT

(mA)

GT

V

, N

OR

MAL

IZED

GAT

E TR

IGG

ER V

OLT

AGE

(VO

LTS)

GT

I ,

NO

RM

ALIZ

ED H

OLD

ING

CU

RR

ENT

(mA)

H

12


GATE OPEN

3





• Blocking Voltage to 800 Volts• Glass Passivated Junctions for Greater Parameter Uniformity and Stability• Isolated TO–220 Type Package for Ease of Mounting• Gate Triggering in Three Modes (MAC218FP Series) or




Peak Repetitive Off-State Voltage(1) (TJ = –40 to +125°C)(1/2 Sine Wave 50 to 60 Hz, Gate Open) MAC218-4FP, MAC218A4FP

MAC218-6FP, MAC218A6FPMAC218-8FP, MAC218A8FPMAC218-10FP, MAC218A10FP

VDRM200400600800

Volts


Peak Nonrepetitive Surge Current (One Full Cycle, 60 Hz, preceded and followed by rated current, TC = +80°C)

ITSM 100 Amps




Peak Gate Current (Pulse Width = 1 µs) IGM 4 Amps












MT1

G

MT2

CASE 221C-02STYLE 3






Peak Off–State Current (Either Direction)(VD = Rated VDRM @ TJ = 125°C, Gate Open)

IDRM — — 2 mA

Peak On-State Voltage (Either Direction)(ITM = 11.3 A Peak; Pulse Width = 1 to 2 ms, Duty Cycle 2%)

VTM — 1.7 2 Volts

Gate Trigger Current (Continuous dc) (VD = 12 Vdc, RL = 12 Ω)Trigger Mode


IGT

————

————

50505075

mA



(Main Terminal Voltage = Rated VDRM, RL = 10 kΩ, TJ = +125°C)MT2(+), G(+); MT2(–), G(–); MT2(+), G(–)MT2(–), G(+) “A” SUFFIX ONLY

VGT

————

0.20.2

0.90.91.11.4

——

222

2.5

——

Volts

Holding Current (Either Direction)(VD = 24 Vdc, Gate Open, Initiating Current = 200 mA)

IH — — 50 mA

Critical Rate of Rise of Commutating Off–State Voltage(VD = Rated VDRM, ITM = 11.3 A, Commutating di/dt = 4.1 A/ms, Gate Unenergized, TC = 80°C)


Critical Rate of Rise of Off–State Voltage(VD = Rated VDRM, Exponential Voltage Rise, Gate Open,TJ = 125°C)

dv/dt — 100 — V/µs

T ,

MAX

IMU

M A

LLO

WAB

LE C

ASE

TEM

PER

ATU

RE

( C

)C

°

P D(A

V)

125

115

105

95

85

75

10

8

6

4

2

00 1 2 3 4 5 6 7 8



0 1 2 3 4 5 6 7 8



, AVE

RAG

E PO

WER

DIS

SIPA

TIO

N (W

ATTS

)


I GT,

NO

RM

ALIZ

ED G

ATE

TRIG

GER

CU

RR

ENT

(mA)

5

3

2

1

0.7

0.5– 60 – 40 – 20 0 20 40 60 80


Figure 3. Normalized Gate Trigger Current


1.8

1.6

1.4

1.2

1

0.8

0.6

0.4


Figure 4. Normalized Gate Trigger Voltage

2

1

0.7

0.5

0.3

0.2


I H, N

OR

MAL

IZED

HO

LDIN

G C

UR

REN

T (m

A)

Figure 5. Normalized Holding Current

V GT,

NO

RM

ALIZ

ED G

ATE

TRIG

GER

VO

LTAG

E (V

OLT

S)

100 120 140 – 60 – 40 – 20 0 20 40 60 80 100 120 140

– 60 – 40 – 20 0 20 40 60 80 100 120 140


GATE OPEN



QUADRANT 4

QUADRANTS123

QUADRANT

1234



. . . designed primarily for full-wave ac control applications such as lighting systems,heater controls, motor controls and power supplies; or wherever full–wave silicon–gate–controlled devices are needed.

• Off–State Voltages to 800 Volts• All Diffused and Glass Passivated Junctions for Parameter Uniformity and Stability• Small, Rugged, Thermowatt Construction for Thermal Resistance and High Heat

Dissipation• Gate Triggering Guaranteed in Three Modes (MAC223 Series) or Four Modes

(MAC223A Series)



Peak Repetitive Off-State Voltage(TJ = –40 to 125°C)(1)

(1/2 Sine Wave 50 to 60 Hz, Gate Open)MAC223-4, MAC223A4MAC223-6, MAC223A6MAC223-8, MAC223A8MAC223–10, MAC223A10

VDRM

200400600800

Volts

On-State RMS Current (TC = 80°C)(Full Cycle Sine Wave 50 to 60 Hz)

IT(RMS) 25 Amps

Peak Non-repetitive Surge Current(One Full Cycle, 60 Hz, TC = 80°C, preceded and followed by rated current)

ITSM 250 Amps


I2t 260 A2s

Peak Gate Current (t 2 µs) IGM 2 Amps

Peak Gate Voltage (t 2 µs) VGM 10 Volts

Peak Gate Power (t 2 µs) PGM 20 Watts

Average Gate Power (TC = 80°C, t 8.3 ms) PG(AV) 0.5 Watts

Operating Junction Temperature Range TJ –40 to 125 °C

Storage Temperature Range Tstg –40 to 150 °C

Mounting Torque — 8 in. lb.




STYLE 4


MT1GMT2






ELECTRICAL CHARACTERISTICS (TC = 25°C and either polarity of MT2 to MT1 voltage unless otherwise noted.)



(VD = Rated VDRM) TJ = 25°CTJ = 125°C

IDRM——

——

102

µAmA

Peak On-State Voltage(ITM = 35 A Peak, Pulse Width 2 ms, Duty Cycle 2%)


Gate Trigger Current (Continuous dc)(VD = 12 V, RL = 100 Ω)MT2(+), G(+); MT2(–), G(–); MT(+), G(–)MT2(–), G(+) “A” SUFFIX ONLY

IGT

——

2030

5075

mA

Gate Trigger Voltage (Continuous dc)(VD = 12 V, RL = 100 Ω)MT2(+), G(+); MT2(–), G(–); MT(+), G(–)MT2(–), G(+) “A” SUFFIX ONLY(VD = Rated VDRM, TJ = 125°C, RL = 10 k)MT(+), G(+); MT2(–), G(–); MT2(+), G(–)MT2(–), G(+) “A” SUFFIX ONLY

VGT

——0.2

0.2

1.11.30.4

0.4

22.5—

—

Volts

Holding Current (VD = 12 V, ITM = 200 mA, Gate Open)

IH — 10 50 mA

Gate Controlled Turn–On Time(VD = Rated VDRM, ITM = 35 A Peak, IG = 200 mA)

tgt — 1.5 — µs

Critical Rate of Rise of Off-State Voltage(VD = Rated VDRM, Exponential Waveform, TC = 125°C)


Critical Rate of Rise of Commutation Voltage(VD = Rated VDRM, ITM = 35 A Peak, Commutatingdi/dt = 12.6 A/ms, Gate Unenergized, TC = 80°C)


1. Ratings apply for open gate conditions. Devices shall not be tested with a constant current source for blocking voltage such that the voltageapplied exceeds the rated blocking voltage.

T ,

MAX

IMU

M A

LLO

WAB

LE C

ASE

TEM

PER

ATU

RE

( C

)C

°

P D

125

115

105

95

85

75

40

30

20

10

00 5.0 10 15 20 25


FIGURE 1 – RMS CURRENT DERATING


FIGURE 2 – ON-STATE POWER DISSIPATION

, AVE

RAG

E PO

WER

DIS

SIPA

TIO

N (W

ATTS

)

0 5.0 10 15 20 25


NO

RM

ALIZ

ED G

ATE

CU

RR

ENT

3.0

2.0

1.0

0.2

0.1– 60 – 40 – 20 0 20 40 60 80






FIGURE 5 – HOLD CURRENT

100 120 140 – 60 – 40 – 20 0 20 40 60 80 100 120 140

– 60 – 40 – 20 0 20 40 60 80 100 120 140

VD = 12 VRL = 100 Ω

200100

0.1

VTM, INSTANTANEOUS ON–STATE VOLTAGE (VOLTS)

i TM

, IN

STAN

TAN

EOU

S O

N–S

TATE

CU

RR

ENT

(AM

PS) FIGURE 6 – TYPICAL ON–STATE CHARACTERISTIC S

0

NO

RM

ALIZ

ED G

ATE

VOLT

AGE

NO

RM

ALIZ

ED H

OLD

CU

RR

ENT

0.3

0.5

3.0

2.0

1.0

0.2

0.1

0.3

0.5

2.0

1.0

0.2

0.1

0.3

0.5

0.5

1.0

5.0

10

50

1.0 2.0 3.0 4.0

VD = 12 VRL = 100 Ω

ITM = 200 mAGate Open TJ = 25°C



. . . designed primarily for full-wave ac control applications, such as lighting systems,heater controls, motor controls and power supplies; or wherever full–wave silicon–gate–controlled devices are needed.

• Off–State Voltages to 800 Volts• All Diffused and Glass Passivated Junctions for Parameter Uniformity and Stability• Small, Rugged Thermowatt Construction for Thermal Resistance and High Heat

Dissipation• Gate Triggering Guaranteed in Three Modes (MAC223FP Series) or




Peak Repetitive Off-State Voltage(1) (TJ = –40 to +125°C,1/2 Sine Wave 50 to 60 Hz, Gate Open)


VDRM

200400600800

Volts

On-State RMS Current (TC = +80°C) Full Cycle Sine Wave 50 to 60 Hz(2) IT(RMS) 25 Amps

Peak Nonrepetitive Surge Current (One Full Cycle, 60 Hz, TC = 80°C,preceded and followed by rated current)

ITSM 250 Amps



Average Gate Power (TC = +80°C, t 8.3 ms) PG(AV) 0.5 Watt












Thermal Resistance, Case to Sink RθCS 2.2 °C/W



MT1

G

MT2

CASE 221C-02STYLE 3






Peak Blocking Current(1) TJ = 25°C(VD = Rated VDRM, Gate Open) TJ = 125°C

IDRM ——

——

102

µAmA



Gate Trigger Current (Continuous dc)(VD = 12 V, RL = 100 Ω)MT2(+), G(+); MT2(–), G(–); MT2(+), G(–)MT2(–), G(+) “A” SUFFIX ONLY

IGT

——

2030

5075

mA

Gate Trigger Voltage (Continuous dc)(VD = 12 V, RL = 100 Ω)MT2(+), G(+); MT2(–), G(–); MT2(+), G(–)MT2(–), G(+) “A” SUFFIX ONLY(VD = Rated VDRM, TJ = 125°C, RL = 10 k)MT(+), G(+); MT2(–), G(–); MT2(+), G(–)MT2(–), G(+) “A” SUFFIX ONLY

VGT

——0.2

0.2

1.11.30.4

0.4

22.5—

—

Volts

Holding Current(VD = 12 V, ITM = 200 mA, Gate Open)

IH — 10 50 mA

Gate Controlled Turn–On Time(VD = Rated VDRM, ITM = 35 A Peak, IG = 200 mA)

tgt — 1.5 — µs

Critical Rate of Rise of Off–State Voltage(VD = Rated VDRM, Exponential Waveform, TC = 125°C)





Figure 1. RMS Current Derating Figure 2. On–State Power Dissipation


15

105

85

75

100 5

95

115

125

T

2520


150

40

20

10

05 10

30

P

20 25, MAX

IMU

M A

LLO

WAB

LE C

ASE

TEM

PER

ATU

RE

( C

)°

C

, AVE

RAG

E PO

WER

DIS

SIPA

TIO

N (W

ATTS

)D

(AV)



Figure 3. Gate Trigger Current Figure 4. Gate Trigger Voltage

Figure 5. Hold Current Figure 6. Typical On–State Characteristics

vTM, INSTANTANEOUS ON–STATE VOLTAGE (VOLTS)

0

100

10

1

0.11 2 3 4


60–60

1

0.30.2

0.140–40 –20 0 20

0.5

23

NO

RM

ALIZ

ED G

ATE

CU

RR

ENT

i

50

5

0.5

200

TJ = 25°C

12010080 140

VD = 12 VRL = 100


60–60

1

0.30.2

0.140–40 –20 0 20

0.5

23

NO

RM

ALIZ

ED G

ATE

VOLT

AGE

12010080 140

VD = 12 VRL = 100


60–60

1

0.30.2

0.140–40 –20 0 20

0.5

2

NO

RM

ALIZ

ED H

OLD

CU

RR

ENT

12010080 140

ITM = 200 mAGATE OPEN

, IN

STAN

TAN

EOU

S O

N–S

TATE

CU

RR

ENT

(AM

PS)

TM


Silicon Bidirectional 40 Amperes RMSTriode Thyristors

. . . designed primarily for full-wave ac control applications such as lighting systems,heater controls, motor controls and power supplies.

• Blocking Voltage to 800 Volts• All Diffused and Glass-Passivated Junctions for Parameter Uniformity and Stability• Gate Triggering Guaranteed in Three Modes (MAC224 Series) or Four Modes

(MAC224A Series)




(TJ = –40 to 125°C,1/2 Sine Wave 50 to 60 Hz, Gate Open)

MAC224-4, MAC224A4MAC224-6, MAC224A6MAC224-8, MAC224A8MAC224-10, MAC224A10

VDRM

200400600800

Volts

On-State RMS Current (TC = 75°C)(2)

(Full Cycle Sine Wave 50 to 60 Hz)IT(RMS) 40 Amps

Peak Non-repetitive Surge Current(One Full Cycle, 60 Hz, TJ = 125°C)

ITSM 350 Amps


Peak Gate Current (t 2 µs) IGM ±2 Amps

Peak Gate Voltage (t 2 µs) VGM ±10 Volts






1. VDRM for all types can be applied on a continuous basis. Blocking voltages shall not be tested with a constant current source (cont.)such that the voltage ratings of the devices are exceeded.

2. This device is rated for use in applications subject to high surge conditions. Care must be taken to insure proper heat sinking when the deviceis to be used at high sustained currents. (See Figure 1 for maximum case temperatures.)



STYLE 4


GMT2 MT1








Peak Blocking Current(Rated VDRM, Gate Open) TJ = 25°C

TJ = 125°C

IDRM——

——

102

µAmA



Gate Trigger Current (Continuous dc)(VD = 12 V, RL = 100 Ω)MT2(+), G(+); MT2(+), G(–); MT2(+), G(–)MT2(–), G(+) “A” SUFFIX ONLY

IGT

——

2540

5075

mA

Gate Trigger Voltage (Continuous dc)(VD = 12 V, RL = 100 Ω)MT2(+), G(+); MT2(–), G(–); MT(+), G(–)MT2(–), G(+) “A” SUFFIX ONLY

VGT

——

1.11.3

22.5

Volts

Gate Non-Trigger Voltage(VD = Rated VDRM, TJ = 125°C, RL = 10 k)MT2(+), G(+); MT2(–), G(–); MT(+), G(–)MT2(–), G(+)

VGD

0.20.2

——

——

Volts

Holding Current (VD = 12 Vdc, Gate Open) IH — 30 75 mA

Gate Controlled Turn-On Time(VD = Rated VDRM, ITM = 56 A Peak, IG = 200 mA)

tgt — 1.5 — µs





*This device is rated for use in applications subject to high surge conditions. Care must be taken to insure proper heat sinking when the device is tobe used at high sustained currents.

FIGURE 2 – ON-STATE POWER DISSIPATIONFIGURE 1 – RMS CURRENT DERATING

75

95

IT(RMS), RMS ON-STATE CURRENT (AMPS)*

25205.0

125

115

85

100 15

105

100

0 2520

24

12

5.0 15

IT(RMS), RMS ON-STATE CURRENT (AMPS)*

DP ,

AVE

RAG

E PO

WER

DIS

SIPA

TIO

N (W

ATTS

)

120

110

100

90

80

30 35 40 30 35 40

6.0

18

30

36

48

42

54

60

CT ,

MAX

IMU

M A

LLO

WAB

LE C

ASE

TEM

PER

ATU

RE

( C

)°



FIGURE 5 – HOLDING CURRENT


FIGURE 6 – TYPICAL ON-STATE CHARACTERISTICS


–60 120–40 0–20 20 40 60 80 100 140


VD = 12 VRL = 100 Ω

3.0

2.0

1.0

0.5

0.30.2

0.1–60 120–40 0–20 20 40 60 80 100 140


3.0

2.0

1.0

0.5

0.30.2

0.1

VD = 12 VRL = 100 Ω

–60 120–40 0–20 20 40 60 80 100 140TJ, JUNCTION TEMPERATURE (°C)

2.0

1.0

0.5

0.30.2

0.1

ITM = 200 mAGate Open

NO

RM

ALIZ

ED G

ATE

VOLT

AGE

NO

RM

ALIZ

ED G

ATE

CU

RR

ENT

NO

RM

ALIZ

ED H

OLD

CU

RR

ENT

VTM, INSTANTANEOUS ON-STATE VOLTAGE (VOLTS)

1.0

10

100

0 1.0 2.0 3.0

TJ = 25°C

TMI

1000

0.1 5 k2 k1 k5002001005020 10 k


t, TIME (ms)

1

0.2

0.5

5

0.02

0.1

0.01210.50.2

0.05

r(t),

TRAN

SIEN

T TH

ERM

AL R

ESIS

TAN

CE

(NO

RM

ALIZ

ED)

, IN

STAN

TAN

EOU

S O

N-S

TATE

CU

RR

ENT

(AM

PS)



. . . designed primarily for industrial and consumer applications for full wave control ofac loads such as appliance controls, heater controls, motor controls, and other powerswitching applications.

• Sensitive Gate Triggering in 3 Modes for AC Triggering on Sinking CurrentSources (MAC228 Series)

• Four Mode Triggering for Drive Circuits that Source Current (MAC228A Series)• All Diffused and Glass–Passivated Junctions for Parameter Uniformity and

Stability• Small, Rugged, Thermowatt Construction for Low Thermal resistance and High

Heat Dissipation• Center Gate Geometry for Uniform Current Spreading




(TJ = –40 to 110°C1/2 Sine Wave 50 to 60 Hz, Gate Open)

MAC228-4, MAC228A4MAC228-6, MAC228A6MAC228-8, MAC228A8MAC228–10, MAC228A10

VDRM

200400600800

Volts

On-State RMS Current (TC = 80°C)Full Cycle Sine Wave 50 to 60 Hz

IT(RMS) 8 Amps

Peak Non-repetitive Surge Current(One Full Cycle 60 Hz, TJ = 110°C)

ITSM 80 Amps


I2t 26 A2s




1. VDRM for all types can be applied on a continuous basis. Blocking voltages shall not be tested with a constant current (continued)source such that the voltage ratings of the devices are exceeded.



STYLE 4

TRIACs8 AMPERES RMS

200 thru 800 VOLTS

MT1GMT2







Mounting Torque 8 in. lb.







Peak Blocking Current(VD = Rated VDRM) TJ = 25°C

TJ = 110°C

IDRM——

——

102

µAmA



Gate Trigger Current (Continuous dc)(VD = 12 V, RL = 100 Ω)MT2(+), G(+); MT2(+), G(–); MT2(–), G(–)MT2(–), G(+) “A” Suffix Only

IGT

——

——

510

mA

Gate Trigger Voltage (Continuous dc)(VD = 12 V, RL = 100 Ω)MT2(+), G(+); MT2(+), G(–); MT2(–), G(–)MT2(–), G(+) “A” Suffix Only(VD = Rated VDRM, TC = 110°C, RL = 10 k)MT2(+), G(+); MT2(+), G(–); MT2(–), G(–)MT2(–), G(+) “A” Suffix Only

VGT

——

0.20.2

——

——

22.5

——

Volts

Holding Current (VD = 12 Vdc, ITM = 200 mA, Gate Open)

IH — — 15 mA

Gate–Controlled Turn–On Time(VD = Rated VDRM, ITM = 16 A Peak, IG = 30 mA)

tgt — 1.5 — µs



Critical Rate of Rise of Commutation Voltage(VD = Rated VDRM, ITM = 11.3 A,Commutating di/dt = 4.1 A/ms, Gate Unenergized, TC = 80°C)




6.00

104

98

92

5.01.0 2.0 3.0 4.0

110

T

7.0 8.0


P

, CAS

E TE

MPE

RAT

UR

E (

C)

C°

6.00

4.0

2.0

05.01.0 2.0 3.0 4.0 7.0 8.0

, AVE

RAG

E PO

WER

(WAT

TS)

(AV)

120°

90°

60°

30°

180°

120°90°

60°

= 30°

6.0

8.0

10

86

80

dc

dc

TJ ≈ 110°C

α

α


α

α


= 180°




• Four Mode Triggering for Drive Circuits that Source Current• All Diffused and Glass–Passivated Junctions for Parameter Uniformity and Stability• Small, Rugged, Thermowatt Construction for Low Thermal resistance and High

Heat Dissipation• Center Gate Geometry for Uniform Current Spreading






VDRM

200400600800

Volts


IT(RMS) 8 Amps

Peak Non–repetitive Surge Current(One Full Cycle 60 Hz, TJ = 110°C)

ITSM 80 Amps


I2t 26 A2s











MT1G

MT2

CASE 221C-02STYLE 3

TRIACs8 AMPERES RMS

200 thru 800 VOLTS










TJ = 110°C

IDRM——

——

102

µAmA




IGT

——

——

510

mA


VGT

——

0.20.2

——

——

22.5

——

Volts


IH — — 15 mA


tgt — 1.5 — µs







6.00

104

98

92

5.01.0 2.0 3.0 4.0

110

T

7.0 8.0


P

, CAS

E TE

MPE

RAT

UR

E (

C)

C°

6.00

4.0

2.0

05.01.0 2.0 3.0 4.0 7.0 8.0

, AVE

RAG

E PO

WER

(WAT

TS)

(AV)

120°

90°

60°

30°

180°

120°90°

60°

= 30°

6.0

8.0

10

86

80

dc

dc

TJ ≈ 110°C

α

α


α

α


= 180°




• All Diffused and Glass–Passivated Junctions for Parameter Uniformity andStability

• Small, Rugged, Thermowatt Construction for Low Thermal resistance and HighHeat Dissipation

• Center Gate Geometry for Uniform Current Spreading• Gate Triggering Guaranteed in Three Modes (MAC229 Series) or Four Modes

(MAC229A Series)





MAC229-4, MAC229A4MAC229-6, MAC229A6MAC229-8, MAC229A8MAC229–10, MAC229A10

VDRM

200400600800

Volts


IT(RMS) 8 Amps


ITSM 80 Amps


I2t 26 A2s




Average Gate Power(TC = 80°C, t 8.3 ms)

PG(AV) 0.5 Watts




1. VDRM for all types can be applied on a continuous basis. Blocking voltages shall not be tested with a constant current source (cont.)such that the voltage ratings of the devices are exceeded.



STYLE 4

TRIACs8 AMPERES RMS

200 thru 800 VOLTS

MT1GMT2









(VD = Rated VDRM, Gate Open) TJ = 25°CTJ = 110°C

IDRM——

——

102

µAmA



Gate Trigger Current (Continuous dc)(VD = 12 V, RL = 100 Ω)MT2(+), G(+); MT2(+), G(–); MT2(–), G(–)MT2(–), G(+) “A” SUFFIX ONLY

IGT

——

——

1015

mA

Gate Trigger Voltage (Continuous dc)(VD = 12 V, RL = 100 Ω)MT2(+), G(+); MT2(+), G(–); MT2(–), G(–)MT2(–), G(+) “A” SUFFIX ONLY(VD = Rated VDRM, TC = 110°C, RL = 10 k)MT2(+), G(+); MT2(+), G(–); MT2(–), G(–) All TypesMT2(–), G(+) “A” SUFFIX ONLY MAC229 series

VGT

——

0.20.2

——

——

22.5

——

Volts

Holding Current (VD = 12 Vdc, ITM = 200 mA, Gate Open)

IH — — 15 mA


tgt — 1.5 — µs







6.00

104

98

92

5.01.0 2.0 3.0 4.0

110

T

7.0 8.0


P

, CAS

E TE

MPE

RAT

UR

E (

C)

C°

6.00

4.0

2.0

05.01.0 2.0 3.0 4.0 7.0 8.0

, AVE

RAG

E PO

WER

(WAT

TS)

(AV)

120°

90°

60°

30°

180°

120°90°

60°

= 30°

6.0

8.0

10

86

80

dc

dc

TJ ≈ 110°C

α

α


α

α


= 180°




• All Diffused and Glass–Passivated Junctions for Parameter Uniformity and Stability• Small, Rugged, Thermowatt Construction for Low Thermal resistance and High

Heat Dissipation• Center Gate Geometry for Uniform Current Spreading• Gate Triggering Guaranteed in Three Modes (MAC229FP Series) or Four Modes

(MAC229AFP Series)




(TJ = –40 to 110°C,1/2 Sine Wave 50 to 60 Hz, Gate Open)


VDRM

200400600800

Volts


IT(RMS) 8 Amps

Peak Non–repetitive Surge Current(One Full Cycle 60 Hz, TJ = 110°C)

ITSM 80 Amps


I2t 26 A2s




Average Gate Power(TC = 80°C, t 8.3 ms)

PG(AV) 0.5 Watts







MT1G

MT2

CASE 221C-02STYLE 3

TRIACs8 AMPERES RMS

200 thru 800 VOLTS










(VD = Rated VDRM, Open Gate) TJ = 25°CTJ = 110°C

IDRM——

——

102

µAmA




IGT

——

——

510

mA


VGT

——

0.20.2

——

——

22.5

——

Volts


IH — — 15 mA


tgt — 1.5 — µs







6.00

104

98

92

5.01.0 2.0 3.0 4.0

110

T

7.0 8.0


P

, CAS

E TE

MPE

RAT

UR

E (

C)

C°

6.00

4.0

2.0

05.01.0 2.0 3.0 4.0 7.0 8.0

, AVE

RAG

E PO

WER

(WAT

TS)

(AV)

120°

90°

60°

30°

180°

120°90°

60°

= 30°

6.0

8.0

10

86

80

dc

dc

TJ ≈ 110°C

α

α


α

α


= 180°




• Sensitive Gate Triggering in Three Trigger Modes for AC Triggering on SinkingCurrent Sources (MAC310 Series)

• Four Mode Triggering (10 mA) for Drive Circuits that Source Current (MAC310ASeries)

• All Diffused and Glass-Passivated Junctions for Parameter Uniformity and Stability• Small, Rugged, Thermowatt Construction for Low Thermal Resistance, High Heat

Dissipation• Center Gate Geometry for Uniform Current Spreading

MAXIMUM RATINGS (TC = 25°C unless otherwise noted.)


Peak Repetitive Off-State Voltage(1) (TJ = –40 to 110°C,1/2 Sine Wave 50 to 60 Hz, Gate Open) MAC310-4, MAC310A4

MAC310-6, MAC310A6MAC310-8, MAC310A8

VDRM200400600

Volts


IT(RMS) 10 Amps


ITSM 100 Amps


Peak Gate Current (t 2 µs) IGM ±2 Amps






Mounting Torque — 8 in-lb

1. VDRM for all types can be applied on a continuous basis. Blocking voltages shall not be tested with a constant (continued)current source such that the voltage ratings of the devices are exceeded.



STYLE 4


MT1

G

MT2








Peak Blocking Current TJ = 25°C(VD = Rated VDRM, TJ = 110°C)

IDRM ——

——

102

mA


VTM — — 2 Volts

Gate Trigger Current (Continuous dc)(VD = 12 V, RL = 100 Ω)

MT2(+), G(+); MT2(+), G(–); MT2(–), G(–)MT2(–), G(+) “A” Suffix Only

IGT

——

——

510

mA

Gate Trigger Voltage (Continuous dc)(VD = 12 V, RL = 100 Ω)

MT2(+), G(+); MT2(+), G(–); MT2(–), G(–)MT2(–), G(+) “A” Suffix Only

(VD = Rated VDRM, TC = 110°C, RL = 10 k)All Trigger Modes

VGT

——

0.2

——

—

22.5

—

Volts


IH — — 15 mA

Gate-Controlled Turn-On Time(VD = Rated VDRM, ITM = 14 A Peak, IG = 30 mA)

tgt — 1.5 — µs



Critical Rate of Rise of Commutation Voltage(VD = Rated VDRM, ITM = 14 A Peak,Commutating di/dt = 5 A/ms, Gate Unenergized, TC = 80°C)


16

20

120

110

100

90


80

90°60°

180°

dc

30°

8 106420


°T

, C

ASE

TEM

PER

ATU

RE

( C

)C

IT(RMS), RMS ON-STATE CURRENT (AMPS)8 106420


dc

90°60°

180°120°

4

0

P

, AV

ERAG

E PO

WER

(WAT

TS)

AV

30°8

12







(MAC320A Series)




MAC320-4, MAC320A4MAC320-6, MAC320A6MAC320-8, MAC320A8MAC320-10, MAC320A10

VDRM

200400600800

Volts


On-State Current RMS (TC = +75°C)(Full Cycle, Sine Wave, 50 to 60 Hz)

IT(RMS) 20 Amp

Peak Surge Current (One Full Cycle, 60 Hz, TC = +75°C)preceded and followed by rated current

ITSM 150 Amp



Peak Gate Current IGM 2 Amp









STYLE 4


MT1

GMT2




Peak Blocking Current(VD Rated VDRM, Gate Open) TJ = 25°C

TJ = +125°C

IDRM——

——

102

µAmA




MT2 (+), G(+); MT2 (+), G(–); MT2 (–), G(–)MT2 (–), G(+) “A” SUFFIX ONLY

IGT

——

——

5075

mA


MT2 (+), G(+); MT2 (+), G(–); MT2 (–), G(–)MT2 (–), G(+) “A” SUFFIX ONLY

(Main Terminal Voltage = Rated VDRM, RL = 10 kΩ, TJ =+110°C)MT2 (+), G(+); MT2 (–), G(–); MT2 (+), G(–);MT2 (–), G(+) “A” SUFFIX ONLY

VGT——

0.20.2

0.91.4

——

22.5

——

Volts


IH — 6 40 mA

Turn-On Time(VD = Rated VDRM, ITM = 28 A,IGT = 120 mA, Rise Time = 0.1 µs, Pulse Width = 2 µs)

tgt — 1.5 — µs

Critical Rate of Rise of Commutation Voltage(VD = Rated VDRM, ITM = 28 A, Commutatingdi/dt = 10 A/ms, Gate Unenergized, TC = +75°C)

dv/dt(C) — 5 — V/µs

110

120

130

2.0 4.0 6.0 8.0 10 12

60

70

80

90

100

14 16

dc

0

FIGURE 1 — RMS CURRENT DERATING

5.0

40

35

30

25

20

15

10

2018

FIGURE 2 — ON-STATE POWER DISSIPATION


50 02.0 4.0 6.0 8.0 10 12 14 160 2018


α = 30°

180°

α = ConductionAngle

α

α


α

α

P D(A

V), A

VER

AGE

POW

ER (W

ATT)

T C, M

AXIM

UM

ALL

OW

ABLE

CAS

E TE

MPE

RAT

UR

E ( C

)°

180°dc

90°

60°α = 30°

60°90°




FIGURE 3 — TYPICAL GATE TRIGGER VOLTAGE

1

30

2

3

5

7

10

20

50

70

100

0.1

0.7

0.5

0.3

4

0.2

0.4 0.8 1.2 1.6 2 2.4 2.8 3.63.2 4.4


i

, IN

STAN

TAN

EOU

S FO

RW

ARD

CU

RR

ENT

(AM

P)TM

TJ = 25°C

V

,

GAT

E TR

IGG

ER V

OLT

AGE

(NO

RM

ALIZ

ED)

GTM

–60 120–40 0–20 20 40 60 80 100 140


0.7

0.5

0.3

3

2

1


–60 120–40 0–20 20 40 60 80 100 140

TJ, JUNCTION TEMPERATURE(°C)

0.7

0.5

0.3

3

2

1


I

,

GAT

E TR

IGG

ER C

UR

REN

T (N

OR

MAL

IZED

)G

TM

125°C



FIGURE 6 — TYPICAL HOLDING CURRENT FIGURE 7 — MAXIMUM ON-R EPETITIVE SURGE CURRENT

0.1 5 k2 k1 k500200100502010 10 k


t, TIME (ms)

1

0.2

0.5

5

0.02

0.1

0.01210.50.2

0.05

r(t),

TRAN

SIEN

T TH

ERM

AL R

ESIS

TAN

CE

(NO

RM

ALIZ

ED)

–60 120–40 0–20 20 40 60 80 100 140


0.7

0.5

0.3

2

1


I ,

HO

LDIN

G C

UR

REN

T (N

OR

MAL

IZED

)H

NUMBER OF CYCLES103 72 51

TC = 80°Cf = 60 Hz


300

200

100

70

50

30

T

, P

EAK

SUR

GE

CU

RR

ENT

(AM

P)SM

3






Dissipation and Durability• Gate Triggering Guaranteed in Three Modes (MAC320FP Series) or






VDRM

200400600800

Volts


On-State RMS Current (TC = +75°C, Full Cycle Sine Wave 50 to 60 Hz)(2) IT(RMS) 20 Amps

Peak Nonrepetitive Surge Current (One Full Cycle, 60 Hz, TC = +75°C,preceded and followed by rated current)

ITSM 150 Amps













2. The case temperature reference point for all TC measurements is a point on the center lead of the package as close as possible to theplastic body.


MT1

G

MT2

CASE 221C-02STYLE 3







TJ = +125°C

IDRM——

——

102

µAmA



Peak Gate Trigger Current(Main Terminal Voltage = 12 Vdc, RL = 100 OhmsMinimum Gate Pulse Width = 2 µs)


IGT

————

————

50505075

mA

Peak Gate Trigger Voltage(Main Terminal Voltage = 12 Vdc, RL = 100 OhmsMinimum Gate Pulse Width = 2 µs)


(Main Terminal Voltage = Rated VDRM, RL = 10 , TJ = +110°C)MT2(+), G(+); MT2(+), G(–)MT2(–), G(–); MT2(–), G(+) “A” SUFFIX ONLY

VGT

————

0.20.2

0.90.91.11.4

——

222

2.5

——

Volts


IH — 6 40 mA


tgt — 1.5 10 µs

Critical Rate of Rise of Commutation Voltage(VD = Rated VDRM, ITM = 28 A, Commutating di/dt = 10 A/ms,Gate Unenergized, TC = +75°C)


110

120

130

2.0 4.0 6.0 8.0 10 12

60

70

80

90

100

14 16

dc

0


5.0

40

35

30

25

20

15

10

2018

Figure 10. On-State PowerDissi pation


50 02.0 4.0 6.0 8.0 10 12 14 160 2018


α = 30°60°

90°

180°


α

α


α

α

P D(A

V), A

VER

AGE

POW

ER (W

ATT)

T C, M

AXIM

UM

ALL

OW

ABLE

CAS

E TE

MPE

RAT

UR

E ( C

)°

180°dc

90°

60°α = 30°




V

,

GAT

E TR

IGG

ER V

OLT

AGE

(NO

RM

ALIZ

ED)

GTM

–60 120–40 0–20 20 40 60 80 100 140


0.7

0.5

0.3

3

2

1



–60 120–40 0–20 20 40 60 80 100 140


0.7

0.5

0.3

3

2

1


I

,

GAT

E TR

IGG

ER C

UR

REN

T (N

OR

MAL

IZED

)G

TM

Figure 13. Maximum On-StateCharacteristics

1

30

2

3

5

7

10

20

50

70

100

0.1

0.7

0.5

0.3

4

0.2

0.4 0.8 1.2 1.6 2 2.4 2.8 3.63.2 4.4


i

, IN

STAN

TAN

EOU

S FO

RW

ARD

CU

RR

ENT

(AM

P)TM

TJ = 25°C

125°C


Figure 14. Typical HoldingCurrent

0.1 5 k2 k1 k500200100502010 10 k

t, TIME (ms)

1

0.2

0.5

5

0.02

0.1

0.01210.50.2

0.05

r(t),

TRAN

SIEN

T TH

ERM

AL R

ESIS

TAN

CE

(NO

RM

ALIZ

ED)



–60 120–40 0–20 20 40 60 80 100 140


0.7

0.5

0.3

2

1


I ,

HO

LDIN

G C

UR

REN

T (N

OR

MAL

IZED

)H

NUMBER OF CYCLES

103 72 51

300

200

100

70

50

30

T

, P

EAK

SUR

GE

CU

RR

ENT

(AM

P)SM

3





. . . designed for full-wave ac control applications primarily in industrial environmentsneeding noise immunity.

• Guaranteed High Commutation Voltagedv/dt — 500 V/µs Min @ TC = 25°C

• High Blocking Voltage — VDRM to 800 V• Photo Glass Passivated Junction for Improved Power Cycling Capability and

Reliability



Peak Repetitive Off-State Voltage(1) (TJ = –40 to +125°C,1/2 Sine Wave 50 to 60 Hz, Open Gate)

MAC321-4MAC321-6MAC321-8MAC321-10

VDRM

200400600800

Volts


On-State Current RMS (TC = +75°CFull Cycle Sine Wave 50 to 60 Hz)

IT(RMS) 20 Amp

Peak Surge Current (One Full Cycle, 60 Hz, TC = +75°Cpreceded and followed by Rated Current)

ITSM 150 Amp


Peak Gate Power (TC = +75°C, Pulse Width = 2.0 µs) PGM 20 Watts


Peak Gate Current IGM 2.0 Amp









STYLE 4


MT1

G

MT2




Peak Blocking Current(VD = Rated VDRM, Gate Open)

TJ = 25°CTJ = +125°C

IDRM

——

——

102.0

µAmA

Peak On-State Voltage (Either Direction)(ITM = 28 A Peak; Pulse Width 2.0 ms, Duty Cycle 2.0%)



MT2(+), G(+)MT2(+), G(–)MT2(–), G(–)

IGT

———

———

100100100

mA


MT2(+), G(+)MT2(+), G(–)MT2(–), G(–)

(Main Terminal Voltage = Rated VDRM, RL = 10 kΩ, TJ = +125°C)MT2(+), G(+); MT2(–), G(–); MT2(+), G(–)

VGT

———

0.2

———

—

2.02.02.0

—

Volts


IH — — 100 mA

Turn-On Time(VD = Rated VDRM, ITM = 28 A, IGT = 120 mA,Rise Time = 0.1 µs, Pulse Width = 2.0 µs)

tgt — 1.5 — µs

Critical Rate of Rise of Off-State Voltage(VD = Rated VDRM, Exponential Voltage Rise, Gate Open)

TJ = 25°CTJ = +125°C

dv/dt(s)

500200

——

——

V/µs

110

120

130

2 4 6 8 10 12

60

70

80

90

100

14 16

dc

0

Figure 17. RMS CurrentDerating

5

40

35

30

25

20

15

10

2018

Figure 18. On-State PowerDissipation


50 02 4 6 8 10 12 14 160 2018


α = 30°60°

90°

180°


α

α


α

α

P D(A

V), A

VER

AGE

POW

ER (W

ATT)

T C, M

AXIM

UM

ALL

OW

ABLE

CAS

E TE

MPE

RAT

UR

E ( C

)°

180°dc

90°

60°α = 30°




Figure 20. Typical Gate Trigger Current Figure 21. Maximum On–State Characteristics

1

30

2

3

5

7

10

20

50

70

100

0.1

0.7

0.5

0.3

4

0.2

0.4 0.8 1.2 1.6 2 2.4 2.8 3.63.2 4.4


i

, IN

STAN

TAN

EOU

S FO

RW

ARD

CU

RR

ENT

(AM

P)TM

TJ = 25°C

V

,

GAT

E TR

IGG

ER V

OLT

AGE

(NO

RM

ALIZ

ED)

GTM

–60 120–40 0–20 20 40 60 80 100 140


0.7

0.5

0.3

3

2

1


–60 120–40 0–20 20 40 60 80 100 140

TJ, JUNCTION TEMPERATURE(°C)

0.7

0.5

0.3

3

2

1


I

,

GAT

E TR

IGG

ER C

UR

REN

T (N

OR

MAL

IZED

)G

TM

125°C

Figure 22. Typical HoldingCurrent

Figure 23. Maximum On-Repetitive SurgeCurrent

–60 120–40 0–20 20 40 60 80 100 140


0.7

0.5

0.3

2

1


I ,

HO

LDIN

G C

UR

REN

T (N

OR

MAL

IZED

)H

NUMBER OF CYCLES103 72 51


300

200

100

70

50

30

T

, P

EAK

SUR

GE

CU

RR

ENT

(AM

P)SM

3


Figure 24. ThermalResponse

0.1 5 k2 k1 k500200100502010 10 k

t, TIME (ms)

1

0.2

0.5

5

0.02

0.1

0.01210.50.2

0.05

r(t),

TRAN

SIEN

T TH

ERM

AL R

ESIS

TAN

CE

(NO

RM

ALIZ

ED)



Diode Thyristors

. . . designed for full-wave triggering in Triac phase control circuits, half-wave SCRtriggering application and as voltage level detectors. Supplied in an inexpensiveplastic TO-226AA package for high-volume requirements, this low-cost plasticpackage is readily adaptable for use in automatic insertion equipment.

• Low Switching Voltage — 8 Volts Typical• Uniform Characteristics in Each Direction• Low On-State Voltage — 1.7 Volts Maximum• Low Off-State Current — 0.1 µA Maximum• Low Temperature Coefficient — 0.02 %/°C Typical



Power Dissipation PD 500 mW

DC Forward Current IF 200 mA

DC Gate Current (Off-State Only) IG(off) 5 mA

Repetitive Peak Forward Current(1% Duty Cycle, 10 µs Pulse Width, TA = 100°C)

IFM(rep) 2 Amps

Non-repetitive Forward Current(10 µs Pulse Width, TA = 25°C)

IFM(nonrep) 6 Amps





SBS(PLASTIC)

MT2

G

MT1

MT1G

MT2

REV 2


ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted.)


Switching Voltage MBS4991MBS4992, MBS4993

VS 67.5

88

109

Vdc

Switching Current MBS4991MBS4992MBS4993

IS ——

17590175

500120250

µAdc

Switching Voltage Differential (See Figure 10) MBS4991MBS4992, MBS4993

VS1–VS2 ——

0.30.1

0.50.2

Vdc

Gate Trigger Current MBS4992(VF = 5 Vdc, RL = 1 k ohm) MBS4993

IGF ——

——

100500

µAdc

Holding Current MBS4991MBS4992MBS4993

IH ———

0.70.20.3

1.50.50.75

mAdc

Off-State Blocking Current(VF = 5 Vdc, TA = 25°C) MBS4991(VF = 5 Vdc, TA = 85°C) MBS4991(VF = 5 Vdc, TA = 25°C) MBS4992, MBS4993(VF = 5 Vdc, TA = 100°C) MBS4992, MBS4993

IB————

0.082

0.086

1100.110

µAdc

Forward On-State Voltage(IF = 175 mAdc) MBS4991(IF = 200 mAdc) MBS4992, MBS4993

VF——

1.41.5

1.71.7

Vdc

Peak Output Voltage (Cc = 0.1 µF, RL = 20 ohms, (Figure 7) Vo 3.5 4.8 — Vdc

Turn-On Time (Figure 8) ton — 1 — µs

Turn-Off Time (Figure 9) toff — 30 — µs

Temperature Coefficient of Switching Voltage (–50 to +125°C) TC — +0.02 — %/°C

Switching Current Differential (See Figure 10) IS1–IS2 — — 100 µA


00.96

0.98

0.99

1.00

1.01

1.02

1.03

1.04

0.97

+25–50

1.0

2.0

3.0

4.0

5.0

6.0

7.0

–250

8.0

–75 +50 +75 +100 +125

FIGURE 1 – SWITCHING VOLTAGE versus TEMPERATURE

TYPICAL ELECTRICAL CHARACTERISTICS

FIGURE 2 – SWITCHING CURRENT versus TEMPERATURE

V S, S

WIT

CH

ING

VO

LTAG

E (N

OR

MAL

IZED

)

I S, S

WIT

CH

ING

CU

RR

ENT

(NO

RM

ALIZ

ED)

TA, AMBIENT TEMPERATURE (°C)0 +25–50 –25–75 +50 +75 +100 +125


15 V0D.U.T.

Cc

Vin

10 msMIN

10 K

RL

V0

FIGURE 7 – PEAK OUTPUT VOLTAGE TEST CIRCUIT

0.01

VF, FORWARD ON-STATE VOLTAGE (VOLTS)


VF = 5.0 VNormalizedto

25°C


0

FIGURE 6 – PEAK OUTPUT VOLTAGE (FUNCTION OF R L AND Cc)

FIGURE 4 – OFF-STATE BLOCKING CURRENTversus TEMPERATURE

FIGURE 3 – HOLDING CURRENT versus TEMPERATURE

FIGURE 5 – ON-STATE VOLTAGE versus FORWARD CURRENT

7.0

TA = 25°C0

1.0

2.0

3.0

4.0

5.0

6.0

0.01 0.02 0.05 0.1 0.2 0.5 1.0 2.0 5.0

RL = 500 Ω

10

Cc, CHARGING CAPACITANCE (µF)

10

1.0

0.1

0 1.0 2.0 3.0 4.0 5.0

1.0

2.0

3.0

4.0

5.0

6.0

7.0

8.0

–75 –50 –25 0 +25 +50 +75 +100 +125

10.0

1.0

0.1

0.01–50 –25 0 +25 +50 +75 +100 +125

RL = 100 ΩRL = 50 ΩRL = 20 ΩRL = 5 Ω

I H, H

OLD

ING

CU

RR

ENT

(NO

RM

ALIZ

ED)

I F, F

ORW

ARD

ON

-STA

TE C

UR

REN

T (A

MP)

V o, P

EAK

OU

TPU

T VO

LTAG

E (V

OLT

S)I B

, OFF

-STA

TE B

LOC

KIN

G C

UR

REN

T (

A)

µ


EQUIVALENT CIRCUIT

FIGURE 10 – DEVICE EQUIVALENT CIRCUIT, CHARACTERISTICS AND SYMBOLS

MT1

MT2

G

MT1

MT2

CIRCUIT SYMBOL

G

CHARACTERISTICS

–IVF2

VS2 IH2

+V–V

IS1

IH1

IS1

VS1

VF1+I

IS2 IB1

MercuryRelay(N.O.)

–

+

5.0 V MT2

D.U.T.

MT1

C

500 Ω100 Ω

FIGURE 9 – TURN-OFF TIME TEST CIRCUIT

VF + 0.1 (VS–VF)

+

VFton

VS

–

+

12 V

AnodeVoltage

D.U.T.0.01 µF

1.0 kΩ

1.0 kΩ

Mercury Relay

FIGURE 8 – TURN-ON TIME TEST CIRCUIT

CHARACTERISTICS

–IVF2

VS2 IH2

+V–V

IS1

IH1

IS1

VS1

VF1+I

IS2 IB1

With the SBS in conduction and the relay contacts open, close the contacts to cause anode A2 to be driven negative. Decrease C until the SBS justremains off when anode A2 becomes positive. The turn off time, toff, is the time from initial contact closure and until anode A2 voltage reacheszero volts.

Turn-on time is measured from the time VS is achieved to the time when the anode voltage drops to within 90% of the difference between VSand VF.


Silicon Controlled RectifiersReverse Blocking Triode Thyristors

PNPN devices designed for line powered consumer applications such as relay andlamp drivers, small motor controls, gate drivers for larger thyristors, and sensing anddetection circuits. Supplied in surface mount package for use in automatedmanufacturing.

• Sensitive Gate Trigger Current• Blocking Voltage to 600 Volts• Glass Passivated Surface for Reliability and Uniformity• Surface Mount Package• Devices Supplied on 1 K Reel




(1/2 Sine Wave, RGK = 1000 Ω, TJ = 25 to 110°C)MCR08BT1MCR08DT1MCR08MT1

VDRM, VRRM

200400600

Volts

On-State Current RMS (TC = 80°C) IT(RMS) 0.8 Amps

Peak Non-repetitive Surge Current ITSM 10 Ampsg(One Full Cycle, 60 Hz, TC = 25°C)

TSM


Peak Gate Power, Forward, TA = 25°C PGM 0.1 Watts

Average Gate Power (TC = 80°C, t = 8.3 ms) PG(AV) 0.01 Watts



Maximum Device Temperature for Soldering Purposes (for 10 Seconds Maximum) TL 260 °C



Thermal Resistance, Junction to AmbientPCB Mounted per Figure 1

RθJA 156 °C/W

Thermal Resistance, Junction to TabMeasured on Anode Tab Adjacent to Epoxy

RθJT 25 °C/W

1. VDRM and VRRM for all types can be applied on a continuous basis. Ratings apply for zero or negative gate voltage; however, positive gatevoltage shall not be applied concurrent with negative potential on the anode. Blocking voltages shall not be tested with a constant source suchthat the voltage ratings of the devices are exceeded.



SCR0.8 AMPERE RMS200 thru 600 Volts

CASE 318E-04(SOT-223)STYLE 10


REV 1


ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted, RGK = 1 KΩ)


Peak Repetitive Forward or Reverse Blocking Current(VAK = Rated VDRM or VRRM, RGK = 1000 Ω) TJ = 25°C

TJ = 110°C

IDRM, IRRM——

——

10200

µAµA

Maximum On-State Voltage (Either Direction)* VTM — — 1.7 Voltsg ( )(IT = 1.0 A Peak, TA = 25°C)

TM

Gate Trigger Current (Continuous dc) IGT — — 200 µAgg ( )(Anode Voltage = 7.0 Vdc, RL = 100 Ω)

GT µ

Holding Current(VD = 7.0 Vdc,Initializing Current = 20 mA, RGK = 1000 Ω)

IH — — 5.0 mA

Gate Trigger Voltage (Continuous dc) VGT — — 0.8 Voltsgg g ( )(Anode Voltage = 7.0 Vdc, RL = 100 Ω)

GT

Critical Rate-of-Rise of Off State Voltage dv/dt 10 — — V/µsg(Vpk = Rated VDRM, TC = 110°C, RGK = 1000 Ω, Exponential Method)

µ

* Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.

Figure 25. PCB for Thermal Impedance andPower Testing of SOT-223

0.0792.0

0.0792.0

0.0591.5

0.0912.3

0.0912.3

0.47212.0

0.0962.44

BOARD MOUNTED VERTICALLY IN CINCH 8840 EDGE CONNECTOR.BOARD THICKNESS = 65 MIL., FOIL THICKNESS = 2.5 MIL.

MATERIAL: G10 FIBERGLASS BASE EPOXY0.98425.0

0.2446.2

0.0591.5

0.0591.5

0.0962.44

0.0962.44

0.0591.5

0.0591.5

0.153.8

inchesmm


PAD AREA = 4.0 cm2, 50OR 60 Hz HALFWAVE

°TH

ERM

AL R

ESIS

TAN

CE,

( C

/W)

2.00 4.0 6.0 8.0 10

TYPICALMAXIMUM

4

1 2 3



L

L

180°

110

85

IT(AV), AVERAGE ON-STATE CURRENT (AMPS)

0.50.40.30.20.10

50 OR 60 Hz HALFWAVE

T A, M

AXIM

UM

ALL

OW

ABLE

AMBI

ENT

TEM

PER

ATU

RE

( C

)°

110

100

90

80

60

50

70


110

100

90

80

60

50

40

30

20

70

Figure 26. On-State Characteristics Figure 27. Junction to Ambient ThermalResistance versus Copper Tab Area

Figure 28. Current Derating, Minimum PadSize

Reference: Ambient Temperature

Figure 29. Current Derating, 1.0 cm SquarePad


FOIL AREA (cm2)vT, INSTANTANEOUS ON-STATE VOLTAGE (VOLTS)

I T, I

NST

ANTA

NEO

US

ON

-STA

TE C

UR

REN

T (A

MPS

)


Figure 30. Current Derating, 2.0 cm SquarePad


10

1.0

0.1

0.014.01.0

110

0.50.30.20.10


0.50.40.30.20.10

0.50.40.30.20.10

0

100

90

80

60

50

40

30

200.4

70T A

, MAX

IMU

M A

LLO

WAB

LEAM

BIEN

T TE

MPE

RAT

UR

E (

C)

°dc

T (ta

b), M

AXIM

UM

ALL

OW

ABLE

TAB

TEM

PER

ATU

RE

( C

)°

Figure 31. Current DeratingReference: Anode Tab

180°

α = 30°

60°90°

60°

120°

60°

dc

180°

120°

1.0 cm2 FOIL, 50 OR60 Hz HALFWAVE

dc

2.0 3.0

TYPICAL AT TJ = 110°CMAX AT TJ = 110°CMAX AT TJ = 25°C

160

140

120

100

60

40

80

120°

90°

60°

90°

1.0 3.0 5.0 7.0 9.0

150

130

110

90

70

50

30

αα = CONDUCTION

ANGLE

50 OR 60 Hz HALFWAVE

αα = CONDUCTION

ANGLE

90°

α = 30°

αα = CONDUCTION

ANGLE

180°

120°

αα = CONDUCTION

ANGLE

α = 30°

dc

α = 30°

θJA

R, J

UN

CTI

ON

TO

AM

BIEN

T

T A, M

AXIM

UM

ALL

OW

ABLE

AMBI

ENT

TEM

PER

ATU

RE

( C

)°


r T, T

RAN

SIEN

T TH

ERM

AL R

ESIS

TAN

CE

NO

RM

ALIZ

ED

8020–40 –20 0 40 60 110

8020–40 –20 0 40 60 110

1000

100

1.0

0.7

1000100.1

IGT, GATE TRIGGER CURRENT (µA)

1.0 100


IVG

T, G

ATE

TRIG

GER

VO

LTAG

E (V

OLT

S)

0.65

0.6

0.55

0.5

0.45

0.4

0.35

0.3

VAK = 7.0 VRL = 140 ΩTJ = 25°C

10

2.0

1.0

0

TJ, JUNCTION TEMPERATURE, (°C)

V GT

, GAT

E TR

IGG

ER V

OLT

AGE

(VO

LTS)

TJ, JUNCTION TEMPERATURE, (°C)

I H, H

OLD

ING

CU

RR

ENT

(NO

RM

ALIZ

ED)

0.7

0.6

0.5

0.4

8020–40 –20 0 40 60 1100.3

1.0

0.1

0.011000.10.0001

MAX

IMU

M A

VER

AGE

POW

ERP


1.0

0.50.30.20.10

0.9

0.8

0.7

0.5

0.4

0.3

0.2

0.1

0.4

0.6

Figure 32. Power Dissipation Figure 33. Thermal Response DeviceMounted on Figure 1 Printed Circuit Board

t, TIME (SECONDS)

dc180°

α = 30°

60°(A

V),D

ISSI

PATI

ON

(WAT

TS)

00.001 0.01 1.0 10

GT

, GAT

E TR

IGG

ER C

UR

REN

T (µ RGK = 1000 Ω, RESISTOR

CURRENT INCLUDED

WITHOUT GATE RESISTOR

VAK = 7.0 VRL = 140 Ω

αα = CONDUCTION

ANGLE

VAK = 7.0 VRL = 3.0 kRGK = 1.0 k

90°

120°

Figure 34. Typical Gate Trigger Voltage versus Junction Temperature

Figure 35. Typical Normalized Holding Currentversus Junction Temperature

Figure 36. Typical Range of V GT versus Measured I GT

Figure 37. Typical Gate Trigger Current versus Junction Temperature

VAK = 7.0 VRL = 140 ΩRGK = 1.0 kΩ

A)


STAT

IC d

v/dt

(V/

S)

µ

HO

LDIN

G C

UR

REN

T (m

A)I

, H

10000

100

STAT

IC d

v/dt

(V/

S)

µ

10,00010 100 10001.0

10000

1000

100

10

1.0

0.110 100 1000 10,000 100,000

CGK, GATE-CATHODE CAPACITANCE (nF)

0.1 1.0 10 100

RGK, GATE-CATHODE RESISTANCE (OHMS)

100

1.0

0.110001.0


10 100 10,000 100,000

10

Figure 38. Holding Current Range versus Gate-Cathode Resistance

Figure 39. Exponential Static dv/dt versus JunctionTemperature and Gate-Cathode Termination Resistance


0.01

IGT = 48 µA

TJ = 25°C

IGT = 7 µA

STAT

IC d

v/dt

(V/

S)

µ

50°

75°

125°

500 V

100 V

STAT

IC d

v/dt

(V/

S)

µ

GATE-CATHODE RESISTANCE (OHMS)

100 1000 10,000 100,00010

5000

500

50

5.0

0.5

1000

500 400 V

TJ = 110°C

50 V

50

10

5.0

10000

100

1.0

1000

500

50

10

5.0

TJ = 110°C400 V (PEAK)

RGK = 10 k

RGK = 100

RGK = 1.0 k

10000

100

1.0

1000

500

50

10

5.0

IGT = 5 µA

IGT = 70 µA

IGT = 35 µA

IGT = 15 µA

110°

TJ = 25°

Vpk = 400 V

200 V

300 V

Figure 40. Exponential Static dv/dt versus Peak Voltage and Gate-Cathode Termination Resistance

Figure 41. Exponential Static dv/dt versusGate-Cathode Capacitance and Resistance

Figure 42. Exponential Static dv/dt versus Gate-Cathode Termination Resistance and

Product Trigger Current Sensitivity


Designed primarily for half–wave ac control applications, such as motorcontrols, heating controls, and power supplies; or wherever half–wave, silicongate–controlled devices are needed.

• Blocking Voltage to 800 Volts• On–State Current Rating of 8 Amperes RMS• High Surge Current Capability — 80 Amperes• Industry Standard TO220 AB Package for Ease of Design• Glass Passivated Junctions for Reliability and Uniformity




Peak Repetitive Reverse Voltage(TJ = –40 to 125°C) MCR8D

MCR8MMCR8N

VDRMVRRM

400600800

Volts

On–State RMS Current(All Conduction Angles)

IT(RMS) 8 A

Peak Non–repetitive Surge Current(One Half Cycle, 60 Hz, TJ = 125°C)

ITSM 80 A

Circuit Fusing Consideration (t = 8.3 ms) I2t 26.5 A2sec

Peak Gate Power (Pulse Width 1.0 µs, TC = 80°C) PGM 5.0 Watts


Peak Gate Current (Pulse Width 1.0 µs, TC = 80°C) IGM 2.0 A





RθJCRθJA

2.062.5

°C/W






STYLE 3

SCRs8 AMPERES RMS

400 thru 800VOLTS


A

KA

G

REV 2




OFF CHARACTERISTICS

Peak Forward Blocking Current TJ = 25°CPeak Reverse Blocking Current TJ = 125°C

(VAK = Rated VDRM or VRRM, Gate Open)

IDRMIRRM

——

——

0.012.0

mA

ON CHARACTERISTICS


Gate Trigger Current (Continuous dc) (VD = 12 V, RL = 100 Ω) IGT 2.0 7.0 15 mA

Gate Trigger Voltage (Continuous dc) (VD = 12 V, RL = 100 Ω) VGT 0.5 0.65 1.0 Volts

Hold Current (Anode Voltage = 12 V) IH 4.0 22 30 mA



dv/dt 50 200 — V/µs


= ConductionAngle

Figure 1. Average Current Derating Figure 2. Maximum On–state PowerDissipation

Figure 3. On–State Characteristics Figure 4. Transient Thermal Response

t, TIME (ms)

0.1

1

0.1

0.011 10 100 1000

IT(AV), AVERAGE ON–STATE CURRENT (AMP)

60

120

110

105

10051 2 3 4

115

125

T

R

7 8


P


3.50.5

10

1

0.131 1.5 2 2.5

100

I 54.54

TRAN

SIEN

T TH

ERM

AL R

(NO

RM

ALIZ

ED)

(t)

, MAX

IMU

M A

LLO

WAB

LE C

ASE

TEM

PER

ATU

RE

( C

)C

°

60

8

4

2

051 2 3 4

6

10

7 8

AVER

AGE

POW

ER (W

ATTS

)(A

V)

1⋅104

, IN

STAN

TAN

EOU

S O

N–S

TATE

CU

RR

ENT

(AM

PS)

T

ZJC(t) = RJC ⋅ R(t)

dc180°

120°90°

60° = 30°

= ConductionAngle

dc180°120°90°60° = 30°

Maximum @ TJ = 125°C


Typical @ TJ = 25°C


Figure 5. Typical Holding Current VersusJunction Temperature

Figure 6. Typical Latching Current VersusJunction Temperature

Figure 7. Typical Gate Trigger Current VersusJunction Temperature

Figure 8. Typical Gate Trigger Voltage VersusJunction Temperature

Figure 9. Typical Exponential Static dv/dt VersusGate Cathode Resistance

Figure 10. Maximum Non–RepetitiveSurge Current

–10


100

10


10

TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

RGK, GATE CATHODE RESISTANCE (OHMS) NUMBER OF CYCLES

I H, H

OLD

ING

CU

RR

ENT

(mA)

I

I V

505 35 65 80

100

STAT

IC d

v/dt

(V/u

S)

–40

4 83

60

50

406

, PEA

K SU

RG

E C

UR

REN

T (A

MP)

I TSM

9 10

70

5 7

20

21

80

10010100

1000 1⋅104

1000

0.60

0.70

0.65

0.50

0.40

0.35

0.45

0.55

0.75

5 65–10

100

135 80 95

10

20 50 110–25–40

–25 95 110 125

, LAT

CH

ING

CU

RR

ENT

(mA)

L

–10 505 35 65 80–40 20–25 95 110 125

0.80

–10 505 35 65 80–40 20–25 95 110 125

, GAT

E TR

IGG

ER V

OLT

AGE

(VO

LTS)

GT

125

, GAT

E TR

IGG

ER C

UR

REN

T (m

A)G

T

Tj = 125°C VPK = 800 V



• Blocking Voltage to 800 Volts• On–State Current Rating of 8 Amperes RMS• High Surge Current Capability — 90 Amperes• Industry Standard TO–220AB Package for Ease of Design• Glass Passivated Junctions for Reliability and Uniformity• Low Trigger Currents, 200µA Maximum for Direct Driving from Integrated Circuits



Peak Repetitive Off–State Voltage (1)Peak Repetitive Reverse Voltage

(TJ = –40 to 110°C; RGK = 1.0 KΩ) MCR8SDMCR8SMMCR8SN

VDRMVRRM

400600800

Volts


IT(RMS) 8 A


ITSM 90 A









RθJCRθJA

2.262.5

°C/W







Style 3

SCRs8 AMPERES RMS

400 thru 800VOLTS


A

KA

G


ELECTRICAL CHARACTERISTICS (TJ = 25°C; RGK = 1.0 KΩ unless otherwise noted)


OFF CHARACTERISTICS


(VAK = Rated VDRM or VRRM, Gate Open) (1)

IDRMIRRM

——

——

10500

µA

ON CHARACTERISTICS

Peak On–State Voltage (ITM = 16 A) (2) VTM — 1.4 1.8 Volts

Gate Trigger Current (Continuous dc) (VD = 12 V, RL = 100 Ω) (3) IGT 5.0 20 200 µA


Hold Current (Anode Voltage = 12 V) IH 0.5 1.0 6.0 mA


Critical Rate of Rise of Off–State Voltage(VD = 67% of Rated VDRM, Exponential Waveform, TJ = 110°C)

(dv/dt) 2.0 10 — V/µs

(1) Devices shall not have a positive gate voltage concurrently with a negative voltage on the anode. Devices should not be tested with a constantcurrent source for forward and reverse blocking capability such that the voltage applied exceeds the rated blocking voltage.

(2) Pulse test: P.W. 2ms, Duty Cycle 2%.

(3) Does not include RGK current.



• Blocking Voltage to 800 Volts• On–State Current Rating of 12 Amperes RMS• High Surge Current Capability — 100 Amperes• Industry Standard TO–220AB Package for Ease of Design• Glass Passivated Junctions for Reliability and Uniformity




(TJ = –40 to 125°C) MCR12DMCR12MMCR12N

VDRMVRRM

400600800

Volts


IT(RMS) 12 A


ITSM 100 A









RθJCRθJA

2.062.5

°C/W







Style 3

SCRs12 AMPERES RMS

400 thru 800VOLTS


A

KA

G




OFF CHARACTERISTICS



IDRMIRRM

——

——

0.012.0

mA

ON CHARACTERISTICS







(dv/dt) 50 200 — V/µs




• Blocking Voltage to 800 Volts• On–State Current Rating of 16 Amperes RMS• High Surge Current Capability — 160 Amperes• Industry Standard TO–220AB Package for Ease of Design• Glass Passivated Junctions for Reliability and Uniformity





VDRMVRRM

400600800

Volts


IT(RMS) 16 A


ITSM 160 A









RθJCRθJA

1.562.5

°C/W






Style 3

SCRs16 AMPERES RMS

400 thru 800VOLTS


A

KA

G

REV 1




OFF CHARACTERISTICS



IDRMIRRM

——

——

0.012.0

mA

ON CHARACTERISTICS







dv/dt 50 200 — V/µs


= ConductionAngle

Figure 1. Average Current Derating Figure 2. Maximum On–State Power Dissipation

Figure 3. On–State Characteristics Figure 4. Transient Thermal Response

t, TIME (ms)

0.1

1

0.1

0.011 10 100 1000


120

120

110

105

100

102 4 6 8

115

125

T

R

14 16


MAX

IMU

M A

VER

AGE

POW

ER P


3.50.5

10

1

0.131 1.5 2 2.5

100

I

TRAN

SIEN

T TH

ERM

AL R

(NO

RM

ALIZ

ED)

(t)

, MAX

IMU

M A

LLO

WAB

LE C

ASE

TEM

PER

ATU

RE

( C

)C

°

120

8

4

20

102 4 6 8

6

10

14 16

DIS

SIPA

TIO

N (W

ATTS

)(A

V)

1⋅104

, IN

STAN

TAN

EOU

S O

N–S

TATE

CU

RR

ENT

(AM

PS)

T

ZJC(t) = RJC(t) ⋅ r(t)

dc

180°120°

90°

60°

= 30°

= ConductionAngle

dc180°120°90°60° = 30°




20

16

1412

18

22

95

90






Figure 9. Typical Exponential Static dv/dt VersusGate Cathode Resistance


–10


100

10


10

TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

RGK, GATE CATHODE RESISTANCE (OHMS) NUMBER OF CYCLES

I H, H

OLD

ING

CU

RR

ENT

(mA)

I

I V

505 35 65 80

100

STAT

IC d

v/dt

(V/u

S)

–40

4 83

110

100

906

, PEA

K SU

RG

E C

UR

REN

T (A

MP)

I TSM

9 10

150

5 7

20

21

160

10010400

1000 1⋅104

1400

0.60

0.70

0.65

0.50

0.40

0.85

0.45

0.55

0.75

5 65–10

100

135 80 95

10

20 50 110–25–40

–25 95 110 125

, LAT

CH

ING

CU

RR

ENT

(mA)

L

–10 505 35 65 80–40 20–25 95 110 125

0.80

–10 505 35 65 80–40 20–25 95 110 125

, GAT

E TR

IGG

ER V

OLT

AGE

(VO

LTS)

GT

125

, GAT

E TR

IGG

ER C

UR

REN

T (m

A)G

T

TJ = 125°C VPK = 800 V 140

130

120

1200

1000

800

600

1 Cycle

TJ = 125°C f = 60 Hz


. . . designed and tested for repetitive peak operation required for CD ignition, fuelignitors, flash circuits, motor controls and low-power switching applications.

• 150 Amperes for 2 µs Safe Area• High dv/dt• Very Low Forward “On” Voltage at High Current• Low-Cost TO-226AA (TO-92)



Peak Repetitive Forward and Reverse Blocking Voltage(RGK = IK, TJ = 25 to 125°C)

MCR22-2MCR22-3MCR22-4MCR22-6MCR22-8

VDRM,VRRM

50100200400600

Volts

On-State Current RMS(All Conduction Angles)

IT(RMS) 1.5 Amps

Peak Non-repetitive Surge Current, TA = 25°C(1/2 Cycle, Sine Wave, 60 Hz)

ITSM 15 Amps


Peak Gate Power, TA = 25°C PGM 0.5 Watt

Average Gate Power, TA = 25°C PG(AV) 0.1 Watt

Peak Forward Gate Current, TA = 25°C(300 µs, 120 PPS)

IFGM 0.2 Amp




Lead Solder Temperature(Lead Length 1/16 from case, 10 s Max)

— +230 °C





K

G

A

KG

A






ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted. RGK = 1000 Ohms.)


Peak Forward or Reverse Blocking Current(VAK = Rated VDRM or VRRM) TC = 25°C

TC = 125°C

IDRM, IRRM——

——

10200

µAµA

Forward “On” Voltage(ITM = 1 A Peak)


Gate Trigger Current (Continuous dc)(1) TC = 25°C(Anode Voltage = 6 Vdc, RL = 100 Ohms) TC = –40°C

IGT ——

30—

200500

µA


VGT

VGD

——0.1

———

0.81.2—

Volts

Holding Current TC = 25°C(Anode Voltage = 12 Vdc) TC = –40°C

IH ——

2—

510

mA

Forward Voltage Application Rate(TC = 125°C)


1. RGK Current Not Included in Measurement.T

, M

AXIM

UM

ALL

OW

ABLE

AAM

BIEN

T TE

MPE

RAT

UR

E (

C)

°

T ,

MAX

IMU

M A

LLO

WAB

LEC

CAS

E TE

MPE

RAT

UR

E (

C)

°

dc

dc


1.8 0 0.2 0.4 0.6 0.8

120

1.00

20

40

60

80

100

140


CURRENT DERATING

FIGURE 2 — MAXIMUM AMBIENT TEMPERATURE

00 0.2 0.4 0.6 0.8 1.0 1.2 1.4 2.0

100

1.6

20

60

140

FIGURE 1 — MAXIMUM CASE TEMPERATURE


α = 180°

α = CONDUCTION ANGLEα = 180°


I ,

INST

ANTA

NEO

US

ON

-STA

TE C

UR

REN

T (A

MP)

T

r(t),

TRAN

SIEN

T TH

ERM

AL R

ESIS

TAN

CE

(NO

RM

ALIZ

ED)

1.5


0 0.5 1.0 2.00.01

0.05

2.5

0.02

0.1

0.03

3.0

0.07

0.2

0.3

0.5

0.7

1.0

2.0

5.0

FIGURE 3 — TYPICAL FORWARD VOLTAGE

25°C

TJ = 125°C

1000

t, TIME (ms)

1000050000.2 200050020010020 50105.02.01.00.5

0.05

0.10.01

0.02

0.07

0.7

0.03

0.1

0.2

0.3

0.5

1.0



P

M

AXIM

UM

AVE

RAG

E PO

WER

DIS

SIPA

TIO

N (W

ATTS

)(A

V)

I ,

HO

LDIN

G C

UR

REN

T (m

A)H

V

, GAT

E TR

IGG

ER V

OLT

AGE

(VO

LTS)

G I

GAT

E TR

IGG

ER C

UR

REN

T (

GT

µ

0.4

0.5

0.6

0.7

0.8

1000.3

–75 –50 0 25 7550 125–25



VAK = 7.0 VRL = 100

80200 1601401201006040



1.0

5.0

2.0

–40

10

–20

VAK = 12 VRL = 100 Ω

1401.0

2.0

3.0

5.0

10

20

30

0–40 –20

50

20 40 60 80 100 120

100

160

TJ JUNCTION TEMPERATURE (°C)


1.8

0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

2.0

0.2 0.6



1.61.20.40

dc

1.4

120°

1.0

90°

0.8

180°

60°30°


A)




• On-State Current Rating of 25 Amperes RMS

• High Surge Current Capability — 300 Amperes

• Industry Standard TO–220AB Package for Ease of Design

• Glass Passivated Junctions for Reliability and Uniformity



Peak Repetitive Off-State Voltage (1)Peak Repetitive Reverse Voltage


VDRMVRRM

400600800

Volts

On-State RMS Current(All Conduction Angles)

IT(RMS) 25 A

Peak Non-repetitive Surge Current(One Half Cycle, 60 Hz, TJ = 125°C)

ITSM 300 A


Peak Gate Power (Pulse Width ≤ 1.0 µs, TC = 80°C) PGM 20.0 Watts


Peak Gate Current (Pulse Width ≤ 1.0 µs, TC = 80°C) IGM 2.0 A





RθJCRθJA

1.562.5

°C/W





CASE 221A–06(TO-220AB)

Style 3

KA

G

SCRs25 AMPERES RMS

400 thru 800VOLTS


A

REV 2




OFF CHARACTERISTICS

Peak Forward Blocking CurrentPeak Reverse Blocking Current

(VAK = Rated VDRM or VRRM, Gate Open) TJ = 25°CTJ = 125°C

IDRMIRRM

——

——

0.012.0

mA

ON CHARACTERISTICS

Peak On-State Voltage* (ITM = 50 A) VTM — — 1.8 Volts

Gate Trigger Current (Continuous dc) (VD = 12 V, RL = 100 Ω) IGT 4.0 10 30 mA


Hold Current (Anode Voltage =12 V) IH 5.0 25 40 mA



dv/dt 50 200 — V/µs


60 ° P (AV

)

0 5 10 15 20 2575

80

85

90

95

100

105

110

115

120

125

Figure 1. Average Current Derating

IT(AV), AVERAGE ON–STATE CURRENT (AMPS)

TC

MAX

IMU

M A

LLO

WAB

LE C

ASE

TEM

PER

ATU

RE

( C

),

= ConductionAngle

dc90° 120° 180°

= 30°

0 5 10 15 20 25

05

10

15

20

25

30

35

Figure 2. Maximum On–State Power Dissipation


dc

90°120°

180°

= 30°

60 °

5

0

°

, AVE

RAG

E PO

WER

DIS

SIPA

TIO

N (W

ATTS

)


H

0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.80.1

1

10

100

Figure 3. On–State Characteristics


Maximum @ TJ= 125°C


Maximum @ TJ= 25°C

I T,

INST

ANTA

NO

US

ON

-STA

TE C

UR

REN

T (A

MPS

)

0.1 1 10 100 10000.01

0.1

1

Figure 4. Transient Thermal Response

1104

R (t)

TRAN

SIEN

T TH

ERM

AL R

(NO

RM

ALIZ

ED)

t, TIME (ms)

ZJC(t) R

JC R(t)

–40 –25 –10 5 20 35 50 65 80 95 110 1251

10

100


I,

HO

LDIN

G C

UR

REN

T (m

A)

TJ, JUNCTION TEMPERATURE (°C)–40 –25 –10 5 20 35 50 65 80 95 110 125

10

100



I L,

LATC

HIN

G C

UR

REN

T (m

A)

–40 –25 –10 5 20 35 50 65 80 95 110 1251

10

100



I GT,

TRIG

GER

CU

RR

ENT

(mA)

–40 –25 –10 5 20 35 50 65 80 95 110 1250.4

0.45

0.5

0.55

0.6

0.65

0.7

0.75

0.8

0.85



V GT,

GAT

E TR

IGG

ER V

OLT

AGE

(VO

LTS)


200 300 400 500 600 700 8000

200

400

600

800

1000

1200

Figure 9. Typical Exponential Static dv/dtVersus Peak Voltage.

Gate–Cathode Open, (dv/dt does not depend on RGK)

VPK , Peak Voltage (Volts)

STAT

IC d

v/dt

(V/u

s)

110°C100°C

85°C

TJ = 125°C

80 85 90 95 100 105 110 115 120 1250

500

1000

1500

2000

2500

Figure 10. Typical Exponential Static dv/dtVersus Junction Temperature.

TJ, Junction Temperature (°C )

STAT

IC d

v/dt

(V/u

s)

Gate Cathode Open,(dv/dt does not depend on RGK )

VPK = 800

VPK = 600VPK = 400

VPK = 275

1 2 3 4 5 6 7 8 9 10160

180

200

220

240

260

280

300


NUMBER OF CYCLES

I TSM

,SU

RG

E C

UR

REN

T (A

MPS

)

TJ=125° C f=60 Hz

1 CYCLE



. . . designed for industrial and consumer applications such as temperature, light andspeed control; process and remote controls; warning systems; capacitive dischargecircuits and MPU interface.

• Center Gate Geometry for Uniform Current Density• All Diffused and Glass-Passivated Junctions for Parameter Uniformity and

Stability• Small, Rugged Thermowatt Construction for Low Thermal Resistance, High Heat

Dissipation and Durability• Low Trigger Currents, 200 µA Maximum for Direct Driving from Integrated Circuits




(TJ = –40 to 110°C,1/2 Sine Wave, RGK = 1kΩ)

MCR72-2MCR72-3MCR72-4MCR72-6MCR72-8MCR72-10

VDRMor

VRRM50100200400600800

Volts

On-State RMS Current (TC = 83°C) IT(RMS) 8 Amps

Peak Non-repetitive Surge Current(1/2 Cycle, 60 Hz, TJ = –40 to 110°C)

ITSM 100 Amps


Peak Gate Voltage (t 10 µs) VGM ± 5 Volts

Peak Gate Current (t 10 µs) IGM 1 Amp


Average Gate Power PG(AV) 0.75 Watts


1. VDRM and VRRM for all types can be applied on a continuous basis. Ratings apply for zero or negative gate voltage; (cont.)however, positive gate voltage shall not be applied concurrent with negative potential on the anode. Blocking voltagesshall not be tested with a constant current source such that the voltage ratings of the devices are exceeded.



STYLE 3


CG

A










ELECTRICAL CHARACTERISTICS (TC = 25°C, RGK = 1 kΩ unless otherwise noted.)


Peak Forward or Reverse Blocking Current(1)

(VAK = Rated VDRM or VRRM) TJ = 25°CTJ = 110°C

IDRM, IRRM——

——

10500

µAµA

On-State Voltage(ITM = 16 A Peak, Pulse Width 1 ms, Duty Cycle 2%)

VTM — 1.7 2 Volts


(VD = 12 V, RL = 100 Ω)IGT — 30 200 µA

Gate Trigger Voltage (Continuous dc)(VD = 12 V, RL = 100 Ω)(VD = Rated VDRM, RL = 10 kΩ, TJ = 110°C)

VGT—0.1

0.5—

1.5—

Volts

Holding Current(VD = 12 V, ITM = 100 mA)

IH — — 6 mA

Critical Rate-of-Rise of Forward Blocking Voltage(VD = Rated VDRM, TJ = 110°C, Exponential Waveform)


Gate Controlled Turn-On Time(VD = Rated VDRM, ITM = 16 A, IG = 2 mA)

tgt — 1 — µs

1. Ratings apply for negative gate voltage or RGK = 1 kΩ. Devices shall not have a positive gate voltage concurrently with a negative voltageon the anode. Devices should not be tested with a constant current source for forward and reverse blocking capability such that the voltageapplied exceeds the rated blocking voltage.

2. Does not include RGK current.

60°


70

80

90

100


2.0 4.00

110

6.00



0

4.0

P, A

VER

AGE

POW

ER D

ISSI

PATI

ON

(WAT

TS)

AV

α = 30°

90°

dc

8.06.04.02.0

8.0

12

16

TC

, MAX

IMU

M C

ASE

TEM

PER

ATU

RE

(C

)°

8.0

α = 30°60°

90°

180°

dc

α = Conduction Angleα = Conduction Angle

αα 180°


0.3120

0.5

1.0

2.0

–40 –20 0 20 40 60 80 90 100

3.0

140TJ, JUNCTION TEMPERATURE (°C)

0.6

0.1

0.2

0.3

0.4

0.5

40

0.7

–60 –40 –20 0 10020 60 80 120

VD = 12 Vdc


NO

RM

ALIZ

ED G

ATE

CU

RR

ENT

V

, G

ATE

TRIG

GER

VO

LTAG

E (V

OLT

S)G

T

FIGURE 4 — GATE VOLTAGEFIGURE 3 — NORMALIZED GATE CURRENT

VD = 12 Vdc



PNPN devices designed for high volume, line-powered consumer applications suchas relay and lamp drivers, small motor controls, gate drivers for larger thyristors, andsensing and detection circuits. Supplied in an inexpensive plastic TO-226AA packagewhich is readily adaptable for use in automatic insertion equipment.

• Sensitive Gate Trigger Current — 200 µA Maximum• Low Reverse and Forward Blocking Current — 100 µA Maximum, TC = 125°C• Low Holding Current — 5 mA Maximum• Glass-Passivated Surface for Reliability and Uniformity




(TJ = 25 to 125°C, RGK = 1 kΩ MCR100–3MCR100–4MCR100–6MCR100–8

VDRMand

VRRM100200400600

Volts

Forward Current RMS (See Figures 1 & 2)(All Conduction Angles)

IT(RMS) 0.8 Amps


ITSM 10 Amps


I2t 0.415 A2s

Peak Gate Power — Forward, TA = 25°C PGM 0.1 Watts

Average Gate Power — Forward, TA = 25°C PGF(AV) 0.01 Watt

Peak Gate Current — Forward, TA = 25°C(300 µs, 120 PPS)

IGFM 1 Amp




Lead Solder Temperature(< 1/16 from case, 10 s max)

— +230 °C





SCRs0.8 AMPERE RMS

100 thru 600 VOLTS

K

G

A

KG

A







ELECTRICAL CHARACTERISTICS (TC = 25°C, RGK = 1 kΩ unless otherwise noted.)



TC = 125°C

IDRM, IRRM——

10100

µAµA

Forward “On” Voltage(1)



IGT — 200 µA


VGT ——0.1

0.81.2—

Volts


IH ——

510

mA


110

40

50

60

70

80

90

100

0 0.1 0.2 0.3 0.4

120

0.5


α

dc

FIGURE 1 – MCR100-7, MCR100-8 CURRENT DERATING(REFERENCE: CASE TEMPERATURE)

100

20

40

60

80

120

FIGURE 2 – MCR100-7, MCR100-8 CURRENT DERATING(REFERENCE: AMBIENT TEMPERATURE)

dc

α

0 0.1 0.2 0.3 0.4


T C, M

AXIM

UM

ALL

OW

ABLE

CAS

E TE

MPE

RAT

UR

E (

C)

°

T A, M

AXIM

UM

ALL

OW

ABLE

AM

BIEN

T°

TEM

PER

ATU

RE

(C

)

α = 30°

α = 30° 60° 90°

90°

120°

120° 180°

CASE MEASUREMENTPOINT — CENTER OFFLAT PORTION

60°

180°


α = CONDUCTION ANGLEα = CONDUCTION ANGLE



Annular PNPN devices designed for low cost, high volume consumer applicationssuch as relay and lamp drivers, small motor controls, gate drivers for larger thyristors,and sensing and detection circuits. Supplied in an inexpensive plastic TO-226AApackage which is readily adaptable for use in automatic insertion equipment.

• Sensitive Gate Trigger Current — 200 µA Maximum• Low Reverse and Forward Blocking Current — 100 µA Maximum, TC = 85°C• Low Holding Current — 5 mA Maximum• Passivated Surface for Reliability and Uniformity




(TC = + 85°C, RGK = 1 kΩ) MCR102MCR103

VDRMVRRM 30

60

Volts

Forward Current RMS (See Figures 1 & 2)(All Conduction Angles)

IT(RMS) 0.8 Amps


ITSM 10 Amps


I2t 0.415 A2s


Average Gate Power — Forward, TA = 25°C PGF(AV) 0.01 Watt

Peak Gate Current — Forward, TA = 25°C(300 µs, 120 PPS)

IGFM 1 Amp




Lead Solder Temperature( 1/16″ from case, 10 s max)

— +230 °C

1. Temperature reference point for all case temperature is center of flat portion of package. (TC = +85°C unless otherwise noted.)2. VDRM and VRRM for all types can be applied on a continuous dc basis without incurring damage. Ratings apply for zero or negative gate

voltage but positive gate voltage shall not be applied concurrently with a negative potential on the anode. When checking forward or reverseblocking capability, thyristor devices should not be tested with a constant current source in a manner that the voltage applied exceeds therated blocking voltage.



SCRs0.8 AMPERES RMS30 and 60 VOLTS

K

G

A

KG

A






ELECTRICAL CHARACTERISTICS (TC = 25°C, RGK = 1000 Ω unless otherwise specified.)



TC = 85°C

IDRM, IRRM——

10100

µAµA




IGT — 200 µA

Gate Trigger Voltage (Continuous dc) TC = 25°C(Anode Voltage = 7 Vdc, RL = 100 Ohms) TC = –65°C

TC = 85°C

VGTVGD

——0.1

0.81.2—

Volts


IH ——

510

mA


10

30

50

70

0 0.1 0.2 0.3 0.4

90

0.5

IF(AV), AVERAGE FORWARD CURRENT (AMP)


70

10

30

50

90


dc

0 0.1 0.2 0.3 0.4

IF(AV), AVERAGE FORWARD CURRENT (AMP)

T C, M

AXIM

UM

ALL

OW

ABLE

CAS

E TE

MPE

RAT

UR

E (

C)

°

T A, M

AXIM

UM

ALL

OW

ABLE

AM

BIEN

T°

TEM

PER

ATU

RE

(C

)

α = 30° α = 30°60°90°

90°

120°

120°

60°180°



180°


CASE MEASUREMENTPOINT — CENTER OFFLAT PORTION

dc

α

α



PNPN devices designed for high volume consumer applications such astemperature, light and speed control; process and remote control, and warningsystems where reliability of operation is important.

• Glass-Passivated Surface for Reliability and Uniformity• Power Rated at Economical Prices• Practical Level Triggering and Holding Characteristics• Flat, Rugged, Thermopad Construction for Low Thermal Resistance, High Heat





(TJ = 110°C, RGK = 1 kΩ)MCR106-2MCR106-3MCR106-4MCR106-6MCR106-8

VDRMand

VRRM 60100200400600

Volts

RMS Forward Current(All Conduction Angles)

IT(RMS) 4 Amps

Average Forward CurrentTC = 93°C orTA = 30°C

IT(AV) 2.55 Amps

Peak Non-repetitive Surge Current(1/2 Cycle, 60 Hz, TJ = –40 to +110°C)

ITSM 25 Amps


I2t 2.6 A2s






1. VDRM and VRRM for all types can be applied on a continuous basis. Ratings apply for zero or negative gate voltage; (cont.)however, positive gate voltage shall not be applied concurrent with negative potential on the anode. Blocking voltagesshall not be tested with a constant current source such that the voltage ratings of the devices are exceeded.




STYLE 2


GA

K

A

*Motorola preferred devicesexcept MCR106–3

K

G

A










ELECTRICAL CHARACTERISTICS (TC = 25°C and RGK = 1000 Ohms unless otherwise noted.)


Peak Forward or Reverse Blocking Current(VAK = Rated VDRM or VRRM) TJ = 25°C

TJ = 110°C

IDRM, IRRM——

——

10200

µAµA


VTM — — 2 Volts


(VAK = 7 Vdc, RL = 100 Ohms)(VAK = 7 Vdc, RL = 100 Ohms, TC = –40°C)

IGT——

——

200500

µA

Gate Trigger Voltage (Continuous dc)(VAK = 7 Vdc, RL = 100 Ohms, TC = 25°C)

VGT — — 1 Volts

Gate Non-Trigger Voltage(VAK = Rated VDRM, RL = 100 Ohms, TJ = 110°C)


Holding Current(VAK = 7 Vdc, TC = 25°C)

IH — — 5 mA

Forward Voltage Application Rate(TJ = 110°C)


1. Torque rating applies with use of compression washer (B52200-F006 or equivalent). Mounting torque in excess of 6 in. lb. does notappreciably lower case-to-sink thermal resistance. Anode lead and heatsink contact pad are common. (See AN209B).For soldering purposes (either terminal connection or device mounting), soldering temperatures shall not exceed +200°C. For optimumresults, an activated flux (oxide removing) is recommended.

2. RGK current is not included in measurement.


f = 60 Hz

3.60 0.4 0.8 1.2 1.6 2.0 2.4 2.8

106

3.282

86

90

98

102

94

120°α = 30°

110

4.0

180°


60°

α0

0.8

α π0

f = 60 Hz

60° 90° 180° dc

90°

90

0 0.1 0.2 0.3 0.4 0.60.530

50

70

110

0.7IT(AV), AVERAGE FORWARD CURRENT (AMP)

dc

π

α = 30°

T ,

MAX

IMU

M A

LLO

WAB

LE C

ASE

TEM

PER

ATU

RE

( C

)C

°

T ,

MAX

IMU

M A

LLO

WAB

LE A

MBI

ENT

ATE

MPE

RAT

UR

E (

C)

°

FIGURE 1 – MAXIMUM CASE TEMPERATURE FIGURE 2 – MAXIMUM AMBIENT TEMPERATURE

CURRENT DERATING


Silicon-Controlled Rectifiers

. . . designed primarily for half-wave ac control applications, such as motor controls,heating controls and power supplies; or wherever half-wave silicon gate-controlled,solid-state devices are needed.

• Glass-Passivated Junctions• Blocking Voltage to 800 Volts• TO-220 Construction — Low Thermal Resistance, High Heat Dissipation and

Durability



Peak Repetitive Forward and Reverse Voltage(1)

(TJ = 25 to 125°C, Gate Open) MCR218–2MCR218–3MCR218–4MCR218–6MCR218–8MCR218–10

VDRMVRRM 50

100200400600800

Volts

Forward Current RMS(All Conduction Angles)

IT(RMS) 8 Amps

Peak Forward Surge Current(1/2 Cycle, Sine Wave, 60 Hz)

ITSM 80 Amps


I2t 26 A2s









K

G

A


STYLE 3





ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted.)


Peak Forward or Reverse Blocking Current(VAK = Rated VDRM or VRRM, Gate Open) TJ = 25°C

TJ = 125°C

IDRM, IRRM——

——

102

µAmA

Peak On-State Voltage(1)

(ITM = 16 A Peak)VTM — 1.5 1.8 Volts

Gate Trigger Current (Continuous dc)(VD = 12 V, RL = 100 Ohms)

IGT — 10 25 mA

Gate Trigger Voltage (Continuous dc)(VD = 12 V, RL = 100 Ohms)(Rated VDRM, RL = 1000 Ohms, TJ = 125°C)

VGT—0.2

——

1.5—

Volts

Holding Current(Anode Voltage = 24 Vdc, Peak Initiating On-State Current = 0.5 A,0.1 to 10 ms Pulse, Gate Trigger Source = 7 V, 20 Ohms)

IH — 16 30 mA

Critical Rate-of-Rise of Off-State Voltage(VD = Rated VDRM, Exponential Waveform, Gate Open, TJ = 125°C)

dv/dt — 100 — V/µs


IT(AV), AVERAGE ON-STATE FORWARD CURRENT (AMPS)

FIGURE 1 – CURRENT DERATING

T C, M

AXIM

UM

ALL

OW

ABLE

CAS

E TE

MPE

RAT

UR

E (

C)

°

85

95

105

115

125

87654321

dc

075

α = 30° 90° 120° 180°60°



–60 120–40 0–20 20 40 60 80 100 140


0.7

0.5

0.3

, NO

RM

ALIZ

ED G

ATE

TRIG

GER

CU

RR

ENT

(mA)

GT

FIGURE 3 — NORMALIZED GATE TRIGGER CURRENT

1.0

0.4

0.9

3.0

2.0

I

1.5

IT(AV), AVG. ON-STATE CURRENT (AMPS)

P (AV

), AV

ERAG

E O

N-S

TATE

PO

WER

DIS

SIPA

TIO

N

3.0

6.0

9.0

12

15

8.07.06.05.04.03.02.01.0

dc

00

α = 30°

90°120° 180°

60°

α = Conduction Angle

(WAT

TS)

α

α VD = 12 Vdc


4.0

2.0

0.5

0.7

100800.4

1406040 120–20 0–40 20

FIGURE 5 — NORMALIZED HOLDING CURRENT


–60

, NO

RM

ALIZ

ED H

OLD

ING

CU

RR

ENT

(mA)

H

0.91.0

1.5

3.0

I

–60 120–40 0–20 20 40 60 80 100 140


0.7

0.5

0.3

, NO

RM

ALIZ

ED G

ATE

TRIG

GER

VO

LTAG

EG

T

FIGURE 4 — NORMALIZED GATE TRIGGER VOLTAGE

1.0

0.4

0.9

1.3

1.2

V

VD = 12 Vdc VD = 12 Vdc


Reverse Blocking Thyristors


• Glass Passivated Junctions with Center Gate Fire for Greater Parameter Uniformityand Stability


• Blocking Voltage to 800 Volts• 80 A Surge Current Capability• Insulated Package Simplifies Mounting




(TJ = –40 to +125°C, Gate Open)MCR218-2FPMCR218-4FPMCR218-6FPMCR218-8FPMCR218-10FP

VDRMVRRM

50200400600800

Volts


Peak Nonrepetitive Surge Current (One Full Cycle, 60 Hz, TC = +70°C)Preceded and followed by rated current

ITSM 80 Amps









2. The case temperature reference point for all TC measurements is a point on the center lead of the package as close as possible to the plastic body.


CASE 221C-02STYLE 2

ISOLATED SCRs8 AMPERES RMS

50 thru 800VOLTS

K

G

A









Peak Forward Blocking Current(VD = Rated VDRM, Gate Open) TJ = 25°C

TJ = 125°C

IDRM——

——

102

µAmA

Peak Reverse Blocking Current(VR = Rated VRRM, TJ = 125°C)

IRRM — — 2 mA


(ITM = 16 A Peak)VTM — 1 1.8 Volts

Gate Trigger Current (Continuous dc)(Anode Voltage = 12 Vdc, RL = 100 Ohms)

IGT — 10 25 mA

Gate Trigger Voltage (Continuous dc)(Anode Voltage = 12 Vdc, RL = 100 Ohms)

VGT — — 1.5 Volts



Holding Current(Anode Voltage = 12 Vdc)

IH — 16 30 mA

Turn-On Time(ITM = 8 A, IGT = 40 mAdc)

tgt — 1.5 — µs

Turn-Off Time (VD = Rated VDRM,ITM = 8 A, IR = 8 A) TJ = 25°C

TJ = 125°C

tq——

1535

——

µs

Critical Rate-of-Rise of Off-State Voltage(Gate Open, VD = Rated VDRM, Exponential Waveform)

dv/dt — 100 — V/µs


87654321

12

9

6

3

IT(AV), AVG. ON-STATE CURRENT (AMPS)

00

60° 90°

120° 180°dc

75

85

95

105

115

876543210

125


90°60° 120°

dc

α



Figure 1. Current Derating Figure 2. On-State Power Dissipation

15

α

P

, A

VER

AGE

ON

-STA

TE P

OW

ER D

ISSI

PATI

ON

(AV)

(WAT

TS)

T ,

MAX

IMU

M A

LLO

WAB

LE C

ASE

TEM

PER

ATU

RE

( C

)C

°

α = 30°


180°

α = 30°


IT

1

0.02

0.03

0.050.070.1

100

0.2

0.3

0.50.7

0.2 0.3 0.5 1 2

1.2

0.1


1 CYCLE

1


TC = 85°Cf = 60 Hz

NUMBER OF CYCLES

65

70

75

80

20

2 3 4 6 8 10

–I

+V

+I

–VIDRM

VDRMIRRM

VTIH





0.10.4

0.01

t, TIME (ms)3 5

55

0.2

0.3

0.5

0.7

7

5

1

2

10

50

3

20

30

70

v F, INSTANTANEOUS ON-STATE VOLTAGE (VOLTS)

2.8 4.43.6 5.2 62

30 50 100 200 300 500 2.0 k10 3.0 k 5.0 k1.0 k

I

,

PEAK

SU

RG

E C

UR

REN

T (A

MP)

TSM

r (t),

TRAN

SIEN

T TH

ERM

AL R

ESIS

TAN

CE

(NO

RM

ALIZ

ED)

Fi ,

INST

ANTA

NEO

US

ON

-STA

TE F

OR

WAR

D C

UR

REN

T (A

MP)

Figure 3. Maximum On-State Characteristics

Figure 4. Maximum Non-Repetitive Surge Current

Figure 5. Characteristics and Symbols


TJ = 25°C

125°C


2

–60

Figure 7. Gate Trigger Current versus Temperature


VD = 12 V

–60

Figure 8. Gate Trigger Voltage versus Temperature

VD = 12 V

Figure 9. Holding Current versus Temperature

–60

VD = 12 V

14012040 10080600 20–20

2

0.4

0.8

1.2

1.6

0–40 14012040 10080600 20–20

2

0.4

0.4

0

1.6

1.2

0.8

1.2

1.6

–40

140120400

0.8

1008060–40 0 20–20


I

, GAT

E TR

IGG

ER C

UR

REN

T (N

OR

MAL

IZED

)G

T

V

, G

ATE

TRIG

GER

VO

LTAG

E (N

OR

MAL

IZED

)G

T

I ,

HO

LDIN

G C

UR

REN

T (N

OR

MAL

IZED

)H


Reverse Blocking Thyristors




• Blocking Voltage to 800 Volts• 300 A Surge Current Capability• Insulated Package Simplifies Mounting




(TJ = –40 to +125°C, Gate Open)MCR225-2FPMCR225-4FPMCR225-6FPMCR225-8FPMCR225-10FP

VDRMVRRM

50200400600800

Volts


Peak Non-repetitive Surge Current (One Full Cycle, 60 Hz, TC = +70°C)Preceded and followed by rated current

ITSM 300 Amps











CASE 221C-02STYLE 2

ISOLATED SCRs25 AMPERES RMS50 thru 800 VOLTS

K

G

A









Peak Forward Blocking Current(VD = Rated VDRM, Gate Open) TJ = 25°C

TJ = 125°C

IDRM——

——

102

µAmA

Peak Reverse Blocking Current(VR = Rated VRRM) TJ = 125°C

IRRM — — 2 mA


(ITM = 50 A)VTM — — 1.8 Volts

Gate Trigger Current (Continuous dc)(Anode Voltage = 12 Vdc, RL = 100 Ohms)

IGT — — 40 mA


VGT — 0.8 1.5 Volts




IH — 20 40 mA


tgt — 1.5 — µs

Turn-Off Time (VDRM = Rated Voltage)(ITM = 25 A, IR = 25 A)(ITM = 25 A, IR = 25 A, TJ = 125°C)

tq——

1535

——

µs


dv/dt — 100 — V/µs


20

32

24

16

8

4 8201612 16128480

90

100

110

120

130

dc

TJ = 125°C

0

60° 90°

α = 30°

180°

0



ααα = CONDUCTION ANGLE


dc90°60°α = 30°

0

P

, A

VER

AGE

POW

ER (W

ATTS

)(A

V)

T ,

MAX

IMU

M C

ASE

TEM

PER

ATU

RE

( C

)C

°

180°


Figure 10. Average Current Derating Figure 11. Maximum On–State Power Dissipation


IT

1

0.02

0.03

0.050.070.1

100

0.2

0.3

0.50.7

0.2 0.3 0.5 1 2

25°C

125°C

0.4

0.1


1 CYCLE

1


TC = 85°Cf = 60 Hz

NUMBER OF CYCLES

225

250

275

300

20

2 3 4 6 8 10

–I

+V

+I

–VIDRM

VDRMIRRM

VTIH





0.10

0.01

t, TIME (ms)3 5

175

0.2

0.3

0.5

0.7

7

5

1

2

10

50

3

20

30

70

vF, INSTANTANEOUS VOLTAGE (VOLTS)1.2 21.6 2.4 2.80.8

30 50 100 200 300 500 2.0 k10 3.0 k 5.0 k 10 k1.0 k

I

,

PEAK

SU

RG

E C

UR

REN

T (A

MP)

TSM

r(t),

TRAN

SIEN

T TH

ERM

AL R

ESIS

TAN

CE

(NO

RM

ALIZ

ED)

Fi ,

INST

ANTA

NEO

US

FOR

WAR

D C

UR

REN

T (A

MPS

)

Figure 12. Maximum Forward Voltage

Figure 13. Maximum Non-Repetitive SurgeCurrent

Figure 14. Characteristics and Symbols

Figure 15. ThermalResponse


2

–60


VD = 12 V

–60

VD = 12 V

–60

VD = 12 V

14012040 10080600 20–20

2

0.4

0.8

1.2

1.6

0–40 14012040 10080600 20–20

2

0.4

0.4

0

1.6

1.2

0.8

1.2

1.6

–40

140120400

0.8

1008060–40 0 20–20


I

, GAT

E TR

IGG

ER C

UR

REN

T (N

OR

MAL

IZED

)G

T

V

, G

ATE

TRIG

GER

VO

LTAG

E (N

OR

MAL

IZED

)G

T

I ,

HO

LDIN

G C

UR

REN

T (N

OR

MAL

IZED

)H

Figure 16. Gate Trigger Current versusTemperature

Figure 17. Gate Trigger Voltage versusTemperature

Figure 18. Holding Current versus Temperature



. . . designed for back-to-back SCR output devices for solid state relays or applicationsrequiring high surge operation.

• Photo Glass Passivated Blocking Junctions for High Temperature Stability,Center Gate for Uniform Parameters

• 400 Amperes Surge Capability• Blocking Voltage to 800 Volts




(TJ = 25 to 125°C, Gate Open)MCR264-4MCR264-6MCR264-8MCR264-10

VDRMVRRM

200400600800

Volts

Forward Current (TC = 80°C)(All Conduction Angles)

IT(RMS)IT(AV)

4025

Amps

Peak Non-repetitive Surge Current – 8.3 ms(1/2 Cycle, Sine Wave) 1.5 ms

ITSM 400450

Amps



Forward Peak Gate Current(300 µs, 120 PPS)

IGM 2 Amps



1. VDRM and VRRM for all types can be applied on a continuous basis. Ratings apply for zero or negative gate voltage; however, positive gatevoltage shall not be applied concurrent with negative potential on the anode. Blocking voltages shall not be tested with a constant currentsource such that the voltage ratings of the devices are exceeded.These devices are rated for use in applications subject to high surge conditions. Care must be taken to insure proper heat sinking whenthe device is to be used at high sustained currents.

REV 1



STYLE 3


K

G

A









TJ = 125°C

IDRM, IRRM——

——

102

µAmA


(ITM = 80 A)VTM — 1.4 2 Volts

Gate Trigger Current (Continuous dc)(Anode Voltage = 12 Vdc, RL = 100 Ohms, TC = – 40°C)

IGT ——

1530

5090

mA


VGT — 1 1.5 Volts




IH — 30 60 mA


tgt — 1.5 — µs



1. Pulse Test: Pulse Width 300 µs, Duty Cycle 2%.


75

85

95

105

115

dc

α


90°

60°

5.0

α = 30°

100

125

15 20 25


10

0



180°

0

15

20

25

30

35

40

45

α

5.0

α = CONDUCTIVE ANGLE

20 2510 15

50

5.0

α = 30°

60°90°

180°

dc

P

, A

VER

AGE

POW

ER (W

ATTS

)(A

V)

T ,

MAX

IMU

M C

ASE

TEM

PER

ATU

RE

( C

)C

°



1 k 10 k5 k50020 300 2 k 3 k2005.03.02.01.0 3010 50 1000.50.3

0.02

0.01

0.03

0.050.07

0.2

0.1

10

20

30

50

70

0.7

0.3

0.5

140120100806040

0.2

–40 200–202.01.81.6

0.5

0.6

0.7

0.8

1.0

0.9

1.1

0.2 0.4 0.6 0.8

–20 14012040

1.0 1.2

10080200 60

40

20

5.0

10

1.4

–60

7.0

100804.0

140 –406040 120–20 0–40 20

FIGURE 6 — TYPICAL FORWARD VOLTAGE

0.1

t, TIME (ms)

1.0





7.0–60

01.0

10

100

vF, INSTANTANEOUS VOLTAGE (VOLTS)

TJ = 25°C

0.4


FIGURE 4 — NEW GATE TRIGGER VOLTAGE





–60

I

, G

ATE

TRIG

GER

CU

RR

ENT

(mA)

GT

V

, G

ATE

TRIG

GER

VO

LTAG

E (V

OLT

S)G

T

I ,

HO

LDIN

G C

UR

REN

T (m

A)H

I ,

INST

ANTA

NEO

US

FORW

ARD

CU

RR

ENT

(AM

PS)

F

r(t),

TRAN

SIEN

T TH

ERM

AL R

ESIS

TAN

CE

(NO

RM

ALIZ

ED)



. . . designed for inverse parallel SCR output devices for solid state relays, welders,battery chargers, motor controls or applications requiring high surge operation.

• Photo Glass Passivated Blocking Junctions for High Temperature Stability,Center Gate for Uniform Parameters

• 550 Amperes Surge Capability• Blocking Voltage to 800 Volts




(TJ = 25 to 125°C, Gate Open)MCR265-2MCR265-4MCR265-6MCR265-8MCR265-10

VDRMVRRM

50200400600800

Volts

Forward Current (TC = 70°C)(All Conduction Angles)

IT(RMS)IT(AV)

5535

Amps

Peak Non-repetitive Surge Current — 8.3 ms(1/2 Cycle, Sine Wave)

ITSM 550 Amps



Forward Peak Gate Current(300 µs, 120 PPS)

IGM 2 Amps



1. VDRM and VRRM for all types can be applied on a continuous basis. Ratings apply for zero or negative gate voltage; however, positive gatevoltage shall not be applied concurrent with negative potential on the anode. Blocking voltages shall not be tested with a constant currentsource such that the voltage ratings of the devices are exceeded.These devices are rated for use in applications subject to high surge conditions. Care must be taken to insure proper heat sinking whenthe device is to be used at high sustained currents.



STYLE 3


K

G

A









TJ = 125°C

IDRM, IRRM——

——

102

µAmA


(ITM = 110 A)VTM — 1.5 1.9 Volts

Gate Trigger Current (Continuous dc)(Anode Voltage = 12 Vdc, RL = 100 Ohms)(TC = –40°C)

IGT——

2040

5090

mA


VGT — 1 1.5 Volts



Holding Current(Anode Voltage = 12 Vdc, Gate Open)

IH — 30 75 mA


tgt — 1.5 — µs



1. Pulse Width 300 µs, Duty Cycle 2%.

6.0

12

18

24

30

36

42

48

60

40

54

3530252015105.040363228242016128.0

93

4.06973778185

97

89

101105109113117121

90°

dc

αα = CONDUCTION ANGLE

0

IT(AV), AVERAGE ON-STATE FORWARD CURRENT (AMPS)*


α = 30°

00

125


α

dc

90°60°

α = 30°



60°

180°

180°

P

, A

VER

AGE

POW

ER (W

ATTS

)(A

V)

T ,

MAX

IMU

M C

ASE

TEM

PER

ATU

RE

( C

)C

°


FIGURE 6 — TYPICAL ON-STATE CHARACTERISTICS




VTM, INSTANTANEOUS ON-STATE VOLTAGE (VOLTS)

20


t, TIME (ms)

0.10.01

1.0

0.70.5

0.3

0.2

0.1

0.070.05

0.03

0.02

2k

TJ = 25°C

10k1k20 3k 5k500300200100500.2 30105.03.02.01.00.50.3

100

1.0

10

2.0

1000

1.00 3.0

2.0

0.3

0.5

0.7

1.0

120

3.0

– 60 – 40 – 20 0 20 40 60 80 100 140

VD = 12 Vdc

–20 1401201008060400 20


–40–60

0.3

0.4

0.5

0.7

1.0

1.5

2.0

2.5

0.25

VD = 12 Vdc

140

VD = 12 Vdc

0

2.0

3.0

0.3

0.5

0.8

1.0

1.5


–60 –40 –20 40 60 80 100 120



NO

RM

ALIZ

ED G

ATE

CU

RR

ENT

NO

RM

ALIZ

ED G

ATE

VOLT

AGE

NO

RM

ALIZ

ED H

OLD

ING

CU

RR

ENT

I

, IN

STAN

TAN

EOU

S O

N-S

TATE

CU

RR

ENT

(AM

PS)

TM

r(t),

TRAN

SIEN

T TH

ERM

AL R

ESIS

TAN

CE

(NO

RM

ALIZ

ED)



. . . designed for industrial and consumer applications such as temperature, light andspeed control; process and remote controls; warning systems; capacitive dischargecircuits and MPU interface.

• Center Gate Geometry for Uniform Current Density• All Diffused and Glass-Passivated Junctions for Parameter Uniformity and Stability• Small, Rugged, Thermowatt Construction for Low Thermal Resistance, High Heat

Dissipation and Durability• Low Trigger Currents, 200 µA Maximum for Direct Driving from Integrated Circuits



Peak Repetitive Forward and Reverse BlockingVoltage(1)

(TJ = –40 to 110°C)(1/2 Sine Wave, RGK = 1 kΩ)

MCR310-2MCR310-3MCR310-4MCR310-6MCR310-8MCR310-10

VDRMor

VRRM

50100200400600800

Volts

On-State RMS Current (TC = 75°C) IT(RMS) 10 Amps

Peak Non-repetitive Surge Current(1/2 Cycle, 60 Hz, TJ = –40 to 110°C)

ITSM 100 Amps



Peak Gate Current (t 10 µs) IGM 1 Amp





Mounting Torque – 8 in.-lb.





1. VDRM and VRRM for all types can be applied on a continuous basis. Ratings apply for zero ornegative gate voltage; however, positive gate voltage shall not be applied concurrent withnegative potential on the anode. Blocking voltages shall not be tested with a constant currentsource such that the voltage ratings of the devices are exceeded.



STYLE 3


CG

A

KA

G


ELECTRICAL CHARACTERISTICS (TC = 25°C, RGK = 1 kΩ unless otherwise noted)


Peak Forward Blocking Current(1) TC = 110°C(TJ = 110°C, VD = Rated VDRM) TC = 25°C

IDRM ——

——

50010

µAµA

Peak Reverse Blocking Current(1) TC = 110°C(TJ = 110°C, VR = Rated VRRM) TC = 25°C

IRRM ——

——

50010

µAµA

On-State Voltage(ITM = 20 A Peak, Pulse Width 1 ms, Duty Cycle 2%)


Gate Trigger Current, Continuous dc(2)

(VD = 12 V, RL = 100 Ω)IGT — 30 200 µA

Gate Trigger Voltage, Continuous dc(VD = 12 V, RL = 100 Ω)(VD = Rated VDRM, RL = 10 kΩ, TJ = 110°C)

VGT—0.1

0.5—

1.5—

Volts

Holding Current(VD = 12 V, ITM = 100 mA)

IH — — 6 mA

Critical Rate of Rise of Forward Blocking Voltage(VD = Rated VDRM, TJ = 110°C, Exponential Waveform)


Gate Controlled Turn-On Time(VD = Rated VDRM, ITM = 20 A, IG = 2 mA)

tgt — 1 — µs

1. Ratings apply for negative gate voltage or RGK = 1 kΩ. Devices shall not have a positive gate voltage concurrently with a negative voltageon the anode. Devices should not be tested with a constant current source for forward and reverse blocking capability such that the voltageapplied exceeds the rated blocking voltage.

2. Does not include RGK current.

Figure 19. Average CurrentDerating


Figure 21. Normalized Gate Current Figure 22. Gate Voltage

0.3120

0.5

1

2

–40 –20 0 20 40 60 80 90 100

3

140

VD = 12 Vdc

8


0 2 4

110

670

80

90

100

10

120


α = 30°

180°

dc


0.6

α

0.1

0.2

0.3

0.4

0.5

40

0.7

–60 –40 –20 0 10020 60 80 120

VD = 12 Vdc

0 2 4 6 8

16


0

4

8

12

20

αα = CONDUCTION ANGLE

10IT(AV), AVERAGE ON-STATE CURRENT (AMPS)

90°

180°

dc

T ,

MAX

IMU

M C

ASE

TEM

PER

ATU

RE

( C

)C

°N

OR

MAL

IZED

GAT

E C

UR

REN

T

P

, AV

ERAG

E PO

WER

DIS

SIPA

TIO

N (W

ATTS

)AV

V

, G

ATE

TRIG

GER

VO

LTAG

E (V

OLT

S)G

T

60°α = 30°60°

90°


. . . PNPN devices designed for high volume consumer applications such astemperature, light, and speed control; process and remote control, and warningsystems where reliability of operation is important.

• Passivated Surface for Reliability and Uniformity• Power Rated at Economical Prices• Practical Level Triggering and Holding Characteristics• Flat, Rugged, Thermopad Construction for Low Thermal Resistance, High Heat

Dissipation and Durability.




(TJ = 25 to 110°C, RGK = 1 kΩ)MCR506-2MCR506-3MCR506-4MCR506-6MCR506-8

VDRMVRRM

50100200400600

Volts

RMS Forward Current (All Conduction Angles) IT(RMS) 6 Amp

Average Forward Current (TC = 93°C) IT(AV) 3.82 Amp

Peak Non-repetitive Surge Current (1/2 Cycle, 60 Hz, TJ = –40 to 110°C) ITSM 40 Amp










2. Torque rating applies with use of torque washer (Shakeproof WD19523 or equivalent). Mounting torque in excess of 6 in. lb. does notappreciably lower case-to-sink thermal resistance. Anode lead and heat sink contact pad are common. (See AN290 B)For soldering purposes (either terminal connection or device mounting), soldering temperatures shall not exceed +225°C. For optimumresults, an activated flux (oxide removing) is recommended.



STYLE 2


KG

A

GA

K

A






ELECTRICAL CHARACTERISTICS (TC = 25°C, RGK = 1000 Ohms unless otherwise noted.)


Peak Forward Blocking Current(VD = Rated VDRM, TJ = 110°C)

IDRM — — 200 µA

Peak Reverse Blocking Current(VR = Rated VRRM, TJ = 110°C)

IRRM — — 200 µA



Gate Trigger Current (Continuous dc)(VAK = 7 Vdc, RL = 100 Ohms)(VAK = 7 Vdc, RL = 100 Ohms, TC = –40°C)

IGT——

——

200500

µA

Gate Trigger Voltage (Continuous dc)(VAK = 7 Vdc, RL = 100 Ohms, TC = 25°C)

VGT — — 1 Volts

Gate Non-Trigger Voltage(VAK = Rated VDRM, RL = 100 Ohms, TJ = 110°C)


Holding Current(VAK = 7 Vdc, TC = 25°C)

IH — — 5 mA

Forward Voltage Application Rate(VD = Rated VDRM, Exponential Waveform, TJ = 110°C)


FIGURE 1 — CURRENT DERATING FIGURE 2 — POWER DISSIPATION

7.06.05.04.03.02.01.0

105

070

75

80

85

90

95

100

110


10.0

0

2.0

4.0

6.0

6.0

8.0

0 1.0 2.0 3.0 4.0 5.0 7.0IT(RMS), RMS ON-STATE CURRENT (AMPS)

T ,

MAX

IMU

M A

LLO

WAB

LE C

ASE

TEM

PER

ATU

RE

( C

)C

°

P

, A

VER

AGE

POW

ER D

ISSI

PATI

ON

(WAT

TS)

(AV)


Reverse Blocking Triode Thyristors. . . PNPN devices designed for high volume, low cost consumer applications such astemperature, light and speed control; process and remote control; and warningsystems where reliability of operation is critical.

• Small Size• Passivated Die Surface for Reliability and Uniformity• Low Level Triggering and Holding Characteristics• Recommend Electrical Replacement for C106• Available in Two Package Styles:

Surface Mount Leadforms — Case 369AMiniature Plastic Package — Straight Leads — Case 369

ORDERING INFORMATION• To Obtain “DPAK” in Surface Mount Leadform (Case 369A):

Shipped in Sleeves — No Suffix, i.e., MCR706AShipped in 16 mm Tape and Reel — Add “RL” Suffix to Device Number, i.e.,MCR706ARL

• To Obtain “DPAK” in Straight Lead Version:Shipped in Sleeves — Add ‘1’ Suffix to Device Number, i.e., MCR706A1


Characteristic Symbol Value Unit


(1/2 Sine Wave)(RGK = 1000 Ohms, MCR703A1, MCR703ATC = –40 to +110°C) MCR704A1, MCR704A

MCR706A1, MCR706AMCR708A1, MCR708A

VDRMor

VRRM100200400600

Volts

Peak Non-repetitive Reverse Blocking Voltage(1/2 Sine Wave, RGK = 1000 Ohms,TC = –40 to +110°C) MCR703A1, MCR703A

MCR704A1, MCR704AMCR706A1, MCR706AMCR708A1, MCR708A

VRSM

150250450650

Volts

Average On-State Current (TC = –40 to +90°C)(TC = +100°C)

IT(AV) 2.61.6

Amps

Surge On-State Current (1/2 Sine Wave, 60 Hz, TC = +90°C)(1/2 Sine Wave, 1.5 ms TC = +90°C)

ITSM 2535

Amps

Circuit Fusing (t = 8.3 ms) I2t 2.6 A2s

Peak Gate Power (Pulse Width = 10 µs, TC = 90°C) PGM 0.5 Watt

Average Gate Power (t = 8.3 ms, TC = 90°C) PG(AV) 0.1 Watt





1. VDRM and VRRM for all types can be applied on a continuous basis. Ratings apply for zero ornegative gate voltage; however, positive gate voltage shall not be applied concurrent withnegative potential on the anode. Blocking voltages shall not be tested with a constant currentsource such that the voltage ratings of the devices are exceeded.



REV 1

CASE 369ASTYLE 5


CASE 369STYLE 5

A

AK

G

KA

A

G

Figure 23. Figure 1.Minimum Pad

Sizes forSurface Mounting


K

GA

0.1654.191

0.2436.172

0.1904.826

inchesmm

0.0631.6

0.1002.54

0.1183.0




Thermal Resistance, Junction to Case RθJC — 8.33 °C/W

Thermal Resistance, Junction to Ambient (Case 369A-04)(1) RθJA — 80 °C/W

Thermal Resistance, Junction to Ambient (Case 369-03)(2) RθJA — 85 °C/W

ELECTRICAL CHARACTERISTICS (TC = 25°C and RGK = 1000 ohms unless otherwise noted.)



TC = 110°C

IDRM, IRRM—— —

10200

µA

Peak Forward “On” Voltage(ITM = 8.2 A Peak, Pulse Width = 1 to 2 ms, 2% Duty Cycle)



(VAK = 12 Vdc, RL = 24 Ohms)(VAK = 12 Vdc, RL = 24 Ohms, TC = –40°C)

IGT——

25—

75300

µA

Gate Trigger Voltage (Continuous dc)(Source Voltage = 12 V, RS = 50 Ohms)(VAK = 12 Vdc, RL = 24 Ohms, TC = –40°C)

VGT — — 1 Volts

Gate Non-Trigger Voltage(VAK = Rated VDRM, RL = 100 Ohms, TC = 110°C)


Holding Current(VAK = 12 Vdc, IGT = 2 mA) TC = 25°C(Initiating On-State Current = 200 mA) TC = –40°C

IH——

——

510

mA

Total Turn-On Time(Source Voltage = 12 V, RS = 6 k Ohms)(ITM = 8.2 A, IGT = 2 mA, Rated VDRM)(Rise Time = 20 ns, Pulse Width = 10 µs)

tgt — 2 — µs

Forward Voltage Application Rate(VD = Rated VDRM, Exponential Waveform, TC = 110°C)


1. Case 369A-04 when surface mounted on minimum pad sizes recommended.2. Case 369-03 standing in free air.3. RGK current not included in measurement.

Figure 24. Maximum CaseTemperature

Figure 25. Maximum Ambient Temperature

f = 60 Hz

3.60 0.4 0.8 1.2 1.6 2 2.4 2.8

106

3.282

86

90

98

102

94

120°α = 30°

110

4

180°


60°

α0

0.8

α π0

f = 60 Hz

60° 90° 180° dc

90°

90

0 0.1 0.2 0.3 0.4 0.60.530

50

70

110

0.7IT(AV), AVERAGE FORWARD CURRENT (AMP)

dc

π

α = 30°

T ,

MAX

IMU

M A

LLO

WAB

LE C

ASE

TEM

PER

ATU

RE

( C

)C

°

T ,

MAX

IMU

M A

LLO

WAB

LE A

MBI

ENT

ATE

MPE

RAT

UR

E (

C)

°


. . . designed for direct interface with the ac power line. Upon reaching the breakovervoltage in each direction, the device switches from a blocking state to a low voltageon–state. Conduction will continue like an SCR until the main terminal current dropsbelow the holding current. The plastic axial lead package provides high pulse currentcapability at low cost. Glass passivation insures reliable operation. Applications are:

• High Pressure Sodium Vapor Lighting• Strobes and Flashers• Ignitors• High Voltage Regulators• Pulse Generators


Rating SymbolMKP1V120MKP1V130 Unit

Off–State Repetitive Voltage VDRM 90 Volts

On–State Current RMS (TL = 80°C, Lead Length = 3/8″,conduction angle = 180°, 60 Hz Sine Wave)

IT(RMS) 0.9 Amp

On–State Surge Current (Non–repetitive)(60 Hz One Cycle Sine Wave, Peak Value)

ITSM 4 Amps



Lead Solder Temperature(Lead Length 1/16″ from Case, 10 s Max)

TL 230 °C



Thermal Resistance, Junction to LeadLead Length = 3/8″

RθJL 40 °C/W

REV 1


CASE 59-04(DO–41)

SIDACsO.9 AMPERES RMS110 thru 280 VOLTS

MT1 MT2

Polarity denoted by cathode band


ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted; both directions)


Breakover VoltageMKP1V120MKP1V130

VBO110120

——

130140

Volts

Repetitive Peak Off–State Current(60 Hz Sine Wave, VD = Rated VDRM) TJ = 125°C

IDRM ——

——

550

µA

Forward “On’’ Voltage(ITM = 1 A)


Dynamic Holding Current IH — — 100 mA

Switching Resistance RS 0.1 — — kΩ

Breakover Current IBO — — 200 µA

Maximum Rate–of–Change of On–State Current MKP1V120, 130 di/dt — 90 — A/µs

0.80

IT(RMS), ON–STATE CURRENT (AMPS)

140

120

40

TA, MAXIMUM AMBIENT TEMPERATURE (°C)

0.4

T

0.2 0.6

100

130

, MAX

IMU

M A

LLO

WAB

LE L

EAD

TEM

PER

ATU

RE

( C

)L

1000

1.0

0.6

0.2

40

I

20 60

0.4

0.8

, ON

–STA

TE C

UR

REN

T (A

MPS

)T(

RM

S)

1.61.21.0 1.4 2.01.8

110

90

80

60

70

50

°

80 120 140

TJ = 125°CSine WaveConduction Angle = 180°C

Assembled in PCBLead Length = 3/8″TJ = 125°C

Sine WaveConduction Angle = 180°C

TL

3/8″ 3/8″



t, TIME (ms)

100.1

0.07

0.03

0.02

0.015.00.2 0.5 1.0 2.0

0.05

0.1

0.2

r(t),

TRAN

SIEN

T TH

ERM

AL R

ESIS

TAN

CE

(NO

RM

ALIZ

ED

0.3

0.50.71.0

20 50 100 200 500 1.0 k 2.0 k 5.0 k 10 k

The temperature of the lead should bemeasured using a thermocouple placed on thelead as close as possible to the tie point. Thethermal mass connected to the tie point isnormally large enough so that it will notsignificantly respond to heat surges generatedin the diode as a result of pulsed operationonce steady–state conditions are achieved.Using the measured value of TL, the junctiontemperature may be determined by:

TJ = TL + TJL

ZJL(t) = RJL • r(t)TJL = Ppk RJL[r(t)]where:TJL = the increase in junction temperature above thelead temperaturer(t) = normalized value of transient thermal resistance attime, t from this figure. For example,r(tp) = normalized value of transient resistance at time tp.

TIMEtp



–60

0.8

0.4

I

–40 –20 100 140

0.6

1.0

1.2


100–60

0.9

0.8V

40–40 –20 0 20

1.0

1.4

, BR

EAKO

VER

VO

LTAG

E (N

OR

MAL

IZED

)BO

8060 120 140

, HO

LDIN

G C

UR

REN

T (N

OR

MAL

IZED

)H

120800 604020


. . . designed for direct interface with the ac power line. Upon reaching the breakovervoltage in each direction, the device switches from a blocking state to a low voltageon–state. Conduction will continue like an SCR until the main terminal current dropsbelow the holding current. The plastic axial lead package provides high pulse currentcapability at low cost. Glass passivation insures reliable operation. Applications are:

• High Pressure Sodium Vapor Lighting• Strobes and Flashers• Ignitors• High Voltage Regulators• Pulse Generators


Rating Symbol Min Max Unit

Repetitive Breakover VoltageMKP3V110MKP3V120MKP3V130

V(BO)100110120

120130140

Volts

Off–State Repetitive Voltage VDRM — 90 Volts

On–State RMS Current IT(RMS) — 1 Amp

On–State Surge Current (Non–repetitive)(60 Hz One Cycle Sine Wave, Peak Value)

ITSM — 20 Amps

Operating Junction Temperature Range TJ –40 +125 °C

Storage Temperature Range Tstg –40 +150 °C

Lead Solder Temperature(Lead Length 1/16″ from Case, 10 s Max)

— — +230 °C



Thermal Resistance, Junction to Lead(Lead Length = 3/8″)

RθJL — 15 °C/W



CASE 267–03SURMETIC 50

PLASTIC AXIAL

SIDACs1 AMPERE RMS

100 thru 135 VOLTS

MT1 MT2



ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted; both directions)


Breakover Current I(BO) — — 200 µA

Repetitive Peak Off–State Current(60 Hz Sine Wave, VD = 90 V)

IDRM — — 10 µA

Forward “On’’ Voltage(ITM = 1 A Peak)


Dynamic Holding Current IH — — 100 mA

Switching Resistance RS 0.1 — — kΩ

Maximum Rate of Change of On–State Current di/dt — 50 — A/µs

CURRENT DERATING

0.80


120


0.4

T

0.2 0.6

100

130

, MAX

IMU

M A

LLO

WAB

LE C

ASE

TEM

PER

ATU

RE

( C

)C

1.00

100

60

20

0.4

T

0.2 0.6

40

80, M

AXIM

UM

ALL

OW

ABLE

AM

BIEN

TA

1.61.21.0 1.4 2.01.8

110

90

80

°

0.8 1.2 1.4

α

α = Conduction AngleTJ Rated = 125°C

α

α = Conduction AngleTJ Rated = 125°C

1.6 1.8 2.00

120

140

= 180°TE

MPE

RAT

UR

E (

C)

°

= 180°



t, TIME (ms)

10

0.03

0.02

0.015.00.2 0.5 1.0 2.0

0.05

0.1

0.2

r(t),

TRAN

SIEN

T TH

ERM

AL R

ESIS

TAN

CE

(NO

RM

ALIZ

ED

0.3

0.5

1.0

20 50 100 200 500 1.0 k 2.0 k 5.0 k 10 k

The temperature of the lead should bemeasured using a thermocouple placed on thelead as close as possible to the tie point. Thethermal mass connected to the tie point isnormally large enough so that it will notsignificantly respond to heat surges generatedin the diode as a result of pulsed operationonce steady–state conditions are achieved.Using the measured value of TL, the junctiontemperature may be determined by:

TJ = TL + TJL

20 k

LEAD LENGTH = 1/4″ZJL(t) = RJL • r(t)TJL = Ppk RJL[r(t)]where:TJL = the increase in junction temperature above thelead temperaturer(t) = normalized value of transient thermal resistance attime, t from this figure. For example,r(tp) = normalized value oftransient resistance at time tp.

TIMEtp



–60

50

0

I

–40 –20 100 140

25

75

100


100–60

10

0

I

40–40 –20 0 20

100

125

, BR

EAKO

VER

CU

RR

ENT

( A

)(B

O)

8060 120 140

, HO

LDIN

G C

UR

REN

T (m

A)H

120800 604020

20

30

40

50

60

70

80

90

150

175

200

225

250


High Voltage Bidirectional TVS Devices

These transient voltage suppression (TVS) devices prevent overvoltagedamage to sensitive circuits by lightning, induction and power line crossings.They are breakover–triggered crowbar protectors. Turn–off occurs when thesurge current falls below the holding current value.

Applications include current loop lines in telephony and control systems,central office stations, repeaters, building and residence entrance terminals andelectronic telecom equipment.

• High Surge Current Capability

• Bidirectional Protection in a Single Device

• Little Change of Voltage Limit with Transient Amplitude or Rate

• Freedom from Wearout Mechanisms Present in Non–Semiconductor De-vices

• Fail–Safe. Shorts When Overstressed, Preventing Continued UnprotectedOperation.

DEVICE RATINGS:–40°C to 50°C for MMT10V275–40°C to 65°C for MMT10V400 (except surge)


Peak Repetitive Off–State Voltage — MaximumMMT10V275MMT10V400

VDM±200±265

Volts

On–State Surge Current — Maximum Nonrepetitive (MMT10V400 –20°C to 65°C)10 x 1000 µs exponential wave, Notes 1, 2, 360 Hz ac, 1000 V(rms), RS = 1.0 kΩ, 1 second60 Hz ac, 480 V(rms), RS = 48 Ω, 2 seconds

ITSM1ISTM2ISTM3

±100±10±1.0

A(pk)A(rms)A(rms)

Rate of Change of On–State Current — Maximum NonrepetitiveCritical Damped Wave, C = 1.2 µF, L = 16 µH, R = 7.4,VCI = 1000 V, I(pk) = 100 A (short circuit), 0 to 50% I (pk)

di/dt 50 A/µs

DEVICE THERMAL RATINGS

Operating Temperature RangeBlocking or Conducting State

TJ1 –40 to +125 °C

Overload Junction Temperature — MaximumConducting State Only

TJ2 +175 °C

Thermal Resistance, Junction to Case — Maximum RθJC 1.5 °C/W

Thermal Resistance, Case to Ambient, Without Heatsink — +200 °C/W




BIDIRECTIONALTHYRISTOR SURGE

SUPPRESSORS25 WATTS STEADY STATE

CASE 416A–01




Characteristics Symbol Min Typ Max Unit

Breakover Voltage(dv/dt = 100 V/µs, ISC = 10 A, Vdc = 1000 V) MMT10V275

MMT10V400

V(BO)1——

——

275400

Volts

Breakover Voltage(f = 60 Hz, ISC = 1.0 A(rms), VOC = 1000 V(rms), MMT10V275RI = 1.0 kΩ, t = 0.5 cycle, Note 2) MMT10V400

V(BO)2——

——

275400

Volts

Breakover Voltage Temperature Coefficient dV(BO)/dTJ — 0.05 — %/°C

Breakdown Voltage(I(BR) = 1.0 mA) MMT10V275

MMT10V400

V(BR)200265

——

——

Volts

Breakdown Voltage Temperature Coefficient dV(BO)/dTJ — 0.11 — %/°C

Off State Current (VD = 160 V) ID — — 3.0 µA

On–State Voltage (IT = 10 A)(PW ≤ 300 µs, Duty Cycle ≤ 2%, Note 2)

VT — 3.0 4.0 Volts

Breakover Current (f = 60 Hz, VDM = 1000 V(rms), RS = 1.0 kΩ) IBO — 500 — mA

Holding Current Note 2(10 x 100 Ms exponential wave, IT = 10 A, V = 52 V, RS = 200 Ω)

IH — 400 — mA

Critical Rate of Rise of Off–State Voltage(Linear waveform, VD = 0.8 x Rated VDRM, TJ = 125°C)

dv/dt 2000 — — V/µs

Capacitance (f = 1.0 MHz, 50 V, 15 mV) CO — 55 — pF

1. Allow cooling before testing second polarity.

2. Measured under pulse conditions to reduce heating.

3. Requires θCS ≤ 6°C/W each side, infinite heatsink.

TA

RθS(A1) RθC(S1) RθJ(C1) RθJ(C2) RθC(S2) RθS(A2)TATS1 TC1 TJ TC2 TS2

PD

Terms in the model signify:TA = Ambient Temp.TS = Heatsink Temp.TC = Case Temp.TJ = Junction Temp.

RθSA = Thermal Resistance, Heatsink to AmbientRθCS = Thermal Resistance, Case to HeatsinkRθJC = Thermal Resistance, Junction to CasePD = Power Dissipation

Subscripts 1 and 2 denote the device terminals, MT1 and MT2, respectively.RθCS = 6°C/W maximum (each side)RθJC = 3°C/W maximum (each side)

Thermal resistance values are:

The RθCS values are estimates for dry mounting with heatsinks contacting theraised pedestal on the package. For minimum thermal resistance, the deviceshould be sandwiched between clean, flat, smooth conducting electrodes andsecurely held in place with a compressive force of 2 pounds maximum. Theelectrodes should contact the entire pedestal area. When the device ismounted symmetrically, the thermal resistances are identical. The values forRθSA and RθCS are controlled by the user and depend on heatsink design andmounting conditions.

Figure 9. Thermal Circuit, Device Mounted Between Heatsinks




80706050403020100

600

550

500

450

400

350

300

250

200

I H, H

OLD

ING

CU

RR

ENT

(mA)

Figure 11. Holding Current TemperatureCoefficient

IH, HOLDING CURRENT AT 0°C (mA)

250200

0

– 1

– 2

– 3

– 4300 400350 450 550500 600

TYPICAL LOW

TYPICAL

I H, H

OLD

ING

CU

RR

ENT

∆TE

MPE

RAT

UR

E C

OEF

FIC

IEN

T (m

A/C

)°

Figure 12. Normalized Maximum 60 Hz V BOversus Junction Temperature


140120100806040200– 20

1.2

1.15

0.9

NO

RM

ALIZ

ED B

REA

KOVE

R V

OLT

AGE

Figure 13. Temperature Dependence of 60 HzBreakover Current

TJ, JUNCTION TEMPERATURE PRIOR TO TEST (°C)

10

1

0.1

1.1

1.05

1

0.95

The thermal coefficient of VF(BR) is similar to that of a zenerdiode. IBO falls with temperature, reducing the zenerimpedance contribution to VBO. This causes the VBOtemperature coefficient perature to be less than or equal to theVF(BR) coefficient. The graph allows the estimation of themaximum voltage rise of either parameter.

NORMALIZEDTO 25°C

140120100806040200– 40 – 20 160

I BO

, NO

RM

ALIZ

ED B

REA

KOVE

R C

UR

REN

T

Note: The behavior of the breakover current during AC operationis complex, due to junction heating, case heating and thermalinteraction between the device halves. Microplasma conductionat the beginning of breakdown sometimes results in higher localcurrent densities and earlier than predicted switching. Thisreduces power dissipation and stress on the device.

MAXIMUM IBO = 1.0 Aat 25°C

MINIMUM IBO UNITFIRST HALF–CYCLEf = 60 HzVOC = 1000 V (rms)IOC = 1.0 A (rms)



. . . designed primarily for half-wave ac control applications, such as motor controls,heating controls and power supplies; or wherever half–wave silicon gate–controlled,solid–state devices are needed.


• Small, Rugged, Thermowatt Construction for Low Thermal Resistance, High HeatDissipation and Durability





(TJ = 25 to 100°C, Gate Open)FAB

S2800 DMN

VRRMVDRM

50100200400600800

Volts

Peak Non–repetitive Reverse Voltage andNon–Repetitive Off–State Voltage(1)

FAB

S2800 DMN

VRSMVDSM

75125250500700900

Volts

RMS Forward Current(All Conduction Angles) TC = 75°C

IT(RMS) 10 Amps

Peak Forward Surge Current (1 Cycle, Sine Wave, 60 Hz, TC = 80°C) ITSM 100 Amps


Forward Peak Gate Power (t 10 µs) PGM 16 Watts







STYLE 3


A KG







Peak Forward or Reverse Blocking Current(VAK = Rated VDRM or VRRM, Gate Open) TC = 25°C

TC = 100°C

IDRM, IRRM——

——

102

µAmA

Instantaneous On–State Voltage,(ITM = 30 A Peak, Pulse Width 1 ms, Duty Cycle 2%)

VT — 1.7 2 Volts


IGT — 8 15 mA

Gate Trigger Voltage (Continuous dc)(VD = 12 Vdc, RL = 30 Ohms)

VGT — 0.9 1.5 Volts

Holding Current(Gate Open, VD = 12 Vdc, IT = 150 mA)

IH — 10 20 mA

Gate Controlled Turn–On Time(VD = Rated VDRM, ITM = 2 A, IGR = 80 mA)

tqt — 1.6 — µs

Circuit Commutated Turn–Off Time(VD = VDRM, ITM = 2 A, Pulse Width = 50 µs,dv/dt = 200 V/µs, di/dt = 10 A/µs, TC = 75°C)

tq — 25 — µs

Critical Rate–of–Rise of Off–State Voltage(VD = Rated VDRM, Exponential Rise, TC = 100°C)

dv/dt — 100 — V/µs

FIGURE 1 – CURRENT DERATING FIGURE 2 – POWER DISSIPATION

IT(AV), IT(RMS), ON–STATE CURRENT (AMPS)

6

100

80

7040 2

90

T

10

8

IT(AV), IT(RMS), MAXIMUM ON–STATE CURRENT (AMP)

60

8

4

2

02 4

6

P

8 10, MAX

IMU

M A

LLO

WAB

LE C

ASE

TEM

PER

ATU

RE

( C

)°

C

, AVE

RAG

E PO

WER

DIS

SIPA

TIO

N (W

ATTS

)(A

V)

12

10MAXIMUM

MAXIMUM

HALF–WAVECURRENT WAVEFORM: A SINUSOIDALLOAD: RESISTIVE OR INDUCTIVE

HALF–WAVECURRENT WAVEFORM: A SINUSOIDALLOAD: RESISTIVE OR INDUCTIVE

IT(AV)

IT(RMS)

RMS CURRENTAV CURRENT



. . . designed primarily for ac power switching. The gate sensitivity of these triacspermits the use of economical transistorized or integrated circuit control circuits, andit enhances their use in low-power phase control and load-switching applications.

• Very High Gate Sensitivity• Low On-State Voltage at High Current Levels• Glass-Passivated Chip for Stability• Small, Rugged Thermopad Construction for Low Thermal Resistance, High Heat



Rating Suffix Symbol Value Unit


(TJ = 25 to 100°C, Gate Open)T2322, T2323

BDM

VDRM 200400600

Volts

RMS On-State Current (TC = 70°C)(Full-Cycle Sine Wave 50 to 60 Hz)

IT(RMS) 2.5 Amps

Peak Non-repetitive Surge Current(One Full Cycle, 60 Hz)

ITSM 25 Amps


I2t 2.6 A2s

Peak Gate Power (1 µs) PGM 10 Watts

Average Gate Power (TC = 60°C + 38.3 ms) PG(AV) 0.15 Watt

Peak Gate Current (1 µs) IGM 0.5 Amp



Mounting Torque (6-32 Screw)(2) — 8 in. lb.


2. Torque rating applies with use of torque washer (Shakeproof WD19523 or equivalent). Mounting Torque in excess of 6 in. lb. does notappreciably lower case-to-sink thermal resistance. Main terminal 2 and heat-sink contact pad are common.For soldering purposes (either terminal connection or device mounting), soldering temperatures shall not exceed +200°C, for 10 seconds.Consult factory for lead bending options.




STYLE 5

SENSITIVE GATE TRIACs2.5 AMPERES RMS200 thru 600 VOLTS


MT1

G

MT2MT1

GMT2

MT2









TJ = 100°C

IDRM——

—0.2

100.75

µAmA

Peak On-State Voltage*(ITM = 10 A) T2323 Series

T2322 Series

VTM——

1.71.7

2.62.2

Volts

Gate Trigger Current (Continuous dc)(VD = 12 V, RL = 30 Ω)

All Modes T2322 Series MT2(+), G(+); MT2(–), G(–) T2323 Series MT2(+), G(–); MT2(–),I G(+) T2323 Series

IGT

———

———

102540

mA

Gate Trigger Voltage (Continuous dc)(VD = 12 Vdc, RL = 30 Ω, TC = 25°C)(VD = VDRM, RL = 125 Ω, TC = 100°C)

VGT—

0.151—

2.2—

Volts


IH — 15 30 mA

Gate Controlled Turn-On Time(VD = Rated VDRM, ITM = 10 A pk, IG = 60 mA)

tgt — 1.8 2.5 µs

Critical Rate-of-Rise of Off-State Voltage(VD = Rated VDRM, Exponential Waveform, TC = 100°C)

dv/dt 10 100 — V/µs

Critical Rate-of-Rise of Commutation Voltage(VD = Rated VDRM, ITM = 3.5 A pk, Commutatingdi/dt = 1.26 A/ms, Gate Unenergized, TC = 90°C)

dv/dt(c) 1 4 — V/µs

*Pulse Test: Pulse Width 300 µs, Duty Cycle 2%.










(TJ = –40 to +100°C, Gate Open)T2500 B

DMN

VDRM

200400600800

Volts

On-State Current RMS (TC = +80°C)(Full Cycle Sine Wave 50 to 60 Hz)

IT(RMS) 6 Amps

Peak Non-repetitive Surge Current(One Full Cycle, 60 Hz, TC = +80°C)

ITSM 60 Amps


I2t 15 A2s


PGM 16 Watts


PG(AV) 0.2 Watt

Peak Gate Trigger Current (Pulse Width = 10 µs) IGTM 4 Amps






STYLE 4

TRIACs6 AMPERES RMS

200 thru 800 VOLTS

MT1

G

MT2







Peak Blocking Current(Rated VDRM, Gate Open,TJ = 100°C)

IDRM — — 2 mA

Maximum On-State Voltage (Either Direction)*(IT = 30 A Peak)

VTM — — 2 Volts

Gate Trigger Current (Continuous dc)(VD = 12 Vdc, RL = 12 Ohms)MT2(+), G(+) MT2(+), G(–)MT2(–), G(–)MT2(–), G(+)

IGT

————

10201530

25602560

mA

Gate Trigger Voltage (Continuous dc) (All Quadrants)(VD = 12 Vdc, RL = 12 Ohms)(VD = VDROM, RL = 125 Ohms, TC = 100°C)

VGT—0.2

1.25—

2.5—

Volts


IH — 15 30 mA

Gate Controlled Turn-On Time(Rated VDRM, IT = 10 A , IGT = 160 mA, Rise Time = 0.1 µs)

tgt — 1.6 — µs

Critical Rate-of-Rise of Commutation Voltage(Rated VDRM, IT(RMS) = 6 A, Commutating di/dt = 3.2 A/ms,Gate Unenergized, TC = 80°C)


Critical Rate-of-Rise of Off-State Voltage(Rated VDRM, Exponential Voltage Rise,Gate Open, TC = 100°C) T2500B

T2500D,M,N

dv/dt

——

10075

——

V/µs





MT2(+)

MT2(–)

MT2(+), G(–) MT2(+), G(+)

MT2(–), G(–) MT2(–), G(+)

G(–) G(+)

ELECTRICAL CHARACTERISTICS of RECOMMENDEDBIDIRECTIONAL SWITCHES

USAGE General

PART NUMBER MBS4991 MBS4992

VS 6.0 – 10 V 7.5 – 9.0 V

IS 350 µA Max 120 µA Max

VS1 – VS2 0.5 V Max 0.2 V Max

TemperatureCoefficient 0.02%/°C Typ

See AN-526 for Theory and Characteristics of Silicon Bidirectional Switches.



• Blocking Voltage to 800 Volts• All Diffused and Glass Passivated Junctions for Greater Parameter Uniformity and

Stability• Small, Rugged, Isolated Construction for Low Thermal Resistance, High Heat





(TJ = –40 to +100°C, Gate Open)T2500BFPT2500DFPT2500MFPT2500NFP

VDRM

200400600800

Volts

On-State RMS Current (TC = +80°C )(2)

(Full Cycle Sine Wave 50 to 60 Hz)IT(RMS) 6 Amps

Peak Non–repetitive Surge Current(One Full Cycle, 60 Hz, TC = +80°C)

ITSM 60 Amps


I2t 40 A2s


PGM 1 Watt


PG(AV) 0.2 Watt


RMS Isolation Voltage (TA = 25°C, Relative Humidity 20%) VISO 1500 Volts





Thermal Resistance, Junction to Case(2)

Case to SinkJunction to Ambient

RθJCRθCSRθJA

2.72.2(typ)

60

°C/W




MT1

G

MT2

CASE 221C-02STYLE 3






Peak Off–State Current (Either Direction)(VD = Rated VDRM, TJ = 100°C, Gate Open)

IDRM — — 2 mA

Maximum On-State Voltage (Either Direction)*(IT = 30 A Peak)

VTM — — 2 Volts


MT2(+), G(+)MT2(+), G(–)MT2(–), G(–)MT2(–), G(+)

IGT

————

10201530

25602560

mA

Gate Trigger Voltage (Continuous dc) (All Quadrants)(VD = 12 Vdc, RL = 12 Ohms)(VD = VDROM, RL = 125 Ohms, TC = 100°C, All Trigger Models)

VGT—0.2

1.25—

2.5—

Volts

Holding Current (Either Direction)(Main Terminal Voltage = 12 Vdc, Gate Open,Initiating Current = 150 mA, TC = 25°C)

IH — 15 30 mA

Gate Controlled Turn-On Time(VD = Rated VDRM, IT = 10 A,IGT = 160 mA, Rise Time 0.1 µs)

tgt — 1.6 — µs

Critical Rate–of–Rise of Commutation Voltage(VD = Rated VDRM, IT(RMS) = 6 A,Commutating di/dt = 3.2 A/ms,Gate Unenergized, TC = 80°C)


Critical Rate–of–Rise of Off–State Voltage(VD = Rated VDRM, Exponential Voltage Rise,Gate Open, TC = 100°C)

dv/dt — 100 — V/µs


Quadrant II Quadrant I

Quadrant III Quadrant IV

MT2(+), G(–) MT2(+), G(+)

MT2(–), G(–) MT2(–), G(+)

Trigger devices are recommended

1. Consistent predictable turn–on

2. Simplified circuitry.3. Fast turn–on time for cooler,

Electrical Characteristics of RecommendedBidirectional Switches

Quadrant Definitions

Part Number

Usage General

MBS4992MBS4991

VS

ISVS1–VS2


6–10 V 7.5–9 V

350 µA Max 120 µA Max

0.5 V Max 0.2 V Max

0.02%/°C Typ

MT2(+)

MT2(–)

G(–) G(+)for gating on Triacs. They provide:

more efficient and reliableoperation.

points.


Bidirectional Triode Thyristors


• Blocking Voltage to 600 Volts• All Diffused and Glass Passivated Junctions for Greater Parameter Uniformity and

Stability• Small, Rugged, Thermowatt Construction for Low Thermal Resistance, High Heat

Dissipation and Durability• T2800 — Four Quadrant Gating




(TJ = –40 to +100°C, Gate Open)T2800 B

D M

VDRM

200400600

Volts

RMS On-State Current (TC = +80°C)(Conduction Angle = 360°)

IT(RMS) 8 Amps

Peak Non-repetitive Surge Current(One Full Cycle, 60 Hz, TJ = +80°C)

ITSM 100 Amps


I2t 40 A2s

Peak Gate Power (Pulse Width = 1 µs) PGM 16 Watts











STYLE 4

TRIACs8 AMPERES RMS

200 thru 600 VOLTS

MT1

G

MT2

REV 1




Peak Blocking Current(VD = Rated VDRM, Gate Open) TC = 25°C

TC = 100°C

IDRM——

——

102

µAmA

Peak On-State Voltage (Either Direction)*(IT = 30 A Peak)

VTM — 1.7 2 Volts

Gate Trigger Current (Continuous dc)(VD = 12 Vdc, RL = 12 Ohms)MT2(+), G(+) T2800MT2(+), G(–) T2800 MT2(–), G(–) T2800MT2(–), G(+) T2800

IGT

————

10201530

25602560

mA

Gate Trigger Voltage (Continuous dc) (All Polarities)(VD = 12 Vdc, RL = 100 Ohms)(RL = 125 Ohms, VD = VDRM, TC = 100°C)

VGT—0.2

1.25—

2.5—

Volts

Holding Current (Either Direction)(VD = 12 Vdc, Gate Open) T2800

IH— 15 30

mA

Gate Controlled Turn-On Time(VD = Rated VDRM, IT = 10 A, IGT = 80 mA, Rise Time = 0.1 µs)

tgt — 1.6 — µs

Critical Rate-of-Rise of Commutation Voltage(VD = Rated VDRM, IT(RMS) = 8 A, Commutating di/dt = 4.1 A/ms,Gate Unenergized, TC = 80°C)


Critical Rate-of-Rise of Off-State Voltage(VD = Rated VDRM, Exponential Voltage Rise,Gate Open, TC = 100°C)

T2800 BDM

dv/dt

100—60

———

———

V/µs


FULL CYCLESINUSOIDALWAVEFORM

0 2 4

100

85

90

80

TYPICAL

2

4

6

8

10

12

108642


0

MAXIMUM

0


6

95

FIGURE 1 – CURRENT DERATING

128

FULL CYCLESINUSOIDALWAVEFORM


T C, M

AXIM

UM

ALL

OW

ABLE

CAS

E TE

MPE

RAT

UR

E ( C

)°

P (AV

), A

VER

AGE

POW

ER D

ISSI

PATI

ON

(WAT

TS)

4–1

Surface MountPackage Information and

Tape and Reel Specifications

Surface Mount Package Information and Tape and Reel Specifications4–2


INFORMATION FOR USING SURFACE MOUNT THYRISTORS

MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS

Surface mount board layout is a critical portion of the totaldesign. The footprint for the semiconductor packages mustbe the correct size to insure proper solder connection

interface between the board and the package. With thecorrect pad geometry, the packages will self align whensubjected to a solder reflow process.

SOT-223

0.2486.3

0.0792.0

0.0591.5

0.0591.5

0.0591.5

0.0792.0

0.153.8

0.0912.3

0.0912.3

mminches

DPAK

0.1904.826

0.1002.54

0.0631.6

0.1654.191

0.1183.0

0.2436.172

mminches

POWER DISSIPATION

The power dissipation of a surface mount thyristor is afunction of the MT2 or anode pad size. This can vary fromthe minimum pad size for soldering to a pad size given formaximum power dissipation. Power dissipation for a surfacemount device is determined by TJ(max), the maximum ratedjunction temperature of the die, RθJA, the thermal resistancefrom the device junction to ambient, and the operatingtemperature, TA. Using the values provided on the datasheets for various packages, PD can be calculated asfollows:

PD =TJ(max) – TA

RθJA

The values for the equation are found in the maximumratings table on the data sheets. For example, substitutingthese values into the equation for a SOT-223 at an ambienttemperature TA of 25°C, one can calculate the powerdissipation of the device to be 550 milliwatts.

PD = 110°C – 25°C156°C/W

= 550 milliwatts

The 156°C/W for the SOT-223 package assumes the useof the recommended footprint on a glass epoxy printed circuitboard to achieve a power dissipation of 550 milliwatts. Thereare other alternatives to achieving higher power dissipationfrom the SOT-223 package. One is to increase the area ofthe MT2 or anode pad. By increasing the area of the MT2 oranode pad, the power dissipation can be increased. Al-though one can almost double the power dissipation with thismethod, one will be giving up area on the printed circuit

board which can defeat the purpose of using surface mounttechnology. A graph of RθJA versus MT2 or anode pad areafor a SOT-223 package is shown in Figure 1.

Figure 1. Junction to AmbientThermal Resistance versus Copper

Tab Area

FOIL AREA (cm2)

θJA

, JU

NC

TIO

N T

O A

MBI

ENT

THER

MAL

30

60708090

160

2.00 4.0 6.0 8.0 10

RES

ISTA

NC

E,

C/W

°

150140130120110

4050

100

TYPICALMAXIMUM

4

1 2 3



R

L

L

Another alternative would be to use a ceramic substrate oran aluminum core board such as Thermal Clad . Using aboard material such as Thermal Clad, an aluminum coreboard, the power dissipation can be doubled using the samefootprint.

4–3Surface Mount Package Information and Tape and Reel SpecificationsMotorola Thyristor Device Data

SOLDER STENCIL GUIDELINES

Prior to placing surface mount components onto a printedcircuit board, solder paste must be applied to the pads. Asolder stencil is required to screen the optimum amount ofsolder paste onto the footprint. The stencil is made of brass

or stainless steel with a typical thickness of 0.008 inches.The stencil opening size should be the same as the pad sizeon the printed circuit board, i.e., a 1:1 registration.

SOLDERING PRECAUTIONS

The melting temperature of solder is higher than the ratedtemperature of the device. When the entire device is heatedto a high temperature, failure to complete soldering within ashort time could result in device failure. Therefore, thefollowing items should always be observed in order tominimize the thermal stress to which the devices aresubjected.

• Always preheat the device.

• The delta temperature between the preheat and solderingshould be 100°C or less.*

• When preheating and soldering, the temperature of theleads and the case must not exceed the maximum temper-ature ratings as shown on the data sheet. When using in-frared heating with the reflow soldering method, the differ-ence shall be a maximum of 10°C.

• The soldering temperature and time shall not exceed260°C for more than 10 seconds.

• When shifting from preheating to soldering, the maximumtemperature gradient shall be 5°C or less.

• After soldering has been completed, the device should beallowed to cool naturally for at least three minutes. Gradualcooling should be used as the use of forced cooling will in-crease the temperature gradient and result in latent failuredue to mechanical stress.

• Mechanical stress or shock should not be applied duringcooling.

*Soldering a device without preheating can cause excessivethermal shock and stress which can result in damage to thedevice.

TYPICAL SOLDER HEATING PROFILE

For any given circuit board, there will be a group of controlsettings that will give the desired heat pattern. The operatormust set temperatures for several heating zones, and afigure for belt speed. Taken together, these control settingsmake up a heating “profile” for that particular circuit board. Onmachines controlled by a computer, the computer remem-bers these profiles from one operating session to the next.Figure 2 shows a typical heating profile for use whensoldering a surface mount device to a printed circuit board.This profile will vary among soldering systems but it is a goodstarting point. Factors that can affect the profile include thetype of soldering system in use, density and types ofcomponents on the board, type of solder used, and the typeof board or substrate material being used. This profile showstemperature versus time. The line on the graph shows theactual temperature that might be experienced on the surface

of a test board at or near a central solder joint. The twoprofiles are based on a high density and a low density board.The Vitronics SMD310 convection/infrared reflow solderingsystem was used to generate this profile. The type of solderused was 62/36/2 Tin Lead Silver with a melting pointbetween 177–189°C. When this type of furnace is used forsolder reflow work, the circuit boards and solder joints tend toheat first. The components on the board are then heated byconduction. The circuit board, because it has a large surfacearea, absorbs the thermal energy more efficiently, thendistributes this energy to the components. Because of thiseffect, the main body of a component may be up to 30degrees cooler than the adjacent solder joints.

STEP 1PREHEATZONE 1“RAMP”

STEP 2VENT

“SOAK”

STEP 3HEATING

ZONES 2 & 5“RAMP”

STEP 4HEATING

ZONES 3 & 6“SOAK”

STEP 5HEATING

ZONES 4 & 7“SPIKE”

STEP 6VENT

STEP 7COOLING

200°C

150°C

100°C

50°C

TIME (3 TO 7 MINUTES TOTAL) TMAX

205° TO219°C

PEAK ATSOLDER

JOINT

DESIRED CURVE FOR LOWMASS ASSEMBLIES

100°C

160°C

170°C

140°C

Figure 2. Typical Solder Heating Profile

150°C

DESIRED CURVE FOR HIGHMASS ASSEMBLIES

SOLDER IS LIQUID FOR40 TO 80 SECONDS

(DEPENDING ONMASS OF ASSEMBLY)



Tape and Reel Specifications

Embossed Tape and Reel is used to facilitate automatic pick and place equipment feed requirements. The tape is used as theshipping container for various products and requires a minimum of handling. The antistatic/conductive tape provides a securecavity for the product when sealed with the “peel-back” cover tape.

• One Reel Size — 7″, 1000 Units• Used for Automatic Pick and Place Feed Systems• Minimizes Product Handling• EIA 481A• SOT-223 in 12 mm Tape

Use the standard device title to order the SOT-223 package in 12 mmTape and Reel. Note that each individual reel has 1000 devices containedin the tape. Also note the minimum lot size is one full reel for each line item,and orders are required to be in increments of the single reel quantity.

• One Reel Size — 13″, 2500 Units• Used for Automatic Handling• Minimizes Product Handling• EIA 481A• DPAK in 16 mm Tape• Add a T4 suffix to the device title to order devices in

16 mm Tape and Reel

Note that each individual reel has 2500 devices contained in the tape. Also note the minimum lot size is one full reel for eachline item, and orders are required to be in increments of the single reel quantity.

OF FEED

DIRECTION

12 mmSOT-223

OF FEED

DIRECTION

16 mmDPAK


TO–92 EIA, IEC, EIAJRadial Tape in Fan FoldBox or On Reel

Radial tape in fan fold box or on reel of the reliable TO–92 package arethe best methods of capturing devices for automatic insertion in printedcircuit boards. These methods of taping are compatible with variousequipment for active and passive component insertion.

• Available in Fan Fold Box• Available on 365 mm Reels• Accommodates All Standard Inserters• Allows Flexible Circuit Board Layout• 2.5 mm Pin Spacing for Soldering• EIA–468, IEC 286–2, EIAJ RC1008B

Ordering Notes:

When ordering radial tape in fan fold box or on reel, specify the style perFigures 3 through 8. Add the suffix “RLR” and “Style” to the device title, i.e.MPS3904RLRA. This will be a standard MPS3904 radial taped andsupplied on a reel per Figure 9.Fan Fold Box Information — Minimum order quantity 1 Box/$200LL.

Order in increments of 2000.Reel Information — Minimum order quantity 1 Reel/$200LL.Reel Information — Order in increments of 2000.

US/European Suffix Conversions

US EUROPE

RLRA RL

RLRE RL1

RLRM ZL1

TO–92RADIALTAPE IN

FAN FOLDBOX ORON REEL



TO–92 EIA RADIAL TAPE IN FAN FOLD BOX OR ON REEL

H2A H2A

H

F1F2

P2 P2

P1P

D

WW1

L1

W2

H2B H2B

T1

T

T2

H4 H5

H1

L

Figure 1. Device Positioning on Tape

Specification

Inches Millimeter

Symbol Item Min Max Min Max

D Tape Feedhole Diameter 0.1496 0.1653 3.8 4.2

D2 Component Lead Thickness Dimension 0.015 0.020 0.38 0.51

F1, F2 Component Lead Pitch 0.0945 0.110 2.4 2.8

H Bottom of Component to Seating Plane .059 .156 1.5 4.0

H1 Feedhole Location 0.3346 0.3741 8.5 9.5

H2A Deflection Left or Right 0 0.039 0 1.0

H2B Deflection Front or Rear 0 0.051 0 1.0

H4 Feedhole to Bottom of Component 0.7086 0.768 18 19.5

H5 Feedhole to Seating Plane 0.610 0.649 15.5 16.5

L Defective Unit Clipped Dimension 0.3346 0.433 8.5 11

L1 Lead Wire Enclosure 0.09842 — 2.5 —

P Feedhole Pitch 0.4921 0.5079 12.5 12.9

P1 Feedhole Center to Center Lead 0.2342 0.2658 5.95 6.75

P2 First Lead Spacing Dimension 0.1397 0.1556 3.55 3.95

T Adhesive Tape Thickness 0.06 0.08 0.15 0.20

T1 Overall Taped Package Thickness — 0.0567 — 1.44

T2 Carrier Strip Thickness 0.014 0.027 0.35 0.65

W Carrier Strip Width 0.6889 0.7481 17.5 19

W1 Adhesive Tape Width 0.2165 0.2841 5.5 6.3

W2 Adhesive Tape Position .0059 0.01968 .15 0.5

NOTES:1. Maximum alignment deviation between leads not to be greater than 0.2 mm.2. Defective components shall be clipped from the carrier tape such that the remaining protrusion (L) does not exceed a maximum of 11 mm.3. Component lead to tape adhesion must meet the pull test requirements established in Figures 5, 6 and 7.4. Maximum non–cumulative variation between tape feed holes shall not exceed 1 mm in 20 pitches.5. Holddown tape not to extend beyond the edge(s) of carrier tape and there shall be no exposure of adhesive.6. No more than 1 consecutive missing component is permitted.7. A tape trailer and leader, having at least three feed holes is required before the first and after the last component.8. Splices will not interfere with the sprocket feed holes.



ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ

ADHESIVE TAPE ONTOP SIDE

FLAT SIDE

CARRIERSTRIP

FLAT SIDE OF TRANSISTORAND ADHESIVE TAPE VISIBLE.

ADHESIVE TAPE ONTOP SIDE

ROUNDED SIDECARRIERSTRIP

ROUNDED SIDE OF TRANSISTOR ANDADHESIVE TAPE VISIBLE.

252 mm

9.92”

58 mm

2.28”MAX

MAX

13”MAX

330 mm

Style M fan fold box is equivalent to styles E andF of reel pack dependent on feed orientation frombox.

Style P fan fold box is equivalent to styles A andB of reel pack dependent on feed orientation frombox.

100 GRAMPULL FORCE

16 mm

HOLDINGFIXTURE HOLDING

FIXTURE

HOLDINGFIXTURE

16 mm

70 GRAMPULL FORCE

500 GRAM PULL FORCE

The component shall not pull free with a 300 gramload applied to the leads for 3 ± 1 second.

The component shall not pull free with a 70 gramload applied to the leads for 3 ± 1 second.

There shall be no deviation in the leads andno component leads shall be pulled free ofthe tape with a 500 gram load applied to thecomponent body for 3 ± 1 second.

Figure 2. Style M Figure 3. Style P Figure 4. Fan Fold Box Dimensions

Figure 5. Test #1 Figure 6. Test #2 Figure 7. Test #3

ADHESION PULL TESTS

FAN FOLD BOX STYLES




REEL STYLES

ARBOR HOLE DIA.30.5mm ± 0.25mm

MARKING NOTE

RECESS DEPTH9.5mm MIN

48 mmMAX

CORE DIA.82mm ± 1mm

HUB RECESS76.2mm ± 1mm

365mm + 3, – 0mm

38.1mm ± 1mm

Material used must not cause deterioration of components or degrade lead solderability

CARRIER STRIP

ADHESIVE TAPE

ROUNDEDSIDE

FEED

Rounded side of transistor and adhesive tape visible.

ADHESIVE TAPE ON REVERSE SIDE

CARRIER STRIPFLAT SIDE

FEED

Flat side of transistor and carrier strip visible(adhesive tape on reverse side).

CARRIER STRIP

ADHESIVE TAPEFLAT SIDE

FEED

Flat side of transistor and adhesive tape visible. Rounded side of transistor and carrier strip visible(adhesive tape on reverse side).

FEED

ADHESIVE TAPE ON REVERSE SIDE

CARRIER STRIP ROUNDEDSIDE

Figure 8. Reel Specifications

Figure 9. Style A Figure 10. Style B

Figure 11. Style E Figure 12. Style F

5–1

Outline Dimensionsand Leadform Options

Outline Dimensions and Leadform Options5–2


Outline Dimensions

STYLE 16:PIN 1. ANODE

2. GATE3. CATHODE

NOTES:1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.2. CONTROLLING DIMENSION: INCH.3. CONTOUR OF PACKAGE BEYOND DIMENSION R

IS UNCONTROLLED.4. DIMENSION F APPLIES BETWEEN P AND L.

DIMENSION D AND J APPLY BETWEEN L AND KMINIMUM. LEAD DIMENSION IS UNCONTROLLEDIN P AND BEYOND DIMENSION K MINIMUM.

STYLE 12:PIN 1. MAIN TERMINAL 1

2. GATE3. MAIN TERMINAL 2

STYLE 3:PIN 1. ANODE

2. ANODE3. CATHODE

STYLE 9:PIN 1. BASE 1

2. EMITTER3. BASE 2

STYLE 10:PIN 1. CATHODE

2. GATE3. ANODE

R

A

P

J

LF

B

K

GH

SECTION X–X

CV

D

N

N

X X

SEATINGPLANE

DIM MIN MAX MIN MAXMILLIMETERSINCHES

A 0.175 0.205 4.45 5.20B 0.170 0.210 4.32 5.33C 0.125 0.165 3.18 4.19D 0.016 0.022 0.41 0.55F 0.016 0.019 0.41 0.48G 0.045 0.055 1.15 1.39H 0.095 0.105 2.42 2.66J 0.015 0.020 0.39 0.50K 0.500 ––– 12.70 –––L 0.250 ––– 6.35 –––N 0.080 0.105 2.04 2.66P ––– 0.100 ––– 2.54R 0.115 ––– 2.93 –––V 0.135 ––– 3.43 –––

1

CASE 29–04TO–226AA (TO-92)

STYLES 3, 9, 10, 12, 16

NOTES:1. POLARITY DENOTED BY CATHODE BAND.2. LEAD DIAMETER NOT CONTROLLED WITHIN F

DIMENSION.

K

A

DK

B

DIM MIN MAX MIN MAXINCHESMILLIMETERS

A 5.97 6.60 0.235 0.260B 2.79 3.05 0.110 0.120D 0.76 0.86 0.030 0.034K 27.94 ––– 1.100 –––


Y14.5M, 1982.2. CONTROLLING DIMENSION: INCH.


2. ANODE3. GATE

STYLE 5:PIN 1. MT 1

2. MT 23. GATE

–B–

–A–M

K

F C

Q

H

VG

S

D

JR

U

1 32

2 PL

MAM0.25 (0.010) B M

MAM0.25 (0.010) B M


A 0.425 0.435 10.80 11.04B 0.295 0.305 7.50 7.74C 0.095 0.105 2.42 2.66D 0.020 0.026 0.51 0.66F 0.115 0.130 2.93 3.30G 0.094 BSC 2.39 BSCH 0.050 0.095 1.27 2.41J 0.015 0.025 0.39 0.63K 0.575 0.655 14.61 16.63M 5 TYP 5 TYPQ 0.148 0.158 3.76 4.01R 0.045 0.055 1.15 1.39S 0.025 0.035 0.64 0.88U 0.145 0.155 3.69 3.93V 0.040 ––– 1.02 –––

CASE 59–04DO–41

CASE 77–08TO–225AA

(Formerly TO-126 )STYLES 2, 5

5–3Outline Dimensions and Leadform OptionsMotorola Thyristor Device Data

OUTLINE DIMENSIONS—continued

CASE 221A–04TO–220AB

STYLES 3, 4

CASE 221A–06TO–220AB

STYLES 3, 4

CASE 221C–02STYLES 2, 3


Y14.5M, 1982.2. CONTROLLING DIMENSION: INCH.3. DIMENSION Z DEFINES A ZONE WHERE ALL

BODY AND LEAD IRREGULARITIES AREALLOWED.


A 0.570 0.620 14.48 15.75B 0.380 0.405 9.66 10.28C 0.160 0.190 4.07 4.82D 0.025 0.035 0.64 0.88F 0.142 0.147 3.61 3.73G 0.095 0.105 2.42 2.66H 0.110 0.155 2.80 3.93J 0.014 0.022 0.36 0.55K 0.500 0.562 12.70 14.27L 0.045 0.055 1.15 1.39N 0.190 0.210 4.83 5.33Q 0.100 0.120 2.54 3.04R 0.080 0.110 2.04 2.79S 0.045 0.055 1.15 1.39T 0.235 0.255 5.97 6.47U 0.000 0.050 0.00 1.27V 0.045 ––– 1.15 –––Z ––– 0.080 ––– 2.04

A

K

L

V

GD

N

Z

H

Q

FB

1 2 3

4

–T– SEATINGPLANE

S

R

J

U

TC


2. ANODE3. GATE4. ANODE


2. MAIN TERMINAL 23. GATE4. MAIN TERMINAL 2


Y14.5M, 1982.2. CONTROLLING DIMENSION: INCH.3. DIMENSION Z DEFINES A ZONE WHERE ALL

BODY AND LEAD IRREGULARITIES AREALLOWED.


A 0.570 0.620 14.48 15.75B 0.380 0.405 9.66 10.28C 0.160 0.190 4.07 4.82D 0.025 0.035 0.64 0.88F 0.142 0.147 3.61 3.73G 0.095 0.105 2.42 2.66H 0.110 0.155 2.80 3.93J 0.018 0.025 0.46 0.64K 0.500 0.562 12.70 14.27L 0.045 0.060 1.15 1.52N 0.190 0.210 4.83 5.33Q 0.100 0.120 2.54 3.04R 0.080 0.110 2.04 2.79S 0.045 0.055 1.15 1.39T 0.235 0.255 5.97 6.47U 0.000 0.050 0.00 1.27V 0.045 ––– 1.15 –––Z ––– 0.080 ––– 2.04

B

Q

H

Z

L

V

G

N

A

K

F

1 2 3

4

D

SEATINGPLANE–T–

CST

U

R

J




2. MAIN TERMINAL 23. GATE4. MAIN TERMINAL 2

1 2 3


Y14.5M, 1982.2. CONTROLLING DIMENSION: INCH.3. LEAD DIMENSIONS UNCONTROLLED WITHIN

DIMENSION Z.


2. ANODE3. GATE

STYLE 3:PIN 1. MT 1

2. MT 23. GATE

–Y–

–B––T–

Q

P

A

K

H

Z

G

L

F

D 3 PL

MBM0.25 (0.010) Y

E

NS

J

R

C

SEATINGPLANE


A 0.680 0.700 17.28 17.78B 0.388 0.408 9.86 10.36C 0.175 0.195 4.45 4.95D 0.025 0.040 0.64 1.01E 0.340 0.355 8.64 9.01F 0.140 0.150 3.56 3.81G 0.100 BSC 2.54 BSCH 0.110 0.155 2.80 3.93J 0.018 0.028 0.46 0.71K 0.500 0.550 12.70 13.97L 0.045 0.070 1.15 1.77N 0.049 ––– 1.25 –––P 0.270 0.290 6.86 7.36Q 0.480 0.500 12.20 12.70R 0.090 0.120 2.29 3.04S 0.105 0.115 2.67 2.92Z 0.070 0.090 1.78 2.28




CASE 267–03

CASE 318E–04SOT–223

STYLES 10. 11

CASE 369–07STYLE 5



STYLE 11:PIN 1. MT 1

2. MT 23. GATE4. MT 2

H

S

FA

B

D

GL

4

1 2 3

0.08 (0003)

C

MK

J

DIMA

MIN MAX MIN MAXMILLIMETERS

0.249 0.263 6.30 6.70

INCHES

B 0.130 0.145 3.30 3.70C 0.060 0.068 1.50 1.75D 0.024 0.035 0.60 0.89F 0.115 0.126 2.90 3.20G 0.087 0.094 2.20 2.40H 0.0008 0.0040 0.020 0.100J 0.009 0.014 0.24 0.35K 0.060 0.078 1.50 2.00L 0.033 0.041 0.85 1.05M 0 10 0 10 S 0.264 0.287 6.70 7.30





STYLE 5:PIN 1. GATE

2. ANODE3. CATHODE4. ANODE

1 2 3

4

V

S

A

K–T–

SEATINGPLANE

R

B

F

GD 3 PL

M0.13 (0.005) T

C

E

JH


A 0.235 0.250 5.97 6.35B 0.250 0.265 6.35 6.73C 0.086 0.094 2.19 2.38D 0.027 0.035 0.69 0.88E 0.033 0.040 0.84 1.01F 0.037 0.047 0.94 1.19G 0.090 BSC 2.29 BSCH 0.034 0.040 0.87 1.01J 0.018 0.023 0.46 0.58K 0.350 0.380 8.89 9.65R 0.175 0.215 4.45 5.46S 0.050 0.090 1.27 2.28V 0.030 0.050 0.77 1.27


Y14.5M, 1982.2. CONTROLLING DIMENSION: INCH.1

2

K

A

K

D

B


A 0.370 0.380 9.40 9.65B 0.190 0.210 4.83 5.33D 0.048 0.052 1.22 1.32K 1.000 ––– 25.40 –––



CASE 369A–13STYLE 5

CASE 416A–01

STYLE 5:PIN 1. GATE

2. ANODE3. CATHODE4. ANODE

D

A

K

B

RV

S

FL

G

2 PL

M0.13 (0.005) T

E

C

U

J

H

–T– SEATINGPLANE

Z


A 0.235 0.250 5.97 6.35B 0.250 0.265 6.35 6.73C 0.086 0.094 2.19 2.38D 0.027 0.035 0.69 0.88E 0.033 0.040 0.84 1.01F 0.037 0.047 0.94 1.19G 0.180 BSC 4.58 BSCH 0.034 0.040 0.87 1.01J 0.018 0.023 0.46 0.58K 0.102 0.114 2.60 2.89L 0.090 BSC 2.29 BSCR 0.175 0.215 4.45 5.46S 0.020 0.050 0.51 1.27U 0.020 ––– 0.51 –––V 0.030 0.050 0.77 1.27Z 0.138 ––– 3.51 –––



1 2 3

4


A 0.110 0.120 2.79 3.05B 0.110 0.120 2.79 3.05C 0.072 0.080 1.83 2.03E 0.006 0.010 0.15 0.25M ––– 4 ––– 4 N 0.073 0.077 1.85 1.96P ––– 0.130 ––– 3.30R 0.065 0.070 1.65 1.78


Y14.5M, 1982.2. CONTROLLING DIMENSION: INCH.3. DIMENSION M AND P MAXIMUM MISALIGNMENT

OF HALFS.

B N R

M

P

N

R

NOTE 3

NOTE 3

–T–0.0127 (0.0005) T

C

A

E



Leadform Options — TO-92 (Case 29) & TO-225AA (Case 77)Plastic packaged semiconductors may be leadformed to a

variety of configurations for insertion into sockets or circuitboards. Leadform options require assignment of a specialpart number before ordering. To order leadformed product,determine the desired leadform, the case number and

applicable leadform number, then contact your local Motorolarepresentative for the special part number and pricing.Leadform orders require a minimum order quantity and arenon-cancellable after processing.

CASE 29LEADFORM 18*

(TO-92 to fit TO-18)

CASE 29LEADFORM 5*

(TO-92 to fit TO-5)

CASE 77LEADFORM VA

CASE 77LEADFORM VB

MOUNTING SURFACE0.100

0.50030° REF.

0.093Typ.

0.018 DIA.

0.200 DIA.PIN CIRCLE

0.5870.593 0.180

0.140

0.250

0.030

0.010 0.090 RAD.

0.150

12

30.100

0.5870.593 0.180

0.140REF.

0.100DIA.

12

3

0.0130.003

RAD.

0.0950.085

0.0550.045

RAD.

5° Typ.

0.2550.285

0.8800.828

0.9270.867

0.0190.01

0.2800.250


TO-92 & TO-225AA Leadform Options (continued)

CASE 77LEADFORM VD

CASE 77LEADFORM VE

CASE 77LEADFORM VK

CASE 77LEADFORM VL

UNDERSIDEOF LEAD

BOTTOM OFHEATSINK

.050 REF.

0.100 ± .01

0.387 ± .01

0.608 ± .010

0.140± .010

UNDERSIDEOF LEAD

BOTTOM OFHEATSINK

0.050 REF.

0.190 MIN

0.680 ± .0150.575 ± .015

0.350 MAX.

CL CL

0.02R ± .005 TYP.

0.094 TYP.

UNDERSIDEOF LEAD

BOTTOM OFHEATSINK

.050 REF.

0.472 ± .0150.497 ± .005

.050 REF.

UNDERSIDEOF LEAD

BOTTOM OFHEATSINK



TO-92 & TO-225AA Leadform Options (continued)

CASE 77LEADFORM VS

UNDERSIDEOF LEAD

BOTTOM OFHEATSINK

0.050 REF.

0.740MIN. 0.840 MIN.

0.278REF.

0.200 ± .01

0.018 RAW LEAD (REF.)

30°REF.

0.180 ± .03

CASE 77LEADFORM VP

MOUNTING SURFACE(Metal)

0.220± .005

0.500 ± .0050.330 ± .005CL CL

0.025 RMAX. TYP.

0.340± .005 0.510

± .005

0.050 MAX.


Leadform Options — TO-220 (Case 221A)

Leadform options require assignment of a special part number before ordering.Contact your local Motorola representative for special part number and pricing.10,000 piece minimum quantity orders are required.Leadform orders are non-cancellable after processing.Leadforms apply to both Motorola Case 221A-04 and 221A-06 except as noted.

•••••

.950 MIN.

LEADFORM BCLEADFORM AS

.100 REF..20 REF.

.620 ± .015

.125 ± .010

0.100 TYP.0.750 MAX.

0.100 TYP.

MOUNTINGSURFACE

1.00 MIN.

0.040 RAD± 0.015

LEADFORM AN

.736 ± .010

MOUNTINGSURFACE

.285 0.020

.380 .02

.240 0.015

.186 .03

.580± .010



TO-220 Leadform Options (continued)

LEADFORM BL

LEADFORM BA

CASE

221A-04

221A-06

A

0.220 Min.

0.190 Min.

B

0.325 Min.

0.290 Min.

LEADFORM AK

LEADFORM AF

MOUNTINGSURFACE

0.020 RAD.TYP.

.500± .02

.600± 0.015

UNDERSIDEOF LEAD

MOUNTINGSURFACE

.095 + .010

.015

.015

.025 RMAX

.050 REF.

.200 REF.

.100 REF.

MOUNTINGSURFACE

.040 MIN.

.150 MIN

.100 REF

.200 REF

.032 REF

.050 REF

.06 R

LEADCL0.018 .005

.660± .02 .557

(REF.)

0.100 TYP.±0.020

0.5860.616

0.100TYP.

CASE

221A-04

221A-06

A

0.325 Min.

0.290 Min.

.017REF

.140 .010

.590 .010 .775

0.015

A

AB



LEADFORM AU

LEADFORM 3 LEADS

.190 ± .020

.095 REF.

LEADFORM BG

0.620 REF.0.780 ± 0.015

LEADFORM AJ

CASE

221A-04

221A-06

A

0.360 ± 0.010

Lead Not Trimmed0.300 Min.

.100 REF.

.200 REF.

.050 REF..032 REF.

.06 R

LEADFORM BS

0.080± 0.015

0.607± 0.015

0.325± 0.020

CASE

221A-04

221A-06

A

0.920 Min.

0.885 Min.

0.296 0.020

A

.574 .01

A

.765 .01

.580 .010

.017 .004




LEADFORM BU

UNDERSIDEOF LEAD

MOUNTINGSURFACE

.094 ± .01.005 ± .005

.102 ± .003

.680 ± .005 0.005± 0.005

0.102 ± 0.005

0.680 ± 0.005

.223± .010

.100 REF..800 ± .0503 LEADS

LEADFORM BD LEADFORM DW

LEADFORM BV

.610 .010

.20 REF.

.735 .010

6–1

Index andCross Reference

IndustryPart Number

MotorolaNearest

Replacement

MotorolaSimilar

ReplacementPage

NumberIndustry

Part Number

MotorolaNearest

Replacement

MotorolaSimilar

ReplacementPage

Number

Index and Cross Reference6–2


Index and Cross ReferenceThe following table represents a cross-reference guide for all Thyristor devices which are manufactured by Motorola. Where

the Motorola part number differs from the Industry part number, the Motorola device is a “form, fit and function” replacement forthe Industry part number; however, some differences in characteristics and/or specifications may exist.

2N1601 MCR12D 3–1412N1602 MCR12D 3–1412N1603 MCR12D 3–1412N1604 MCR12D 3–1412N1770 MCR12D 3–1412N1771 MCR12D 3–1412N1771A MCR12D 3–141

2N1772 MCR12D 3–1412N1772A MCR12D 3–1412N1773 MCR12D 3–1412N1773A MCR12D 3–1412N1774 MCR12D 3–1412N1774A MCR12D 3–1412N1775 MCR12D 3–141

2N1775A MCR12D 3–1412N1776 MCR12D 3–1412N1776A MCR12D 3–1412N1777 MCR12D 3–1412N1777A MCR12D 3–1412N1778 MCR12M 3–1412N1778A MCR12M 3–141

2N2575 2N6505 3–262N2576 2N6507 3–262N2679 MCR102 3–1562N2680 MCR103 3–1562N2682 MCR100–4 3–1542N2683 MCR102 3–1562N2684 MCR103 3–156

2N2685 MCR100–3 3–1542N2686 MCR100–4 3–1542N2687 MCR102 3–1562N2688 MCR103 3–1562N2689 MCR100–3 3–1542N2690 MCR100–4 3–1542N2919 MCR12M 3–141

2N3001 MCR102 3–1562N3002 MCR103 3–1562N3003 MCR100–3 3–1542N3004 MCR100–4 3–1542N3005 MCR102 3–1562N3006 MCR103 3–1562N3007 MCR100–3 3–154

2N3008 MCR100–4 3–1542N3027 MCR102 3–1562N3028 MCR103 3–1562N3029 MCR100–3 3–1542N3030 MCR102 3–1562N3031 MCR103 3–1562N3032 MCR100–3 3–154

2N3228 S2800B 3–1932N3254 MCR102 3–1562N3255 MCR102 3–1562N3256 MCR103 3–1562N3257 MCR102 3–1562N3258 MCR102 3–1562N3259 MCR103 3–156

2N3269 MCR12D 3–1412N3270 MCR12D 3–1412N3271 MCR12D 3–1412N3272 MCR12D 3–1412N3668 2N6506 3–262N3669 2N6506 3–262N3936 MCR12D 3–141

2N3937 MCR12D 3–1412N3938 MCR12D 3–1412N3939 MCR12D 3–1412N3940 MCR12M 3–1412N4096 MCR103 3–1562N4097 MCR100–3 3–1542N4098 MCR100–4 3–154

2N4101 S2800M 3–1932N4102 S2800M 3–1932N4103 2N6508 3–262N4108 MCR103 3–1562N4109 MCR100–3 3–1542N4110 MCR100–4 3–1542N4144 MCR102 3–156

2N4145 MCR102 3–1562N4147 MCR103 3–1562N4148 MCR100–3 3–1542N4149 MCR100–4 3–1542N4167 MCR12D 3–1412N4168 MCR12D 3–1412N4169 MCR12D 3–141

2N4170 MCR12D 3–1412N4171 MCR12D 3–1412N4172 MCR12D 3–1412N4173 MCR12M 3–1412N4174 MCR12M 3–1412N4183 MCR12D 3–1412N4184 MCR12D 3–141

2N4185 MCR12D 3–1412N4186 MCR12D 3–1412N4187 MCR12D 3–1412N4188 MCR12D 3–1412N4189 MCR12M 3–1412N4190 MCR12M 3–1412N4332 MCR102 3–156

2N4333 MCR103 3–1562N4334 MCR100–3 3–1542N4335 MCR100–4 3–1542N4336 MCR100–4 3–1542N4441 MCR218–2 3–1612N4442 MCR218–4 3–1612N4443 MCR218–6 3–161

2N4444 MCR218–8 3–1612N5060 2N5060 3–22N5061 2N5061 3–22N5062 2N5062 3–22N5064 2N5064 3–22N5722 MCR100–6 3–1542N5724 MCR103 3–156

2N5725 MCR100–3 3–1542N5726 MCR100–4 3–1542N5754 2N6071 3–102N5755 2N6071 3–102N5756 2N6073 3–102N5757 2N6073 3–102N6027 2N6027 3–6

2N6028 2N6028 3–62N6068 2N6071 3–102N6068A 2N6071A 3–102N6069 2N6071 3–102N6069A 2N6071A 3–102N6070 2N6071 3–102N6070A 2N6071A 3–10

IndustryPart Number

MotorolaNearest

Replacement

MotorolaSimilar

ReplacementPage

NumberIndustry

Part Number

MotorolaNearest

Replacement

MotorolaSimilar

ReplacementPage

Number

6–3Index and Cross ReferenceMotorola Thyristor Device Data

2N6071 2N6071 3–102N6071A 2N6071A 3–102N6072 2N6073 3–102N6072A 2N6073A 3–102N6073 2N6073 3–102N6073A 2N6073A 3–102N6074B 2N6075B 3–10

2N6075 2N6075 3–102N6075B 2N6075B 3–102N6151 MAC210A4 3–752N6152 MAC210A6 3–752N6153 MAC210A8 3–752N6154 MAC210A4 3–752N6155 MAC210A6 3–75

2N6156 MAC210A8 3–752N6234 2N6238 3–152N6235 2N6238 3–152N6236 2N6237 3–152N6237 2N6237 3–152N6238 2N6238 3–152N6239 2N6239 3–15

2N6240 2N6240 3–152N6241 2N6241 3–152N6342 2N6342 3–182N6342A 2N6344 3–222N6343 2N6343 3–182N6343 MAC9D 3–492N6343A MAC12D 3–53

2N6344 2N6344 3–182N6344 MAC9M 3–492N6344A MAC12D 3–532N6345 2N6345 3–182N6345 MAC9N 3–492N6345A 2N6345A MAC12M 3–532N6346 2N6346 3–18

2N6346A 2N6346A 3–222N6347 2N6347 3–182N6347A 2N6347A 3–222N6348 2N6348 3–182N6348A 2N6348A 3–222N6349 2N6349 3–182N6349A 2N6349A 3–22

2N6394 MCR12D 3–1412N6395 MCR12D 3–1412N6396 MCR12D 3–1412N6397 MCR12D 3–1412N6397 MCR12D 3–1412N6398 MCR12M 3–1412N6398 MCR12M 3–141

2N6399 MCR12N 3–1412N6399 MCR12N 3–1412N6400 MCR16D 3–1432N6401 MCR16D 3–1432N6402 MCR16D 3–1432N6403 MCR16D 3–1432N6403 MCR16D 3–143

2N6404 MCR16M 3–1432N6404 MCR16M 3–1432N6405 MCR16N 3–1432N6405 MCR16N 3–1432N6504 2N6504 3–262N6505 2N6505 3–262N6506 2N6506 3–26

2N6507 2N6507 3–262N6508 2N6508 3–262N6509 2N6509 3–262N877 MCR102 3–1562N878 MCR103 3–1562N879 MCR100–3 3–1542N880 MCR100–4 3–154

2N881 MCR100–4 3–1542N884 MCR102 3–1562N885 MCR102 3–1562N886 MCR103 3–1562N887 MCR100–3 3–1542N888 MCR100–4 3–1542N889 MCR100–4 3–154

2N948 MCR102 3–1562N949 MCR103 3–1562N950 MCR100–3 3–154BRB10–400B MAC12D 3–53BRX44 BRX44 3–30BRX45 BRX45 3–30BRX46 BRX46 3–30

BRX47 BRX47 3–30BRX49 BRX49 3–30BRY55M–300 BRY55–400 3–32BRY55M–400 BRY55–400 3–32BRY55M–600 BRY55–600 3–32BRY55–100 BRY55–100 3–32BRY55–200 BRY55–200 3–32

BRY55–30 BRY55–30 3–32BRY55–400 BRY55–400 3–32BRY55–500 BRY55–500 3–32BRY55–60 BRY55–60 3–32BRY55–600 BRY55–600 3–32BT137G–600 MAC9M 3–49BT137G–800 MAC9N 3–49

BT137G400 MAC9D 3–49BT137–500E MAC228A8 3–106BT137–500F T2800M 3–201BT137–500G MAC228A8 3–106BT137–600E MAC228A8 3–106BT137–600F T2800M 3–201BT137–600G MAC228A8 3–106

BT137–800E MAC228A10 3–106BT137–800G MAC228A10 3–106BT138–500G 2N6348A 3–22BT138–600G 2N6348A 3–22BT139G–400 MAC16D 3–67BT139G–600 MAC16M 3–67BT139G–800 MAC16N 3–67

BT149A 2N5062 3–2BT149B 2N5064 3–2BT149D MCR100–6 3–154BT149E MCR100–8 3–154BT149F 2N5061 3–2BT149M MCR100–8 3–154BT151–500R MCR12M 3–141

BT151–650R MCR12N 3–141BT151–800A MCR12N 3–141BT152–400R 2N6507 3–26BT152–600R 2N6508 3–26BT152–800R 2N6509 3–26BT153 MCR218–8 3–161BTA04–200A T2500BFP 3–199

BTA04–400A T2500DFP 3–199BTA04–600A T2500MFP 3–199BTA04–800A T2500NFP 3–199BTA06–200A T2500BFP 3–199BTA06–200C T2500BFP 3–199BTA06–400A T2500DFP 3–199BTA06–400C T2500DFP 3–199

BTA06–600A T2500MFP 3–199BTA06–600C T2500MFP 3–199BTA06–800A T2500NFP 3–199BTA06–800C T2500NFP 3–199BTA08–200A MAC229A4FP 3–112BTA08–200C MAC229A4FP 3–112BTA08–400A MAC229A6FP 3–112

IndustryPart Number

MotorolaNearest

Replacement

MotorolaSimilar

ReplacementPage

NumberIndustry

Part Number

MotorolaNearest

Replacement

MotorolaSimilar

ReplacementPage

Number



BTA08–400C MAC229A6FP 3–112BTA08–600A MAC229A8FP 3–112BTA08–600C MAC229A8FP 3–112BTA08–800A MAC229A10FP 3–112BTA08–800C MAC229A10FP 3–112BTA10–200B MAC210A4FP 3–79BTA10–200C MAC210A4FP 3–79

BTA10–400B MAC210A6FP 3–79BTA10–400C MAC210A6FP 3–79BTA10–600B MAC210A8FP 3–79BTA10–600C MAC210A8FP 3–79BTA10–800B MAC210A10FP 3–79BTA10–800C MAC210A10FP 3–79BTA12–200B MAC212A4FP 3–87

BTA12–200C MAC212A4FP 3–87BTA12–400B MAC212A6FP 3–87BTA12–400C MAC212A6FP 3–87BTA12–600B MAC212A8FP 3–87BTA12–600C MAC212A8FP 3–87BTA12–800B MAC212A10FP 3–87BTA12–800C MAC212A10FP 3–87

BTA16–200B MAC320A4FP 3–120BTA16–200C MAC320A4FP 3–120BTA16–400B MAC320A6FP 3–120BTA16–400C MAC320A6FP 3–120BTA16–600B MAC320A8FP 3–120BTA16–600C MAC320A8FP 3–120BTA16–800B MAC320A10FP 3–120

BTA16–800C MAC320A10FP 3–120BTA20C T2801D MAC9D 3–49BTA20D T2801D MAC9D 3–49BTA20E T2801M MAC9M 3–49BTA21C MAC9D 3–49BTA21D MAC9D 3–49BTA21E MAC9M 3–49

BTA22B MAC12D 3–53BTA22C MAC12D 3–53BTA22D MAC12D 3–53BTA22E MAC12M 3–53BTA22M MAC12M 3–53BTA23B 2N6346A 3–22BTA23C 2N6347A 3–22

BTA23D 2N6347A 3–22BTA23E 2N6348A 3–22BTA23M 2N6348A 3–22BTB06–200B MAC9D 3–49BTB06–400B MAC9D 3–49BTB06–700B MAC9N 3–49BTB08–400BW MAC9D 3–49

BTB08–400CW MAC9D 3–49BTB08–600BW MAC9M 3–49BTB08–600CW MAC9M 3–49BTB08–800BW MAC9N 3–49BTB08–800CW MAC9N 3–49BTB08–200C MAC229A4 3–110BTB08–200S MAC228A4 3–106

BTB08–400C MAC229A6 3–110BTB08–400S MAC228A6 3–106BTB08–700S MAC228A10 3–106BTB08–800C MAC229A10 3–110BTB10–200B MAC12D 3–53BTB10–200C MAC310A4 3–114BTB10–400C MAC310A6 3–114

BTB10–600C MAC310A8 3–114BTB10–700B MAC12N 3–53BTB10–800C MAC210A10 3–75BTB12–200B MAC212A4 3–83BTB12–200C MAC310A4 3–114BTB12–400B MAC212A6 3–83BTB12–400C MAC310A6 3–114

BTB12–600B MAC212A8 3–83BTB12–600C MAC310A8 3–114BTB12–800B MAC212A10 3–83BTB16–400BW MAC15D 3–55BTB16–400CW MAC15D 3–55BTB16–600BW MAC15M 3–55BTB16–600CW MAC15M 3–55

BTB16–800BW MAC15N 3–55BTB16–800CW MAC15N 3–55BTB16–200B MAC320A4 3–116BTB16–400B MAC320A6 3–116BTB16–600B MAC320A8 3–116BTB16–800B MAC320A10 3–116BTB24–200B MAC223A4FP 3–100

BTB24–400B MAC223A6FP 3–100BTB24–600B MAC223A8FP 3–100BTB24–800B MAC223A10FP 3–100C103A 2N5062 3–2C103B 2N5064 3–2C103Y 2N5060 3–2C103YY 2N5061 3–2

C106A C106A 3–34C106B C106B 3–34C106D C106D 3–34C106E C106M 3–34C106E1 C106M 3–34C106E2 C106M 3–34C106F C106F 3–34

C106M C106M 3–34C106M1 C106M 3–34C106M2 C106M 3–34C106M41 C106M 3–34C106N C106M 3–34C106Q1 C106M 3–34C106Q11 C106M 3–34

C106Q2 C106M 3–34C106Q21 C106M 3–34C106Q4 C106M 3–34C106S C106M 3–34C107E C106M 3–34C107M C106M 3–34C108A1 MCR106–2 3–158

C108B1 MCR106–4 3–158C108C1 MCR106–6 3–158C108D1 MCR106–6 3–158C108E1 MCR106–8 3–158C108M1 MCR106–8 3–158C108M2 MCR106–8 3–158C108Y1 MCR106–2 3–158

C10A MCR12D 3–141C10B MCR12D 3–141C10F MCR12D 3–141C10G MCR12D 3–141C10V MCR12D 3–141C11A MCR12D 3–141C11B MCR12D 3–141

C11C MCR12D 3–141C11D MCR12D 3–141C11E MCR12M 3–141C11F MCR12D 3–141C11G MCR12D 3–141C11H MCR12D 3–141C11M MCR12M 3–141

C11U MCR12D 3–141C122A C122A1 3–37C122B C122B1 3–37C122D C122D1 3–37C122D1 MCR8D 3–137C122F C122F1 3–37C122F1 MCR8D 3–137

IndustryPart Number

MotorolaNearest

Replacement

MotorolaSimilar

ReplacementPage

NumberIndustry

Part Number

MotorolaNearest

Replacement

MotorolaSimilar

ReplacementPage

Number


C122F1 C122F1 3–37C122M C122M1 3–37C122M1 MCR8M 3–137C122M1 C122M1 3–37C122N C122N1 3–37C122N1 MCR8N 3–137C122N1 C122N1 3–37

C122S C122N1 3–37C122S1 C122N1 3–37C126A MCR12D 3–141C126B MCR12D 3–141C126C MCR12D 3–141C126D MCR12D 3–141C126E MCR12M 3–141

C126F MCR12D 3–141C126M MCR12M 3–141C127A MCR16D 3–143C127B MCR16D 3–143C127C MCR16D 3–143C127D MCR16D 3–143C15B MCR12D 3–141

C15C MCR12D 3–141C15D MCR12D 3–141C15F MCR12D 3–141C15G MCR12D 3–141C15H MCR12D 3–141C20A MCR12D 3–141C20B MCR12D 3–141

C20C MCR12D 3–141C20D MCR12D 3–141C20F MCR12D 3–141C20U MCR12D 3–141EC103A 2N5062 3–2EC103A1 MCR22–3 3–145EC103A2 MCR22–3 3–145

EC103A3 MCR22–3 3–145EC103B MCR100–4 3–154EC103B MCR22–4 3–145EC103B1 MCR22–4 3–145EC103B3 MCR22–4 3–145EC103C MCR100–6 3–154EC103C1 MCR22–6 3–145

EC103C2 MCR22–6 3–145EC103C3 MCR22–6 3–145EC103D MCR100–6 3–154EC103D1 MCR22–6 3–145EC103D2 MCR22–6 3–145EC103D3 MCR22–6 3–145EC103E MCR22–8 3–145

EC103E1 MCR22–8 3–145EC103E2 MCR22–8 3–145EC103E3 MCR22–8 3–145EC103M MCR22–8 3–145EC103M1 MCR22–8 3–145EC103M2 MCR22–8 3–145EC103M3 MCR22–8 3–145

EC103Y MCR102 3–156EC103Y1 MCR22–2 3–145EC103Y2 MCR22–2 3–145EC103Y3 MCR22–2 3–145F0810BH MCR218–4 3–161F0810DH MCR218–6 3–161F0810MH MCR218–8 3–161

F0810NH MCR218–10 3–161F1612BH MCR12D 3–141F1612DH MCR12M 3–141F1612NH MCR12N 3–141L2001F71 2N6071A 3–10L2001F91 2N6071 3–10L2001L3 2N6071A 3–10

L2001L5 T2322B 3–195L2001L7 T2322B 3–195L2001L9 T2322B 3–195L2001M7 2N6071A 3–10L2001M9 2N6071 3–10L2003M3 2N6071A 3–10L2003M7 2N6071A 3–10

L2003M9 2N6071 3–10L2004F51 2N6071A 3–10L2004F71 2N6071 3–10L2004F91 2N6071 3–10L2004L5 2N6071A 3–10L2004L9 2N6071A 3–10L2006L6 MAC228A4 3–106

L2006L7 MAC228A4 3–106L2008L6 MAC228A4 3–106L2008L7 MAC228A4 3–106L2008L9 MAC228A4 3–106L200E3 MAC97A4 3–71L200E5 MAC97A4 3–71L200E7 MAC97–4 3–71

L200E9 MAC97–4 3–71L4001F71 2N6073A 3–10L4001F91 2N6073 3–10L4001L7 T2322D 3–195L4001L9 T2322D 3–195L4001M7 2N6073A 3–10L4001M9 2N6073 3–10

L4003M7 2N6073A 3–10L4003M9 2N6073 3–10L4004F51 2N6073A 3–10L4004F71 2N6073 3–10L4004F91 2N6073 3–10L4004L5 2N6073A 3–10L4004L7 2N6073A 3–10

L4004L9 2N6073A 3–10L4006L6 MAC228A6 3–106L4006L7 MAC228A6 3–106L4006L9 MAC228A6 3–106L4008L6 MAC228A6 3–106L4008L7 MAC228A6 3–106L4008L9 MAC228A6 3–106

L400E3 MAC97A6 3–71L400E5 MAC97A6 3–71L400E7 MAC97–6 3–71L400E9 MAC97–6 3–71MAC08BTI MAC08BTI 3–40MAC08DTI MAC08DTI 3–40MAC08MTI MAC08MTI 3–40

MAC10–4 MAC210A4 3–75MAC10–6 MAC210A6 3–75MAC10–8 MAC210A8 3–75MAC11–4 MAC210A4 3–75MAC11–6 MAC210A6 3–75MAC11–8 MAC210A8 3–75MAC137G500 MAC8D 3–45

MAC137G600 MAC8M 3–45MAC137G700 MAC8N 3–45MAC137G800 MAC8N 3–45MAC137–500 MAC9D 3–49MAC137–600 MAC9M 3–49MAC137–700 MAC9M 3–49MAC137–800 MAC9N 3–49

MAC15–10 MAC16N 3–67MAC15–6 MAC16D 3–67MAC15–8 MAC16M 3–67MAC154 MAC15–4 3–59MAC156 MAC15–6 3–59MAC15A10 MAC16N 3–67MAC15A10 MAC15A10 3–59

IndustryPart Number

MotorolaNearest

Replacement

MotorolaSimilar

ReplacementPage

NumberIndustry

Part Number

MotorolaNearest

Replacement

MotorolaSimilar

ReplacementPage

Number



MAC15A10FP MAC15A10FP 3–63MAC15A4 MAC16D 3–67MAC15A4FP MAC15A4FP 3–63MAC15A5 MAC15A6 3–59MAC15A6 MAC16D 3–67MAC15A6 MAC15A6 3–59MAC15A6FP MAC15A6FP 3–63

MAC15A7 MAC15A8 3–59MAC15A8 MAC16M 3–67MAC15A8 MAC15A8 3–59MAC15A8FP MAC15A8FP 3–63MAC15A9 MAC15A10 3–59MAC15–10 MAC15–10 3–59MAC15–10FP MAC15–10FP 3–63

MAC15–4 MAC16D 3–67MAC15–4 MAC15–4 3–59MAC15–4FP MAC15–4FP 3–63MAC15–5 MAC15–6 3–59MAC15–6 MAC15–6 3–59MAC15–6FP MAC15–6FP 3–63MAC15–8 MAC15–8 3–59

MAC15–8FP MAC15–8FP 3–63MAC15–9 MAC15–10 3–59MAC16–10 MAC16N 3–67MAC16–4 MAC16D 3–67MAC16–6 MAC16D 3–67MAC16–8 MAC16M 3–67MAC20A10 MAC15–10FP 3–63

MAC20A4 MAC15–4FP 3–63MAC20A5 MAC15–6FP 3–63MAC20A6 MAC15–6FP 3–63MAC20A7 MAC15–8FP 3–63MAC20A9 MAC15–8FP 3–63MAC20–10 MAC15–10FP 3–63MAC20–4 MAC15–4FP 3–63

MAC20–5 MAC15–6FP 3–63MAC20–6 MAC15–6FP 3–63MAC20–7 MAC15–8FP 3–63MAC20–8 MAC15–8FP 3–63MAC210A10 MAC210A10 3–75MAC210A10FP MAC210A10FP 3–79MAC210A4 MAC210A4 3–75

MAC210A4FP MAC210A4FP 3–79MAC210A5 MAC210A6 3–75MAC210A6 MAC210A6 3–75MAC210A6FP MAC210A6FP 3–79MAC210A7 MAC210A8 3–75MAC210A8 MAC210A8 3–75MAC210A8FP MAC210A8FP 3–79

MAC210A9 MAC210A10 3–75MAC210–10 MAC210–10 3–75MAC210–10FP MAC210–1OFP 3–79MAC210–4 MAC210–4 3–75MAC210–4FP MAC210–4FP 3–79MAC210–5 MAC210–6 3–75MAC210–6 MAC210–6 3–75

MAC210–6FP MAC210–6FP 3–79MAC210–7 MAC210–8 3–75MAC210–8 MAC210–8 3–75MAC210–8FP MAC210–8FP 3–79MAC210–9 MAC210–10 3–75MAC212A10 MAC212A10 3–83MAC212A10FP MAC212A10FP 3–87

MAC212A4 MAC212A4 3–83MAC212A4FP MAC212A4FP 3–87MAC212A6 MAC212A6 3–83MAC212A6FP MAC212A6FP 3–87MAC212A8 MAC212A8 3–83MAC212A8FP MAC212A8FP 3–87MAC212–10 MAC212–10 3–83

MAC212–10FP MAC212–10FP 3–87MAC212–4 MAC212–4 3–83MAC212–4FP MAC212–4FP 3–87MAC212–6 MAC212–6 3–83MAC212–6FP MAC212–6FP 3–87MAC212–8 MAC212–8 3–83MAC212–8FP MAC212–8FP 3–87

MAC213–10 MAC12N 3–53MAC213–4 MAC12D 3–53MAC213–6 MAC12D 3–53MAC213–8 MAC12M 3–53MAC218A10 MAC218A10 3–91MAC218A10FP MAC218A10FP 3–94MAC218A4 MAC218A4 3–91

MAC218A4FP MAC218A4FP 3–94MAC218A6 MAC218A6 3–91MAC218A6FP MAC218A6FP 3–94MAC218A8 MAC218A8 3–91MAC218A8FP MAC218A8FP 3–94MAC218–10 MAC218–10 3–91MAC218–10FP MAC218–10FP 3–94

MAC218–4 MAC218–4 3–91MAC218–4FP MAC218–4FP 3–94MAC218–6 MAC218–6 3–91MAC218–6FP MAC218–6FP 3–94MAC218–8 MAC218–8 3–91MAC218–8FP MAC218–8FP 3–94MAC219–10 MAC9N 3–49

MAC219–4 MAC9D 3–49MAC219–6 MAC9D 3–49MAC219–8 MAC9M 3–49MAC223A1 MAC223A4 3–97MAC223A10 MAC223A10 3–97MAC223A10FP MAC223A10FP 3–100MAC223A2 MAC223A4 3–97

MAC223A3 MAC223A4 3–97MAC223A4 MAC223A4 3–97MAC223A4FP MAC223A4FP 3–100MAC223A5 MAC223A6 3–97MAC223A6 MAC223A6 3–97MAC223A6FP MAC223A6FP 3–100MAC223A7 MAC223A8 3–97

MAC223A8 MAC223A8 3–97MAC223A8FP MAC223A8FP 3–100MAC223A9 MAC223A10 3–97MAC223–1 MAC223–4 3–97MAC223–10 MAC223–10 3–97MAC223–10FP MAC223–10FP 3–100MAC223–2 MAC223–4 3–97

MAC223–3 MAC223–4 3–97MAC223–4 MAC223–4 3–97MAC223–4FP MAC223–4FP 3–100MAC223–5 MAC223–6 3–97MAC223–6 MAC223–6 3–97MAC223–6FP MAC223–6FP 3–100MAC223–7 MAC223–8 3–97

MAC223–8 MAC223–8 3–97MAC223–8FP MAC223–8FP 3–100MAC223–9 MAC223–10 3–97MAC224A10 MAC224A10 3–103MAC224A4 MAC224A4 3–103MAC224A5 MAC224A6 3–103MAC224A6 MAC224A6 3–103

MAC224A7 MAC224A8 3–103MAC224A8 MAC224A8 3–103MAC224A9 MAC224A10 3–103MAC224–10 MAC224–10 3–103MAC224–4 MAC224–4 3–103MAC224–5 MAC224–6 3–103MAC224–6 MAC224–6 3–103

IndustryPart Number

MotorolaNearest

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Number


MAC224–7 MAC224–8 3–103MAC224–8 MAC224–8 3–103MAC224–9 MAC224–10 3–103MAC228A10 MAC228A10 3–106MAC228A10FP MAC228A10FP 3–108MAC228A2 MAC228A4 3–106MAC228A3 MAC228A4 3–106

MAC228A4 MAC228A4 3–106MAC228A4FP MAC228A4FP 3–108MAC228A5 MAC228A6 3–106MAC228A6 MAC228A6 3–106MAC228A6FP MAC228A6FP 3–108MAC228A7 MAC228A8 3–106MAC228A8 MAC228A8 3–106

MAC228A8FP MAC228A8FP 3–108MAC228A9 MAC228A10 3–106MAC228–10 MAC228–10 3–106MAC228–10FP MAC228–10FP 3–108MAC228–2 MAC228–4 3–106MAC228–3 MAC228–4 3–106MAC228–4 MAC228–4 3–106

MAC228–4FP MAC228–4FP 3–108MAC228–5 MAC228–6 3–106MAC228–6 MAC228–6 3–106MAC228–6FP MAC228–6FP 3–108MAC228–7 MAC228–8 3–106MAC228–8 MAC228–8 3–106MAC228–8FP MAC228–8FP 3–108

MAC228–9 MAC228–10 3–106MAC229A10 MAC229A10 3–110MAC229A10FP MAC229A10FP 3–112MAC229A4 MAC229A4 3–110MAC229A4FP MAC229A4FP 3–112MAC229A6 MAC229A6 3–110MAC229A6FP MAC229A6FP 3–112

MAC229A8FP MAC229A8FP 3–112MAC229–10 MAC229–10 3–110MAC229–10FP MAC229–10FP 3–112MAC229–4 MAC229–4 3–110MAC229–4FP MAC229–4FP 3–112MAC229–6 MAC229–6 3–110MAC229–6FP MAC229–6FP 3–112

MAC229–8 MAC229–8 3–110MAC229–8FP MAC229–8FP 3–112MAC25A10 MAC223–10FP 3–100MAC25A4 MAC223–4 3–97MAC25A9 MAC223–10FP 3–100MAC25–10 MAC223–10FP 3–100MAC25–9 MAC223–10FP 3–100

MAC310A4 MAC310A4 3–114MAC310A6 MAC310A6 3–114MAC310A8 MAC310A8 3–114MAC310–4 MAC310–4 3–114MAC310–6 MAC310–6 3–114MAC310–8 MAC310–8 3–114MAC320–10 MAC16N 3–67

MAC320–4 MAC16D 3–67MAC320–6 MAC16D 3–67MAC320–8 MAC16M 3–67MAC320A10 MAC16N 3–67MAC320A10 MAC320A10 3–116MAC320A10FP MAC320A10FP 3–120MAC320A4 MAC16D 3–67

MAC320A4 MAC320A4 3–116MAC320A4FP MAC320A4FP 3–120MAC320A6 MAC16D 3–67MAC320A6 MAC320A6 3–116MAC320A6FP MAC320A6FP 3–120MAC320A8 MAC16M 3–67MAC320A8 MAC320A8 3–116

MAC320A8FP MAC320A8FP 3–120MAC320–10 MAC320–10 3–116MAC320–10FP MAC320–10FP 3–120MAC320–4 MAC320–4 3–116MAC320–4FP MAC320–4FP 3–120MAC320–6 MAC320–6 3–116MAC320–6FP MAC320–6FP 3–120

MAC320–8 MAC320–8 3–116MAC320–8FP MAC320–8FP 3–120MAC321–10 MAC321–10 3–124MAC321–4 MAC321–4 3–124MAC321–6 MAC321–6 3–124MAC321–8 MAC321–8 3–124MAC515A10 MAC15–10FP 3–63

MAC515A4 MAC15–4FP 3–63MAC515A5 MAC15–6FP 3–63MAC515A6 MAC15–6FP 3–63MAC515A7 MAC15–8FP 3–63MAC515A8 MAC15–8FP 3–63MAC515A9 MAC15–10FP 3–63MAC515–10 MAC15–10FP 3–63

MAC515–4 MAC15–4FP 3–63MAC515–5 MAC15–6FP 3–63MAC515–6 MAC15–6FP 3–63MAC515–7 MAC15–8FP 3–63MAC515–8 MAC15–8FP 3–63MAC515–9 MAC15–10FP 3–63MAC525A10 MAC223–10FP 3–100

MAC525A9 MAC223–10FP 3–100MAC525–10 MAC223–10FP 3–100MAC525–4 MAC223–4 3–97MAC525–5 MAC223–6 3–97MAC525–6 MAC223–6 3–97MAC525–7 MAC223–8 3–97MAC525–8 MAC223–8 3–97

MAC525–9 MAC223–10 3–97MAC77–2 2N6071 3–10MAC77–3 2N6071 3–10MAC77–4 2N6071 3–10MAC77–6 2N6073 3–10MAC77–8 2N6075 3–10MAC91A1 MAC97A4 3–71

MAC91A2 MAC97A4 3–71MAC91A3 MAC97A4 3–71MAC91A4 MAC97A4 3–71MAC91A5 MAC97A6 3–71MAC91A6 MAC97A6 3–71MAC91A7 MAC97A8 3–71MAC91A8 MAC97A8 3–71

MAC91–1 MAC97–4 3–71MAC91–2 MAC97–4 3–71MAC91–3 MAC97–4 3–71MAC91–4 MAC97–4 3–71MAC91–5 MAC97–6 3–71MAC91–6 MAC97–6 3–71MAC91–7 MAC97–8 3–71

MAC91–8 MAC97–8 3–71MAC92A1 MAC97A4 3–71MAC92A2 MAC97A4 3–71MAC92A3 MAC97A4 3–71MAC92A4 MAC97A4 3–71MAC92A5 MAC97A6 3–71MAC92A6 MAC97A6 3–71

MAC92A7 MAC97A8 3–71MAC92A8 MAC97A8 3–71MAC92–1 MAC97–4 3–71MAC92–2 MAC97–4 3–71MAC92–3 MAC97–4 3–71MAC92–4 MAC97–4 3–71MAC92–5 MAC97–6 3–71

IndustryPart Number

MotorolaNearest

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MotorolaNearest

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Number



MAC92–6 MAC97–6 3–71MAC92–7 MAC97–8 3–71MAC92–8 MAC97–8 3–71MAC93A1 MAC97A4 3–71MAC93A2 MAC97A4 3–71MAC93A3 MAC97A4 3–71MAC93A4 MAC97A4 3–71

MAC93A5 MAC97A6 3–71MAC93A6 MAC97A6 3–71MAC93A7 MAC97A8 3–71MAC93A8 MAC97A8 3–71MAC93–1 MAC97–4 3–71MAC93–2 MAC97–4 3–71MAC93–3 MAC97–4 3–71

MAC93–4 MAC97–4 3–71MAC93–5 MAC97–6 3–71MAC93–6 MAC97–6 3–71MAC93–7 MAC97–8 3–71MAC93–8 MAC97–8 3–71MAC94A1 MAC97–4 3–71MAC94A2 MAC97–4 3–71

MAC94A3 MAC97–4 3–71MAC94A4 MAC97–4 3–71MAC94A5 MAC97–6 3–71MAC94A6 MAC97–6 3–71MAC94A7 MAC97–8 3–71MAC94A8 MAC97–6 3–71MAC94–1 MAC97–4 3–71


MAC95A1 MAC97A4 3–71MAC95A2 MAC97A4 3–71MAC95A3 MAC97A4 3–71MAC95A4 MAC97A4 3–71MAC95A5 MAC97A6 3–71MAC95A6 MAC97A6 3–71MAC95A7 MAC97A8 3–71

MAC95A8 MAC97A8 3–71MAC95–1 MAC97A4 3–71MAC95–2 MAC97A4 3–71MAC95–3 MAC97A4 3–71MAC95–4 MAC97A4 3–71MAC95–5 MAC97A6 3–71MAC95–6 MAC97A6 3–71

MAC95–7 MAC97A8 3–71MAC95–8 MAC97A8 3–71MAC96A1 MAC97A4 3–71MAC96A2 MAC97A4 3–71MAC96A3 MAC97A4 3–71MAC96A4 MAC97A4 3–71MAC96A5 MAC97A6 3–71

MAC96A6 MAC97A6 3–71MAC96A7 MAC97A8 3–71MAC96A8 MAC97A8 3–71MAC96–1 MAC97A4 3–71MAC96–2 MAC97A4 3–71MAC96–3 MAC97A4 3–71MAC96–4 MAC97A4 3–71

MAC96–5 MAC97A6 3–71MAC96–6 MAC97A6 3–71MAC96–7 MAC97A8 3–71MAC96–8 MAC97A8 3–71MAC97A1 MAC97A4 3–71MAC97A2 MAC97A4 3–71MAC97A3 MAC97A4 3–71

MAC97A4 MAC97A4 3–71MAC97A5 MAC97A6 3–71MAC97A6 MAC97A6 3–71MAC97A7 MAC97A8 3–71MAC97A8 MAC97A8 3–71MAC97B1 MAC97B4 3–71MAC97B2 MAC97B4 3–71

MAC97B3 MAC97B4 3–71MAC97B4 MAC97B4 3–71MAC97B5 MAC97B6 3–71MAC97B6 MAC97B6 3–71MAC97B7 MAC97B8 3–71MAC97B8 MAC97B8 3–71MAC97–1 MAC97–4 3–71


MACH15D MAC15D 3–55MACH15M MAC15M 3–55MACH15N MAC15N 3–55MBS4991 MBS4991 3–128MBS4992 MBS4992 3–128MBS4993 MBS4993 3–128MCR08BT1 MCR08BT1 3–132

MCR08DT1 MCR08DT1 3–132MCR08MT1 MCR08MT1 3–132MCR100–3 MCR100–3 3–154MCR100–4 MCR100–4 3–154MCR100–5 MCR100–6 3–154MCR100–6 MCR100–6 3–154MCR100–7 MCR100–8 3–154

MCR100–8 MCR100–8 3–154MCR101 MCR102 3–156MCR102 MCR102 3–156MCR103 MCR103 3–156MCR104 MCR100–3 3–154MCR106–1 MCR106–2 3–158MCR106–2 MCR106–2 3–158

MCR106–3 MCR106–3 3–158MCR106–4 MCR106–4 3–158MCR106–5 MCR106–6 3–158MCR106–6 MCR106–6 3–158MCR106–7 MCR106–8 3–158MCR106–8 MCR106–8 3–158MCR107–2 MCR106–2 3–158


MCR115 MCR100–4 3–154MCR120 MCR100–4 3–154MCR218–10 MCR8N 3–137MCR218–4 MCR8D 3–137MCR218–6 MCR8D 3–137MCR218–8 MCR8M 3–137MCR218–10 MCR218–10 3–161


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MotorolaNearest

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MCR218–9 MCR218–10 3–161MCR220–5 MCR12D 3–141MCR220–7 MCR12M 3–141MCR220–9 MCR12N 3–141MCR221–5 MCR16D 3–143MCR221–9 MCR16D 3–143MCR225–10FP MCR225–10FP 3–168

MCR225–2FP MCR225–2FP 3–168MCR225–4FP MCR225–4FP 3–168MCR225–5 2N6507 3–26MCR225–6FP MCR225–6FP 3–168MCR225–7 2N6508 3–26MCR225–8FP MCR225–8FP 3–168MCR225–9 2N6509 3–26



MCR265–8 MCR265–8 3–175MCR3000–10C MCR218–10 3–161MCR3000–2 MCR218–2 3–161MCR3000–3C MCR218–3 3–161MCR3000–5C MCR218–6 3–161MCR3000–6 MCR218–6 3–161MCR3000–7C MCR218–8 3–161

MCR3000–8 MCR218–8 3–161MCR3000–9C MCR218–10 3–161MCR300–4 MCR218–4 3–161MCR306–1 2N6237 3–15MCR306–2 2N6237 3–15MCR306–3 2N6238 3–15MCR306–4 2N6239 3–15

MCR306–5 2N6240 3–15MCR306–6 2N6240 3–15MCR310–10 MCR310–10 3–178MCR310–2 MCR310–2 3–178MCR310–3 MCR310–3 3–178MCR310–4 MCR310–4 3–178MCR310–6 MCR310–6 3–178


MCR525–10 2N6509 3–26MCR525–4 2N6506 3–26MCR525–5 2N6507 3–26MCR525–6 2N6507 3–26MCR525–7 2N6508 3–26MCR525–8 2N6508 3–26MCR525–9 2N6509 3–26

MCR568–1 MCR12D 3–141MCR568–2 MCR12D 3–141MCR568–3 MCR12D 3–141MCR568–6 MCR12M 3–141MCR569–1 MCR12D 3–141MCR569–2 MCR12D 3–141MCR569–3 MCR12D 3–141

MCR569–6 MCR12M 3–141MCR68–2 MCR12D 3–141MCR68–3 MCR12D 3–141MCR68–4 MCR12D 3–141MCR69–2 MCR16D 3–143MCR69–3 MCR16D 3–143MCR69–6 MCR16M 3–143

MCR703A MCR703A 3–182MCR703A1 MCR703A1 3–182MCR704A1 MCR704A1 3–182MCR706A MCR706A 3–182MCR706A1 MCR706A1 3–182MCR708A MCR708A 3–182MCR708A1 MCR708A1 3–182

MCR72–10 MCR8SN 3–139MCR72–4 MCR8SD 3–139MCR72–6 MCR8SD 3–139MCR72–8 MCR8SM 3–139MCR72–1 MCR72–2 3–151MCR72–2 MCR72–2 3–151MCR72–3 MCR72–3 3–151

MCR72–4 MCR72–4 3–151MCR72–5 MCR72–6 3–151MCR72–6 MCR72–6 3–151MCR72–8 MCR72–8 3–151MK1V115 MKP3V110 3–187MK1V125 MKP3V120 3–187MK1V135 MKP3V130 3–187

MKP1V120 MKP1V120 3–184MKP1V130 MKP1V130 3–184MKP3V120 MKP3V120 3–187MKP3V130 MKP3V130 3–187MKP9V120 MKP1V120 3–184MKP9V130 MKP1V130 3–184PO100BA MCR100–4 3–154

PO100DA MCR100–6 3–154PO100MA MCR100–8 3–154PO102AA MCR100–4 3–154PO102BA MCR100–4 3–154PO102CA MCR100–4 3–154PO102DA MCR100–6 3–154PO103BA MCR100–4 3–154

PO103DA MCR100–6 3–154PO103MA MCR100–8 3–154Q2001L3 T2322B 3–195Q2001L4 T2322B 3–195Q2001M3 T2322B 3–195Q2001M4 2N6071 3–10Q2003L3 2N6071A 3–10

Q2003L4 2N6071A 3–10Q2003M3 2N6071A 3–10Q2003M4 2N6071 3–10Q2003P3 2N6071A 3–10Q2003P4 2N6071 3–10Q2004F31 2N6071A 3–10Q2004F41 2N6071 3–10

Q2004L3 2N6071A 3–10Q2004L4 2N6071A 3–10Q2006F31 2N6071 3–10Q2006F41 2N6071 3–10Q2006L5 MAC9D 3–49Q2006R4 T2500B 3–197Q2008F41 T2800B 3–201

Q2008L4 T2800B 3–201Q2008R4 T2800B 3–201Q200E3 MAC97–4 3–71Q200E4 MAC97–4 3–71Q2010F41 MAC12D 3–53Q2010L4 MAC210A4FP 3–79Q2010L45 MAC12D 3–53

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Q2010R4 MAC12D 3–53Q2012L5 MAC212A4FP 3–87Q2012R5 2N6346A 3–22Q2015L5 MAC15A4FP 3–63Q2015R5 MAC15A4 3–59Q201E3 MAC97–4 3–71Q201E4 MAC97–4 3–71

Q2025L5 MAC223A4FP 3–100Q2025R5 MAC223A4 3–97Q4001M3 2N6073A 3–10Q4001M4 2N6073 3–10Q4003L3 2N6073A 3–10Q4003L4 2N6073A 3–10Q4003M3 2N6073A 3–10

Q4003M4 2N6073 3–10Q4003P3 2N6073A 3–10Q4003P4 2N6073 3–10Q4004F31 2N6073A 3–10Q4004F41 2N6073 3–10Q4004L3 2N6073A 3–10Q4004L4 2N6073A 3–10

Q4006F41 2N6073 3–10Q4006L4 T2500D 3–197Q4006L5 MAC9D 3–49Q4006R4 T2500D 3–197Q4008F41 T2800D 3–201Q4008L4 MAC218A6FP 3–94Q4008L4A T2800D 3–201

Q4008R4 MAC9D 3–49Q4008R4 T2800D 3–201Q400E3 MAC97–6 3–71Q400E4 MAC97–6 3–71Q4010F41 MAC12D 3–53Q4010L4 MAC210A6FP 3–79Q4010L5 MAC12D 3–53

Q4010R4 MAC12D 3–53Q4012L5 MAC212A6FP 3–87Q4012R5 2N6347A 3–22Q4015L5 MAC15A6FP 3–63Q4015R5 MAC15A6 3–59Q4015R5 MAC16D 3–67Q4025L6 MAC223A6FP 3–100

Q4025P MAC223–6 3–97Q4025R5 MAC223A6 3–97Q5004F41 2N6075 3–10Q5006F41 T2500M 3–197Q5006L4 T2500M 3–197Q5006L5 MAC9M 3–49Q5006R4 T2500M 3–197

Q5008F41 T2800D 3–201Q5008L4 T2800M 3–201Q5008L4A T2800M 3–201Q5008R4 T2800M 3–201Q5010F41 MAC12M 3–53Q5010L4 MAC12M 3–53Q5010L5 MAC12M 3–53

Q5010R4 MAC12M 3–53Q5012L5 2N6348A 3–22Q5012R5 2N6348A 3–22Q5015L5 MAC15A8 3–59Q5015R5 MAC15A8 3–59Q5025L5 MAC223A8 3–97Q5025R5 MAC223A8 3–97

Q6004F41 2N6075 3–10Q6006F51 2N6075 3–10Q6006L5 MAC9M 3–49Q6006R5 MAC9M 3–49Q6008F51 MAC9M 3–49Q6008L5 MAC218A8FP 3–94Q6008R4 MAC9M 3–49

Q6010L5 MAC210A8FP 3–79Q6010R5 MAC12M 3–53Q6012L5 MAC212A8FP 3–87Q6012R5 2N6348A 3–22Q6015L5 MAC15A8FP 3–63Q6015R5 MAC15A8 3–59Q6015R5 MAC16M 3–67

Q6015R5 MAC16N 3–67Q6025L5 MAC223A8FP 3–100Q6025R5 MAC223A8 3–97Q8008R4 MAC9N 3–49Q8010L5 MAC12N 3–53Q8010R5 MAC12N 3–53Q8015L5 MAC15A10 3–59

Q8015R5 MAC15A10 3–59S0303LS3 MCR106–2 3–158S0303MS2 2N6237 3–15S0303MS3 2N6237 3–15S0306FS21 MCR72–2 3–151S0306FS31 MCR72–2 3–151S0306L S2800F 3–193

S1001L MCR106–3 3–158S1001LS1 MCR106–3 3–158S1001LS3 MCR106–3 3–158S1003L MCR106–3 3–158S1003LS1 MCR106–3 3–158S1003LS2 MCR106–3 3–158S1003LS3 MCR106–3 3–158

S1003MS2 2N6238 3–15S1003MS3 2N6238 3–15S1006FS21 MCR72–3 3–151S1006FS31 MCR72–3 3–151S1006L S2800A 3–193S1006LS2 MCR72–3 3–151S1006LS3 MCR72–3 3–151

S1008F1 MCR218–3 3–161S1008F3 MCR218–3 3–161S1008FS21 MCR72–3 3–151S1008FS31 MCR72–3 3–151S1008L MCR218–3 3–161S1008LS2 MCR72–3 3–151S1008LS3 MCR72–3 3–151

S1008R S2800A 3–193S1010F1 MCR12D 3–141S1010L MCR12D 3–141S1012L MCR12D 3–141S1012R MCR12D 3–141S1015L MCR16D 3–143S1016R MCR16D 3–143

S1020L 2N6505 3–26S1025R 2N6505 3–26S106E C106M 3–34S106M C106M 3–34S107M C106M 3–34S1207BH MCR12D 3–141S1207DH MCR12D 3–141

S1207MH MCR12M 3–141S1207NH MCR12N 3–141S1210BH MCR12M 3–141S1210DH MCR12M 3–141S1210MH MCR12M 3–141S1210NH MCR12N 3–141S1610BH MCR16D 3–143

S1610DH MCR16D 3–143S1610NH MCR16D 3–143S2001L MCR106–4 3–158S2001LS1 MCR106–4 3–158S2001LS2 MCR106–4 3–158S2001LS3 MCR106–4 3–158S2003L MCR106–4 3–158

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S2003LS1 MCR106–4 3–158S2003LS2 MCR106–4 3–158S2003LS3 MCR106–4 3–158S2003MS2 2N6239 3–15S2003MS3 2N6239 3–15S2006FS21 MCR72–4 3–151S2006FS31 MCR72–4 3–151

S2006L S2800B 3–193S2006LS2 MCR72–4 3–151S2006LS3 MCR72–4 3–151S2008F1 MCR218–4 3–161S2008F3 MCR218–4 3–161S2008FS21 MCR72–4 3–151S2008FS31 MCR72–4 3–151

S2008LS2 MCR72–4 3–151S2008LS3 MCR72–4 3–151S2008R S2800B 3–193S2010L MCR12D 3–141S2012L MCR12D 3–141S2012R MCR12D 3–141S2015L MCR16D 3–143

S2016R MCR16D 3–143S2020L 2N6506 3–26S2025R 2N6506 3–26S2060A 2N6238 3–15S2060B 2N6239 3–15S2060C MCR106–6 3–158S2060D 2N6240 3–15

S2060E MCR106–8 3–158S2060F 2N6237 3–15S2060M 2N6241 3–15S2060Q 2N6237 3–15S2060Y 2N6237 3–15S2061A 2N6238 3–15S2061B 2N6239 3–15

S2061C MCR106–6 3–158S2061D 2N6240 3–15S2061E MCR106–8 3–158S2061F 2N6237 3–15S2061M 2N6241 3–15S2061Q 2N6237 3–15S2061Y 2N6237 3–15

S2062A 2N6238 3–15S2062B 2N6239 3–15S2062C MCR106–6 3–158S2062D 2N6240 3–15S2062E MCR106–8 3–158S2062F 2N6237 3–15S2062M 2N6241 3–15

S2062Q 2N6237 3–15S2062Y 2N6237 3–15S2610B S2800B 3–193S2610D S2800D 3–193S2610M S2800M 3–193S2620B S2800B 3–193S2620D S2800D 3–193

S2620M S2800M 3–193S2710B S2800B 3–193S2710D S2800D 3–193S2710M S2800M 3–193S2800A S2800A 3–193S2800B S2800B 3–193S2800C S2800D 3–193

S2800D MCR12D 3–141S2800D S2800D 3–193S2800E S2800M 3–193S2800F S2800F 3–193S2800M MCR12M 3–141S2800M S2800M 3–193S2800N MCR12N 3–141

S2800N S2800N 3–193S4001L MCR106–6 3–158S4001LS1 MCR106–6 3–158S4001LS2 MCR106–6 3–158S4001LS2 MCR106–6 3–158S4003L MCR106–6 3–158S4003LS1 MCR106–6 3–158

S4003LS2 MCR106–6 3–158S4003LS3 MCR106–6 3–158S4003MS2 2N6240 3–15S4003MS3 2N6240 3–15S4006FS21 MCR72–6 3–151S4006FS31 MCR72–6 3–151S4006L S2800D 3–193

S4006LS2 MCR72–6 3–151S4006LS3 MCR72–6 3–151S4008F1 MCR218–6 3–161S4008F3 MCR218–6 3–161S4008FS21 MCR72–6 3–151S4008FS31 MCR72–6 3–151S4008L MCR218–6 3–161

S4008LS2 MCR72–6 3–151S4008LS3 MCR72–6 3–151S4008R MCR8D 3–137S4008R S2800D 3–193S4010L MCR12D 3–141S4012L MCR12D 3–141S4012R MCR12D 3–141

S4012R MCR12D 3–141S4015L MCR16D 3–143S4016R MCR12D 3–141S4016R MCR16D 3–143S4020L 2N6507 3–26S4025R 2N6507 3–26S5008L MCR218–8 3–161

S6000C MCR12D 3–141S6000E MCR12M 3–141S6000S MCR12N 3–141S6001L MCR106–8 3–158S6003L MCR106–8 3–158S6006L S2800M 3–193S6008F MCR218–8 3–161

S6008F1 S2800M 3–193S6008F3 MCR218–8 3–161S6008L S2800M 3–193S6008R MCR8M 3–137S6008R S2800M 3–193S6010L MCR12M 3–141S6012L MCR12M 3–141

S6012R MCR12M 3–141S6012R MCR12M 3–141S6016R MCR12M 3–141S6020 2N6508 3–26S6025R 2N6508 3–26S6100C MCR16D 3–143S6100S MCR16D 3–143

S8008R MCR8N 3–137S8012R MCR12N 3–141S8016R MCR12N 3–141S8016R MCR16D 3–143S8020L 2N6509 3–26S8025R 2N6509 3–26SC129B MAC223A4 3–97

SC129D MAC223A6 3–97SC129E MAC223A8 3–97SC129M MAC223A8 3–97SC136A 2N6071 3–10SC136B 2N6071 3–10SC136C 2N6073 3–10SC136D 2N6073 3–10

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SC136E 2N6075 3–10SC136M 2N6075 3–10SC141A MAC9D 3–49SC141B MAC9D 3–49SC141C MAC9D 3–49SC141D MAC9D 3–49SC141D MAC9D 3–49

SC141E MAC9M 3–49SC141M MAC9M 3–49SC141M MAC9M 3–49SC141N MAC9N 3–49SC141N MAC9N 3–49SC143B MAC9D 3–49SC143D MAC9D 3–49

SC143E MAC9M 3–49SC143M MAC9M 3–49SC146A MAC12D 3–53SC146B MAC12D 3–53SC146C MAC12D 3–53SC146D MAC12D 3–53SC146E MAC12M 3–53

SC146F MAC12D 3–53SC146M MAC12M 3–53SC146N MAC12M 3–53SC146S MAC12N 3–53SC149B MAC12N 3–53SC149D MAC12D 3–53SC149E MAC12M 3–53

SC149F MAC12D 3–53SC149M ‘ MAC12M 3–53SC151B MAC15A4 3–59SC151D MAC15A6 3–59SC151E MAC15A8 3–59SC151M MAC15A8 3–59SC160B MAC223–4 3–97

SC160D MAC223–6 3–97SC160E MAC223–8 3–97SC160M MAC223–8 3–97SC92A MAC97A4 3–71SC92B MAC97A4 3–71SC92D MAC97A6 3–71SC92F MAC97A4 3–71

SISC141C MAC9D 3–49SISC141D MAC9D 3–49SISC141E MAC9M 3–49SISC141M MAC9M 3–49SISC141N MAC9N 3–49SISC141S MAC9N 3–49SISC146C MAC12D 3–53

SISC146D MAC12D 3–53SISC146M MAC12M 3–53SISC146N MAC12N 3–53SISC146S MAC12M 3–53SISC149C 2N6347A 3–22SISC149D 2N6347A 3–22SISC149E 2N6348A 3–22

SISC149M 2N6348A 3–22SM1ZG45 MAC15D 3–55SM1ZS45 MAC15M 3–55SM8G45A MAC9D 3–49SM8J45A MAC9M 3–49SO301L MCR106–2 3–158SO301L MCR12D 3–141

SO301LS1 MCR106–2 3–158SO301LS2 MCR106–2 3–158SO301LS3 MCR106–2 3–158SO303L MCR106–2 3–158SO303LS1 MCR106–2 3–158SO303LS2 MCR106–2 3–158SO306LS2 MCR72–2 3–151

SO306LS3 MCR72–2 3–151SO308F1 MCR218–2 3–161SO308F3 MCR218–2 3–161SO308FS21 MCR72–2 3–151SO308FS31 MCR72–2 3–151SO308FS4 MCR72–2 3–151SO308LS2 MCR72–2 3–151

SO308LS3 MCR72–2 3–151SO310F1 MCR12D 3–141SO312L MCR12D 3–141SO312R MCR12D 3–141SO315L MCR16D 3–143SO316R MCR16D 3–143SO320L 2N6504 3–26

SO325R 2N6504 3–26SO501L MCR106–2 3–158SO501LS1 MCR106–2 3–158SO501LS2 MCR106–2 3–158SO501LS3 MCR106–2 3–158SO503L MCR106–2 3–158SO503LS1 MCR106–2 3–158

SO503LS2 MCR106–2 3–158SO503LS3 MCR106–2 3–158SO503MS2 2N6238 3–15SO503MS3 2N6238 3–15SO505FS21 MCR72–2 3–151SO505FS31 MCR72–2 3–151SO506FS21 MCR72–2 3–151

SO506FS31 MCR72–2 3–151SO506LS2 MCR72–2 3–151SO506LS3 MCR72–2 3–151SO508F1 MCR218–2 3–161SO508F3 MCR218–2 3–161SO508FS31 MCR72–2 3–151SO508LS2 MCR72–2 3–151

SO508LS3 MCR72–2 3–151SO508S21 MCR72–2 3–151SO510L MCR12D 3–141SO512L MCR12D 3–141SO512R MCR12D 3–141SO515L MCR12D 3–141SO516R MCR16D 3–143

SO520L 2N6504 3–26SO802BH MCR72–4 3–151SO802DH MCR72–6 3–151SO802NH MCR72–10 3–151T1012BH MAC210A4 3–75T1012DH MAC210A6 3–75T1012MH MAC210A8 3–75

T1012NH MAC210A10 3–75T1013BH MAC210A4 3–75T1013DH MAC210A6 3–75T1013MH MAC210A8 3–75T1013NH MAC210A10 3–75T106E1 C106M 3–34T106M1 C106M 3–34

T107E1 C106M 3–34T107M1 C106M 3–34T1213BH MAC212A4 3–83T1213DH MAC212A6 3–83T1213MH MAC212A8 3–83T1213NH MAC212A10 3–83T1612BH MAC15A4 3–59

T1612DH MAC15A6 3–59T1612MH MAC15A8 3–59T1612NH MAC15A10 3–59T1613BH MAC15A4 3–59T1613DH MAC15A6 3–59T1613MH MAC15A8 3–59T1613NH MAC15A10 3–59

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Number


T2301D 2N6073B 3–10T2301F 2N6071B 3–10T2301M 2N6075B 3–10T2302A 2N6071A 3–10T2302B 2N6071A 3–10T2302C 2N6073A 3–10T2302D 2N6073A 3–10

T2302F 2N6071A 3–10T2302PA 2N6071A 3–10T2302PB 2N6071A 3–10T2302PC 2N6073A 3–10T2302PD 2N6073A 3–10T2302PF 2N6071A 3–10T2303F 2N6071A 3–10

T2304B 2N6071A 3–10T2304D 2N6073A 3–10T2305B 2N6071A 3–10T2305D 2N6073A 3–10T2306A 2N6071A 3–10T2306B 2N6071A 3–10T2306D 2N6073A 3–10

T2311A 2N6071A 3–10T2312A 2N6071A 3–10T2312B 2N6071A 3–10T2312D 2N6071A 3–10T2312F 2N6071A 3–10T2313A 2N6071A 3–10T2313B 2N6071A 3–10

T2313D 2N6071A 3–10T2313F 2N6071A 3–10T2322A T2322B 3–195T2322B T2322B 3–195T2322C T2322D 3–195T2322D T2322D 3–195T2322E T2322M 3–195

T2322F T2322B 3–195T2322M T2322M 3–195T2322N T2322M 3–195T2323A T2323B 3–195T2323B T2323B 3–195T2323C T2323D 3–195T2323D T2323D 3–195

T2323E T2323M 3–195T2323F T2323B 3–195T2323M T2323M 3–195T2323N T2323M 3–195T2500A T2500B 3–197T2500B T2500B 3–197T2500BFP T2500BFP 3–199

T2500C T2500D 3–197T2500D MAC8D 3–45T2500D T2500D 3–197T2500DFP T2500DFP 3–199T2500E T2500M 3–197T2500M MAC8M 3–45T2500M T2500M 3–197

T2500MFP T2500MFP 3–199T2500N MAC8N 3–45T2500N T2500N 3–197T2500NFP T2500NFP 3–199T2500S T2500N 3–197T2506B T2500B 3–197T2506D T2500D 3–197

T2512BH MAC223A4 3–97T2512DH MAC223A6 3–97T2512MH MAC223A8 3–97T2512NH MAC223A10 3–97T2513BH MAC223A4 3–97T2513DH MAC223A6 3–97T2513MH MAC223A8 3–97

T2513NH MAC223A10 3–97T2800A T2800B 3–201T2800B T2800B 3–201T2800C T2800D 3–201T2800D MAC8D 3–45T2800D T2800D 3–201T2800E T2800M 3–201

T2800F T2800B 3–201T2800M MAC8M 3–45T2800M T2800M 3–201T2800N 2N6349 3–18T2800N MAC8N 3–45T2801A T2801B MAC8D 3–45T2801B T2801B MAC8D 3–45

T2801C T2801D MAC8D 3–45T2801D T2801D MAC8D 3–45T2801E T2801M MAC8M 3–45T2801M T2801M MAC8M 3–45T2801N T2801N MAC8N 3–45T2802A T2802B MAC9D 3–49T2802B T2802B MAC9D 3–49

T2802C T2802D MAC9D 3–49T2802D T2802D MAC9D 3–49T2802E T2802M MAC9M 3–49T2802F T2802B MAC9D 3–49T2802M T2802M MAC9M 3–49T2802N 2N6345 3–18T2806B T2800B 3–201

T2806C T2800D 3–201T2806D T2800D 3–201T2806N MAC218A10 3–91T2850A 2N6346A 3–22T2850B 2N6346A 3–22T2850D 2N6347A 3–22T2850E 2N6347A 3–22

T2850M T2800M 3–201T2851B MAC9D 3–49T2851C MAC9D 3–49T2851D MAC9D 3–49T2851E MAC9M 3–49T2856B T2800B 3–201T2856C T2800D 3–201

T2856D T2800D 3–201T2856M T2800M 3–201T4700B MAC15A4 3–59T4700C MAC15A6 3–59T4700D MAC15A6 3–59T4700E MAC15A8 3–59T4700F MAC15A4 3–59

T4700M MAC15A8 3–59T4700N MAC15A10 3–59T4706B MAC15A4 3–59T4706D MAC15A6 3–59T6000A MAC15A4 3–59T6000B MAC15A4 3–59T6000C MAC15A6 3–59

T6000D MAC15A6 3–59T6000E MAC15A8 3–59T6000F MAC15A4 3–59T6000M MAC15A8 3–59T6000N MAC15A10 3–59T6001A MAC15A4 3–59T6001B MAC15A4 3–59

T6001C MAC15A6 3–59T6001D MAC15A6 3–59T6001E MAC15A8 3–59T6001F MAC15A4 3–59T6001M MAC15A8 3–59T6001N MAC15A10 3–59T6006A MAC15A4 3–59

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T6006B MAC15A4 3–59T6006C MAC15A6 3–59T6006D MAC15A6 3–59T6006E MAC15A8 3–59T6006F MAC15A4 3–59T6006M MAC15A8 3–59T6006N MAC15A10 3–59

TE205 MCR100–4 3–154TE305 MCR100–6 3–154TE405 MCR100–6 3–154TE505 MCR100–8 3–154TE605 MCR100–8 3–154TIC126A MCR12D 3–141TIC126B MCR12D 3–141

TIC126C MCR12D 3–141TIC126D MCR12D 3–141TIC126E MCR12M 3–141TIC126F MCR12D 3–141TIC126M MCR12M 3–141TIC206A 2N6071A 3–10TIC206B 2N6071A 3–10

TIC206D 2N6073A 3–10TIC215A 2N6071A 3–10TIC215B 2N6071A 3–10TIC215D 2N6073A 3–10TIC216A MAC228A4 3–106TIC216B MAC228A4 3–106TIC216D MAC228A6 3–106

TIC226B MAC9N 3–49TIC226D MAC9D 3–49TIC246B MAC15A4 3–59TIC246D MAC15A6 3–59TIC253B MAC15–4FP 3–63TIC253D MAC15–6FP 3–63TIC253E MAC15–8FP 3–63

TIC253M MAC15–8FP 3–63TIC39A 2N6238 3–15TIC39B 2N6239 3–15TIC39C MCR100–6 3–154TIC39D 2N6240 3–15TIC39E MCR100–8 3–154TIC39F 2N6237 3–15

TIC39Y 2N6237 3–15TIC44 2N5060 3–2TIC45 2N5061 3–2TIC46 2N5062 3–2TIC47 2N5064 3–2TIC60 2N5060 3–2TIC61 2N5061 3–2

TIC62 2N5062 3–2TIC63 2N5064 3–2TIC64 2N5064 3–2TL1003 MCR218–3 3–161TL1006 MCR218–3 3–161TL106–05 MCR106–2 3–158TL106–1 MCR106–3 3–158

TL106–2 MCR106–4 3–158TL106–4 MCR106–6 3–158TL106–6 MCR106–8 3–158TL107–05 MCR106–2 3–158TL107–1 MCR106–3 3–158TL107–2 MCR106–4 3–158TL107–4 MCR106–6 3–158

TL107–6 MCR106–8 3–158TL2003 MCR218–4 3–161TL2006 MCR218–4 3–161TL4003 MCR218–6 3–161TL4006 MCR218–6 3–161TL6003 MCR218–8 3–161TL6006 MCR218–8 3–161

TL8003 MCR218–10 3–161TL8006 MCR218–10 3–161TLC111A T2322B 3–195TLC111B T2322B 3–195TLC113A T2322B 3–195TLC113B T2322B 3–195TLC221A T2322B 3–195

TLC221B T2322B 3–195TLC223A T2322B 3–195TLC223B T2322B 3–195TLC226A MCR706A1 3–182TLS106–05 MCR106–2 3–158TLS106–1 MCR106–3 3–158TLS106–2 MCR106–4 3–158

TLS106–4 MCR106–6 3–158TLS106–6 MCR106–8 3–158TLS107–05 MCR106–2 3–158TLS107–1 MCR106–3 3–158TLS107–2 MCR106–4 3–158TLS107–4 MCR106–6 3–158TLS107–6 MCR106–8 3–158

TO1010BH MAC210A4 3–75TO1010DH MAC210A6 3–75TO1010MH MAC210A8 3–75TO1010NH MAC210A10 3–75TO409BJ T2500BFP 3–199TO409DJ T2500DFP 3–199TO409MJ T2500MFP 3–199

TO409NJ T2500NFP 3–199TO410BJ T2500BFP 3–199TO410DJ T2500DFP 3–199TO410MJ T2500MFP 3–199TO410NJ T2500NFP 3–199TO505BH T2500B 3–197TO505DH T2500D 3–197

TO505MH T2500M 3–197TO505NH T2500N 3–197TO509BH T2500B 3–197TO509DH T2500D 3–197TO509MH T2500M 3–197TO509NH T2500N 3–197TO510BH T2500B 3–197

TO510DH T2500D 3–197TO510MH T2500M 3–197TO510NH T2500N 3–197TO512BH T2500B 3–197TO512DH T2500D 3–197TO512MH T2500M 3–197TO512NH T2500N 3–197

TO610BH T2500B 3–197TO610BJ T2500BFP 3–199TO610DH T2500D 3–197TO610DJ T2500DFP 3–199TO610MH T2500M 3–197TO610MJ T2500MFP 3–199TO610NH T2500N 3–197

TO610NJ T2500NFP 3–199TO612BH T2500B 3–197TO612BJ T2500BFP 3–199TO612DH T2500D 3–197TO612DJ T2500DFP 3–199TO612MH T2500M 3–197TO612MJ T2500MFP 3–199

TO612NH T2500N 3–197TO612NJ T2500NFP 3–199TO805BH MAC228A4 3–106TO805DH MAC228A6 3–106TO805MH MAC228A8 3–106TO805NH MAC228A10 3–106TO809BH MAC228A4 3–106

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TO809DH MAC228A6 3–106TO809MH MAC228A8 3–106TO809NH MAC228A10 3–106TO810BH MAC229A4 3–110TO810BJ MAC229A4FP 3–112TO810DH MAC229A6 3–110TO810DJ MAC229A6FP 3–112

TO810MJ MAC229A8FP 3–112TO810NH MAC229A10 3–110TO810NJ MAC229A10FP 3–112TXN058 MCR218–2FP 3–164TXN108 MCR218–4FP 3–164TXN208 MCR218–4FP 3–164TXN408 MCR218–6FP 3–164

TXN608 MCR218–8FP 3–164TXN808 MCR218–10FP 3–164TY1004 MCR218–3 3–161TY1008 MCR218–3 3–161TY1010 MCR12D 3–141TY2004 MCR218–4 3–161TY2008 MCR218–4 3–161

TY2010 MCR12D 3–141TY3004 MCR218–6 3–161TY3008 MCR218–6 3–161TY3010 MCR218–6 3–161TY4004 MCR218–6 3–161TY4008 MCR218–6 3–161TY4010 MCR12D 3–141

TY5004 MCR218–8 3–161TY5008 MCR218–8 3–161TY5010 MCR12M 3–141TY504 MCR218–2 3–161TY508 MCR218–2 3–161TY510 MCR12D 3–141TY6004 MCR218–8 3–161

TY6008 MCR218–8 3–161TY6010 MCR12M 3–141TY8008 MCR218–10 3–161TY8010 MCR12M 3–141TYAL–1110B MAC12D 3–53TYAL–1110M MAC12M 3–53TYAL–1115B MAC15A4 3–59

TYAL–1115M MAC15A4 3–59TYAL–118M MAC9D 3–49TYN0512 MCR12D 3–141TYN112 MCR12D 3–141TYN116 MCR16D 3–143TYN208 MCR218–4 3–161TYN212 MCR12D 3–141

TYN216 MCR16D 3–143TYN408 MCR8D 3–137TYN412 MCR12D 3–141TYN416 MCR12D 3–141TYN608 MCR218–8FP 3–164TYN608 MCR8M 3–137TYN612 MCR12M 3–141

TYN612 MCR12M 3–141TYN616 MCR12M 3–141TYN682 2N6504 3–26TYN683 2N6505 3–26TYN685 2N6506 3–26TYN688 2N6507 3–26TYN690 2N6508 3–26

TYN692 2N6509 3–26TYN808 MCR218–10FP 3–164TYN808 MCR8N 3–137TYN812 MCR12N 3–141TYN812 MCR12N 3–141TYN816 MCR12N 3–141TYNO516 MCR16D 3–143

TYS406–6 MCR106–8 3–158TYS407–6 MCR106–8 3–158TYS606–1 MCR72–3 3–151TYS606–2 MCR72–4 3–151TYS606–4 MCR72–6 3–151TYS606–5 MCR72–2 3–151TYS606–8 MCR72–10 3–151

TYS806–1 MCR72–3 3–151TYS806–2 MCR72–4 3–151TYS806–4 MCR72–6 3–151TYS806–5 MCR72–2 3–151XO102BA 2N5064 3–2XO102DA MCR100–6 3–154XO102MA MCR100–8 3–154

XO202BA MCR22–4 3–145XO202DA MCR22–6 3–145XO202MBA MCR22–8 3–145XO402ME C106M 3–34ZO109BA MCR100–4 3–154ZO109DA MCR100–6 3–154ZO109MA MCR100–8 3–154

ZO402ME 2N6075B 3–10ZO402MF 2N6075B 3–10ZO405ME 2N6075B 3–10ZO409ME C106M 3–34ZO410BE MCR106–4 3–158ZO410DE MCR106–6 3–158ZO410ME MCR106–8 3–158

For:colleenPrinted on:Tue, Jun 30, 1998 10:17:58From book:SALESOFF (MAR95) VIEW in DL137_BACK (6D) VIEDocument:SALES_US (MAR95) VIEWLast saved on:Mon, Jun 29, 1998 22:03:57Document:SALES_EURO (MAR95) VIEWLast saved on:Mon, Jun 29, 1998 22:04:00Document:DL137_BK_TABS VIEWLast saved on:Mon, Jun 29, 1998 22:04:03

For changes to this information contact Technical Publications at FAX (602) 244-6561

3/1/95

MOTOROLA DISTRIBUTOR AND WORLDWIDE SALES OFFICESAUTHORIZED NORTH AMERICAN DISTRIBUTORS

UNITED STATESALABAMA

HuntsvilleArrow/Schweber Electronics (205)837-6955. . . . Future Electronics (205)830-2322. . . . . . . . . . . . Hamilton Hallmark (205)837-8700. . . . . . . . . . . . Newark (205)837-9091. . . . . . . . . . . . . . . . . . . . . Time Electronics 1-800-789-TIME. . . . . . . . . . . . Wyle Laboratories (205)830–1119. . . . . . . . . . . .

ARIZONAPhoenix

Future Electronics (602)968-7140. . . . . . . . . . . . Hamilton Hallmark (602)437-1200. . . . . . . . . . . . . Wyle Laboratories (602)437-2088. . . . . . . . . . . .

TempeArrow/Schweber Electronics (602)431-0030. . . . Newark (602)966-6340. . . . . . . . . . . . . . . . . . . . . Time Electronics 1-800-789-TIME. . . . . . . . . . . .

CALIFORNIAAgoura Hills

Time Electronics Corporate 1-800-789-TIME. . . . Belmont

Richardson Electronics (415)592-9225. . . . . . . Calabassas

Arrow/Schweber Electronics (818)880-9686. . . . Wyle Laboratories (818)880-9000. . . . . . . . . . . .

ChatsworthFuture Electronics (818)865-0040. . . . . . . . . . . . Time Electronics 1-800-789-TIME. . . . . . . . . . . .

Costa MesaHamilton Hallmark (714)641-4100. . . . . . . . . . . .

Culver CityHamilton Hallmark (213)558-2000. . . . . . . . . . . .

Garden GroveNewark (714-893-4909. . . . . . . . . . . . . . . . . . . . .

IrvineArrow/Schweber Electronics (714)587-0404. . . Future Electronics (714)250-4141. . . . . . . . . . . . Wyle Laboratories Corporate (714)753-9953. . . . Wyle Laboratories (714)863-9953. . . . . . . . . . . .

Los AngelesWyle Laboratories (818)880-9000. . . . . . . . . . . .

Mountain ViewRichardson Electronics (415)960-6900. . . . . . .

OrangeNewark (714)634-8224. . . . . . . . . . . . . . . . . . . . .

Palo AltoNewark (415)812-6300. . . . . . . . . . . . . . . . . . . . .

RocklinHamilton Hallmark (916)624-9781. . . . . . . . . . .

SacramentoNewark (916)721-1633. . . . . . . . . . . . . . . . . . . . . Wyle Laboratories (916)638-5282. . . . . . . . . . . .

San DiegoArrow/Schweber Electronics (619)565-4800. . . Future Electronics (619)625-2800. . . . . . . . . . . . Hamilton Hallmark (619)571-7540. . . . . . . . . . . . Newark (619)453-8211. . . . . . . . . . . . . . . . . . . . . . Wyle Laboratories (619)565-9171. . . . . . . . . . . .

San JoseArrow/Schweber Electronics (408)441-9700. . . . Arrow/Schweber Electronics (408)428-6400. . . . Future Electronics (408)434-1122. . . . . . . . . . . . .

Santa ClaraWyle Laboratories (408)727-2500. . . . . . . . . . . .

SunnyvaleHamilton Hallmark (408)435-3500. . . . . . . . . . . . Time Electronics 1-800-789-TIME. . . . . . . . . . . .

TorranceTime Electronics 1-800-789-TIME. . . . . . . . . . . .

TustinTime Electronics 1-800-789-TIME. . . . . . . . . . . .

West HillsNewark (818)888-3718. . . . . . . . . . . . . . . . . . . . .

Woodland HillsHamilton Hallmark (818)594-0404. . . . . . . . . . . . Richardson Electronics (615)594-5600. . . . . . .

COLORADOLakewood

Future Electronics (303)232-2008. . . . . . . . . . . . Denver

Newark (303)757-3351. . . . . . . . . . . . . . . . . . . . . Englewood

Arrow/Schweber Electronics (303)799-0258. . . . Hamilton Hallmark (303)790-1662. . . . . . . . . . . Time Electronics 1-800-789-TIME. . . . . . . . . . . .

ThorntonWyle Laboratories (303)457-9953. . . . . . . . . . . .

CONNECTICUTBloomfield

Newark (203)243-1731. . . . . . . . . . . . . . . . . . . . . Chesire

Future Electronics (203)250-0083. . . . . . . . . . . . Hamilton Hallmark (203)271-2844. . . . . . . . . . .

SouthburyTime Electronics 1-800-789-TIME. . . . . . . . . . . .

WallingfortArrow/Schweber Electronics (203)265-7741. . . .

FLORIDAAltamonte Springs

Future Electronics (407)767-8414. . . . . . . . . . . . Clearwater

Future Electronics (813)530-1222. . . . . . . . . . . . Deerfield Beach

Arrow/Schweber Electronics (305)429-8200. . . . Wyle Laboratories (305)420-0500. . . . . . . . . . . .

Ft. LauderdaleFuture Electronics (305)436-4043. . . . . . . . . . . . Hamilton Hallmark (305)484-5482. . . . . . . . . . . . Time Electronics 1-800-789-TIME. . . . . . . . . . . .

Lake MaryArrow/Schweber Electronics (407)333-9300. . . .

Largo/Tampa/St. PetersburgHamilton Hallmark (813)541-7440. . . . . . . . . . . . Newark (813)287-1578. . . . . . . . . . . . . . . . . . . . . Wyle Laboratories (813)576-3004. . . . . . . . . . . .

OrlandoNewark (407)896-8350. . . . . . . . . . . . . . . . . . . . . Time Electronics 1-800-789-TIME. . . . . . . . . . . .

PlantationNewark (305)424-4400. . . . . . . . . . . . . . . . . . . . .

Winter ParkHamilton Hallmark (407)657-3300. . . . . . . . . . . Richardson Electronics (407)644-1453. . . . . . .

GEORGIAAtlanta

Time Electronics 1-800-789-TIME. . . . . . . . . . . . Wyle Laboratories (404)441-9045. . . . . . . . . . . .

DuluthArrow/Schweber Electronics (404)497-1300. . . . Hamilton Hallmark (404)623-5475. . . . . . . . . . .

NorcrossFuture Electronics (404)441-7676. . . . . . . . . . . . Newark (404)448-1300. . . . . . . . . . . . . . . . . . . . . Wyle Laboratories (404)441-9045. . . . . . . . . . . .

ILLINOISAddison

Wyle Laboratories (708)620-0969. . . . . . . . . . . . Bensenville

Hamilton Hallmark (708)860-7780. . . . . . . . . . . . Chicago

Newark Electronics Corp. (312)784-5100. . . . . Hoffman Estates

Future Electronics (708)882-1255. . . . . . . . . . . .

ItascaArrow/Schweber Electronics (708)250-0500. . .

LaFoxRichardson Electronics (708)208-2401. . . . . . .

SchaumburgNewark (708)310-8980. . . . . . . . . . . . . . . . . . . . . Time Electronics 1-800-789-TIME. . . . . . . . . . . .

INDIANAIndianapolis

Arrow/Schweber Electronics (317)299-2071. . . . Hamilton Hallmark (317)872-8875. . . . . . . . . . . Newark (317)259-0085. . . . . . . . . . . . . . . . . . . . . Time Electronics 1-800-789-TIME. . . . . . . . . . . .

Ft. WayneNewark (219)484-0766. . . . . . . . . . . . . . . . . . . . .

IOWACedar Rapids

Newark (319)393-3800. . . . . . . . . . . . . . . . . . . . . Time Electronics 1-800-789-TIME. . . . . . . . . . . .

KANSASLenexa

Arrow/Schweber Electronics (913)541-9542. . . . Hamilton Hallmark (913)888-4747. . . . . . . . . . .

Overland ParkFuture Electronics (913)649-1531. . . . . . . . . . . . Newark (913)677-0727. . . . . . . . . . . . . . . . . . . . . Time Electronics 1-800-789-TIME. . . . . . . . . . . .

MARYLANDColumbia

Arrow/Schweber Electronics (301)596-7800. . . . Future Electronics (410)290-0600. . . . . . . . . . . . Hamilton Hallmark (410)988-9800. . . . . . . . . . . Time Electronics 1-800-789-TIME. . . . . . . . . . . . Wyle Laboratories (410)312-4844. . . . . . . . . . . .

HanoverNewark (410)712-6922. . . . . . . . . . . . . . . . . . . . .

MASSACHUSETTSBoston

Arrow/Schweber Electronics (617)271-9953. . . . Bolton

Future Corporate (508)779-3000. . . . . . . . . . . . . Burlington

Wyle Laboratories (617)271-9953. . . . . . . . . . . . Norwell

Richardson Electronics (617)871-5162. . . . . . . Peabody

Time Electronics 1-800-789-TIME. . . . . . . . . . . . Hamiltion Hallmark (508)532-3701. . . . . . . . . . .

WoburnNewark (617)935-8350. . . . . . . . . . . . . . . . . . . . .

MICHIGANDetroit

Newark (313)967-0600. . . . . . . . . . . . . . . . . . . . . Grand Rapids

Future Electronics (616)698-6800. . . . . . . . . . . . Livonia

Arrow/Schweber Electronics (313)462-2290. . . . Future Electronics (313)261-5270. . . . . . . . . . . . Hamilton Hallmark (313)347-4020. . . . . . . . . . . Time Electronics 1-800-789-TIME. . . . . . . . . . . .

MINNESOTABloomington

Wyle Laboratories (612)853-2280. . . . . . . . . . . . . Eden Prairie

Arrow/Schweber Electronics (612)941-5280. . . . Future Electronics (612)944-2200. . . . . . . . . . . . Hamilton Hallmark (612)881-2600. . . . . . . . . . . Time Electronics 1-800-789-TIME. . . . . . . . . . . .

MinneapolisNewark (612)331-6350. . . . . . . . . . . . . . . . . . . . .

Earth CityHamilton Hallmark (314)291-5350. . . . . . . . . . .


3/1/95

AUTHORIZED DISTRIBUTORS – continued

UNITED STATES – continuedMISSOURI

St. LouisArrow/Schweber Electronics (314)567-6888. . . . Future Electronics (314)469-6805. . . . . . . . . . . . Newark (314)298-2505. . . . . . . . . . . . . . . . . . . . . Time Electronics 1-800-789-TIME. . . . . . . . . . . .

NEW JERSEYCherry Hill

Hamilton Hallmark (609)424-0100. . . . . . . . . . . . East Brunswick

Newark (908)937-6600. . . . . . . . . . . . . . . . . . . . . Marlton

Arrow/Schweber Electronics (609)596-8000. . . . Future Electronics (609)596-4080. . . . . . . . . . . .

PinebrookArrow/Schweber Electronics (201)227-7880. . . . Wyle Laboratories (201)882-8358. . . . . . . . . . . .

ParsippanyFuture Electronics (201)299-0400. . . . . . . . . . . . Hamilton Hallmark (201)515-1641. . . . . . . . . . .

WayneTime Electronics 1-800-789-TIME. . . . . . . . . . . .

NEW MEXICOAlbuquerque

Alliance Electronics (505)292-3360. . . . . . . . . . Hamilton Hallmark (505)828-1058. . . . . . . . . . . . Newark (505)828-1878. . . . . . . . . . . . . . . . . . . . .

NEW YORKCommack

Newark (516)499-1216. . . . . . . . . . . . . . . . . . . . . Hauppauge

Arrow/Schweber Electronics (516)231-1000. . . . Future Electronics (516)234-4000. . . . . . . . . . . . Hamilton Hallmark (516)434-7400. . . . . . . . . . .

KonkomaHamilton Hallmark (516)737-0600. . . . . . . . . . .

MelvilleWyle Laboratories (516)293-8446. . . . . . . . . . . .

PittsfordNewark (716)381-4244. . . . . . . . . . . . . . . . . . . . .

RochesterArrow/Schweber Electronics (716)427-0300. . . . Future Electronics (716)272-1120. . . . . . . . . . . . . Hamilton Hallmark (716)475-9130. . . . . . . . . . . . Richardson Electronics (716)264-1100. . . . . . . . Time Electronics 1-800-789-TIME. . . . . . . . . . . .

Rockville CentreRichardson Electronics (516)872-4400. . . . . . .

SyracuseFuture Electronics (315)451-2371. . . . . . . . . . . . Time Electronics 1-800-789-TIME. . . . . . . . . . . .

NORTH CAROLINACharlotte

Future Electronics (704)455-9030. . . . . . . . . . . . Richardson Electronics (704)548-9042. . . . . . .

RaleighArrow/Schweber Electronics (919)876-3132. . . . Future Electronics (919)790-7111. . . . . . . . . . . . . Hamilton Hallmark (919)872-0712. . . . . . . . . . . Newark (919)781-7677. . . . . . . . . . . . . . . . . . . . . Time Electronics 1-800-789-TIME. . . . . . . . . . . .

OHIOCenterville

Arrow/Schweber Electronics (513)435-5563. . . . Cleveland

Newark (216)391-9330. . . . . . . . . . . . . . . . . . . . . Time Electronics 1-800-789-TIME. . . . . . . . . . . .

ColumbusNewark (614)326-0352. . . . . . . . . . . . . . . . . . . . . Time Electronics 1-800-789-TIME. . . . . . . . . . . .

DaytonFuture Electronics (513)426-0090. . . . . . . . . . . . Hamilton Hallmark (513)439-6735. . . . . . . . . . . Newark (513)294-8980. . . . . . . . . . . . . . . . . . . . . Time Electronics 1-800-789-TIME. . . . . . . . . . . .

Mayfield HeightsFuture Electronics (216)449-6996. . . . . . . . . . . .

SolonArrow/Schweber Electronics (216)248-3990. . . . Hamilton Hallmark (216)498-1100. . . . . . . . . . . .

WorthingtonHamilton Hallmark (614)888-3313. . . . . . . . . . .

OKLAHOMATulsa

Hamilton Hallmark (918)254-6110. . . . . . . . . . . . Newark (918)252-5070. . . . . . . . . . . . . . . . . . . . .

OREGONBeaverton

Arrow/Almac Electronics Corp. (503)629-8090. . Future Electronics (503)645-9454. . . . . . . . . . . . Hamilton Hallmark (503)528-6200. . . . . . . . . . . Wyle Laboratories (503)643-7900. . . . . . . . . . . .

PortlandNewark (503)297-1984. . . . . . . . . . . . . . . . . . . . . Time Electronics 1-800-789-TIME. . . . . . . . . . . .

PENNSYLVANIAFt. Washington

Newark (215)654-1434. . . . . . . . . . . . . . . . . . . . . Mt. Laurel

Wyle Laboratories (609)439-9110. . . . . . . . . . . . . Montgomeryville

Richardson Electronics (215)628-0805. . . . . . . Philadelphia

Time Electronics 1-800-789-TIME. . . . . . . . . . . . Wyle Laboratories (609)439-9110. . . . . . . . . . . . .

PittsburghArrow/Schweber Electronics (412)963-6807. . . . Newark (412)788-4790. . . . . . . . . . . . . . . . . . . . . Time Electronics 1-800-789-TIME. . . . . . . . . . . .

TENNESSEEFranklin

Richardson Electronics (615)791-4900. . . . . . . Knoxville

Newark (615)588-6493. . . . . . . . . . . . . . . . . . . . .

TEXASAustin

Arrow/Schweber Electronics (512)835-4180. . . . Future Electronics (512)502-0991. . . . . . . . . . . . Hamilton Hallmark (512)258-8818. . . . . . . . . . . Newark (512)338-0287. . . . . . . . . . . . . . . . . . . . . Time Electronics 1-800-789-TIME. . . . . . . . . . . . Wyle Laboratories (512)345-8853. . . . . . . . . . . .

CarolltonArrow/Schweber Electronics (214)380-6464. . . .

DallasFuture Electronics (214)437-2437. . . . . . . . . . . . Hamilton Hallmark (214)553-4300. . . . . . . . . . . Richardson Electronics (214)239-3680. . . . . . . Time Electronics 1-800-789-TIME. . . . . . . . . . . . Wyle Laboratories (214)235-9953. . . . . . . . . . . .

Ft. WorthAllied Electronics (817)336-5401. . . . . . . . . . . . .

HoustonArrow/Schweber Electronics (713)530-4700. . . . Future Electronics (713)785-1155. . . . . . . . . . . . . Hamilton Hallmark (713)781-6100. . . . . . . . . . . Newark (713)270-4800. . . . . . . . . . . . . . . . . . . . . Time Electronics 1-800-789-TIME. . . . . . . . . . . . Wyle Laboratories (713)879-9953. . . . . . . . . . . .

RichardsonNewark (214)235-1998. . . . . . . . . . . . . . . . . . . . .

UTAHSalt Lake City

Arrow/Schweber Electronics (801)973-6913. . . . Future Electronics (801)467-4448. . . . . . . . . . . . Hamilton Hallmark (801)266-2022. . . . . . . . . . . . Newark (801)261-5660. . . . . . . . . . . . . . . . . . . . . Wyle Laboratories (801)974–9953. . . . . . . . . . . .

West Valley CityTime Electronics 1-800-789-TIME. . . . . . . . . . . . Wyle Laboratories (801)974-9953. . . . . . . . . . . .

WASHINGTONBellevue

Almac Electronics Corp. (206)643-9992. . . . . . Newark (206)641-9800. . . . . . . . . . . . . . . . . . . . . Richardson Electronics (206)646-7224. . . . . . .

BothellFuture Electronics (206)489-3400. . . . . . . . . . . .

RedmondHamilton Hallmark (206)881-6697. . . . . . . . . . . . Time Electronics 1-800-789-TIME. . . . . . . . . . . . Wyle Laboratories (206)881-1150. . . . . . . . . . . . .

SeattleWyle Laboratories. (206)881-1150. . . . . . . . . . . . .

SpokaneArrow/Almac Electronics Corp. (509)924-9500. .

WISCONSINBrookfield

Arrow/Schweber Electronics (414)792-0150. . . . Future Electronics (414)879-0244. . . . . . . . . . . .

MilwaukeeTime Electronics 1-800-789-TIME. . . . . . . . . . . .

New BerlinHamilton Hallmark (414)780-7200. . . . . . . . . . .

WauwatosaNewark (414)453-9100. . . . . . . . . . . . . . . . . . . . .

WaukeshaWyle Laboratories (414)879-0434. . . . . . . . . . . .

CANADAALBERTA

CalgaryElectro Sonic Inc. (403)255-9550. . . . . . . . . . . Future Electronics (403)250-5550. . . . . . . . . . . . Hamilton/Hallmark (800)663–5500. . . . . . . . . . . .

EdmontonFuture Electronics (403)438-2858. . . . . . . . . . . . Hamilton/Hallmark (800)663-5500. . . . . . . . . . .

SaskatchewanHamilton/Hallmark (800)663–5500. . . . . . . . . . .

BRITISH COLUMBIAVancouver

Arrow Electronics (604)421-2333. . . . . . . . . . . . Electro Sonic Inc. (604)273-2911. . . . . . . . . . . . . Future Electronics (604)294-1166. . . . . . . . . . . . . Hamilton/Hallmark (604)420-4101. . . . . . . . . . . .

MANITOBAWinnipeg

Electro Sonic Inc. (204)783-3105. . . . . . . . . . . Future Electronics (204)944-1446. . . . . . . . . . . . Hamilton/Hallmark (800)663-5500. . . . . . . . . . . .

ONTARIOOttawa

Arrow Electronics (613)226-6903. . . . . . . . . . . . Electro Sonic Inc. (613)728-8333. . . . . . . . . . . . Future Electronics (613)820-8313. . . . . . . . . . . . Hamilton/Hallmark (613)226-1700. . . . . . . . . . . .

TorontoArrow Electronics (905)670-7769. . . . . . . . . . . . Electro Sonic Inc. (416)494-1666. . . . . . . . . . . . Future Electronics (905)612-9200. . . . . . . . . . . . Hamilton Hallmark (905)564-6060. . . . . . . . . . . . Newark (519)685–4280. . . . . . . . . . . . . . . . . . . . .

(905)670–2888(800)463–9275

Richardson Electronics (905)795–6300. . . . . . . FAI (905)612–9888. . . . . . . . . . . . . . . . . . . . . . . . .

QUEBECMontreal

Arrow Electronics (514)421-7411. . . . . . . . . . . . . Future Electronics (514)694-7710. . . . . . . . . . . . Hamilton Hallmark (514)335-1000. . . . . . . . . . . . Newark (800)463-9275. . . . . . . . . . . . . . . . . . . . . Richardson Electronics (514)748–1770. . . . . . .

Quebec CityFuture Electronics (418)877-6666. . . . . . . . . . . .


3/1/95

SALES OFFICESUNITED STATESALABAMA, Huntsville (205)464-6800. . . . . .

ALASKA, (800)635-8291. . . . . . . . . . . . . . . . .

ARIZONA, Tempe (602)302-8056. . . . . . . . . .

CALIFORNIA, Agoura Hills (818)706-1929. . .

CALIFORNIA, Los Angeles (310)417-8848. .

CALIFORNIA, Irvine (714)753-7360. . . . . . . .

CALIFORNIA, San Diego (619)541-2163. . . .

CALIFORNIA, Sunnyvale (408)749-0510. . . .

COLORADO,Colorado Springs (719)599-7497. . . . . . . . . .

COLORADO, Denver (303)337-3434. . . . . . .

CONNECTICUT,Wallingford (203)949-4100. . . . . . . . . . . . . . .

FLORIDA, Maitland (407)628-2636. . . . . . . . .

FLORIDA, Pompano Beach/Ft. Lauderdale (305)351-6040. . . . . . . . . . . .

FLORIDA, Clearwater (813)538-7750. . . . . .

GEORGIA, Atlanta (404)729-7100. . . . . . . . .

IDAHO, Boise (208)323-9413. . . . . . . . . . . . . .

ILLINOIS, Chicago/Hoffman Estates (708)413-2500. . . . . . . . . . Shaumburg (708)413-2500. . . . . . . . . . . . . .

INDIANA, Fort Wayne (219)436-5818. . . . . .

INDIANA, Indianapolis (317)571-0400. . . . . .

INDIANA, Kokomo (317)455-5100. . . . . . . . .

IOWA, Cedar Rapids (319)378-0383. . . . . . .

KANSAS, Kansas City/Mission (913)451-8555. . . . . . . . . . . . . . . . . .

MARYLAND, Columbia (410)381-1570. . . . .

MASSACHUSETTS, Marlborough (508)481-8100. . . . . . . . . . . . . .

MASSACHUSETTS,Woburn (617)932-9700. . . . . . . . . . . . . . . . . .

MICHIGAN, Detroit (313)347-6800. . . . . . . . .

MINNESOTA, Minnetonka (612)932-1500. . . .

MISSOURI, St. Louis (314)275-7380. . . . . . .

NEW JERSEY, Fairfield (201)808-2400. . . . .

NEW YORK, Fairport (716)425-4000. . . . . . .

NEW YORK, Hauppauge (516)361-7000. . . .

NEW YORK, Fishkill (914)896-0511. . . . . . . .

NORTH CAROLINA,Raleigh (919)870-4355. . . . . . . . . . . . . . . . . .

OHIO, Cleveland (216)349-3100. . . . . . . . . . .

OHIO, Columbus/

Worthington (614)431-8492. . . . . . . . . . . . . .

OHIO, Dayton (513)495-6800. . . . . . . . . . . . . .

OKLAHOMA, Tulsa (800)544-9496. . . . . . . .

OREGON, Portland (503)641-3681. . . . . . . . .

PENNSYLVANIA, Colmar (215)997-1020. . . .

Philadelphia/Horsham (215)957-4100. . . . .

TENNESSEE, Knoxville (615)690-5593. . . . .

TEXAS, Austin (512)502-2100. . . . . . . . . . . . . TEXAS, Houston (800)343-2692. . . . . . . . . . .

TEXAS, Plano (214)516-5100. . . . . . . . . . . . .

TEXAS, Seguin (210)372-7620. . . . . . . . . . . .

VIRGINIA, Richmond (804)285-2100. . . . . . .

UTAH, CSI @ (801)561-5099. . . . . . . . . . . . . .

WASHINGTON, Bellevue (206)454-4160. . . .

Seattle Access (206)622-9960. . . . . . . . . . .

WISCONSIN, Milwaukee/Brookfield (414)792-0122. . . . . . . . . . . . . . . .

Field Applications Engineering AvailableThrough All Sales Offices

CANADABRITISH COLUMBIA,

Vancouver (604)293-7650. . . . . . . . . . . . . . . .

ONTARIO, Toronto (416)497-8181. . . . . . . . .

ONTARIO, Ottawa (613)226-3491. . . . . . . . . .

QUEBEC, Montreal (514)333-3300. . . . . . . . .

INTERNATIONALAUSTRALIA, Melbourne (61-3)887-0711. . .

AUSTRALIA, Sydney 61(2)906-3855. . . . . . .

BRAZIL, Sao Paulo 55(11)815-4200. . . . . . .

CHINA, Beijing 86-505-2180. . . . . . . . . . . . . .

FINLAND, Helsinki 358-0-351 61191. . . . . . .

car phone 358(49)211501. . . . . . . . . . . . . . .

FRANCE, Paris 33134 635900. . . . . . . . . . . .

GERMANY, Langenhagen/

Hannover 49(511)786880. . . . . . . . . . . . . . .

GERMANY, Munich 49 89 92103-0. . . . . . . . .

GERMANY, Nuremberg 49 911 96-3190. . . .

GERMANY, Sindelfingen 49 7031 79 710. . . .

GERMANY, Wiesbaden 49 611 973050. . . . .

HONG KONG, Kwai Fong 852-6106888. . . .

Tai Po 852-6668333. . . . . . . . . . . . . . . . . . . . INDIA, Bangalore (91-812)627094. . . . . . . . .

ISRAEL, Herzlia 972–9–590222. . . . . . . . . .

ITALY, Milan 39(2)82201. . . . . . . . . . . . . . . . .

JAPAN, Fukuoka 81-92–725–7583. . . . . . . . .

JAPAN, Gotanda 81-3-5487-8311. . . . . . . . . .

JAPAN, Nagoya 81-52-232-3500. . . . . . . . . .

JAPAN, Osaka 81-6-305-1802. . . . . . . . . . . . .

JAPAN, Sendai 81-22-268-4333. . . . . . . . . . .

JAPAN, Takamatsu 81-878-37-9972. . . . . . . .

JAPAN, Tokyo 81-3-3440-3311. . . . . . . . . . . .

KOREA, Pusan 82(51)4635-035. . . . . . . . . . .

KOREA, Seoul 82(2)554-5118. . . . . . . . . . . . .

MALAYSIA, Penang 60(4)374514. . . . . . . . .

MEXICO, Mexico City 52(5)282-0230. . . . . . .

MEXICO, Guadalajara 52(36)21-8977. . . . . .

Marketing 52(36)21-2023. . . . . . . . . . . . . . . .

Customer Service 52(36)669-9160. . . . . . . .

NETHERLANDS, Best (31)4998 612 11. . . .

PUERTO RICO, San Juan (809)793-2170. . .

SINGAPORE (65)4818188. . . . . . . . . . . . . . .

SPAIN, Madrid 34(1)457-8204. . . . . . . . . . . . .

or 34(1)457-8254. . . . . . . . . . . . . . . . . . . . . . .

SWEDEN, Solna 46(8)734-8800. . . . . . . . . . .

SWITZERLAND, Geneva 41(22)799 11 11. .

SWITZERLAND, Zurich 41(1)730-4074. . . . .

TAIWAN, Taipei 886(2)717-7089. . . . . . . . . . .

THAILAND, Bangkok 66(2)254-4910. . . . . . .

UNITED KINGDOM, Aylesbury 44(296)395-252. . . . . . . . . . . . . . .

FULL LINE REPRESENTATIVESCALIFORNIA , Loomis

Galena Technology Group (916)652-0268. . .

NEVADA, Reno

Galena Tech. Group (702)746-0642. . . . . . .

NEW MEXICO, Albuquerque

S&S Technologies, Inc. (505)298-7177. . . .

UTAH, Salt Lake City

Utah Comp. Sales, Inc. (801)561-5099. . . . .

WASHINGTON, Spokane

Doug Kenley (509)924-2322. . . . . . . . . . . . .

HYBRID/MCM COMPONENTSUPPLIERS

Chip Supply (407)298-7100. . . . . . . . . . . . . . .

Elmo Semiconductor (818)768-7400. . . . . . . .

Minco Technology Labs Inc. (512)834-2022. .

Semi Dice Inc. (310)594-4631. . . . . . . . . . . . .


3/1/95

SALES OFFICESINTERNATIONAL MOTOROLA DISTRIBUTOR AND SALES OFFICES

AUTHORIZED DISTRIBUTORSAUSTRALIA

VSI Electronics (NZ) Ltd (64)9 579-6603. . . . . . . . VSI Promark Elec. Pty Ltd (61)2 439-4655. . . . . . . Veltek Pty Ltd (61)3 808-7511. . . . . . . . . . . . . . . . .

AUSTRIAEBV Austria (43) 222 894 1774. . . . . . . . . . . . . . . . Elbatex GmbH (43) 222 86 3211. . . . . . . . . . . . . . .

BENELUXDiode Belgium (32) 2 725 4660. . . . . . . . . . . . . . . Diode Components BV (31) 340 29 1234. . . . . . . EBV Belgium (32) 2 720 9936. . . . . . . . . . . . . . . . . EBV Holland (31) 3465 623 53. . . . . . . . . . . . . . . . Rodelco Electronics (31) 767 84911. . . . . . . . . . . . Rodelco N.V. (32) 2 460 0560. . . . . . . . . . . . . . . . .

CHINAAdvanced Electronics Ltd. (852)305-3633. . . . . . China El. App. Corp. Xiamen Co. (86)592 553-487. . Nanco Electronics Supply Ltd. (852) 333-5121. . . . . Qing Cheng Enterprises Ltd. (852) 493-4202. . . .

DENMARKAvnet Nortec A/S Denmark (45) 428 42000. . . . . . EBV Denmark (45) 398 905 11. . . . . . . . . . . . . . . . .

FINLANDArrow Field OY (35) 807 775 71. . . . . . . . . . . . . . .

FRANCEArrow Electronique (33) 1 49 78 49 78. . . . . . . . . . Avnet Components (33) 1 49 65 25 00. . . . . . . . . . EBV France (33) 1 64 68 86 00. . . . . . . . . . . . . . . . Scaib (33) 1 46 87 23 13. . . . . . . . . . . . . . . . . . . . .

GERMANYAvnet E2000 (49) 89 4511001. . . . . . . . . . . . . . . . . EBV Germany (49) 89 456100. . . . . . . . . . . . . . . . . Future Electronics GmbH (49) 89-957 195-0. . . . . Jermyn GmbH (49) 6431-5080. . . . . . . . . . . . . . . . . Muetron, Mueller

GmbH & Co. (49) 421-305 60. . . . . . . . . . . . . . . Sasco GmbH (49) 89-46110. . . . . . . . . . . . . . . . . . . Spoerle Electronic (49) 6103-304-0. . . . . . . . . . . .

HONG KONGNanshing Clr. & Chem. Co. Ltd (852) 333-5121. . . . Wong’s Kong King Semi. Ltd. (852) 357-8888. . . .

INDIACanyon Products Ltd (852) 755-2583. . . . . . . . . . .

ITALYAvnet Adelsy SpA (39) 2 38103100. . . . . . . . . . . . EBV Italy (39) 2 66017111. . . . . . . . . . . . . . . . . . . . Silverstar SpA (39) 2 66 12 51. . . . . . . . . . . . . . . . .

JAPANAMSC Co., Ltd. 81-422-54-6800. . . . . . . . . . . . . . . Marubun Corporation 81-3-3639-8951. . . . . . . . . . OMRON Corporation 81-3-3779–9053. . . . . . . . . . Fuji Electronics Co., Ltd. 81-3-3814-1411. . . . . . . Tokyo Electron Ltd. 81-3-5561–7254. . . . . . . . . . . Nippon Motorola Micro Elec. 81-3-3280-7300. . . . .

KOREALite-On Korea Ltd. (82)2 858-3853. . . . . . . . . . . . . Lee Ma Industrial Co. Ltd. (82)2 739-5257. . . . . . . Jung Kwang Sa (82)51 802-2153. . . . . . . . . . . . . .

NORWAYAvnet Nortec A/S Norway (47) 6 664 6210. . . . . .

SCANDINAVIAITT Multikomponent AB (46) 8 830 020. . . . . . . . . . Avnet Nortec (S) (46) 8 705 1800. . . . . . . . . . . . . . Avnet Nortec (DK) (45) 42 842 000. . . . . . . . . . . . Avnet Nortec (N) (47) 6 684 210. . . . . . . . . . . . . . . .

SINGAPOREAlexan Commercial (63)2 405-952. . . . . . . . . . . . . GEIC (65) 298-7633. . . . . . . . . . . . . . . . . . . . . . . . . P.T. Ometraco (62)22 630-805. . . . . . . . . . . . . . . . . Uraco Impex Asia Pte Ltd. (65)5457811. . . . . . . . Shapiphat Ltd. (66)2 221-5384. . . . . . . . . . . . . . . . .

SPAINAmitron Arrow (34) 1 304 30 40. . . . . . . . . . . . . . . . EBV Spain (34) 9 358 86 08. . . . . . . . . . . . . . . . . . . Selco S.A. (34) 1 359 43 48. . . . . . . . . . . . . . . . . . .

SWEDENAvnet Nortec AB (48) 8 629 14 00. . . . . . . . . . . . . .

SWITZERLANDEBV Switzerland (41) 1 740 10 90. . . . . . . . . . . . . . Elbatex AG (41) 56 275 165. . . . . . . . . . . . . . . . . .

TAIWANMercuries & Assoc. Ltd (886)2 503-1111. . . . . . . Solomon Technology Corp. (886)2 760-5858. . . . . Strong Electronics Co. Ltd. (886)2 917-9917. . . . . .

UNITED KINGDOMArrow Electronics (UK) Ltd (44) 234 272733. . . . . Avnet/Access (44) 462 480888. . . . . . . . . . . . . . . . Future Electronics Ltd. (44) 753 687000. . . . . . . . Macro Marketing Ltd. (44) 628 604 383. . . . . . . . .

CANADAAll Provinces – Newark (800)463-9275. . . . . . . . .

ALBERTACalgary

Electro Sonic Inc. (403)255-9550. . . . . . . .

Future Electronics (403)250-5550. . . . . . . . . Hamilton/Hallmark (800)663–5500. . . . . . . .

EdmontonFuture Electronics (403)438-2858. . . . . . . . . Hamilton/Hallmark (800)663-5500. . . . . . . .

SaskatchewanHamilton/Hallmark (800)663–5500. . . . . . . .

BRITISH COLUMBIAVancouver

Arrow Electronics (604)421–2333. . . . . . . . . Electro Sonic Inc. (604)273–2911. . . . . . . . . Future Electronics (604)294-1166. . . . . . . . . . Hamilton/Avnet Electronics (604)420-4101.

MANITOBAWinnipeg

Electro Sonic Inc. (209)783-3105. . . . . . . . Future Electronics (204)944-1446. . . . . . . . . Hamilton/Hallmark (800)663–5500. . . . . . . .

ONTARIOOttawa

Arrow Electronics (613)226-6903. . . . . . . . . Electro Sonic Inc. (613)728-8333. . . . . . . . . Future Electronics (613)820-8313. . . . . . . . . Hamilton/Hallmark (613)226-1700. . . . . . . .

TorontoArrow Electronics (416)670-7769. . . . . . . . . Electro Sonic Inc. (416)494-1666. . . . . . . . . Future Electronics (905)612–9200. . . . . . . . . Hamilton/Hallmark (905)564–6060. . . . . . . . Newark (519)685–4280. . . . . . . . . . . . . . . . . .

(905)670–2888Richardson Electronics (905)795–6300. . . . FAI (905)612–9888. . . . . . . . . . . . . . . . . . . . . .

QUEBECMontreal

Arrow Electronics (514)421-7411. . . . . . . . . . Future Electronics (514)694-7710. . . . . . . . . Hamilton/Hallmark (514)335-1000. . . . . . . . Richardson (514)748–1770. . . . . . . . . . . . . . .

Quebec CityArrow Electronics (418)687-4231. . . . . . . . . Future Electronics (418)682-8092. . . . . . . . .

St. LaurentRichardson Electronics (514)748-1770. . . .

SALES OFFICESCANADABRITISH COLUMBIA, Vancouver (604)293-7650. . . . ONTARIO, Toronto (416)497-8181. . . . . . . . . . . . . . ONTARIO, Ottawa (613)226-3491. . . . . . . . . . . . . . . QUEBEC, Montreal (514)333-3300. . . . . . . . . . . . . . INTERNATIONALAUSTRALIA, Melbourne (61-3)887-0711. . . . . . . . . AUSTRALIA, Sydney 61(2)906-3855. . . . . . . . . . . . BRAZIL, Sao Paulo 55(11)815-4200. . . . . . . . . . . . . CHINA, Beijing 86-505-2180. . . . . . . . . . . . . . . . . . . . CHINA, Guangzhou (86) 20 331-1626. . . . . . . . . . . CHINA, Shanghai (86) 21 279-8206. . . . . . . . . . . . . CHINA, Singapore (65) 481-8188. . . . . . . . . . . . . . . . CHINA, Tianjin (86) 22 506-972. . . . . . . . . . . . . . . . . FINLAND, Helsinki 358-0-351 61191. . . . . . . . . . . . .

car phone 358(49)211501. . . . . . . . . . . . . . . . . . . . . FRANCE, Paris 33134 635900. . . . . . . . . . . . . . . . . . GERMANY, Langenhagen/

Hannover 49(511)786880. . . . . . . . . . . . . . . . . . . . . GERMANY, Munich 49 89 92103-0. . . . . . . . . . . . . . . GERMANY, Nuremberg 49 911 96-3190. . . . . . . . . . GERMANY, Sindelfingen 49 7031 79 710. . . . . . . . . GERMANY, Wiesbaden 49 611 973050. . . . . . . . . . HONG KONG, Kwai Fong 852-6106888. . . . . . . . . .

Tai Po 852-6668333. . . . . . . . . . . . . . . . . . . . . . . . . . INDIA, Bangalore (91-812)627094. . . . . . . . . . . . . . ISRAEL, Herzlia 972–9–590222. . . . . . . . . . . . . . . . ITALY, Milan 39(2)82201. . . . . . . . . . . . . . . . . . . . . . . JAPAN, Fukuoka 81-92–725–7583. . . . . . . . . . . . . . JAPAN, Gotanda 81-3-5487-8311. . . . . . . . . . . . . . . JAPAN, Nagoya 81-52-232-3500. . . . . . . . . . . . . . . JAPAN, Osaka 81-6-305-1802. . . . . . . . . . . . . . . . . . JAPAN, Sendai 81-22-268-4333. . . . . . . . . . . . . . . . JAPAN, Takamatsu 81-878-37-9972. . . . . . . . . . . . . JAPAN, Tokyo 81-3-3440-3311. . . . . . . . . . . . . . . . . KOREA, Pusan 82(51)4635-035. . . . . . . . . . . . . . . .

KOREA, Seoul 82(2)554-5118. . . . . . . . . . . . . . . . . . . MALAYSIA, Penang 60(4)374514. . . . . . . . . . . . . . . MEXICO, Mexico City 52(5)282-0230. . . . . . . . . . . . MEXICO, Guadalajara 52(36)21-8977. . . . . . . . . . .

Marketing 52(36)21-2023. . . . . . . . . . . . . . . . . . . . . Customer Service 52(36)669-9160. . . . . . . . . . . .

NETHERLANDS, Best (31)4998 612 11. . . . . . . . . . PHILIPPINES, Manila (63)2 822-0625. . . . . . . . . . . . PUERTO RICO, San Juan (809)793-2170. . . . . . . . SINGAPORE (65)4818188. . . . . . . . . . . . . . . . . . . . . SPAIN, Madrid 34(1)457-8204. . . . . . . . . . . . . . . . . .

or 34(1)457-8254. . . . . . . . . . . . . . . . . . . . . . . . . . . . SWEDEN, Solna 46(8)734-8800. . . . . . . . . . . . . . . . SWITZERLAND, Geneva 41(22)799 11 11. . . . . . . . SWITZERLAND, Zurich 41(1)730-4074. . . . . . . . . . TAIWAN, Taipei 886(2)717-7089. . . . . . . . . . . . . . . . THAILAND, Bangkok 66(2)254-4910. . . . . . . . . . . . UNITED KINGDOM, Aylesbury 44(296)395-252. . . . .

1Theory and Applications(Chapters 1 thru 9)

2 Selector Guide

3 Data Sheets

4Surface MountPackage Information andTape and Reel Specifications

5Outline Dimensionsand Leadform Options

6Index andCross Reference

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