664 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 9, NO. 6, NOVEMBER 2010

Research Letters

Threshold Voltage Variations Make Full Adders Reliabilities Similar

Walid Ibrahim, Senior Member, IEEE, and Valeriu Beiu, Senior Member, IEEE

Abstract—Addition is the most widely used arithmetic opera-tion in digital applications. The reliability of full adder (FA) cellsis crucial as they affect arithmetic logic and floating-point units, aswell as cache/memory address calculations. This letter studies thereliability of five different FA designs. The analysis starts from thedevice level by estimating the effects threshold voltage variationswill have on the reliability of scaled CMOS transistors. These es-timations will then be used to calculate the reliability of the sumand carry_out signals. This letter will also briefly explore the ef-fects of increasing the reliability of devices and of using gate-levelredundancy schemes on the reliability of FAs.

Index Terms—Adders, Bayesian network (BN), CMOS, reliabil-ity, threshold voltage, variations.

I. INTRODUCTION

ADDITION is by far the most widely used arithmetic op-eration in today’s digital applications. Besides the basic

addition operation, full adder (FA) cells are essential buildingblocks for many other operations including subtraction, mul-tiplication, division, and address calculations. Therefore, theirperformances are crucial, affecting the overall performancesof the systems they are a part of. At the same time, the sus-tained massive growth of the mobile appliances market is push-ing the demand for power-efficient VLSI circuits. This was themain driving force behind many research papers during the lastdecade [1]–[3]. The main design objective of such papers hasconstantly been to create faster FA cells while also reducing theirpower consumption. All of these designs implicitly assumed thatthe gates themselves are reliable (enough); therefore, reliabilitywas never considered as one of the optimization criteria.

The latest ITRS predicts that reliability issues are going tobe one of the greatest threats to scaling [4], which should be-come difficult when going beyond 10 nm as many more “errors[will] arise from the difficulty of providing highly precise di-

Manuscript received March 6, 2010; revised May 26, 2010; accepted July 12,2010. Date of publication August 16, 2010; date of current version November10, 2010. The review of this paper was arranged by Associate EditorD. Hammerstrom.

W. Ibrahim is with the Faculty of IT, United Arab Emirates University, AlAin 17551, Abu Dhabi, UAE, and also with the Department of Systems andComputer Engineering, Carleton University, Ottawa, ON K1S 5B6, Canada(e-mail: walidibr@uaeu.ac.ae).

V. Beiu is with the Faculty of IT, United Arab Emirates University, Al Ain17551, Abu Dhabi, UAE, and also with the School of Computing and In-telligent Systems, University of Ulster, Coleraine BT52 1SA, U.K. (e-mail:vbeiu@uaeu.ac.ae).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TNANO.2010.2066573

mensional control needed to fabricate the devices and also frominterference from the local environment.”

From the process perspective, CMOS scaling has been usedsuccessfully over the last four decades to improve the perfor-mance of VLSI designs. With CMOS geometries shrinkingbelow 32 nm, the available reliability margins are drasticallybeing reduced as the CMOS transistors are introducing larger-and-larger parameter fluctuations/variations [5]. These lead todevice-to-device fluctuations in key parameters, including thethreshold voltage (Vth ) [6].

In this letter, the effect of Vth variations on the reliabilityof five FAs is thoroughly investigated, and two approaches toimprove on their reliability (by improving the reliability at boththe device and the gate levels) are analyzed. The rest of theletter is organized as follows. The state of the art is presentedin Section II. Accurate FA reliability calculations are discussedin Section III, followed by simulation results in Section IV.Concluding remarks are provided in Section V.

II. STATE OF THE ART

Very recently, the reliability of (future) nanoscale FA cellshas attracted the attention of several research teams [7]–[13].The probability transfer matrix technique has been used in [8]and [9] to evaluate the reliability of FAs implemented withquantum-dot cellular automata (QCA). The simulation resultsshowed that the FA should have a probability of failure (PF) lessthan 10−7 in order to reach 99% reliability for a 128-bit ripplecarry adder [8]. This is inline with simulations results from [9],which showed that PFGATE should be below 10−7 in order toachieve 99.999% reliability for a 2-bit adder.

Monte Carlo (MC) simulations have been used in [10] toevaluate the energy and reliability of four different FAs. Theauthors concluded that reliability and energy become closelylinked in ultra-low power regimes and error-aware logic designcan produce a great reduction in energy consumption.

In [11], Choi et al. used binary decision diagram (BDD)to design a new single-electron transistor FA cell. They usedMC simulations to study the sensitivity of the proposed FA toprocess variations. The sensitivity of the proposed FA was alsocompared to the sensitivity of a majority (MAJ) based and athreshold logic gate (TLG)-based FA. The simulation resultsshowed that the BBD FA can tolerate 2.85 times and 4 timesmore background charge variations than the MAJ and the TLGFAs, respectively.

MC simulations were also used by Stanisavljevicet al. [12] to investigate the effect of introducing hardware re-dundancy on the reliability of a standard CMOS (mirrored) 4-bit

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Fig. 1. Four FA implementations: (a) NAND-FA; (b) XOR-FA; (c) MAJ-FA; (d) MIN-FA.

FA consisting of 100 transistors. In their experiments, the au-thors calculated the amount of redundancy required to keep thePF of the 4-bit adder below 10−4 . The simulation results haveshown that a four-layer reliable architecture with fixed and adap-tive thresholds require, respectively, 55% and 80% less redun-dancy than the classical R-fold modular redundancy techniqueto achieve the required reliability threshold (10−4).

Finally, in [13], we have studied and compared the relia-bility of four different FA cells starting from the gate-levelassuming that all the gates have PFGATE = constant. Theresults were extended to the device level by assuming thatPFGATE = 1 − (1 − PFDEV)n , where PFDEV is the device PF,and n is the number of devices a gate has. We concluded thataccurate evaluation of the FAs’ reliability should rely on accu-rate reliability calculation at both the device- and the gate-level.These cannot be obtained by simply estimating the reliabilityat the gate level, considering the number of devices per gate,and should rely on MC simulations and/or on better fault/defectmodels.

III. FULL ADDERS RELIABILITY

As mentioned earlier, accurate reliability calculations at thegate and circuit levels have to rely on very precise calculationsfrom the device level. Recently, we have estimated the prob-abilities of failure of nMOS (PFnMOS ) and pMOS (PFpMOS )transistors due to Vth variations [14], for the 16 and 22 nmpredictive technology models (PTM) for high-performance ap-plications version V2.1, incorporating high-k, metal gate, andstress effects [15]. These estimations were based on recent Vthfluctuations results reported in the literature [6] (using the Glas-gow 3-D atomistic drift-diffusion device simulator).

Here, we built upon these results and use our own Bayesiannetwork (BN)-based tool [16] to accurately calculate the re-liability of five FA cells. BN is an acyclic graph model thatrepresents a set of nodes and their probabilistic dependencies.Each node in the graph has an associated conditional probabilitytable (CPT) that defines the probabilistic relationships betweenall the different input combinations and the node’s output. Itis important to mention that the accuracy of the BN tool de-pends (to a great extend) on how accurate are the CPTs, andthe inference algorithms (e.g., exact versus approximate) usedto calculate the output probabilities.

Our BN tool calculates PFFA in two steps. In the first step, thetool identifies the different types of gates used to implement theFA and calculates their PFGATE very accurately. Starting fromthe gate’s schematic, the BN tool creates a device-level reliabil-

ity model for each gate. The nodes in these models represent theindividual CMOS transistors and the connecting wires. The BNtool uses analytical PFDEV equations (introduced in [14]) to setthe CPT values for each CMOS transistor. Once the reliabilitymodel of a gate is created, the BN tool uses exact BN inferencesto calculate PFGATE , and the expected output signal for eachinput vector applied to the inputs. In the second step, the BNtool creates a reliability model for each FA. The nodes in thesemodels represent the individual gates and their interconnections.The accurate PFGATE obtained in the first step is used to set theCPT of each individual gate, while the applied input vectors areused as evidence variables. Exact BN inference is used (oncemore) to calculate PFFA .

IV. SIMULATION RESULTS

The BN tool discussed earlier was used to evaluate the relia-bility of the classical 28 transistors FA (28T-FA) [18], as well asthe four FA cells, as shown in Fig. 1. Although the BN tool cal-culates PF for all the possible input vectors, only the worst casePF is reported in this study. In case of the 28T-FA, PF28T-FAis calculated in only one step (the first), as this FA is in fact asingle gate of 28 transistors.

Fig. 2 illustrates the expected PF of the five FAs in 22 nmtechnology. Fig. 2(a) reveals that the 28T-FA has the best re-liability performance for the Sum signal. The 28T-FA is 100%better than MAJ-FA, 66% better than the MIN-FA, and 33%better than both the XOR-FA and the NAND-FA. These results arequite different from the results reported in [13], which showedthat MAJ-FA and MIN-FA are always better than the NAND-FAand XOR-FA. This is mainly because the effects of the gates’schematics were neglected in [13]. In case of PFCout , Fig. 2(b)shows that the 28T-FA, MAJ-FA, and MIN-FA have identi-cal PFCout , which is 300% better than NAND-FA, and 200%better than XOR-FA. When the overall PFFA is estimated asPFFA = PFSum + PFCout × PFSum × PFCout , the 28T-FA out-performs MIN-FA by 40%, MAJ-FA and XOR-FA by 60%, andNAND-FA by 100% [see Fig. 2(c)].

The results presented in Fig. 2 show very clearly that Vthvariations will significantly affect the reliability of the five FAswhen bulk CMOS is scaled to 22 nm. Allowing 20% variation atthe input leads to PFFA of about 10−4 . It also shows that the PFFAfor all the five FAs are reasonably similar to one another. Thevery simple explanation for these “kind of uniform” behaviorsis that PFFA is very strongly influenced by the reliability ofthe nMOS transistors (pMOS transistors exhibit smaller Vth

666 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 9, NO. 6, NOVEMBER 2010

Fig. 2. PF of four FA cells at 16 nm: (a) sum signal; (b) carryout (Cout) signal; (c) PFFA .

Fig. 3. RII of MIN-FA when increasing the reliability by: (a) using vN-MUX; (b) increasing VDD ; (c) increasing VDD (by 10%) and using vN-MUX.

variations [14]). This claim can be understood from Fig. 2,where we have also plotted PFnMOS .

The second experiment investigates the effect of introducinggate-level redundancy and/or increasing the reliability at the de-vice level on PFMIN-FA . MIN-FA has been selected as its overallreliability outperforms the other three gate-level FAs. In this ex-periment, the reliability enhancements are estimated using theclassical reliability improvement factor (RII) [17], defined asRII = log(R1)/ log(R2) (where R1 and R2 are the reliabil-ities of the original and the improved MIN-FA, respectively).Fig. 3(a) shows that using MAJ-3 von-Neumann multiplexing(vM-MUX) at the smallest redundancy factor (i.e., RF = 6)will enhance the reliability of MIN-FA by about six orders ofmagnitude at 15% input variations. However, this significantRII diminishes quickly to only two orders of magnitude at 25%input variations. Fig. 3(b) illustrates the effect of gradually in-creasing VDD at 20% input variations. It shows that increasingVDD by (only) 10% will improve PFMIN-FA by four orders ofmagnitude. Finally, Fig. 3(c) compares the effect of introducingvN-MUX (RF = 6), and/or increasing VDD by 10% onPFMIN-FA . It shows that increasing VDD by 10% outperformsvN-MUX (RF = 6), starting from 16% input variations. It alsoshows that using both techniques simultaneously drasticallyboosts the RII (by 11 and 4 orders of magnitude at 20% and30% input variations, respectively).

V. CONCLUSION

The results we have presented show that none of the five FAcells analyzed has a major reliability advantage over the otherFAs. This behavior is due to the fact that they all rely on the same(sensitive/unreliable) CMOS transistors. Therefore, it seems thatimproving the reliability at the device level is an essential step,

(much) more effective than relying on different FA designs. Ad-ditionally, redundancy schemes (like, e.g., vN-MUX) could beused at the gate level, but preferably in combination with relia-bility improvements at the device-level (e.g., matching, resizing,VDD adjustments).

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