three-phase phase-lock loop for distorted utilities

Three-phase phase-lock loop for distorted utilities

A.M. Salamah, S.J. Finney and B.W. Williams

Abstract: A novel three-phase phase-locked loop (PLL) structure suitable for phase and angularfrequency derivation from distorted ac utility voltages is presented. The proposed PLL hasa simple structure; a conventional three-phase PLL followed by a proportional-integral (PI)-controlledmoving average filter togetherwith a phase-locking algorithm.The objective of the proposed techniqueis to capture the fundamental phase angle and angular frequency of three-phase clean, distorted,balanced or unbalanced ac utilities. The PLL gives fast, accurate angular frequency and phaselocking and is robust to utility distortion such as line notching, random noise, voltage imbalance,phase loss, phase imbalance, harmonics, dc offsets and frequencyvariation. The analysis presented sub-stantiates the immunity of the proposed PLL to unbalanced and distorted utility conditions. The PLLtechnique is simulated and digital signal processor (DSP)-implemented for a three-phase system toverify the analytical results. The simulated and experimental results, for numerous utility conditions,demonstrate its phase-tracking ability, whereas the conventional technique fails to lock accurately inhighly distorted, three-phase grid-connected operation.

1 Introduction

Phase-lock loops (PLLs) have been extensively used in powersystem, power electronics for some time.Applications includethe generation of thyristor firing angles [1] for high-performance sinusoidal inverters [2]. Numerous approacheshave been proposed on the basis of a variety of techniques,principally, zero-crossing and two-axis transformation [1–6]. Excluding phase loss and high-distortion conditions,good performance is achieved using zero-crossing techniquesfor thyristor-based applications [1, 2]. The performance ofsensitive utility-grid-connected systems such as activefilters, UPS and distributed generation systems depends onthe quality and precision of the utility-voltage information[3, 4]. Zero-crossing techniques fail to meet the sensitivityrequired by such applications [2–4]. Fig. 1 shows thegeneral block diagram of a three-phase, grid-connectedpower converter. The phase angle of the utility-voltagevector is the basic information for most grid-connectedpower conditioning equipment. This information may beused to synchronise the turning on/off of power devices, tocalculate and control the flow of active/reactive power or totransform the feedback variables to a reference frame suitablefor control purposes. Besides utility-interface applications,PLL methods are also used in motor control to estimate theelectrical angular speed of the rotor [5, 6]. The lock qualitydirectly affects the performance of the control loops in thementioned applications. In such applications, accurate, fastdetection of the utility-voltage phase angle is essential inassuring the correct generation of the reference signals.Thus, PLL topologies must handle distorted utility voltagesif intended for applications involving utility-voltage vectortracking [7–11]. The angle information is typically extractedusing some form of PLL [3].

# The Institution of Engineering and Technology 2007

doi:10.1049/iet-epa:20070036

Paper first received 22nd January and in revised form 19th April 2007

The authors are with the Department of Electrical and Electronic Engineering,Strathclyde University, 204 George Street, Royal College Building, Glasgow,G1 1XW, UK

E-mail: [email protected]

IET Electr. Power Appl., 2007, 1, (6), pp. 937–945

Recently there has been increased interest in PLL topolo-gies for grid-connected systems [3–7]. The three-phase PLLdiscussed in [7, 10] uses a synchronous reference frame(SRF) to detect the phase angle, frequency and amplitude ofthe utility-voltage vector. Better SRF PLL performance, forunbalanced utility voltages, is achieved by separating the posi-tive and negative voltage sequences and feeding back only thepositive sequence. The PLL structure introduced in [8] utilisesaweighted least-squaremethod as an alternative to calculatingthe positive and negative utility-voltage sequences; thisimproves PLL tracking performance. An important issue istuning the PI or lead–lag controller used in PLL topologies[9]. Some PLL structures that use the positive sequenceapproach [7–11], fail with some types of distortion, especiallythat typical in three-phase systems (asymmetrical distortionon the three phases). Conventional techniques do not functionaccurately in phase-loss conditions or in a highly distortedenvironment. The random noise, found in the supply voltageor generated bymeasurement devices, has not been previouslyinvestigated. The effect of random noise is detrimental to con-ventional PLL operation.This paper investigates a novel three-phase PLL which

is capable of locking to the phase and frequency of thethree-phase ac supply voltage under distorted conditions(amplitude distortion, frequency distortion, phase distortion,three-phase harmonics and phase loss; all having randomnoise). The PLL analysis, simulation and practical resultswill show that the proposed PLL has a fast, accurate response.

2 Conventional three-phase PLL

The conventional three-phase PLL topology is illustrated inFig. 2 [6]. The instantaneous phase-angle u is detected bysynchronising the PLL rotating reference frame to theutility-voltage vector [5–7]. The PI controller sets thedirect (or quadrature) axis reference voltage Vd (or Vq) tozero. This results in the reference being locked to theutility-voltage vector phase angle. Consequentially, thevoltage vector frequency and amplitude are by products.Tuning of the feedback gains requires determination ofthe equivalent linear model [10].

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It has been shown that this basic PLL is significantlydegraded in the presence of only slight disturbances [12].Other techniques, such as zero crossing and the digitalPLL discussed in [9–11, 13–22], show even poorer per-formance when subjected to slight supply distortion.

3 Proposed three-phase PLL

Fig. 3 shows the block diagram of the proposed three-phasePLL. It has three cascaded stages: a conventional PLL fol-lowed by an average PI controller and a phase locker.Parameters of the conventional PLL are tuned as in [11,12]. The first phase-lock loop uses the supply voltagevector [Va Vb Vc]

T, which is transformed into the d–qframe. The direct voltage component Vd is regulated tozero using a PI controller. For a balanced supply, the con-troller output is the supply voltage angular frequency vwhich after integration gives the supply voltage phase uWith distorted utilities, v and u are distorted proportionallyto the supply distortion level. For applications sensitive to vand u, supply harmonics are filtered, which delays the PLLresponse by at least a few supply cycles. However, somedistortion types require sluggish filters or cannot be cor-rected by filters (phase-loss and phase-angle imbalances).The proposed solution uses a controlled moving averagealgorithm in the process to extract v. The average of vand the first stage output angle u are transferred to aphase locker, where u is recovered from any distortion.

4 Mathematical analysis of the proposed PLL

Mathematical analysis can substantiate that the proposedPLL is capable of locking to distorted three-phase acinputs. The first PLL stage converts the three-phase

Fig. 2 Block diagram of the conventional PLL

Fig. 1 PLL in a three-phase system

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[Va Vb Vc]T, input to d–q components [Vd Vq]

T

Vq

Vd

� �¼ T

Va

Vb

Vc

24

35 (1)

where

T ¼ð2=3Þ cos u �ð1=3Þ cos uþ ð1=

ffiffiffi3

pÞ sin u

ð2=3Þ cos u �ð1=3Þ sin u� ð1=ffiffiffi3

pÞ cos u

"

�ð1=3Þ cos u� ð1=ffiffiffi3

pÞ sin u

�ð1=3Þ sin u� ð1=ffiffiffi3

pÞ cos u

#

and u is the first controller output angle.Let the three-phase input time-variant vector [Va Vb Vc]

T

have the general form

Va

Vb

Vc

24

35 ¼ V

sin u

sin (u� ð2=3Þp)sin (uþ ð2=3Þp)

24

35þ

vavbvc

24

35 (2)

where V and u are the balanced voltage amplitudeand instantaneous phase of the supply waveform and[Va Vb Vc]

T, is an unbalancing voltage vector. Substituting(2) to (1) gives

Vq

Vd

� �¼ V

cos (u� u)þ a(t) cos uþ b(t) sin u

sin (u� u)þ a(t) sin uþ b(t) cos u

� �(3)

where

a(t) ¼2

3na �

1

3nb �

1

3nc and b(t) ¼

1ffiffiffi3

p nb þ1ffiffiffi3

p nc

a(t) and b(t) represent the distortion content of the three-phase ac supply voltage. Since most distortion has a dcshift periodic nature with integer multiples of the funda-mental frequency, a(t) and b(t) are considered dc-shifted(a0, b0) periodic functions with superimposed zero-meanrandom noise, namely

a(t)

b(t)

� �¼

a0 þP

n¼1,2,...

an sin (nvt þ wn)

b0 þP

n¼1,2,...

bn sin (nvt þ gn)

264

375 (4)

For a balanced source, a(t) and b(t) are both zero. Thus thecontroller must minimise (to zero) the direct voltage com-ponent Vd when u ¼ u. Similarly, the controller must mini-mise (to zero) the quadrature voltage component Vq whenu ¼ u+ p/2 (where the sign depends on the three-phasesupply sequence). From (3), for an unbalanced supply,reducing the direct voltage component to zero gives a uerror in the v function of (a(t)sin uþ b(t)cos u), andreducing the quadrature voltage component to zero givesan error function of (a(t)cos uþ b(t)sin u).Generally, distorted v and u can be characterised as

v

u

� �¼

vþP

n¼1,2,...

cn sin (nvt þ 1n)þ j(t)

uþÐ P

n¼1,2,...

cn sin (nvt þ 1n)þ j(t)dt þ cu

264

375(5)

where j(t) is uniform random noise and Cu is the integrationconstant which equals+1/2p if the feedback is Vd and zeroif the feedback is Vq (non-dc terms are influenced by PI set-tings). In (5), the non-dc terms are removed by averaging vover one complete supply cycle. The averaging window size

IET Electr. Power Appl., Vol. 1, No. 6, November 2007

Fig. 3 Proposed three-phase PLL

a Block diagramb PI-controlled averaging block diagramc Phase-locker block diagram of the proposed three-phase PLL

is determined by a PI controller as shown in Fig. 3. Theerror signal e(k), at an instant k, fed to the PI controller isgiven by

e(k) ¼vs

v� window(k � 1) (6)

where vs ¼ 2p /Ts (Ts is the sampling period of the control-ler). The PI controller output represents the next averagingwindow for the average stage. The averaging stage com-putes the average using

�v(k) ¼

Pi¼k

i¼k�window(k�1)

v(i)

window(k � 1), k � window(k � 1) (7)

where window(k) is determined from the PI controlleroutput as

window(k) ¼ window(k � 1)þ kp2(e(k)� e(k � 1))

þ ki2e(k) (8)

where kp2 and ki2 are the controller proportional and integralcoefficients. The average controller algorithm is pro-grammed using MATLAB and the m-file is presented inthe appendix (Section 10). From (4) and (5), the dc


components in the supply (mainly due to measurementand signal-conditioning circuitry) result in distortion in vand u with a frequency equal to that of the fundamental.Thus in worse case, a tuned controller locks to the requiredwindow in one ac supply cycle if the supply contains a dccomponent. Integration of v cannot be used to determinethe phase angle u because the integration constant cudepends on the harmonics and the controller coefficients.Instead, (5) shows that the subtraction of v from v gives,in steady state (v ’ v), the distortion content, ev, in v.That is

ev ¼ v� v (9)

and in steady state

ev ¼X

n¼1,2,...

cn sin (nvt þ 1n)þ j(t) (10)

Integrating the result and then subtracting from u gives u

u ¼ u�

ðev dt � cu (12)

Equation (12) is valid only if the initial integration con-dition is zero, otherwise a dc error appears in the integration

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Fig. 4 Relation between the input total harmonic distortion (THD), PU and vunbalance,udeviation

a, c, e and g Conventional PLLb, d, f and h Proposed PLL

output which is proportional to the initial drift. This dc iseliminated by resetting the integration to zero at the begin-ning of the first cycle, as shown in Fig. 3c. Thus one ac maincycle is needed before valid estimates are available.

5 Parameter selection for the proposed PLL

Parameters kpl and kil are selected using the conventionalmethod mentioned in [9]. For a 220-V, 50-Hz system theoptimum kpl and kil ranges are 30 � kpl � 70 and10 000 � kil � 60 000 kp2 and ki2 selection in (8) for theproposed PLL is based on the required performance and

Table 1: Simulation parameter values used for theconventional PLL and the PI average controller

kp1 30 V/rad

ki1 10 000 V/ (rad.s)

kp2 0.1 rad/s

ki2 0.01 rad/s2

Tk ¼ 1/fk 0.0001 s

940

the maximum permissible supply distortion level. Assumekp2 ¼ 0. Since ki2 changes the averaging window size inproportion to the distortion level, large ki2 values, atcertain distortion levels, may cause the controller to lockto the angular frequency but with undesired behaviour.For example if the window size is halved (for one corre-sponding cycle), the controller output angular frequencywill oscillate around the actual angular frequency. On theother hand, if the window size is doubled (for one corre-sponding cycle), the controller output angular frequencywill lock to the actual angular frequency but in double thesupply period, that is a slower response is obtained. Thuski2 should be as small as possible to maintain the window-size change as follows

jwindow(k)� window(k � 1)j �1

2� windowactual (13)

where windowactual ¼ vs/v. Substituting Ki2 ¼ 0 from (8)in (13) gives

ki2 � e �1

2�vs

v(14)


Fig. 5 Angle simulation for slightly and highly distorted supply

a and b ac supply voltagesc and d Conventional angular frequency outpute and f Proposed angular frequency outputg and h Supply actual phase anglei and j Conventional phase angle output (shifted by a quarter cycle)k and l Proposed phase angle outputm Conventional angular frequency output with minimum PI settings


where e is the maximum window-size error change and isgiven by

e ¼ max{je(i)j}, k � i � k � window(k � 1)

e is a design parameter which depends on the supply distor-tion level and the values of Kpl and Kil. e is estimated fromthe simulation results under worst possible distortion and atmaximum it should be half the window size. On the otherhand, the smaller the ki2, the more sluggish the response.Thus ki2 should be selected to have a reasonable settlingtime. Applications sensitive to the frequency informationmay require a shorter settling time. ki2 is selected to havethe minimum possible settling time, which is one supplycycle. This may show an aggressive response to high distor-tion which compromises the settling time response. For asettling time of one supply cycle, ki2 should be able to com-pensate for the window-size error summation in one cycle,that is

ki2 �Xi¼k


e(i) �1

2�vs

v(15)

Since

e �vs

v�

Xi¼k


e(i) (16)

Table 3: Parameters for high distortion utility

Va 0 . sin(vtþ 10)þ 10 sin(5vtþ 10)

þ 10 sin(7vtþ 10)þ j(t)þ 10

V

Vb 50 sin(vt2 (2/3)p þ10)

þ 10 sin(5vt2 (2/3)p þ10)

þ 10 sin(7vt2 (2/3)pþ10)þ j(t)

þ 20

V

Vc 100 sin(vtþ (2/3)p þ10)

þ 10 sin(5vtþ (2/3)p þ10)

þ 10 sin(7vtþ (2/3)p þ10)þ j(t)

þ 20

V

j(t) uniform random noise, 20 Vpp,

zero mean

V

10 1 rad

v 2 . p . 50 rad/s

Table 2: Parameters for slightly distorted utility

Va 105 sin(vtþ 10)þ 5 sin(5vtþ 10)

þ 1 sin(7vtþ 10)þ j(t)

V

Vb 95 sin(vt2 (2/3)p þ10)

þ 5 sin(5vt2 (2/3)p þ10)

þ 1 sin(7vt2 (2/3)pþ10)þ j(t)

V

Vc 100 sin(vtþ (2/3)p þ10)

þ 5 sin(5vtþ (2/3)p þ10)

þ 1 sin(7vtþ (2/3)p þ10)þ j(t)

V


zero mean

V

10 rad

v 2.p.50 rad/s

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Fig. 6 Simulation output for a transient frequency step change from 50 to 60 Hz and back to 50 Hz; angle simulation for slightly and highlydistorted supply

a and b ac supply voltagesc and d Conventional angular frequency outpute and f Proposed angular frequency outputg and h Supply actual phase anglei and j Conventional phase angle outputk and l Proposed phase angle outputm and n Supply frequency


We have

ki2 �1

2 � e(17)

From (14) and (17), the region for Ki2 is

vs

v�

1

2 � e� ki2 �

1

2 � e(18)

kp2 is selected such that the PI controller integral resettime Ti2 is faster than the system dynamics (windowdynamics). Therefore l/Ti2 . Tsupply, where Tsupply is thesupply period.

Ti2 ,1

Tsupply

(19)

Since Ti2 ¼ kp2=ki2, kp2, is given by

kp2 ,ki2

Tsupply

(20)

For a sampling frequency of 10 kHz, in a 220-V, 50-Hz acsystem, e is chosen to be 100 (half the window size). From(18), ki2 is given by l � ki2 � 1/200. From (20), assumingki2 ¼ 0.01, kp2 is given by kp2 , 1/2. kp2 ¼ 0.1 is used.

6 Qualitative analysis

To compare the operation of the conventional and proposedPLLs, a number of simulations are used to study distortioneffects on both PLL outputs. The conventional PLL par-ameters are varied to cover the practical parameter rangesused in [8–12], and where kpl and kil take the minimumand maximum values mentioned in [9] (kpl ¼ [30–70] andkil ¼ [10 000–60 000]). In each simulation, the proposedPLL parameters kpl and kil are the same as the conventionalvalues to allow a valid comparison. kp2 and ki2 are constant,ki2 ¼ 0.01 and ki2 ¼ 0.1. The results are for an input three-phase supply THD of 0%, 25%, and 50% and an unbalancein phase (c) amplitude of 0%, 25%, 50%, 75% and 100%.Fig. 4 shows the results of the conventional and proposedPLLs for THD and PU, where PU stands for phase (c) unba-lance and is defined by

PU ¼jVc � Vaj

Va

� 100

and vunbalance and udeviation are defined by

vunbalence ¼max jvoutput � vexactj

vexact

� 100

and udeviation ¼ max juoutput � uexactj

where voutput and uoutput are the PLL output angular fre-quency and phase angle. Variables vexact and uexact areexact supply angular frequency and phase angle.Applications such as parallel inverter operation, interfa-

cing to the grid, and active filtering are sensitive to supplyphase-angle error. For example when interfacing invertersto the grid, the active power P and reactive power Q deliv-ered to the grid are given by [23]

P ¼EV

Xsin d

Q ¼EV cos d� V

2

X

(21)


where X ¼ vL is the output reactance of the inverter, and dis the phase angle between the inverter output voltage E andthe grid voltage V From (21), the error in the grid phaseangle will be transferred to d which in turn affects P andQ. The error in P and Q is directly proportional to despecially when d is small, since sin(d) ’ d.

7 Simulation and practical results

Simulation and practical experiments were performed toverify that the proposed PLL is capable of tracking a dis-torted supply angular frequency and accurately locking tothe supply phase.

7.1 Simulation

Simulation is carried out using MATLAB/SIMULINK.Table 1 shows the simulation parameter values used forthe conventional PLL and the PI average controller. Fig. 5shows two simulation outputs for a slightly distortedutility with parameters shown in Table 2, and a high distor-tion utility with parameters shown in Table 3.Fig. 5 illustrates the capability of the proposed controller

to accurately lock to the supply angular frequency andphase, in one supply cycle (0.020 s).The conventional approach is unable to function accu-

rately when the supply distortion increases, as shown inFig. 5i and j. Fig. 5m shows the conventional PLL angularfrequency output with minimum stable PI settings(kpl ¼ 1 V/rad kil ¼ 300 V/(rad s)) which shows high dis-tortion plus a sluggish response in reaching steady state(0.15 s).Fig. 6 shows the simulation output for a transient fre-

quency step change from 50 to 60 Hz and back to 50 Hz.The simulation is carried out for both ideal and distorted uti-lities. The parameters used in the simulation are shown inTables 4 (ideal utility) and Table 5 (distorted).

Table 4: Ideal utility

Va 100 sin(vtþ 10) V

Vb 100 sin(vt2 (2/3)p þ10) V

Vc 100 sin(vtþ (2/3)p þ10) V

10 1 rad

v 2 . p . 50– 2 . p . 60 rad/s

Table 5: Distorted utility

Va 0 . sin(vtþ 10)þ 10 sin(5vtþ 10)

þ 10 sin(7vtþ 10)þ j(t)þ 10

V

Vb 50 sin(vt2 (2/3)p þ10)

þ 10 sin(5vt2 (2/3)p þ10)

þ 10 sin(7vt2 (2/3)p þ10)þ j(t)

þ 20

V

Vc 100 sin(vtþ (2/3)p þ10)

þ 10 sin(5vtþ (2/3)p þ10)

þ 10 sin(7vtþ (2/3)p

þ 10)þ j(t)þ 20

V

j(t) uniform random noise, 20 Vpp, zero

mean

V

10 1 rad

v 2 . p . 50– 2 . p . 60 rad/s

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The simulation results shown in Fig. 6 substantiate thatthe proposed controller can track step changes in supply fre-quency and can lock to the supply angular frequency andphase accurately in one ac supply cycle. As mentionedand shown in Fig. 6g, the proposed PLL takes one cycleto give the correct result. Under ideal clean and balancedconditions, the conventional PLL tracks the input supplyparameters faster than the proposed technique but this isnot practical as the supply is far from ideal (at least thevoltage measurement produces offset and noise). The con-ventional approach has difficulty tracking the frequencychanges as the supply distortion increases, as shown inFigs. 6i and j.

Fig. 7 compares the responses for a temporary loss ofphase. The supply is purely sinusoidal, 50 Hz, with ampli-tude and initial phase shift as in Table 4. Phase (a) is lostat 0.05 s and regained at 0.15 s. Fig. 7c shows the conven-tional PLL angular frequency output, where the stepchanges in phase (a) cause an instantaneous angular fre-quency jump at the instances 0.05 s and 0.15 s. For the con-ventional approach, the angular frequency (Fig. 7c) and thephase angle output (Fig. 7d) are highly distorted. Figs. 7eand f show the robustness of the proposed algorithm to

Fig. 7 Angle simulation for a temporary phase loss

a ac supply voltagesb Supply actual phase anglec and d Conventional angular frequency and phase angle outpute and f Proposed angular frequency and phase angle output

Table 6: Slightly distorted parameters for theconventional and proposed PLLs


þ 1 sin(7vtþ 10)þ j(t)

V

Vb 80 sin(vt2 (2/3)p þ10)

þ 5 sin(5vt2 (2/3)p þ10)

þ 1 sin(7vt2 (2/3)pþ10)þ j(t)

V

Vc 95 sin(vtþ (2/3)p þ10)

þ 5 sin(5vtþ (2/3)p þ10)


V


zero mean

V

10 random rad

v 2 . p . 50 rad/s

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phase-loss conditions, where the angular frequency outputstabilises in one ac cycle, without the large oscillationsthat occur with the conventional PLL. In simulationresults shown, the conventional PLL phase angle does notphase back like the proposed PLL, since the controlleroutput angle is always shifted by +p/2 as mentioned inSection 4 (u ¼ u+p/2). Thus the conventional outputangle will be leading or lagging by 0.005 s. This phaseshift has been taken into consideration in the proposedPLL by adding p/2, as shown in Fig. 3c.

Table 7: Highly distorted parameters for theconventional and proposed PLL


þ 1 sin(7vtþ 10)þj(t)

V

Vb j(t) V

Vc 95 sin(vtþ (2/3)p þ10)

þ 5 sin(5vtþ (2/3)p þ10)


V


zero mean

V

10 random rad

v 2.p.50 rad/s

Fig. 8 Practical angle measurements for slightly and highly dis-torted supply

a and b Supply voltagesc and d Conventional angular frequency outpute and f Proposed angular frequency outputg and h Conventional phase angle outputi and j Proposed phase angle output


7.2 Practical experimentation

Practically, the algorithm has been implemented in a150 Hz Infineon TC1796 microcontroller. The algorithmtakes 3050 instruction cycles per sample. The controllerparameters are as in Table 1. Tables 6 and 7 show theslightly and highly distorted supply parameters injectedinto the conventional and proposed PLLs.The practical results shown in Fig. 8 verify the ability of

the proposed PLL controller to accurately lock to the supplyangular frequency and phase in one ac supply cycle. PartsFigs. 8c and d confirm the limitations associated with theconventional PLL approach.

8 Conclusion

A novel three-phase PLL structure has been proposed,analysed, and compared with the traditional PLLapproach. The algorithm was assessed by simulation andpractically to validate the approach. The test conditionsvaried from pure to slightly and highly distorted three-phase ac inputs. The simulation and practical resultsconfirm the immunity of the proposed PLL to noise anddistortion. Comparison between the proposed and conven-tional PLLs under a phase-loss condition highlights theaccuracy and robustness of the proposed algorithm.Also, the transient response of the proposed PLL wastested and it responds in one ac supply cycle. Supplyangular frequency locking and phase angle tracking arebetter than with the conventional PLL. The resultsconfirm the adequacy of the proposed PLL for powersystem control applications.

9 References

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Prentice Hall, NJ, 1991)4 Mohan, N., Undeland, M. and Robbins, P.: ‘Power elctronics:

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11 Arruda, L.N., Cardoso, B.J., Silva, S.M., Silva, S.R. and Diniz,A.S.A.C.: ‘Wide bandwidth single and three phase PLL structuresfor utility conditions’. Proc. EPE, 2001, in press

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10 Appendix

Fig. 9 Shows the MATLAB m-file. MATLAB m-file for the pro-posed average controller

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three-phase phase-lock loop for distorted utilities

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