this week’s subjectfand.kaist.ac.kr/lectures/lec9.pdf · 2019-04-29 · 1 lec. 9 this week’s...
TRANSCRIPT
Lec. 91
This Week’s Subject
•DRAM & Flexible RRAM
•p-channel MOSFET (PMOS)
• CMOS: Complementary Metal Oxide Semiconductor
• CMOS Logic InverterNAND gateNOR gate
• CMOS Integration & Layout
• GaAs MESFET (JFET)
• Flexible Inorganic Semiconductor Technology
Lec. 92
DRAM (Dynamic Random Access Memory)
Schematic DRAM Chip Architecture:
PADRow Decoder
Col
. Dec
.
Memory Cell
Array
Col
. Dec
.
Col
. Dec
.
Col
. Dec
.
Row Decoder
Row Decoder
Row Decoder
RAS (row access strobe)Supplementary
Lec. 93
DRAM cell (Or Display)
Periphery circuits
∼1cm
Cell array(core) ∼
3cm
Word line
+ + + +
Transfer gate [access]B
it lin
e
- - - - Capacitor(or OLED )
I/O gate, CMOS TRData sense/amplifier
Data read Data refresh
Storage node
DRAM:
◎ Random access: row decoder → Select word linecolumn decoder → Select bit line
◎ Need to refresh the charge loss in the capacitor (μsec) Display (LCD or OLED):
◎ Active Matrix: with transistor in each cell. Fast speed, Large pixel
◎ Passive Matrix: w/o transistor. Slow respond speed(~250msec), small pixel
Lec. 94
p-channel MOSFET
Circuit diagram
Transfer curve (Id-Vg curve)
Id-Vd curve
-
-
-
-
-
-
Source electrode
Gate electrode
Drain electrode
n-type Si substrate
Source (p+) Drain (p+)
Gate
Gate oxide
p-channel MOSFET (PMOS)
-IDS
-VG-VTh=-0.5V
Vd=-1V
-1.8V0V
Lec. 95
CMOS Logic (Inverter)
Complementary Metal Oxide Semiconductor: NMOS+PMOS
Reference (Ground)
Reference
•Inverter : building block of integrated circuits
Vtn=-Vtp
Vgp=Vin-Vdd
Vgn=Vin
Vdsn=VoutVdsp=Vout-Vdd
1, 0 0, 1
Pull-down NMOS
Pull-up PMOS
Vin Vout
0 1
1 0
Pull-up PMOS
Lec. 96
CMOS Logic (Inverter)
Reference (Ground)
Reference(1.8V)
1.8V digital 1
1.8V
Vtn=0.5V on
Vtp=-0.5V off
Vgn=1.8V
Vgp= 0V
Pull down by NMOS 0V
0V digital 0
1 Ohm
100 Ohm
1.8V
0V
Digital 1 is inverted to digital 0
Vgp=Vin-Vdd
Lec. 97
CMOS Logic (Inverter)
Reference (Ground)
Reference(1.8V)
1.8V digital 1
0V
Vtn=0.5V off
Vtp=-0.5V on
Vgn=0V
Vgp= -1.8V
Pull up by PMOS 1.79V
0V digital 0
100 Ohm
1 Ohm
1.8V
1.79V
Digital 0 is inverted to digital 1
Vgp=Vin-Vdd
Lec. 98
CMOS Logic (NAND Gate)
VDD
The output is high when either of inputs A or B is high, or if neither is high. In other words, it is normally high, going low only if both A and B are high.
Pull-down NMOS
Pull-down NMOS
Pull-up PMOS
Lec. 99
CMOS Logic (NOR Gate)
VDD
The output is high only when neither A nor B is high. That is, it is normally high but any kind of non-zero input will take it low.
Pull-down NMOS
Pull-up PMOS
Pull-up PMOS
Lec. 910
CMOS Inverter Layout
Ref: CMOS VLSI Design, N.Weste, Addison Wiley,
Lec. 911
CMOS Inverter Mask Layout
Lec. 912
a) Starting Material•Dopant type : p-type (boron)•Orientation : (100)•Resistivity : 13±2•Wafer size : 4 inch
b) Initial oxidation•Temperature : 1000C 130min.•Thickness : 6000±6000Å
d) Well mask• PR coat, soft bake• Align, Exposure• Develop, • Hard bake
e) Oxide etch•7:1 BHF 6min
f) P/R strip•Acetone, IPA, DI wafer
g) Well implantation•Ion species : P+
•Dose : 3.6x1012/cm2
•Energy : 120keV
Mask 1
Lec. 913
(h)
(i)
(j)
(k)
(l)
Mask 2
Mask 3
i) Gate oxidation •Temperature : 950C, 31min.•Thickness : 250±20Å
i) Poly deposition •Temperature : 625C•Thickness : 3500±300Å
j) Gate mask•P/R coat, soft bake•Align, Exposure•Develop, CD check •Hard bake
j) Poly etch• RIE (Plasma etching)
k) Oxide Growthl) N+ S/D implantation
•Ion species : As+
•Dose : 5x1015/cm2
•Energy : 80keV
Lec. 914
Repeats using p+ diffusion mask
(m)
(n)
(p)
(o)
Mask 4
Mask 5
o) N+ S/D implantation •Ion species : BF2
+
•Dose : 3x1015/cm2
•Energy : 40keV
p) Contact etch RIE : CHF3+CF4+Ar
Lec. 915
Mask 6
r) Metal deposition•Target : Al-1% Si•Thickness : 0.7m
r) Metal etch•Reactant gas : BCl3+Cl2 RIE
(r)
Lec. 916
GaAs MESFET
Normally III-V Sc, High mobility, frequency device
Si Ge GaAs InAs n (cm
2/Vꞏs) 1400 3900 8500 30000 p (cm
2/Vꞏs) 470 1900 400 500
MESFET (Metal Semiconductor Field Effect Transistor): one type of JFET(junction field effect transistor)
N type GaAs
Lec. 917
Normally off MESFET
(enhancement mode)
Lec. 918
Flexible Single Crystal Silicon from SOI
Appl. Phys. Lett. 84, 5398 (2004)
Si (100 nm)BOX
• Very thin and flexible • High performance similar to Si VLSI technology• Well established technology
Lec. 919
Large Area, Selective Transfer of µs-Si using PDMS Stamp
PDMS stamp
Transfer µs-Si from stamp to PET
µs-Si on SOI wafer
Contact
Remaining SOI wafer
PET
10 mm
1 cm
Sacrificial SiO2 layer
Mother substrate
Adv. Mater. 17, 2336, 2005
100 µm
20 cm
Lec. 920
High Performance Device on Plastic Substrate
On
Off
I ds(A
)
-6 -4 -2 0 2 4 6
0
50
100
150
200
250
300
1E-101E-91E-81E-71E-61E-51E-41E-30.01
I DS(u
A)
VGS(V)
µ= 520 cm2/Vs,
on/off=106
Vth= 0.7 V
Vds=0.1V
IEEE Elect. Device Letters. 27, 460, 2006Appl. Phys. Lett. 90, 213501, 2007
Lec. 9
Flexible III-V HEMTs
---
Id-Vd Id-Vg
(Chap 5.8 & Chap 6.3.2)
Si-doped AlGaAs
Undoped GaAs
Journal of Applied Physics, 100, 124507 2006
Lec. 922
Flexible 3D Heterogeneous Integration
Nature Materials, 5, 33, 2006
15 µm
µs-GaN on Si wafer 3D direct integration
µs-Sc
• Direct transfer of µs-Sc
500 µm
•Heterogeneous 3D integration on Plastics
Science, 314, 1754, 2006
Lec. 923
• Resistive Random Access Memory (RRAM)
Kim, K. IEEE Tech. Dig. IEDM, 1-4, 2010.• Neuromophic Systems
Jo, S.H et al. Nano Lett. 10, 1297, 2010
.
D. Strukov et al., Nature, 453, 80, 2008
First proposed in 1971
Memristor, Missing Fundamental Circuit Element
Lec. 924
Flexible one transistor-one memristor (1T-1M) memory
Nano Lett., 11(12), 5438, 2011
Lec. 925
1T-1M Structure
Circuit Diagram
VSET = -2.1 V, VSET = 2.7 V
ON/OFF ratio of 50 at -0.5 V (VREAD)
Nano Lett., 11(12), 5438, 2011
Lec. 926
Random Access Operation
Nano Lett., 11(12), 5438, 2011
Lec. 927
Flexible LSI for Implantable Devices
Using 0.18µm CMOSACS Nano, 7, 4545, 2013
Lec. 928
Electrical Properties of Flexible Devices
M1
GG
M2
S
GG S
Input Port
Output Port200 μm
RFICs (RF Switches)
Stable Operations on PlasticsACS Nano, 7, 4545, 2013
Lec. 9
Roll to Roll ACF Packaged Flexible NAND Flash Memory
Adv. Mater. 28, 8371, 2016
Lec. 9
Read voltage
Endurance Retention
Transfer Curve
Flexible NAND Flash Memory – Unit Cell Operation
Adv. Mater. 28, 8371, 2016
Lec. 9Adv. Mater. 26, 7480, 2014
Flexible one selector-one resistor (1S1R) memory
Lec. 9
Flexible Crossbar Memory using ILLO
Adv. Mater. 26, 7480, 2014
Lec. 9
Flexible Oxide TFTs using ILLO
TFT structure
• IZO thickness of 20 nm• GI thickness of 176 nm
Adv. Func. Mater. 26, 6170, 2016
Lec. 9
Flexible Oxide TFTs using ILLO
Transfer Curve
On glass On plasticμ* (cm2/Vs) 37.3 36.8
SS (V/dec) 0.31 0.32
Von (V) -0.6 -0.7
ΔV (V) 0.015 0.017
Output Curve
*@ 15 V
Negative Bias (-20 V)Negative Bias (-20 V)
Adv. Func. Mater. 26, 6170, 2016
Lec. 9
Self-Structured Nano-filament for Phase Change Memory
ACS Nano 9, 6587, 2015
Lec. 9
Comparison between ILED and OLED
Adv. Func. Mater., 10.1002/adfm.201808075
Lec. 937
Flexible GaN LED
Nano Energy 1, 145, 2012
Blue White
Lec. 9
Optogenetics
icsSteps of optogenetics nChannelrhodopsin 2 and Halrhodopsin
Nature 458 1025 2009
Lec. 9
Flexible Vetical micro LED
Nano Energy 447, 44, 2018
Lec. 9
Flexible VLED on Motor Cortex Behavior Control
Nano Energy 447, 44, 2018
Lec. 9
Flexible Monolithic GaN LED
Adv. Mater. 30, 1800649, 2018