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MSC - 06779
NONAL AERONAUTICS AND SPACE ADMINISTRATION
INFORMATION SYSTEMS DIVISION INTERNAL NOTE
AN INTRODUCTION TO THE BANNING
DESIGN AUTOMATION SYSTEM
FOR SHUTTLE MICROELECTRONIC
HARDWARE DEVELOPMENT
10831) AN INTRODUCTION TO THE N80-12282
.SIGN AUTOMATION SYSTEM FOR SHUTTLE!RONIC HARDWARE DEVELOPMENT (NASA)i3/MF A01 CSCL 09C Unclas
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MICROELECTRONICS SECTION's?
ENGINEERING STANDARDS AND TEST BRANCHr.
MANNED SPACECRAFT CENTER
HOUSTON,TE;XAS
APRIL 3, 1972
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MSC - 06779
INFORMATION SYSTEMS DIVISION INTERNAL NOTE
AN INTRODUCTION TO THE BANNING DESIGN
AUTOMATION SYSTEM FOR SHUTTLE MICROELECTRONIC
HARDWARE DEVELOPMENT
PREPARED BY:
William J. McCrady
APPROVED BY:
Robert L. StubblefieldChief, Engineering Standards and Test Branch
Alfred B. EickmeierAssistant Chief for Instrumentation
16aul H. VavraChief, Information systems Division
NATIONAL AERONAUTICS AND SPACE ADMINISTRATION
MANNED SPACECRAFT CENTER
HOUSTON, TEXAS
April 3, 1972
I
AN INTRODUCTION TO THE
13,ANNINGDESIGN AUTOMATION SYSTEM FOR
SHUTTLE MICROELL-MMIC HARDWARE DEVELOPW
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PREPARED BYRr^,Y']UllUCTPILX'J'Y 4T' TILL
William J. Mc Grady OltI.GINAL PAGL; IS POOR
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TABLE OF CONTENTS
4
.Page
LIST OF FIGURES . . . . . . . . . . . . . . . . . . . . 1 i
TABLE I - ELECTRICAL CHARACTERISTICS OF THEBANNING STANDARD CELLS . . . . . . . . . . . . . 7
1.0 ABSTRACT . . . . . . . . . . . . . . . . . . . . . . .
2.0 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . iv
3.0 WHAT IS BANNING? . . . . . . . . . . . . . . . . . . . . . 1
4.0 WHY IS BANNING NEEDED? . . . . . . . , . . . . . . . . . 2
5.0 HOW DOES BANNING WORK? . . . . . . . . . . . . . . . . 4
6.0 WHO CAN USE BANNING? . . . . . . . . . . . . . . . . . . 6
7.0 WHERE DID MSC GET THE BANNING PROGRAMS? . . . . . . . . . . 6
8.0 CONCLUSIONS . . . . . . . . . . . . . . . . . . . . . . . . 7
9.0 APPENDICES
APPENDIX A - WHAT IS MOS? . . . . . . . . . . . . . . . . . A-1
APPENDIX B - EXAMPLE OF MOS ARTWORKSHOWING OVERLAY SCHEME . . . . . . . D-1
APPENDIX C — LIST OF STANDARD CELLS . . . . . . . . . . . . C-1
APPENDIX D — GLOSSARY OF TERMS USEDINTHIS REPORT ............................... D-1
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LIST OF FIGURES
Figure 1 - Logic Diagram Prepared PAGEUsing Banning Standard Ce-11s .......................8
Figure 2 - Box Plot of I/O Register ChipShowing the Interconnection ofBanning Standard Cells .............................g
Figure 3 - Example of Banning StandardCell Data Sheets .......... ........................10
Figure 4 - Simplified Flowchart for HardwareFabrication Using the BanningDesign Programs ....................................12
Figure 5 - Simplified Diagram of an MOSInsulated-Gate Field-Effect Transistor .............13
ii
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1.0 ABSTRACT
This paper describes the BANNING MOS (Metal-Oxide-Semiconductor)
design system that has recently been implemented at MSC on the
Univac 1108 computers in the Computation and Analysis Division.
This system has been designed to complement rather than supplant
the normal design activities associated with the design and
fabrication of low-power digital electronic equipment. BANNING
is user-oriented and requires no programming experience to use
effectively. It provides the user a simulation capability to aid
in his circuit design and it eliminates most of the manual op-
erations involved in the layout and artwork generation of inte-
grated circuits. This report is organized to answer in as few
words as possible five of the most commonly asked questions about
BANNING. An example of its operation is given and some additional
background reading is provided in the Appendices. Appendix A gives
a very brief explanation of how an MOS transistor works and
Appendix D contains a glossary of the more important terms used in
this report.
iii
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IV
"He was slowly going madDesigning circuits pad by pad.He screamed and woke,Then thanked the blokeWhose fertile mind had fathered CAD"
--- Anonymous
2,0 INTRODUCTION
The Banning computer-aided design (CAD) programs were written to
prevent nightmares such as this one. This brochure was prepared
to familiarize the reader with the Banning design system without
presenting a detailed description of its operation. There are
several volumes of documentation available which describes Banning
at any level of detail desired, but they are user-oriented and are
not suitable for someone desiring only a general overview of the
subject. The material presented here is intended primarily for
potential users of the system, and this includes almost anyone
involved in the design and/or fabrication of anionic hardware. The
format of this brochure should make it useful to managers and decision-
makers as well. If, after reading the material presented here,
the reader desires further information about Banning, he is encouraged
to consult any member of the Microelectronics Section.
3.0 WHAT IS BANNING?
Banning is a collection of five major computer programs
which translate a logic design, such as that shown in
w Figure 1, into precision photomasks, or artwork, for
producing P-channel MOS (Metal-Oxide-Semiconductor) LSI
(Large-Scale4 ntegrated) circuits. l These programs are
written in Fortran V for the Univac 1108 computer and consist
of the following;
• Placement-Routing-Folding (PRF) Program
i• Artwork Program
• Signal Trace Program
• 4ogic Block Simulator (LOGSIM)
e Transient Analysis Program
MOS technology was selected for use with Banning because
it is basically a simple process and therefore very
economical,, The fabrication process requires only four masks
compared with five, six or more for competing technologies.
MOS artwork preparation is by far the most critical as well
as the most time-consuming step in the fabrication of MOS
Appendix D contains a glossary of most of the terms usedin this report plus many others commonly used by integratedcircuit users.
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circuits. It is therefore, a step requiring as much automation
as is practical. As will shortly be seen, Banning does an
admirable job in attaining this goal.
For those without a clear understanding of what is meant by
an MOS mask, Appendix B is offered, which shows a four maskf
i
set that overlay, or register, to form one of the samplerF
Banning cells. By way of comparison, Figure 2 is a checkplot
of an MOS circuit which shows how exactly 65 Banning cells
similar to this one are interconnected to achieve a desired
function. Note that to save plotting time the cells are
represented by boxes since the cell structure itself is in-
variant.
4.0 WHY IS BANNING NEEDED?
Banning permits the logic designer to convert his logic designs
into working microminiaturized systems in a minimum of time
with the highest possible probability of success. Factors
which make this possible and other advantages to the user
of Banning are:
• Improved turnaround time
Final precision artwork is available in several days
compared to the month or more required for the manual
procedure.
2
W
e Elimination of layout design rule violations
Each cell has already beer, designed, fabricated, and
tested, and has accumulated many device - hours in
the field. It is guaranteed to perform according to
the specifications on its data sheet (see figure 3).
In addition, each cell design has been digitized,
check-plottod and stored on tape. Subsequent uses
of a given cell are therefore free of human error.
• Improved accuracy
The manual operations associated with digitizing or
rubylith cutting are complo tely eliminated. Complex
manual artwork frequently has errors that escape
detection until much time and money have been invested
in the design.
• Simulation availability
Signal Trace and LOGSIM perform in minutes highly
accurate time analyses for the designer which would
otherwise take him weeks to perform, if indeed that
level of simulation could be done at all by hand cal-
culations.
• Low cost
MOS fabrication is a relatively inexpensive process
compared with the fabrication of other semiconductor
devices such as NPN or PNP transistors, Device pro-
cessing time is on t) -_ order of a few days under
optimum conditions.
3
5.q HOW DOES BANNING WORK?
Banning uses a library of 120 different building blocks, or
standard cells, that are interconnected to form working
systems. An example of one of these cells is shown in
Figure. 3 which shows the schematic and logic symbols for
the cell as well as its truth table and input-output cap-
aciti es . Table I summarizes the electrical characteristics
of the Banning cells. A ,omplete list of the logic cells
avai1abla to Banning users is given in Appendix C. The
engineer designs his logic using the standard cells con-
tained in the li brary and then or.-des up a deck of data cards.
The logic block simu`a l:,or (LOGSIM) checks the input cards
looking for coding errors and then calculates rise and
fall times, delays, node voltages, etc. The designer then
analyzes the printed output in order to verify whether or not
his logic performs as expected,
If the LOGSIM results agree with his design goals, then data
cards are prepared and entered into the PRF program which
selects the required standard cells, places them on a coordinate
system, and interconnects them according to the designer's
input data. After all wiring has been completed, Signal Trace,
essentially a subroutine of PRF, then uses the node capacitance
loading data calculated by PRF to calculate rise and fall
tines for each node in the circuit. The results are output
on a printer plot which the designer must then study to
determine if any of his cells have been overloaded. If a
^y
M
4
particular cell has been overloaded he must either reduce ther
capacitance of that net, insert a cell with more driving
capability2 , or else redesign his logic.
The PRF program outputs its data to the Artwork program which10 then converts the PRF coordinate data into commands to drive
an automatic plotting machine. There are two plotting machinesw
available anti in use at present - a Gerber Series 1000 equipped
with a phutohead and a D. W. Mann Pattern Generator. The
Artwork program also performs various utility functions such
as adding cells to the library or deleting them. An
example of a typical circuit which has been plotted is shown
on the cover of this document. The plot shown is the metal
mask (level 4). Note that t,ie structure of each cell is visible,
wslereas in Fi oure 2 onl v the outlines are shown.
The Transient Analysis Program is used primarily for standard
cell design to evaluate their response times. Although
. this program is not yet available at MSC, a much better
program is available for performing this same function. SCEPTREM
(System for Circuit Evaluation and Prediction of Transient
Radiation Effects) was written to analyze radiation effects
The standard ce i rary as both 2 picofarad and 4picofarad cells plus output drivers with various drivingcapabilities.
5
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on electronics and contains an excellent transient analysis
routine. SCEPTRE is now available on the Univac 1108.
Figure 4 is a flowchart that shows the relationships between
the various programs.
6.0 WHO CAN USE BANNING?
Anyone who does logic design and testing. A complete set
of user manuals is available which de ,̂ cribes the step-by-step
procedure for turning a logic design into a working set of
photomasks. No programming experience is necessary to use
Banning. In addition, the Microelectronics Laboratory is
now set up to process the Banning output and can have sample
quantities of chips ready for testing within a few weeks
of final artwork submittal.
7.o WHERE DID 14SC GET THE BANNING PROGRAMS?
The basic Banning programs were given to NASA by another
Government agency which prefers to remain anonymous. Due to
the fact that these programs originally were run ► iing on a
GE 625 computer, initial efforts to run them on the the
Univac 1108 met with limited success. These early problems
have been overcome and the basic programs have been updated
and considerably expanded to meet MSC's own particular re-
quirements.
Y
6
TABLE I
ELECTRICAL CHARACTERISTICS OF THEBANNING CELLS
PARAMETER SYMBOL MINIMUM MAXIMUM
Power Supply V0D -13.3 -15.5
Clock Voltage VGG -23.8 -27.4
Threshold Voltage VT -3.5 -4.5
Case TemperatureTAMB -55°C +125°C
Clock Frequency -- -- 860 kHz
Clock PulsR Width -- 510 nsec --
Logic "1" V1 -9.0 -15.3
Logic "0" V +0.3 -3.5
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8.0 CONCLUSIONS
Tots report has briefly summarized the salient characteristics
of the BANNING MOS design system and has attempted to show the
interrelationships between the various programs. No attempt
has been made to give input and output formats since the y are
highly dependent on options selected by the user and would
only require further explanation. It is hoped that the reader
will inquire about further documentation on all or part of the
BANNING system and also about plans for further development.
7
,.
71,
Page 8
DATA BIT STROBE IN/OUT LOADPO
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FIGURE 1
LOGIC DIAGRAM PREPAF^M USING BANNING STANDARD "ELI S
This is one bit of a six bit I/O register chip.Arrows at upper right denote lines common to allsix bits. See Figure 2 for a complete plot of trigchi p as produced by Banning.
4
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FIGURE 2
BOX PLOT OF I/O REGISTER CHIPDAWN AT A SCALE OF 50:1 BY A GERBER 600 PLOTTER
A
B
P
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CELL 1/0 CAPACITIES
CAPACITOR PIN CAPACITY IN fF
CA 2 420
JeB
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PATTERN NO. 4600
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Page 10
BANNING THICK OXIDE STANDARD CELLSTATIC REGISTER, 4PF PATTERN NO.460010, 02 1"I" OUTPUT
7FI 13 U R 3A] APRIL 1968
SCHEMATIC LOGIC SYMBOL
A 01 SR I 4p
B S
A 2 ¢, i S RI
Y4P
EQUIVALENT LOGIC
A GGCG P
B
TRUTH TABLE
A t-1 B t-1 l 1 B t 2 P
0 Pt-1
0 0 0 1 Pt-1
0 1 0 0 1 0
1 l 0 0 1 1
`MEANS EITHER STATEB IS THE SAMPLE INPUTDURING 4 2 B MUST EQUAL ZERO
LOGIC EQUATIONS
P Pt-1 ; 2 + t 2 B At -1 Bt-1 + 8 t-1 Pt-1
TSCALE0.1mil
A 98230 [STATIv ROUTPUTER
9600 FIGURE 3- - E3 -1
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Page 12
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SYSTEM}^11RDWA}^E
REQUIREMENTS ""^"SPECIFICATIONS
NEWCELLDESIGN
CIRCUITTYPE —FILE
PARTITIONING
PJACEMENT-ROUTING-FOLDING (PRF)
MANUAL -----,r ARTWORKINPUT
F _, SIGNALTRACE
STANDARDCELLLIBRARY
GERBER PLOTTER.OR
MANN PATTERN G- ERATOR
DEVICE FABRICATION(MICROELECTRONICS LAB)
ELECTRICALTEST DELIVERY
FIGURE 4
GENERAL FLOWCHART FOR HARDWARE FABRICATION USING THE
BANNING DESIGN PROGRAMS (SHOWN WITH HEAVY OUTLINES)
Page 13
SOURCTCONTACT
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INSULATED SILICONDRAIN
OATSFl- DIOXIDE CONTACTCONTACT /
P-DIFFUSION WELL -- ".^ `^I P-DIFFUSION WELL
N-TYPE SILICON SUBSTRATE
(b)
High resistance from source to drain
SOURCEINSULATED
CONTACTGATT SILICON
CO TCONTACT o -V DIOXIDE
f P-DIFFUSION WELL' ++t+ + *+1 P-DIFFUSION WELL t
N-TYPE SILICON SUBSTRATE
(a)
Low resistance from source to drain
FIGURE S
SIMPLIFIED DIAGRAM OF AN MOS INSULATED-BATE
FIELD-EFFOOT TRANSISTOR
4
4
i APPENDIX A
WHAT IS MOS?
MOS is the abbreviation for a metal-oxide-semiconductor sand-
wich which functions much like an ordinary transistor,
with the exception that an MOS transistor has a much higher
input impedance and can be built much smaller and at a lower
cost. A glance at Figure 5 will reveal the reason for the
high input impedance. The input signal is applied to the
electrode labelled "gate" which is insulated from the semi-
conductor surface by the non-conducting silicon dioxide. The
term "insulated gate field effect transistor" is sometimes
used to describe this structure.
The "gate" electrode of the device is appropriately named
because it controls the flow of current from the region
labelled "source" to the region labelled "drain". The source,
obviously, is connected to a source of positive charge such
as the plus terminal of a power supply or battery. When
current flows from the source it is "collected" by the drain
region. Note that the source-body and the drain-body P-N
diodes are normally back-biased and hence do not pass
current. This is insured merely by connecting the body to
the most positive potential in the circuit.
The reader may have surmised already that the gate is
analogous to the base of an ordinary transistor, the source
to ;p ro emitter, and tno drain to the collector. It is here
A-1
A-2
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that the analogy ends since the flow of current from source
to drain is controlled by the electric field at the surface
of the silicon and and not by -the injection of electrons or
holes into the silicon. This leu;:c to the secret of operation
of an MOS transistor, and that is the manner in which the
gate electrode controls the flow of current from source to
drain. As indicated above, the flow is controlled or modu-
lated by an electric field established between the gate and
the semiconductor. By definition, a semiconductor such as
silicon can be easily switched from a conducting to a non-
conducting state by the application of an electric field.
For example, with no voltage applied to the gate no current
can flow, since the intervening silicon is N-type, or contains
an excess of electrons. Now if a negative voltage is applied
to the gate, the electrons in the silicon are repelled and a
thin region of silicon at the surface is converted to P-type,
thus "shorting" out the source and drain. The resistance
of this path is determined by the magnitude of voltage on
the gate and hence the ability of the gate voltage to
modulate the current flow.
w
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APPENDIX Q
EXAMPLE OF MOS ARTWORK SHOWING OVERLAY SCHE14E
A
4
I
i
APPENDIX C
LIST OF BANNING STANDARD CELLS
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APPENDIX D
GLOSSARY OF TERMS
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ACCEPTOR - See DOPANT.
ARTWORK - A precise geometrical representation of a PC board)integrated or hybrid circuit, or any other assembly to be con-
, structed which requires a precise Layout. The layout is usuallymade on cut-and-strip rubylith, photographic film, or by applyingtape to a transparent background. Artwork is usually done at 10-100times final size and th(,! photographically reduced.
BALL BOND - A micro-connection to a micro-miniaturized circuit. Thebona gets its name from the gold ball which is formed by surfacetension when a fine gold wire (0.001 inch) is flame-cut. The goldball is then bonded to an aluminum pad on the microcircuit with theapplication of heat and pressure. This bond is for the purpose ofconnecting the chip to the package and then to the outside world.
BONDING PAD - A metallized area on the surface of a microcircuitchip (or die) to which a bond will be made. This pad is usuallyformed of aluminum and is usually about 5 mils on a side. SeePROBE PADS
BIPOLAR TRANSISTOR - The common NPN or PNP transistor whose actiondepends upon majority carrier (be it holes or electrons) flow thatis modulated by the injection of minority carriers into the baseregion of the transistor.
CHANNEL - See either P-CHANNEL or N-CHANNEL.
CHIP - Also called a die. It refers to a single microcircuitfunction, such as a gate or flip flop, on a piece of silicontypically 100 miles on a side and about 12 mils thick. A siliconwafer about 1-2 inches in diameter usually contains hundreds ofthese chips which are then separated from each other by scribingthe wafer and then breaking it.
DIE - See CHIP.
DIFFUSION - A process for injecting dopant atoms into the siliconcrystal lattice to achieve the required impurity level. Dopantatoms close to the silicon surface will, at elevated temperatureson the order of 10000C, migrate into the silicon because of theconcentration gradient. An analogous situation is the dispersionof a drop of colored dye in a glass of water.
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DONOR - See AOPANT
DOPANT - A substance such as boron, arsenic on phosphorus which isplaced in the silicon lattice in controlled amounts to achieve the
•
required conductivity. The uwo types of dopants are donors, which"donate" an electron to the crystal, and acceptors which "accept"an electron when introduced into the silicon crystal. Diffusionand epitaxy are the most common methods for It the silicon.
DRAIN - A highly doped diffused region in a MOS transistor in whichthe flow of majority carriers terminate. The drain is analogousto the collector of a conventional, or bipolar, transistor or theplate of a vacuum tube.
EPITAXY - The growing of one material on another. in the strictersense, the growing of single crystal material on a single crystalsubstrate, the crystal orientation of the new material dependingon the orientation of the host material (also called the substrate).Normally the crystal is doped while it is growing to permit thegrowth of N-type material on a P-type substrate, or vase-versa.
FIELD EFFECT - See MOS.
FORTRAN - A user-oriented programming language which is an acronymfor FORmula TRAN'slation. Fortran statements are translated by thesystem compiler into a more basic language that the machine canunderstand. Machine language, though more efficient, is harder to learnand use than is Fortran.
GATE - The region of a MOS transistor that lies between the source anddrain and controls the majority current flow. The gate is analogousto the base of a conventional, or bipolar, transistor or to the controlgrid of a vacuum tube.
HOLE - A position in the crystal lattice which can be filled by anelectron, thus influencing current flow. Acceptors such as boronaccept an electron when introduced into the lattice because theirvalence is +3 while that of silicon is +4. At room temperaturemost of the boron atoms are negatively ionized and a hole existswherever the electron came From.
INTEGRATED CIRCUIT - An electronic device containing several activeand/or passive elements which perform all or part of some function.An example is a silicon chip containing several transistors enddiffused resistors which are interconnected to form a TTL gate.
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LSI - The abbreviation for Large-Scale-Integration, which refers toa recent technology development which allows many different gatingfunctions to be placed on a single chip. Any chip containing 100or more equivalent gates is generally referred to as LSI. An11 equivalent gate s' contains about three or four transistors and anequivalent number of resistors. Resistors are rarely found in LSIcircuits, their function being performed by properly biased tran-sistors. See MSI.
METALLIZATION - A conductive coating which serves to interconnectcomponents, for example, on a hybrid substrate or on an integratedcircuit wafer. On integrated circuits the metallization is usuallyaluminum which has been evaporated over the entire wafer (in a vacuumby heating) and then selectively etched.
MICROCIRCUIT - An ultra-small functional electronic circuit or assemblywhich contains many resistors and transistors in a package usually nolarger than a single transistor can. These packages are commonlyknown as flat packs, TO-cans, dual-inline packages, etc. Thetechnology which made microcircuits possible is generally referred toas minroelectronics.
MICROELECTRONICS - That branch of the electronics art which has to dowith the development of microminiature electronic components, circuitsand systems.
MIL - A unit of measurement commonly aced in microelectronic parlanceand is equal to one-thousandths (0.001) of an inch.
MOS - An acronym for metal-oxide-semiconductor. An MOS transistoroperates on the field effect principle and has an insulated gate, asource, and drain as electrodes. The gate is insulated from thesource and drain by a thin oxide layer which gives it a very highinput impedance. Another type of field effect transistor is thejunction field-effect (JFET) in which the drain-to-source conductionis controlled by a P-N junction located "between the source and drain.The voltage applied to the P-N junction varies the width of itsdepletion region which, in turn, controls the source-to-drain conduction.
MSI - The abbreviation for Medium-Scale-Integration. It refers tointegrated circuit chips which contain approximately 50-100 equivalentgates. Die with less than 50 gates are referred to as SSI (Small-Scale-Integration). See LSI .
N-CHANNEL - A thin conductive path on the silicon surface in whichconduction occurs primarily by majority-type free electrons. In otherwords, the region near the surface is normally P-type silicon but hasbeen "inverted" due to either positive charges in the oxide or to anapplied positive potential. See P-CHANNEL.
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N-TYPE - Refers to silicon that has been doped with a donor, such asphosphorus, which adds a free election to the lattice structure, thusaltering its conductivity. See P-TYPE.
• P•CHANNEL - A thin conductive path on the silicon surface in whichconduction occurs primarily by majority-type free holes. In otherwords, the region near the surface is normally N-type silicon but hasbeen "inverted" due to either negative charge in the oxide or to anapplied negative potential. See N-CHANNEL,
PHOTONASK - A photographically produced device used to "shadow", orshield, either a substrate during a vacuum deposition process, on awafer coated with photosensitive resist.
12PICOFARAD - A unit of capacitance equal to 10 - farads (1 farad to 1ooulomb/volt).
PROBE; PADS - Special metal contacts on an integrated circuit designedfor electrical probing rather than for bonding. A probe is a finesteel rod that tapers to a point with a tip about one mil in diameter.It is attached to mcropositioners for very fine control.
P-TYPE - Refers to silicon that has been doped with an acceptor, suchas boron, which ties up an electron thereby creating an extra hole inthe crystal. The conductivity is altered to an extent dependent onthe boron concentration. (See N-TYPE).
RESIST - Also known as photoresist. A photosensitive liquid that hasthe ability to "resist" the attach of most etchants used in semiconductorprocessing. A few drop, of the resist are applied to the oxidized wagerusing an eye dropper and the excess removed by spinning the wafer athigh speed. Only a thin film of resist remains which is then driedand cured. The entire wafer is exposed to light through a photomaskand the areas that are exposed harden. The areas that are not exposedrinse away, thus exposing a hole or via to the material beneath. Afteretching, the remaining resist is stripped away leaving the desired oxidepattern.
SCRIBING - The process of scoring the silicon in special lanes dividingthe active areas. The lanes are called scribe lanes and the scribingis usually done with a very hard substance such as a diamond point.
SILICON - An element classed as a semiconductor since its conductivitycan be changed over several orders of magnitude by introducingcontrolled impurities with concentrations no greater than a fewparts per million.
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SILICON DIOXIDE - A compound Formed by the oxidation of silicon whosechemical formula is 5102 . The oxidation takes place very slowly atroom temperature but can be accelerated by heating the silicon to hightemperatures (800 . 120000) in the presence of steam or oxygen.Silicon dioxide acts as a barrier to the passage of dopants such asboron or phosphorous and thus can be used to selectively create N orP regions in the silicon.
SUBSTRATE - A material upon which epitaxial layers, thick filmdepositions, or thin film depositions are made, or within whichdiffusions are made. The substrate gives mechanical rigidity tothe structure and aids in conducting heat away from the activeregions.
THRESHOLD VOLTAGE The voltage which must be applied to the gateof an MOS transistor to initiate conduction between the source anddrain.
WAFER. - A substrate that is thin with surface areas that are parallel.An example is a silicon slice about 2 inches in diameter and 12 milsthick.
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