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3 CBnI
C-MOS ARRAY DESIGN TECHNIQUES(NASA-CH-150799) C-mos AM(AY DESIGN Nal -12328
TECHNIQUES (RCA Advanced Technology Labs.)
I 67 p HC AJ4 /MF A01 CSCL 09CU t ► C 1 d:3
G3/33 36939
A. FellerAdvanced Technology laboratoriesDefense Electronic ProductsRCACamden, H.J.
Prepared for
NASA/Marshall Space Might CenterHuntsville, Alabama
n/w
C-MOS ARRAY DESIGN TECHNIQUES
by A. Feller
J
Prepared under Contract No. NAS 12-2233 byADVANCED TECHNOLOGY LABORATORIES
DEFENSE ELECTRONIC PRODUCTSRCA
Camden, New Jersey
for
NASA/Marshall Space Flight CenterHuntsville, Alabama
r.
't
ABSTRACT
.3 entire complement of standard cells and oomponents, except for the Set-Reset
Flip-Flop, have been completed. Two levels of checking were performed cn each
device. A description of each logic cell and a detailed topological layout are included.
All the related computer programs have been coded and one level of debugging has
been completed.
The logic for the test chip was modified and updated. This test chip served as the
first test vehicle to exercise the standard cell complementary MOS(C-MOS) automatic
artwork generation capability.
iii/iv
PREFACE
Program Objectives
The objectives of this program are to develop and demonstrate the capability of
automatically generating precision artwork for complementary MOS (C-MOS) integrated
circuit arrays. The program encompasses the following design objectives:
1. Standard cell family - a basic family of standard circuit yells will be de-signed. Family members include:
a. Inverter.
b. Two-, three- and four-input NOR's.
c. D-type and set-reset flip-flops.
d. Two-, three- and four-input NAND's.
e. Transmission and protective devices.
f. Special process and mask components.
2. Circuit description:
a. Static logic.
b. Single supply.
c. Logic swing - approximately equal to supply.
d. Speed - a function of the process and the supply voltages. A realisticobjective of nominal stage delays of 13 to 16ns with fan-outs of 2.5 loadsappears to be obtainable with factory processes expected to be opera-tional at the time chip fabrication is scheduled. This assumes a supplyvoltage of 10 volts.
3. Computer programs - Four major computer programs will be implementedfor the C-MOS technology:
a. Placement, routing and folding program - This program will providefor the automatic orientation or cell placement, tho cell interconnections,and an acceptable form factor.
b. Artwork program - This program will generate the instruction for anautomatic artwork generator to plot the final mask artwork at some ac-ceptable scale.
v
O
c. CalComp check plot - This program permits a composite check plot tobe generated on a low-cost plotter for checking and optimization reasons.
d. Manual modification program - This program aids in implementingmanual modifications when desired.
4. C -MOS standard cell basic system design including:
a. Cell orientation.
b. Power distribution.
c. Low-leakage isolation.
d. Variable standard cell heights.
e. Production design rules.
f. P-type tunnel.
g. Standard guard band interface height.
h. Maximum utilization of P-MOB programs.
5. Design of tests and generation of artwork for test chip encompassing:
a. Static and dynamic evaluation of representative cells.
b. Test of C -MOB system.
c. Evaluation of programs.
d. Determination of process and device parameters.
c. Correlation.
6. Design criteria - The selection of the device geometries and therefore thestandard cell height will reflect tradeoffs which consider the following:
a. Design rules that are compatible with factory and production standards.This decision is based on insuring as reliable a device as possiblesince production standards are based on exhaustive preproduction eval-uation and conservative quality control.
b. Process parameters and characteristics either now in production or soonto be. Introduction of processes having significantly reduced thresholdvoltages and lower doping levels promise to deliver significant improve-ments in performance.
c. Increased gate density.
d. C:,ip dimension compatible with good yield.
e. Compatibflity with computer programs.
f. Low power.
g. Competitive speeds.
vi
Scope of Work
The scope of this program encompasses the various phases of technology and
families of computer programs required to automatically produce artwork for com-
plex functional C-MOS integrated circuits arrays starting with the partitioned logic.
Included in the program scope are the basis circuit designs and layouts for a defined
standard cell family. Also included is the conceptual design and implementation of the
C-MOS array or chip layout that considers systems, logic, and partition requirements,
electrical and packaging considerations, mask generation and processing and fabrica-
tion constraints.
The required computer programs represent a family of programs. These pro-
grams are written in an atmosphere of close contact and continuing communication
with circuit and device technologists forming part of the group responsible for this
program.
Conclusions
Generation of the seven levels of artwo the first logic design using this
new technology has been accomplished with no fundamental problems experienced when
combining the basic chip design concepts, the cell design and layouts, and the computer
programming techniques.
vii
Summary of Recommendations
It is recommended that the program ooddnue since all objectives appear achievable
within the program schedule and costs.
it is recommended that the fabrication of tha test chip proceed without delay so
that the program can be completed on schedule. With fabrication of the test chip,
which NASA had stipulated it would arrange for, the successful implementation of the
program will be easier to evaluate.
viii
TABLE OF CONTENTS
Sect ion Page
i INTRODUCTION ........................................... 1
2 COMPUTER PROGRAM FOR C-MOS DESIGNAUTOMATION ...................................... 0...... 2A. C-MOS Placement Routing and Folding (PRF)
Programs ............................................. 2
3 STATUS OF THE DESIGN OF STANDARD CELLS .............. 3
4 C-MOS STANDARD CELL ENGINEERING LIBRARY............ 5
5 C-MOS STANDARD CELL TOPOLOGIES ...................... IS
r ELECTRICAL CHARACTERIZATION OF THE C-MOBSTANDARDCELL .......................................... 39
7 DESIGN OF THE C-MOS STATIC SHIFT CELL ................ 46
8 C-MOS STANDARD CELL ARRAY NO. 1 - NASATESTCHIP ................................................ 51
9 NEW TECHNOLOGY ............... ........................ 54A. C-MOS Static Shift Register ............................. 54
10 PROGRAM FOR NEXT REPORTING INTERVAL ............... 54
11 CONCLUSION .............................................. 55
ix
LIST OF ILLUSTRATIONS
F iguro page
1 C-MOS Standard Cell Design Status ........................... 4
2 Data for Inverter Cell No. 1110 ............................... 6
3 Data for Two-Input NOR Cell No. 1120 ........................ 7
4 Data for Three-Input NOR Cell No. 1130 ......... . . . . . . . . . . . . . . 8
5 Data for Four-Input NOR Cell No. 1140 ........................ 9
6 Data for Two-Input NAND Cell No. 1220 ............... . ....... 107 Data for Three-Input NAND Cell No. 1230 ........... . .... . .... 118 Data for Four-Input NAND Cell No, 1240 ,,,,,, , , , , , , , , , , , . , , . , , 12
9 Data for Begin Shift Cell No. 1260 ................. . .. . ....... 13
10 Data for Middle Shift Cell No. 1270 ........................... 14
11 Data for End Shift Cell No. 1280 .............................. 1512 Data for Free Shift Cell No. 1290 ............................. 1613 Data for Buffer Inverter Cell No. 1310 ........................ 1714 Composite Topology (Levels 1 through 6) for Inverter
Cell No. 1110 .............................................. 1915 Composite Topology (Levels 1 through 6) for Two-Input
NORCell No. 1120 .......................................... 20Ili Composite Topology (Levels 1 through 6) for Three-Input
NORCell No. 1130 .......................................... 2117 Composite Topology (Levels 1 through 6) for Four-Input
NOR Cell No. 1140 .......................................... 2218 Composite Topology (Levels 1 through 6) for Two-Input
NANDCell No. 1220 ......................................... 2319 Composite Topology (Levels 1 through 6) for Three-Input
NAND Cell No. 1230 ......................................... 2420 Composite Topology (Levels 1 through 6) for Four-Input
NAND Cell No, 1240 ..... . ................................... 2521 Composite Topology (Levels i through 6) for Begin Shift
Cell No. 1260 ............................................... 2622 Composite and Individual Topologies (Levels 1 through 6)
for Middle Shift Cell No. 1270 ................................ 2723 Composite Topology (Levels 1 through 6) for End Shift
Cell No. 1280 ............................................... 2924 Composite Topology (Levels 1 through 6) for Free Shift
Call No. 1290 ............................................... 3025 Composite Topology (Levels 1 through 6) for Buffer
Inverter Cell No. 1310 ....................................... 31
x
l4gure Pap
LIST OF ILLUSTRATIONS (Continued)
26 Composite Topology (Levels 1 through 6) for N&PTransistors Cell No. 1210 • • • ... • • • • • • • • . • ......... :2
27 Composite Topology (Levels 1 through 6) for TestResistors Cell No. 1250 ....... • • • • ....... • • .. • • • . • 33
28 Composite Topology (Lev812 I through 6) for MillerTest Cell No. 1410 .............................. 34
29 Composite Topology (Levels 1 through 7) for InputPad Cell No. 9010 .............................. 35
30 Composite Topology (Levels 2 through 7) for OutputPad Cell No, 9020 .............................. 35
31 Composite Topology (Levels 3, 6, and 7) for GroundPad Cell No. 9100 ............................... 36
32 Composite Topology (Levels 3 through 7) for PowerPad Cell No. 9110 ............................... 36
33 Composite Topology (Levels 1 through 7) for TestTransistor Cell No. 9300 .......................... 37
34 Composite Topology (Levels 2 through 6) for TunnelEnd Cell No. 9500 ............................... 38
35 Composite Topology (Levels .1 through 3) for End CapCell No. 9600 ................................. 36
16 Schematic and Typical Computed and Measured Waveformsfor RCA CD 4007 Cascaded Inverters .................. 40
37 Schematic and Transient Response for Three Cascaded two-input NOR Cells (No. 1120) with Delay CharacteristicsCalculated on the Basis of Optimum Process Parameters ..... 42
38 Schematic and Transient Response for Three CascadedTwo-Input NOR Cells (No. 1120) with Delay CharacteristicsCalculated on the Basis of Nominal Process Parameters .... 43
39 First Step in the Characterization of Three-Input NOR Cell 4540 Circuit for Second Version of C-MOS Static Shift Register
Cell ........................................ 4741 Circuit for Third Version of C-MOS Static Shift Register
Cell ........................................ 4742 Circuit for Fourth Version of C-MOS Static Shift Register
Cell ........................................ 4943 Simulated Performance with Zero Clock Skew of Fourth
Version of Static Shift Register ............. . . . . . . . . . 4944 Performance with 40-no Clock Skew of Fourth Version of
Static shift Register ............................. 5045 NASA C-MOS Test Chip, Logic Diagram ................ 52•16 NASA C-MOS Standard Cell Test Chip Metallization Level
Mask Artwork ................................. 53
xi
LIST OF TABLES
Number Page
1 Parameter Rai ges for Characterization of StandardCells .......................................... 41
1
xii
Bootion i
INTRODUCTION
Quarterly Report No. Z oo mrs the period from March 15, 1970 to June 1E, 1970.
The information presented in this report imludes:
(1) Status of the computer programs for the automatic generation of the maskartwork for the complementary MOB (C-MOP) integrated circuit arrays.
(Z) Descriptions of the logic function, circuit configuration, and other engineeringdata for the C-MCS Standard Cell family.
(3) The seven-level topological composite drawing for each logic cell.
(4) Status of the Standard Cell family
(5) Characterization of each Standard Cell
(6) Description of C-MOB Standard Cell Array No. 1 - Test Chip.
f 1
0
Section 2
COMPUTER PROGRAM FOR C-MOS DESIGN AUTOMATION
A. C-MOS PLACEMENT ROUTING AND FOLDING (PRF) PROGRAMS.
Coding of the modifications for the Placement, Routing and Folding programs
waH completed. A CALCOMP plot of the first standard cell array, the test chip, was
used to exerci p . and test the programs. This debugging process was used to check
the Placement, twuting, and Folding Programs and the artwork generation, CALCOMP,
Manual Modification, and other subroutines.
The debugging process also checked in various degrees all of the improvemen'. i
in the Placement. Routing and Folding Programs that were coded during this reporting
quarter. These improvements* include the following:
(1) Restart Capability
(2) Input Modifica"on 1
(3) Input Modification 2
(4) Fixed Location Component
(5) Special Border Modification
((;) Chip Description Data
(7) Pad Relocation Capability.
The changes and modifications that arose out of the PRF program debugging
phases ware incorporated into the programs. The programs were then subjected to
essentially their final test, the generation of the seven-level final mask artwork for
the test chip. No errors were detected in the several program routines during the
generation of this final mask artwork.
*Descriptions of each of these capabilities can be found in Quarterly Report No. 1.
2
L
Section 3
STATUS OF THE DESIGN OF STANDARD CE LIB
As indicated bythe bar graph in Figure 1, all special-purpose and mask components
have been configured, laid out, digitized, checked, and finalized. Electrical cell char-
acterization dojs not apply to these cells. The functional logic cells (inverter, Buffer-
Inverter, Two- Three- and Four-Input NOR, Two-, Three- and Four-Input NAND, and
the Begin, Middle, End, and Free Shift) have bead configured, laid out, digitized,
checked, and finalized. Electrical characterization of these cells has begun as
Indicated in the bar graph. Errors were uncovered and corrected in several cells.
The emphasis in this reporting period has been to resure that all cells associated with
the test chip are oorreot and Hilly characterized before the test chip is fabricated.
Several layout arrangements for the Set-Reset Flip-Flop (Cell No. 1420) have
been considered.
3
Coll No. I Cell Name
9010
9020
9100
9110
9210
9220
9230
9240
9250
9400
9410
9500
%00
9300
1110
1120
11.10
1140
1210
1220
1230
1240
1250
1260
1270
1280
1290
1310
1410
1420
Input Pad
Output Pad
Ground Pad
VD Pod
Chip Alignment Key
Chip Alignment Key
Chip Alignment Key
Chip Alignment Key
Photo Alignment Key
RCA Symbol
NASA Symbol
Tunnel End
End Cop
Test Transistor
Inverter
Two-Input NOR
Three-Input NOR
Four-Input NOR
N & P Transistors
Two-input NAND
Three-taput NAND
Four-Input NAND
Test Resistors
Begin Shift
Middle Shift
End Shift
Free Shift
Buffer Inverter
Miller Test
Set-Reset Flip-Flop
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
ompoomwmm
Man
N/A
N/A
7t*N/A is not applicable
Figure 1. C-MOS Standard Cell Design Statue unvo mood .4011 30Na PIVNIDx'do
4
f;
Section 4
C-MOS STANDARD CELL ENGINEERING LIBRARY
The present family of C-MOS Standard Cell logical building blocks are described
in Figures 2 through 1S.
The library will provide the engineer with complete electrical, logical, and topolo-
gical specifications for the family of cells. This data is presented in this section and
is another independent section. The information in this section is in a form useful for
systems design, logic Jesign, and the preparation of inputs to the Standard Cell Design
Automaton (DA) system for array design and analysis. The 7-level topological composites
for each standard cell are presented in Section 5. Section 5 will be of particular impor-
tance when new cells are to be added.
Each cell is listed by type and library number. To aid the logic designer, the
logic symbol, Boolean expression, and truth table are given for each cell. The logic
symbol and the truth table provide all necessary data to partition and generate the con-
nection lists for any proposed logic system. More detailed cell information may be
obtained by examining the circuit schematics or the composite topological layouts which
are included in Section 5. The circuit designer will find the latter an invaluable aid in
the analysis of interface problems between existing cells and proposed new cells.
When cell characterization is completed, input and output pin capacitance values and
standard cell rise times, fall times, and propagation delays (as a function of output
pin loading) will be included.
5
P'
A ]PAGE i
lt QUACK
C-MOS STANDARD CELLINVERTER
CELL NO. 1110
SCHEMATIC
LOGIC SYMBOL
+V1 A, 3 X, 2
P
I
A, 3 X, 2LOGIC EQUATION
N
X=A
TRUTH TABLE
CELL 1/0 CAPACITANCE VALUES
A X IN I CAPACITANCE W)
0 12
1 03
DYNAMIC ELECTRICAL CHARACTERISTICS*CHARACTERIS= TIME (es)
PAIR DELAY
RISE TIME
FALL TIME
19
8
7
•C = 2.0 PF
Figure 2. Data for Inverter Cell No. 1110
6
P
C-MOS STANDARD CELLTWO-INPUT NOR
CELL NO. 1120
SCHEMATIC
tV
8,4
"TP
A,3 P
X, 2
N N
LOGIC SYMBOL
8,4
:z>----o X,2A,3
LOGIC EQUATION
X = A + B
TRUTH TABLE
A B X
0 0 1
0 1 0
1 0 0
1 1 0
CELL 1/0 CAPACITANCE VALUESPIN CAPACITANCE ('F)
2
3
4
DYNAMIC ELECTRICAL CHARACTERISTICS*
CHARACTERISTIC TIME (es)
PAIR DELAY
RISE TIME
FALL TIME
22
7
8
•C - 2.0 pF
Figure 3. Data for Two-Input NOR Cell No. 1120
LOGIC SYMBOL
C, O8,4 —o X, 2A, 3 :>
LOGIC EQUATION
X=A+B+C
C•MOS STANDARD CELLTHREE-INPUT NOR
CELL NO. 1130
TRUTH TABLE
A B C X
0 0 0 1
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 0
CELL 1/0 CAPACITANCE VALUESPIN CAPACITANCE (PF)
2
3
4
5
DYNAMIC ELECTRICAL CHARACTERISTICS•CHARACTERISTIC TIME (as)
PAIR DELAY
RISE TIME
FALL TIME
•C =YOPF
Figure 4. Data for Thmo--,,taut NOR Cell No. 1130
8
LOGIC SYMSOL
D,6C,5 X,20,4A, 3
LOGIC EQUATION
X=A+B +C +D
CELI I/n rAPArITAYri VA1 lireT411TY TAl1 t
C-MOS STANDARD CELLFOUR-INPUT NIA
CELL NO.1140
v
C-MOS STANDARD CELLTwo -INPUT NAND
CELL NO. i210
SCHEMATIC
+v
P P
X, 2
A,3 N
B,4 N
LOGIC SYMBOL
A, 32
8,4
LOGIC EQUATION
A=A-1
TRUTH TABLE
A 8 X
0 0 1
0 1 1
t 0 1
1 1
I
0
CELL 1/0 CAPACITANCE VALUESPIN CAPACITANCE (FF)
2
3
4
DYNAMIC ELECTRICAL CHARACTERISTICS•
CHARACTERISTIC TIME (06)
PAIR DELAY
RISE TIME
FALL TIME
J*CL 2 2.0 PF
Figure 6. Data for Two-Input NAND Cell No. 1220
10
Is
C-MOS STANDARD CELLTRREE-INPUT NMI
CELL N0. 1130
SCHEMATIC
LOGIC SYMBOL
tV
A,3 Q--
P ► P 0,4 p—o x, 2
c,ex, t
A,i N
LOGIC EQUATION164
C, 0(,N X = A•B•C
TRUTH TABLE
A B C X
0 0 0 1
0 0 1 1
0 1 0 i
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0
CELL 1/0 CAPACITANCE VALUESPIN CAPACITANCE (vF)
2
3
4
S
DYNAMIC ELECTRICAL CHARACTERISTICS'
CNARACTERISTIC TIME (ms)
PAIR DELAY
RISE TIME
FALL TIME
•C - 2.0 PF
Figure 7. Data for Three-Input NAND Cell No. 1230
11
LOGIC SYMBOL
A,30 + 4 p_-0X, 2C, 0o, s
LOGIC EQUATION
X = A-B•C•D
C-MOS STANDARD CELLFOUR-INPUT NANO CELL NI. 124
TRUTH TABLEA B C D X
0 0 0 0 1
0 0 0 1 1
0 0 1 0 1
0 0 1 1 i
0 1 0 0 1
0 1 0 1 1
0 1 1 O 1
0 1 1 1 1
t 0 0 0 i
I 0 0 1 1
i 0 1 0 1
1 0 1 1 i
1 1 J 0 1
1 1 0 1 1
i 1 t 0 i
t 1 1 1 0
CELL 1/0 CAPACITANCE VALUESPIN CAPACITANCE W)
2
3
4
5
6
DYNAMIC ELECTRICAL CHARACTERISTICS•
CHARACTERISTIC TWE (no.
PAIR DELAY
RISE TIME
FALL TIME
•CL=2.0pF
Figure 8. Data for Four-Input NAND Cell No. 1240
12
C-MCS STANDARD CELL1E11N SIR
CELL NO. 1211
SCHEMAYIC
N N N
N Na 0,7
0.^ o a.•
P ► P
P P
rV ♦V
LOGIC SYMBOLi +4 G, 5
°, 7
D, 3
I- tL---
LOGIC EQUATION
TRUTH TABLE
C D Q Q
L -H 0 0 1
L*H 1 1 0
H •L Q $
L Q Q
H Q b
'EITHER STATE
CELL 1/0 CAPACITANCE VALUESPIN CAPACITANCE (pf)
3
4
S
6
7
DYNAMIC ELECTRICAL CHARACTERISTICS'
CHARACTERISTIC TIME (as)
PAIR DELAY
RISE TIME
FALL TIME
'C • 2.0 PF
Figure 9. Data for Begin S►!tt Cell No. 1260
13
LOGIC EQUATION
C•MOS STANDARD CELLMIDDLE SNIFT
CELL NO.12T0
TRUTH TABLE
C D Q G
L -H 0 0 1
L 44 1 1 0
H--L Q p
L •
t
I Q Q
H • Q
'EITHER STATE
CELL 1/0 CAPACITANCE VALUE$PIN CAPACITANCE (pF)
3
4
S
6
7
DYNAMIC ELECTRICAL CNARACTlRISTICS•
CNARAVERISTIC TIME (as)
PAIR DELAY
RISE T WE
FALL TIME
• C = 2.0 PF
Figure 10. Data for Middle Shift Cell No. 1270
14
C-MOS STANDARD CELLEND SNNFT CELL N0.1100
SCHEMATIC
E,A
N N N
N N 0, 7
P P P
P
c,+va +v
LOGIC EQUATION
TRUTH TABLE
C D Q 0L-•H 0 0 1
L •H 1 1 0
H-L Q p
L Q Q
M • Q
'EITHER STATE
CELL 1/0 CAPACITANCE VALUESPIN CAPACITANCE tPF)
9
4
S
6
7
DYNAMIC ELECTRICAL CHARACTERISTICS'CHARACTERISTK TIME (86)
PAIR DELAY
RISE TIME
FALL TIME
z2
Figure 11. Data for End Shift Cell No. 1280
15
CELL N9.1299
LOGIC EQUATION
CMOS STANDARD CELLFREE SHIFT
SCHEMATIC
N N 0, 7
^. ^ P a,•
► ►
Fv +VC,
TRUTH TABLE
C D 0 Q
L ••H 0 0 1
L •H ) 1 0
H-L 0
L 0 0
H 0 b
I 'EITHER STATE
CELL 1/0 CAPACITANCE VALUESPIN CAPACITANCE W)
3
t
S
6
7
DYNAMIC ELECTRICAL CHARACTERISTICS'
CHARACTERIS" C TIME (no)
PAIR DELAY
RISE TIME
FALL TIME
•C = 2.0 PF
Figure 12. Data for Free Shift Cell No. : P 90
16
C-MOS STANDARD CELLBUFFER INVERTER
CELL N0. 1310
SCHEMATIC
LOGIC SYMBOL
+VA, X, 2
P
A,3 X, 2LOGIC EQUATION
N
X=A
TRUTH TABLE
CELL 1/0 CAPACITANCE VALUESPIN I CAPACITANCE (PF)
A X
0 ) 2
) D3
i
DYNAMIC ELECTRICAL CHARACTERISTICS'
CHARACTERISTIC TIME in*)
PAIR DELAY
RISE TIME
FALL TIME
'CL = 2.D PF
Figure 13. Data for Buffer inverter Cell No. 1310
17
18
Section 5
CMaS STANDARD CELL TOPOLOGIES
The detailed composite topological CALCOMP plots for each of the cells listed in
Figure 1 are presented in Figures 14 through 35. The correct generation of the
composite and each of the seven mask levels for each cell serves as one of the checking
and monitoring steps in validating the various design steps which constitute the de-
sign cycle of each of the Standard Cells.
13ocauso of the rolative complexity of cell No. 1260, the Begin Shift cell, topologies
of each of the first six levels are included in Figure 22 with the composite to facilitate
tho usefulness of the composite layout.
lb
ORIGINAL; PAGE I3
AR POOR QUALITY
4 .
1 ^
.y
t
1 .t.
t
a
^
,tt
} H
^f
f-t
a1'1it 44
{+ 'S. I;;11L, I
+
`? -!'.1 AVE
t
^ 1.
d ♦ i4J j.^ r :I «r+
'iI
^ ;';7 ^ +i f :-,^ rl
d ,.
:1:^1
i J Ja•
iV4 ? ,1
#i 11
f
r
lti,Fitt
2 3OUT IN
Figure 14. Composite Topole ;; 1 1A-vels 1 through 6) for Inverter Cell No. 1110
19
+
i
P-rTi
1.
:1 yV l:
t`1 +-^ f+- r1 r^wr
., ^^ `.+ }' .t r^^ flit r.T
iI ^
l { ' tt^ ♦ M - r ^ -^r1•+
t l i ^1 ^,Fi; 1 1 r:
f t
; 1 1
^ -
y^;J 1 t
.j
, i; I 1{
F4 Irr ♦ , i^
j" {4
1' 1
OUT IN IN
Figure 15. Composite Topology (Levels 1 through G) for Two-Input NOR Cell No. IM
20
9
ORIGINAL PAGE I3OF POOR QUALITY
2 3 4 °OUT IN IN IN
Figure 16. Composite Topology (Levels l through G) for 'Three-Input NOR Cell No. 1130
21
tt', ' I'
1I
1 .I.`1 1 Il
^1 f+ ^.it 11
.1'
1 il. 1{.^1 1.11 ;;
i
r, I 1 {
1 I' !,11
+ ,^ j Ii'J
Z JI
I
i^ iJ •+ ji '+4
AI
fit 1±ft
' 4 .f}t f r x
r ,
i Ji"J J1
It
fi r;,i i J ^i; , ra` r r
1
of
TIV
I 1
, r
44 i
^! 'i+ ail ^( '^';i ;I U
r
11
I
;^.i
! ! TillI,
Q 3 4 5 5OUT IN IN IN IN
Figure 17. Composite Tolvlogy (1.evch; i th t-wi ;h C) for Four -Inimt NUR Cell No. 1140
ORIGINAL PAGE IS
All
till
4
,
jr
i
2 .
3 4.
OUT I N IN
Figure 18. Compoaite Topology (Lcvci:; t lhic>^^ ( ,I) f, or Tw!s-Input NAND Cell A'o. 1220
23
-;-t n4 -
? ( r ^ t ^i
1 '$2(} (
+ ^^^ 1 ay I^' a 'r
i / 1
t I ^ 1
i
(
11 I Ia t
2.
4 5
OUT IN IN IN
Fi!*ure 19. (.omposite Toix)lolry (LCVC]s 1 t1wough 6) for nrec-Input NAND Cell No. 1230
24
01UGINAL PAGE I8
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Figure 20. Composite Topology (Levels 1 through t: ) for Four-Input NAND Cell No. 1240
25
b 4 5 6 7IN CLOCK CLOCK OUT OUT
Figure 21. Composite Topology (Levels 1 through 6) for Begin Shift Cell No. 1260
26
j
S
ORIGINAL PAGE I3OF POOk QUALITY
•17 J. iii
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1 Figure 22. Composite and IndividualTopologies (Levels 1
► through • 6) for MiddleShift Cell No. 1270
V/28
ORIGINAL PAGE ISOF POOR OUA 1 Yry
a s b s 7IN CLOCK CLOCK OUT OUT
Figure 23. Composite Topology (Levels 1 through 6) forEnd Shift Cell No. 1280
29
3 4 S 6 7IN CLOCK CLOCK OUT OUT
Figure 24. Composite Topology (Levels 1 through 6) forFree Shift Cell No. 1290
3v
ORIGINAL p4GE 13OF ppQR QUALITy
11 11"1 111 Iii:
OUT ^N
Figure 25. Composite Topology (Levels 1 through 6) forBuffer Inverter Cell No. 1310
i
31
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j i
fill1e i { 1 , 1,
III{:^^ M:I, .-Y 4,11 ;:
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Figure 26. Cnmlxmite 'roix)iogy (Levels 1 through 6) forN& P Transistors Cell No. 12110
:12
"RIGINAL PAGE 19OF POOR QUALITY
t
iI
t l̂ ,'Tl Fill,I;I I{
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Figure 27. Composite Topology (Levels 1 through 6) forTest Resistors Cell No. 1250
33
Figure 28. Composite Topology (Levels 1 throw 6) forMiller Test Cell No. 1410
ORIGINAL, PAGE 13OE POOR QUALITY
Figure 29. Composite Topology (Levels I through 7) forInput Pad Call. No. 9010
44 4 j ? + r
{
i.
It
T +' + t
i- } ^^ l r4 j ^ i ^ t ^' t 1
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Figure 30. Composite Topology (Levels 2 throw 7) forOutput Pad Cell No. 9020
35
Figure 31. Composite Topology (Levels 3, 6 ,and 7) forGround Pad Cell No. 9100
Figure 32. Composite Topology (Levels 3 through 7) forPower Pad Cell No. 9110
36
Ec^wN
Abpi
m.r
v
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m
0U
OIUGINAL PAGE I3
D$ POOR QUAIdTY
37
^^GWAVC^)R QMUAL
Figure 34. Composite Topology (Levels 2 through 6) forTunnel End Cell No. 9500
Figure 35. Composite Topology (Levels 1 through 3) forEnd Cap Cell No. 9600
38
Section 6
ELECTRICAL CHARACTERIZATION OF THE CMO8 STANDARD CELL
This section describes those steps taken to date to verify and authenticate the
circuit analysis techniques that are used to generate the delay characteristics for the
standard cell ihmily. The propogation delay for cell No. 1120, the taro-input NOR, is
generated using these correlated results. This first step correlation will be updated
and refined after experimental measurements on the fabricated test chip have been
made.
To obtain the parameters for the models used, both do and transient measurements
were taken on several oommeroially available RCA C-MOS Integrated Circuits that
were processed using the new low-voltage process. From the de measurements, the
threshold voltage, substrate doping levels, channel mobilities, and channel lengths for
the transistors in each circuit are obtained. A typical comparison of the measured
transient response of several cascaded inverters with the computed transient re-
ponse using experimentally measured device parameters is illustrated in Figure 36.
A computed accuracy of greater than 10% (4ns/40ns) after three stages of logic was
obtained as indicated in Figure 36. This correlation has been further improved by
noting that the 0.8-pF Miller capacitance, shown in the schematic of Figure 36, was
underestimated. Measurement at the pins of the IC package later indicated an
actual Miller capacitance of 1.5 pF. When this measured values of capacitance is
used, instead of the estimated value, correlations considerably better than 10% are
obtained.
Having verinsd the accuracy of the RCA C-MOS Analysis Program, computed
transient responses of C-MOB Standard Cell No. 1120 (Two-Input NOR) were generated.
39
dwCvW
JQ
h
so
a
04
U
UU
a^ AC
w
O
Q Q Q Q O Q Q Q Q OQ O! m ti tp 0 v to N
40
A schematic and the transient response for three cascaded Two-Input NOR cells are
presented i,-k F4pr+e 37. The optimum prods parameters assumed resulted in a
comp :lid 18-as pair delay. The delay characteristics for the same cascaded Two-
Input NOR cells calculated on the basis of nominal process parameters are presented
in Figure 38. The somewhat slower speed (as indicated by the 23-ns pair delay) is
attributable entirely to the higher substrate doping levels assumed for the nominal
process parameters. For both oases nodes 5, 7. and 9 had 3.0-pF loads.
In addition to verWag the accuracy of the circuit analysis techniques that are to
be used for the electrical characterisation of the standard cells, it is also necessary
to determine nominal values for the new low-voltage process transistor parameters.
The parameter spread used for the delay calculations are presented in Table 1-
TABLE 1. PARAMETER RANGES FOR CHARACTERIZATIONOF STANDARD CELLS
Parameter Worst-Case Value Best-Case Value
NA(cm g) 5.0 x 1018 1.0 x 1018
ND (CM-3 ) 5.0 x 101b 2.0 x 1015
TM(cm) .105 x 104 .100 x 10-4
VTN, VTP(V) 2.5, -2.7 1.3, -2.0
A W pp (cm2/ V-s.) 400, 153 440, 170
Similarly, values for the P -N juwdon capacitance per unit area and the MOB gate
capacitance per unit area have been determined. Presently the following values of
capacitance are being used.
41
9 10
O O
K K
Nu ^
Z z
00
ms
aUOz^
wOmw
U
eO
S+
w
V
U
H
m
w
M>
O
9
In
1^!M'f
^fNCv
n W
2^-
a
0
to
>~
O^
C vs m ti a m a M a - o$11 OA
42
It'd !eo cx x
qr
^ tZ =
P_0
Q
x'
0Nrl
i+
z^
pG o
z40 1^
cu
^ ^ Z^ ^ O
o ^^a0
g ^
v $ U^W
U
O
h
Q O! • !► ^0 h ^ IH N
SIIOA
— O
43
C NP a Capacitance per unit area between N+ dlftsion and P well = 0. 21 pF/milt
C PN
= Capacitance per unit area between P+ diffusion and N- substrate-0.12pF/mil2
C M0B - Capacitanoe per unit area between gate metallization and N+ or P+diffusions _ 0. 20 pF/mill
The first step in the characterization of the Three-Input NOR cell is presented in
Figure 39. The solid lines represent the intended transistor logic, while the dashed
lines represent the parasitic capacitance values. it is in the calculation of the parasitic
capacitance values that the P-N junction and MOB gate capacitance per unit area values
are needed.
44
4 .r^,-n nz r
m
+V
r c-F —I(
I P
C PL ..^^.
CUSP
CI1
P
C P
-lr
r
cap
Cl
iI
P
L+ —CtDP
EGLEND:
C I= CAPACITANCE OF SOURCEAND/OR DRAIN TO
SUBSTRATE.
C/SP'N = CAPACITANCE OF GATE TOSOURCE OF P (OR N)TRANSISTOR.
C111DP,N = CAPACITANCE OF GATE TODRAIN OF P (OR N)TRANSISTOR.
C O =CAPACITANCE OF OUTPUTDRAINS.
---— I -^F * c°
N N N
I I I"
Figure 99. First Step in the Maracteriaerion of Three-hpd NOR Cell
45
Section 7
DESIGN OF THE C-MOB STATIC SHIFT CELL
The C -MOB Static Shift cell has gone through, a series of designs. In each design
it is necessary to consider the topological and layout problems in addition to the cir-
cuit problems. A revision of the first circuit which allowed a compact layout (9.6 mils
for the string cell) is shown in Figure 40. (See circuit description in Quarterly Report
No. 1. ) In this circuit the P-channel transmission devices could not transmit the logic
node "zero' without attenuation at the storage rode. This created the danger that the
capacitive noise due to the attempted entry of data when the clock was high would
partially turn on the wrong data gate. Further in this design the incoming data must
overpower the previously "on" P-channel device in the holding circuit of the flip-flop,
which put additional strain on design tolerances.
To avoid the problem of the imperfect transmission device, a new circuit, shown
in Figure 41, was devised. A layout based on this circul.t was the same size (9.6 mils
for the string cell) as the previous cell. In this circuit two clock lines (clock and cfocli)
must be transmitted between the string cells, compared to only one before. However,
only r) ic data interconnection is needed between the cells where two were needed before
(data and data). The original philosophy of having a single cell layout with five pads
along the bottom for use when needed is still preserved, and three connections along
each side of the cell are available for adjacent cells when needed. The number of
transistors (10) in this design is the same as that for the previous design. In this de-
sign it is still necessary to overpower the holding transistors in the flip-flop in order
to enter data stored at a storage node which becomes isolated from its data source as
the clock goes high. The difference is that data of either polarity is jam-transferred
into the same side of the flip-flop from a single data storage node through a super-inverter
ft
46
0
iC
v
a
C
c
D
C
e
^TIM ♦10V
Figure 40. Circuit br Second Version of C-MOB Static Shift Register Cell
Figure 41. Circuit IDr Third Version of C-MOB Static Shift Register Cell
47
which can drive one and one-half times the output current. These two series transistors
have to have three times the channel width as the output transistors. The really impor-
tant difference, however, is that instead of two P-channel transmission devices on a
single clock, a parallel N-channel and P-channel transmission device now works off
of clock and clock. This allows transmission of data of either polarity without attenua-
tion, which yields significant improvement in'the noise immunity at the storage node.
The circuit, shown in Figure 42, was simulated with $ c-3*+_nected to D to make a
triggerable flip-flop. Results of the simulation showed very good noise immunity at
the storage node. However, the simulation indicated speeds not compatible with the
speeds of the other C-MOB cells. This performance was associated with the fact that the
inverter, which forced information into the flip-flop, can supply only one and one-half
times the current of the output stage, which opposes this new data current. Therefore,
the current available to charge the output capacitance is one and one-half minus one,
or only one-half of the current which the output stage can supply, which is actually
only three -quarters that of the basic inverter-.
The design was improved significantly by adding two transistors to the configuration
shown in Figure 41 to make the configuration shown in Figure 42. This opened the
circuit path of the opposing output when new data was entered.
The two new series transistors in the Q output stage disconnect the regular out•,mt
when the clock goea high, allowing the data entry stage, which is then activated, to
enter the new data without opposition. The current driving ability and consequently
the speed can now be fully compatible with the other C-MOS cells. All the other fea-
tures of the old circuit are retained. The new cell layout is increased in width by
only 0.9 mil to 10.5 mils for the string cell, a small price to pay for a three-fold
speed improvement.
The simulated performance with zero clock skew of the circuit of Figure 42 con-
nected as a binary counter is shown in Figure 43. The parameter values used in
these computations are not the experimentally correlated values used in Section 6
t^.
48
C
Q
C
C
Q
C
Figure 49. Circuit for Fourth Version of C-MOB Static Shift Register Cell
•10
C0
+10
C0
+10
VOLTS Q0
+10
b0
+10
^1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1I 1 10 w 40 w w 100 w 140 180 100 2w
TIME (ns )
Figure 43. Simulated Performance with Zero Clock Skew of FourthVersion of Static Shift Resister
49
10
VOLTS 5
o^
since it was done at an earlier time. However, the values are not substantially
ditfereaL
The performance of the register with a 40-ns clock skew is shown in Figure 44.
This value was deemed the %per limit of clock skew based on results using clock
skews 50 us or higher.
TIME (ns)
VOL) b e
is
0050 100 150 200 250 300
TIME ( ns) .
Figure 44. Performance with 40-no Clock Skew ofFourth Version of Static Shift Register
50
Section 8
C-MOS STANDARD CELL ARRAY NO. 1 - NASA TEST CHIP
All of the cells and components required for the test chip have been completed.
Two design reviews were performed. The logic of the test chip, the interconnections,
pin allocations and definitions have been checked. The final logic contained on the test
chip is shown in Figure 46.
A set of input data describing the test chip was prepared for the PRF, artwork,
and CALCOMP plotting programs. A CALCOMP plot of the test chip containing the
outline of all cells was generated. The original chip size was about 120 by 105 mils.
With the use of the Msstual Modifications program, various modifications anti improve-
ments were made. This included movement and placement of pads to provide a more
uniform arrangement to facilitate bonding. In addition, Wanels were removed from
certain outputs to increase the accuracy gad reproducibility of parameter, perfor-
mance and characterization measurements when they are made on the fabricated chip.
Finally, the application of the Manual Modifications program faOlitated the reduction
of the chip size to Mpro3dmately 100 by 98 mils.
Following evaluation of the CALCOMP plots the final 7-level mask artwork was
plotted on the automatic plotter. Level 6, the metallization level, is shown in Figure
46.
51
F p
I E
^^ e F lc;l
zI
8tin
0N
NZ
3}aWJO
a4
WNWZ
N
NWy^- z
a
S
^ WW ~
WW J> JZ
YWJO
a
q
aNa
H
Vri
a
z
rJ d
w
2
52
am
r
r-
ORIGINAL, PAGE IS
DZ POOR QUALJTx
rrvC
6if
Figure 46. NASA C-MOS Standard Cell Test ChipMetallization Level Mask Artwork
53
L
Section 9
NEW TECHNOLOGY
A. C-MOS STATIC SHIFT REGISTER
A Patent Disclosure (RCA Docket No. 63,427) for the C-MOB Static Shift Register
described in Section 7 of this report is now being processed by RCA.
Section 10 .
PROGRAM FOR NEXT REPORTING INTERVAL
The next report will be a monthly report covering the period from June lb, 1970
to July 15, 1970, the seventh month of this contract. The test chip will be run through
the design automation cycle using the updated corrected tape. The working plates will
be fabricated.
Cell characterization for the average propogation delay will continue.
ft
54
8ectioq 12 ORIGINAE PAGE ISOF MOR QUALITx
CONC LUIM
A11 of the basic r "erate the mask artwork for C-MOS standard
eel l integrated circuit, arraaAssitAsm complets&
included among thwI mraeota are;
1. Creation, dew► E f the standardeell circuit complement includingchecking. . --aft-Completion aMAMa%Wat the varima ltomputer programs required in thedesign automa W15PM '"'
3. Creation wW &€r-U0&*6aidw+d cell array concept.
4. Creation, deanitte% SMkoelp of the logic for the test chip.
5. Preliminary rwrr of tis /sat chip through the Design Automation (DA) cycleusing CALCOMP fAW9A' dek`points.
6. Final mask arlw+sek -s•ss^M^erw.
Examination of the final artwoft suggested further improvements to increase
accuracy. The test chip wiL, tierefore, be re-run through the DMA cycle.
ti
55/" AM'AM'-- t
iE